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SEQUEL: ASEQUEL: A S Solver for circuit olver for circuit EQEQuations uations with with UUser-defined ser-defined ELELementsements

Prof. Mahesh B. PatilProf. Mahesh B. Patil

www.ee.ittb.ac.in/faculty/mbp/sequel1.htmlwww.ee.ittb.ac.in/faculty/mbp/sequel1.html

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• Allows user-defined elements

• Based on the Sparse Tableau Approach: no need for “through” and “across” variables

• DC, transient, small-signal, noise

• Mixed-signal simulation

• Electrothermal simulation

• Sensitivity analysis (exact)

FeaturesFeatures

Continued

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• Switched capacitor circuits

• Efficient “steady-state waveform” computation

• Perfectly “general” elements are possible (mechanical, thermal etc)

• Runs on GNU/Linux and Solaris

• Free!!

FeaturesFeaturesAcademia Industry Meet 2002, Electrical Engineering Department

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Block Diagram of SEQUELBlock Diagram of SEQUELAcademia Industry Meet 2002, Electrical Engineering Department

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• All elements are divided into (a) purely electrical, (b) pure digital, (c) DAC type, (d) ADC type.

• After every analog time point, process the ADC type elements.

• After every digital time point, solve the analog equations if there are DAC type elements.

• Use the event-driven strategy for digital elements.

Mixed-signal simulationMixed-signal simulationAcademia Industry Meet 2002, Electrical Engineering Department

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Mixed-signal example:Mixed-signal example:Academia Industry Meet 2002, Electrical Engineering Department

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• Modern MOS transistors are very difficult to model analytically (small gate lengths, complex doping profiles etc.)

• Model development (if at all possible) is a long and tedious process: it could take a year!

• The LUT approach provides a quick way to estimate circuit performance without model development.

Look-up table approach for MOS circuit Look-up table approach for MOS circuit simulationsimulation

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• Very easy to incorporate new elements

• SEQUEL is already being used at IIT Bombay for R and D, and course work.

• SEQUEL allows efficient “steady-state waveform” computation, which is not offered by any other general-purpose simulator.

Power electronics Power electronics examplesexamples

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Power electronics examplesPower electronics examplesAcademia Industry Meet 2002, Electrical Engineering Department

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Power electronics examplesPower electronics examplesAcademia Industry Meet 2002, Electrical Engineering Department

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• Very often, one is interested only in the steady-state solution and not how it was attained.

• This problem can be converted into a much smaller problem with the state variables as the only unknowns. The Newton-Raphson method can be used to solve the new problem.

Steady-state waveform computation in Steady-state waveform computation in Power Electronics Power Electronics

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Example N1 N2

Buck Converter 740 4

1-phase half-controlled bridge converter

31501-phase half wave

rectifier

Cuk Converter

Boost Converter 31250

625 3

17125Induction motor problem

42003-phase diode bridge rectifier

4110

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AcknowledgementsAcknowledgements

• Prof. M.C.Chandorkar, • Prof. B.G.Fernandes, • Prof. V.Agarwal, • Prof. K.Chatterjee, • Prof. A.M.Kulkarni, • Prof. S.V.Kulkarni

from the PEPS group

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• Parallel implementation

• Simulation of “regular” circuits (e.g., displays) in collaboration with IITK

• GUI

• Commercial package?

Future PlansFuture PlansAcademia Industry Meet 2002, Electrical Engineering Department

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Fast Circuit Simulators at IIT BombayFast Circuit Simulators at IIT Bombay

Prof. H.NarayananProf. H.Narayanan

hn@ee.iitb.ac.inhn@ee.iitb.ac.in

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BREMICS (1986, 87, 90) for analog simulation of networks arising out of digital circuits (MOS transistors, resistors, capacitors)

• could handle 1000 nodes, 2000 edges. For the restricted class much faster (5 to 10 times) than SPICE on PCs.

• BITSIM (1991-92) general purpose (SPICE like) simulator based on conjugate gradient method for solution of linear equations and the hybrid analysis for writing equations. Could handle 3000-4000 nodes, 8000 edges originally on SUN, now on Pentiums. Work done through several B.Tech and M.Tech. projects and through a research engineer

(Dr. Subir Roy)

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Currently “Large Circuit Simulations” by Parallelization is actively pursued

The innermost subroutine of a general purpose simulator is a DC circuit analyzer (voltage sources, current sources, resistors, controlled sources)

We parallelize this by the “Multiport Decomposition Method”

Our simulator can currently solve

700,000 nodes, 1.4 million edges dc circuit in about 10 minutes using 8 processors (Pentium IV ‘s) connected through a 100 MBPS link

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Application of large dc circuit analyzerpplication of large dc circuit analyzer

100,000 RC

Elements

1000RC

Elements

Few terminals

Same terminal

behaviour

Same terminal

behaviour

1) The Multi port Reduction Problem

arises while modelling “short circuits” in chips at high frequency Continued

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we have constructed a few such reduction algorithms andwe have constructed a few such reduction algorithms andimplemented them. e.g. SARN reduces RC circuit with implemented them. e.g. SARN reduces RC circuit with 100,000 nodes 200,000 edges 50 terminals in ½ hour to 1000 100,000 nodes 200,000 edges 50 terminals in ½ hour to 1000 node circuit with 50 terminalsnode circuit with 50 terminals..

2) Solving a large Combinational optimization problems a) Network flow problems

b) Minimum cost flow problems

Both of these can be posed as nonlinear static circuit analysisproblems

Innermost subroutine is a DC analyzer.

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3) Parallelizing large Sparse linear equations The equation are made to appear like those

of a dc circuit and then given to the dc analyzer to solve by “Multi port Decomposition”.