Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond

Mark RodwellUniversity of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 faxISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco

Applications of InP HBTsOptical Fiber Transceivers

40 Gb/s:InP and SiGe HBT both feasible ICs now available; market has vanished

80 & 160 Gb/s may come in timewithin feasibility for scaled InP HBTworld may not need capacity for some timeWDM might be better use of fiber bandwidthmmWave Transmission65-80 GHz, 120-160 GHz, 220-300 GHz Links Low atmospheric attenuation (weather permitting). High antenna gains (short wavelengths). 10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power59-64 GHz LANs: short range, wideband, broadcast Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought

Motivation for InP HBTsParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower tc , higher J base electron diffusivity40 cm2/s~2-4 cm2/slower tb base sheet resistivity 500 Ohm5000 Ohmlower Rbb comparable breakdown fieldsConsequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidthProblem for InP: SiGe has much better scaling & parasitic reductionTechnology comparison today: Production SiGe and InP have comparable speed SiGe has much higher integration scales Production 1 mm InP: low NRE, fast design cycle for SSI/MSI ICs to ~90 GHz (cost includes design time as well as $/mm2

Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes

InP HBT fabrication processes todayMesa processes with self-aligned base contacts: Research labsModerately low yield 1000 HBTs/IC 300 GHz ft, 400 GHz fmax , 7 V BVCEO, 100 GHz clock ~ 0.5 mm emitter width Mesa processes with non-self-aligned base contacts: Production in GaAs HBT foundries (cell phone power amps) Somewhat better yield 3000 HBTs/IC (?) 150 GHz ft, 180 GHz fmax , 7 V BVCEO, 70-90 GHz clock 0.8 mm emitter width, 1.0 $/mm2 Exotic research processes for reduced Ccb: 1) transferred-substrate, 2) strongly undercut collector mesa technology demonstrations, not IC technologies Present research processes in InP community: early development phases combine InP materials advantages with SiGe-like processes junction regrowth, dielectric sidewalls, trenches, pedestal implants more detail in later slides

ScalingRequired transistor design changes required to double transistor bandwidth easily derived by basic geometric calculations(C s, t s, I/C s all reduced 2:1)

key device parameterrequired changecollector depletion layer thicknessdecrease 2:1base thicknessdecrease 0.707:1emitter junction widthdecrease 4:1collector junction widthdecrease 4:1emitter resistance per unit emitter areadecrease 4:1current densityincrease 4:1base contact resistivity (if contacts lie above collector junction)decrease 4:1base contact resistivity (if contacts do not lie above collector junction)unchanged

Parasitic Reductionthick extrinsic base : low resistancethin intrinsic base: low transit timewide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)wide base contacts: low resistance narrow collector junction: low capacitanceAt a given scaling generation, intelligent choice of device geometry reduces extrinsic parasiticsMuch more fully developed in Si

Optical Transmitters / Receivers are Mixed-Signal ICsTIA: small-signal LIA: often limiting MUX/CMU & DMUX/CDR:mostly digitalSmall-signal cutoff frequencies (ft , fmax) are ~ predictive of analog speedLimiting and digital speed much more strongly determined by (I/C) ratios

InP HBT has been well-optimized for ft & fmax, less well for digital speed

How do we improve gate delay ?

Why isn't base+collector transit time so important ?Depletion capacitances present over full voltage swing, no large-signal reduction

Scaling Laws, Collector Current Density, Ccb charging timeCollector Field Collapse (Kirk Effect)Collector Depletion Layer CollapseCollector capacitance charging time is reduced by thinning the collector while increasing current

Challenges with Scaling:Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length sets minimum size for collector Solution: reduce base contact resistivity narrower base contacts allowed Solution: decouple base & collector dimensions e.g. buried SiO2 in junction (SiGe)

Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements

Current Density: self-heating, current-induced dopant migration, dark-line defect formation Loss of breakdown avalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP) .sufficient for logic, insufficient for powerYield submicron InP processes have progressively decreasing yield

Technology Roadmaps for 40 / 80 / 160 Gb/s

Parameter

Mesa HBT

Generation 1

Mesa HBT

Generation 2

Mesa HBT

Generation 3

Simulated MS-DFF speed (no interconnects)

62 GHz

125 GHz

237 GHz

Emitter Junction Width

1 m

0.8 m

0.2 m

Parasitic Resistivity

50 -m2

20 -m2

5 -m2

Base Thickness

400

300

250

Doping

5 1019 /cm2

7 1019 /cm2

1020 /cm2

Sheet resistance

750

700

700

Contact resistance

150 -m2

20 -m2

10 -m2

Collector Width

3 m

1.6 m

m

Collector Thickness

3000

2000

1000

Current Density

1 mA/m2

2.3 mA/m2

9.3 mA/m2

Acollector/Aemitter

4.55

2.6

2.6

170

260

500

170

440

700

1.7 ps/V

0.63 ps/V

0.31 ps/V

0.5 ps

0.19 ps

0.093 ps

0.8

0.65

0.52

1.7 ps

0.72 ps

0.18 ps

0.1

0.15

0.15

_946408068.unknown

_1079032737.unknown

_1079032928.unknown

_1079034300.unknown

_1079032819.unknown

_1079032681.unknown

_946407858.unknown

InP-collector DHBTs: Self-Aligned Mesa Structure M Dahlstrom (UCSB/ONR), Amy Liu (IQE)200 nm InP collector, 30 nm InGaAs base8(1019) /cm3 base doping

1 mm base contacts, 0.5 mm x 7.5 mm emitter junction0.7 mm emitter contact Vce=1.7 V J=3.7E5 A/cm2Vbr,ceo=7 VCollector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um 0.7 um base contact width 0.3 um base contact width

Submicron InAlAs/InGaAs HBTs: High power gains at very high frequenciesGains are high at 220 GHz, but fmax cant be extrapolatedUCSB/ONR: Miguel Urteagatransferred-substrate device6-40, 75-110, 140-220 GHz

fmax = 460 GHz ft = 139 GHzInP-Collector Double Heterojunction Bipolar Transistors0.5 m x 8 m emitter (mask)0.4 m x 7.5 m emitter (junction)1.0 m x 8.75 m collector3000 collector drift region VBR,CEO = 8 V @ JE =5*104 A/cm2UCSB/ONR: S. Leetransferred-substrate process

Large-Area (High Current) DHBTs for mm-Wave Power8-finger device: 1 x 16 mm emitter, 2 x 20 mm collector UCSB/ARO: Y. WeiVBR,CBO> 7VKey challenges with high-current HBTs: - thermal stability (ballasting)- minimal base feed metal parasitic resistance - reliable electromagnetic models of feed networks

InP/InGaAs/InP Metamorphic DHBTs on GaAs substrates

UCSB/ONR: Young-Min KimComparable performance to lattice-matched of similar design.

Potential for SSI/MSI InP HBTs in cheap GaAs HBT foundry processes.

174 GHz, 6.3 dB, Single-Transistor AmplifierUCSB/ONR: Miguel Urteaga0.3 um transferred-substrate HBT

0

.

2

p

F

5

0

3

0

1

.

2

p

s

5

0

3

0

0

.

2

p

s

8

0

1

.

2

p

s

0

.

6

p

s

8

0

1

.

2

p

s

5

0

I

N

O

U

T

Multi-Stage 140-220 GHz Amplifiers Three-stage amplifier designs: 12.0 dB gain at 170 GHz 8.5 dB gain at 195 GHzCascaded 50 W stages with interstage blocking capacitors

Cell Dimensions: 1.6 mm x 0.59 mm0.3 um transferred-substrate HBT UCSB/ONR: Miguel Urteaga

75 GHz, 80 mW Power Amplifier 0.4 0.9 mm die, AE = 16 x (1mm x 16 mm) = 256 mm2transferred-substrate process Bias: Ic=130 mA, Vce=4.5 V UCSB/ARO: Y. Wei250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers

87 GHz HBT static frequency dividerInAlAs /InGaAs/InP MESA DHBT 400 base, 2000 collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax2.5 x 105 A/cm2 operation UCSB/ONR: PK Sundararajan

InPhi slides

InPhi slides

OC-768 Linear ComponentsFrequency (GHz)Transimpedance (dB ohms) (single-ended) Transimpedance Amplifier26 dB Limiting Amplifier43 Gb/sDesign Challenges: Gain flatnessPeaking due to interconnect inductance,gm element phase shift, Ccb variation, photodiode parasitics, single-ended / differential converter.Jaganathan & PullelaVetury, Pullela, Rodwelllcurves with, withoutPIN parasitics-7.8 dBm sensitivity @ 10-12 BER (231-1) PRBS

OC-768 Modulator Driver 30 dB gain, 40 GHz bandwidth, >10 dB S11 & S22 8 ps rise/fall (20-80%) , ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differentialDesign Issues: Gain flatnessDistributed line losses, current handling & loaded Z0Complexity of transmission-line layoutAssociated low-frequency droop Emitter follower negative resistance peakingEfficacy of bypass capacitancesCommon-mode traveling-wave instabilityK. Krishnamurti et al

OC-768 Digital Components4:1 Multiplexer / CMU 47 Gb/s1:4 Demultiplexer / CDR (recovered 10 Gb/s data)

Very strong features of SiGe-bipolar transistors

High current density 10 mA/mm2T-shaped polysilicon emitter 0.25 mm junction wide contact low resistance, high yieldThin intrinsic base: low tbThick extrinsic base: low RbbLow Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic baseHigh-yield, planar processing high levels of integration LSI and VLSI capabilitiesSiGe clock rates up to 65 GHz Much more complex ICs than feasible in InP HBT InP HBT must reach higher integration scales or will cease to compete

Submicron InP HBT Development: ResearchObjective: speed extrinsic parasitic reduction deep submicron scaling Objective: yieldplanar process eliminate liftoff eliminate undercut etches

Target Applications: High speed (>100 GHz) digital & mixed signal. 160 Gb/s optical fiber transmission Similar research effortsRockwell/GCS/UCSB Vitesse. Lucent. TRW. HRL Labs. Double-poly (SiGe-like) HBTPlanar HBT: Dielectric Sidewall Process

InP HBTsInP has better electron transport than SiGe faster if comparable-quality fabrication processes are employed. Adaptation of 1-mm GaAs (cell phone) HBT foundry process to InP Inexpensive, low NRE, low mask cost, fast design cycle Good process for SSI/MSI optical fiber and mm-wave ICs Not good for larger-scale digital / mixed-signal ICsConventional but more highly scaled InP HBT processes millimeter-wave power to 200 GHz, perhaps beyond. Future markets ? Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes 3:1 higher bandwidth at a given scaling generation 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.