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5nm
www.guc-asic.com
2.5D Package
Technology & Design
5nm ASIC Platform Total Solution
DesignMethodology
Technology & Design IP
Eco-System
2.5DPackage
Industry Leading5nm ASIC Platform
GUC has launched the industry’s leading ASIC platform for high performance computing, artificial intelligence, machine learning, and networking applications on 5nm technology. The platform covers a comprehensive 5nm IP ecosystem and advanced 2.5D package ( CoWoS, InFO_oS ) solution.
GUC 5nm Breakthroughs 5nm test chip MPW tape out in March ‘19
Target speed: 2.0GHz @ 0.75V, 650MHz @ 0.4V
Low voltage characterization ( 0.3V ~ 0.85V )
Performance correlation, Power / IR correlation
5nm Design Flow Ready to Go APR flow, sign-off flow, Re-K flow
with large chip tool qualification
GUC In-House IP Portfolio HBM2E 3.2Gbps
EMS 16G / 25G SerDes
TCAM
Die-to-Die interconnect IP
Customized standard cell library & SRAM macro
Partner IP Portfolio PCIe 4.0 / 5.0 / CCIX
DDR4 / 5 with DIMM
56G SerDes
112G SerDes
56G SerDes (chiplet)
112G SerDes (chiplet)
GUC HEADQUARTERS, HSINCHU, TAIWAN [email protected]
GUC TAIPEI [email protected]
GUC NORTH [email protected]
GUC KOREA+82-10-4590-0975 [email protected]
GUC EUROPE [email protected]
www.guc-asic.com
2.5D Advanced Package DesignGUC specializes in heterogeneous and homogeneous multi-chip integration solutions ( e.g. HBM, 56G / 112G SerDes ), using CoWoS and InFo 2.5D packaging and large die partitioning that improves chip yield and effective cost.
Die 1 Die 2 SOC
SerD
es
SerD
es
GUC D2D IP Roadmap & Value PropositionThe most optimized solution on power, area and speed for multi-die integration by InFO or CoWoS
Power : below 0.25 pJ/bit (single 0.75V power supply required)
Area : 0.7 Tbps/mm2 (RX and TX)
Beachfront : 0.7 Tbps/mm (RX and TX)
Speed : 8 Gbps/lane
Less substrate layers required
Reliable Solution
No BER, error correction is not used
DFT functionality for separate dies testing and InFO/CoWoS assembly testing
Redundant lanes embedded to achieve better yield
GUC provides Total Service Package, including sub-system built, SI/PI/Themal co-sim and sub-system bring-up services
2020 2021
N7
N5P
D2D
TPO Silicon Proven
D2D PHY
D2D PHY
