Inexpensive high-speed intensified CID camera controller

  • Published on

  • View

  • Download

Embed Size (px)


  • Inexpensive highspeed intensified CID camera controllerJ. S. Shakal Citation: Review of Scientific Instruments 64, 946 (1993); doi: 10.1063/1.1144147 View online: View Table of Contents: Published by the AIP Publishing Articles you may be interested in Using a High-Speed Camera to Measure the Speed of Sound Phys. Teach. 50, 45 (2012); 10.1119/1.3670086 Off the shelf inexpensive digital highspeed photography from CASIO Phys. Teach. 48, 559 (2010); 10.1119/1.3502522 The highspeed camera ULTRACAM AIP Conf. Proc. 848, 808 (2006); 10.1063/1.2348063 Highspeed infrared camera Rev. Sci. Instrum. 63, 3662 (1992); 10.1063/1.1143594 HighSpeed Framing Disk Camera Rev. Sci. Instrum. 29, 862 (1958); 10.1063/1.1716022

    This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: Downloaded to IP: On: Thu, 27 Nov 2014 03:20:30

  • lnexpensive high-speed intensified CID camera controller J. S. Shakala) Engine Research Center, Department of Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53 706

    (Received 29 July 1992; accepted for publication 23 November 1992)

    Image intensifiers are an essential part of many qualitative and quantitative imaging experiments. When temporal resolution is desired, continuous mode intensifiers such as first-generation intensifiers and ungated second-generation intensifiers are not suitable, and a gateable intensifier must be used. For laser fluorescence experiments, a controller providing synchronization on the order of nanoseconds between the microchannel plate of the intensifier and laser is usually needed. Such controllers are expensive and often designed for general purpose use, e.g., multichannel delay generators. However, by utilizing recently introduced integrated circuits, a low-cost, accurate, and versatile controller can be constructed. The device described in this article has an overall insertion delay of under 40 ns and jitter of under 3 ns. It can be controlled by front-panel switches or by a personal computer for automated operation. The device permits asynchronous triggering of a CID camera while leaving the camera-frame grabber timing cycle uninterrupted. Other uses are also suggested, and construction details are given.


    With the lower cost and increased performance of frame grabbers, pulsed lasers, solid-state cameras (CCD, CID, etc.), and gateable intensifiers, high-speed imaging experiments have become more popular. But to utilize the high-speed characteristics of these components, a way of synchronizing them is needed. In chemical kinetics studies, for example, an image of the fluorescing species is often desired. In this case the laser must be fired to excite the transition, followed by intensifier triggering (usually a fraction of a microsecond later) and then frame grabber triggering. For asynchronous applications, the camera also needs to be cleared, activated, and read out at the appro- priate time. A controller is thus needed to synchronize the laser, camera, intensifier, and frame grabber. The unit de- scribed in this article is designed to interface with an EOSI Model 91006 intensified CID camera (Electra-Optical Ser- vices Incorporated, Charlottesville, WV), an externally triggered frame grabber and a generic pulsed laser requir- ing charge and fire signals. The intensifier, a second- generation DEP Model XX145OCJ (Ziemer & Associates, Tempe, AZ) and CID camera (CID) Technologies Incor- porated, Liverpool, NY) could also be purchased sepa- rately and a custom system built.

    The camera and gate controller (referred hereafter as CGC) described in this article could also be used for other purposes, such as (a) a stand-alone, computer-controlled, nanosecond level delay generator; (b) a stand-alone, computer-controlled high-speed pulse width modulator; (c) a stand-alone asynchronous CID camera and frame grabber controller. Design details will be discussed first, followed by operation characteristics, and then test results will be presented.

    a)Permanent address: Internal Combustion Engine Laboratory, Univer- sity of Wisconsin-Madison, Madison, WI 53706.


    An ICID-based imaging system using the CGC de- scribed in this article is shown schematically in Fig. 1 and described briefly below. The ICID camera unit consists of a Model 3710 CIDTEC CID camera head coupled to an image intensifier and associated intensifier control electron- ics. The CIDTEC control unit provides the timing base for the camera and frame grabber, an ITEX VS-lOO-AT (Im- aging Technology Incorporated, Woburn, MA). It also multiplexes the video feed from the camera head into an RS-330 composite video signal, along with providing cer- tain timing wave forms to the frame grabber control cir- cuitry in the CGC. The EOSI gate drive box contains a high voltage dc power supply and switching element (op- tocoupler) for the intensifier gate.

    The CGC contains a laser interface and frame grabber driver, a programmable delay generator, and a program- mable width generator. The laser interface contains a high- speed 50-Q driver and the frame grabber driver contains logic necessary to acquire an image from an asynchronous external trigger. The Programmable Delay Generator pro- vides three 255-ns ranges of trigger delay in 1-ns incre- ments and a total programmed delay of 755 ns. The Pro- grammable Width Generator provides incremental pulse width generation over a range of 12 bits or 4096 to 1. Two interchangeable ICs allow increments of 5 or 50 ns, result- ing in maximum programmed pulse widths of 20 475 and 204 750 ns, respectively. The CGC can be built with stan- dard Vector Board and conventional soldering tech- niques. The entire circuit was powered by a modular dc power supply, which was in turn supplied by a EMURFI filtered ac/ac converter with transient protection. A grounded metal enclosure was used for additional noise protection.

    The PC is equipped with a frame grabber and with at least 14 channels of digital I/O. The frame grabber is op- erated as a slave to the CIDTEC control unit. The monitor

    946 Rev. Sci. Instrum. 64 (4), April 1993 0034.6746/93/040946-06$06.00 0 1993 American Institute of Physics 946 This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: Downloaded to IP: On: Thu, 27 Nov 2014 03:20:30



    PIG. 1. Imaging setup showing an example of how the camera and gate control circuit could be used.

    is used to view the captured image before storing on the PCs hard drive.

    The CGC is a modular design, containing three units: (1) programmable width generator and data latch, (2) programmable delay generator, (3) high-speed camera, la- ser, and frame grabber interface.

    Figure 2 shows a schematic corresponding to the three modules. An alternative design would place the width and delay generators together in unit 1 and the data latch alone in unit 2. The 14 lines of TTL level I/O from the PC consist of 12 data lines and two address lines. The control mode selector switches programming control between the hexadecimal switches (HW) and the PC. Figure 3 shows how this part is wired. The programmable width generator (Data Delay Devices, Clifton, NJ) requires a power-on- reset, which is provided by a momentary switch (manual reset) or by simultaneously addressing both devices with the PC. The circuit to do this is shown in Fig. 4. The hexadecimal DIP switches (AMP Incorporated, Harris- burg, PA) have screwdriver slots and are mounted on sep- arate boards to allow front-panel access. Wiring diagrams for these two small boards shown in Figs. S(a) and 5(b). The DIP switches are referred to as DSl, DS2, and for the 12-bit case, DS3, while DC14 is a 14-pin DIP ribbon wire connector. Thumbwheel switches could also be used here, provided they are hexadecimal coded.

    A low insertion delay was the primary design objective of the CGC. Noise immunity was also a key objective as

    PIG. 2. Schematic of the programmable width generator, data latch, programmable delay generator, camera control, and frame grabber and laser trigger. For use without a laser, the gate is self-triggered by con- necting the Laser and Trigger-In signals.

    TO PIN Q


    TO PIN 4 (PWG) AND PIN 43 (PDG) -I


    44 . r. 25 24 23 ---------------mm----- ----------------------

    1 e 3 4 B... 22

    FIG. 3. Wiring diagram for the control mode switch, a double-pole double-throw device. Pin numbers refer to the width generator/data latch card. Card sockets are numbered according to the sequence in the lower diagram. The card would plug in component-side up, so contacts(pins) 1 through 22 are on the bottom and 23 through 44 on the top.

    was the minimization of signal cross talk, especially in the camera control section. Large ground planes and oversized power and ground buses were designed into the circuits. Decoupling capacitors (0.1 pF) are used on the voltage supply line(s) of every IC, these are not shown in the accompanying diagrams. All resistance values are given in Ohms.


    The delay generator will now be described in more detail. As shown in Fig. 6, the Sync-In line (pin 28) is from a laser or from the Fire-Out line if no laser is used. Switch DS2 inserts 100-n termination resistors into the Sync-In line to match the source impedance. Termination resistances of TTL, 100, 50, 33, and 25 0 are thus avail- able, for zero, one, two, three, or four elements turned on., The Sync-In line triggers the delay generator through a retriggerable monostable multivibrator (Ul ) and OR gate


    / Ik t-h 101?~~~

    FIG. 4. Programmable width generator reset circuit diagram. A momen- tary contact switch shorts pins 1 and 5 to reset. The reset signal appears on pin 2, which is connected to pin 35 of the width generator/latch card. The two address bits enter via pins 6 and 7.

    947 Rev. Sci. Instrum., Vol. 64, No. 4, April 1993 Camera controller 947 This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: Downloaded to IP: On: Thu, 27 Nov 2014 03:20:30



    4 14 DATA BIT 1



    PINOUT 1 N/C 8 COMMON 2 N/c

    2 iis: 5 DATA BIT 8 3 DATA BIT 7 7 COMMON


    9 DATA BIT 6 10 DATA BIT5 11 DATA BIT 4 12 DATA BIT 3 13 DATA BIT 2 14 DATA BIT 1

    FIG. 5. Hexadecimal DIP switch units for hardware control of the gate width (a) and gate delay (b). Each hexadecimal digit corresponds to four programming bits. The commons are all connected to the control mode switch, shown in Fig. 3. These switches are most useful for quickly dialing in a particular operating condition.

    (U2). This is needed because the delay generator requires a trigger at least as long as the maximum programmable delay time, 255 ns in this case. Using the OR gate, the propagation delay of the relatively slow multivibrator does not add to the overall insertion delay, and about 20 ns is saved. The minimum duration for the Sync-In signal is 20 ns. The delay generator section is based on the Data Delay Devices PDU- 18F- 1 programmable delay generator (U4). This unit has eight bits of input to permit delays of 0 to 255 ns in increments of 1 ns and its output appears at pin 34.

    For longer total delays, a fixed delay unit (U3 ) can be activated to insert a 250~ns or a 500~ns delay in series with the delay provided by the delay generator. This unit, a DDU-7F-500 (Data Delay Devices) is activated by adjust- ing the setting of switch DSl. The settings are described

    FIG. 6. Wiring diagram of the programmable delay generator circuit card.

    948 Rev. Sci. Instrum., Vol. 84, No. 4, April 1993 Camera controller 948

    below in Table I. This simple design does not allow more than one element of DS 1 on at the same time without risking damage to the circuit. The power should therefore be turned off when adjusting this switch.

    The delay generator may be programmed manually with the pair of DIP switches [in Fig. 5(b)] or remotely by a PC and digital I/O board, as described later. The eight data lines, from the g-bit hex DIP switch and the width generator/data latch card, enter via pins 35 through 42, and pin 43 is connected tom the control mode switch as noted in Fig. 4.

    When controlled by the PC, the front panel mode switch must first be set to the PC position. Failure to do this may result in damage to the computers I/O board. To set a delay with the PC, the user inputs the desired delay, i.e., some integer number of nanoseconds from 0 to 755. For values above 255 ns the table below should be con- sulted to determine the correct setting for DSl. The soft- ware will convert this integer value to its binary equivalent and add 4096 to make bit number 13 high in order to address the delay unit. The final.value is written out and held for a minimum of 0.1 ms with asoftware delay loop to allow time for latching. The programmed delay value may be changed during operation, while writing an image to the hard disk for example.

    The camera control section, shown in Fig. 7, will now be described in more detail. The notation used here follows

    TABLE I. DSl settings for use of the fixed delay unit.

    Element of DSI ON

    1 2 3 4


    (Not Connected) 250-ns delay activated 500-m delay activated

    Disable FDU

    This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: htt...


View more >