Inexpensive highspeed intensified CID camera controllerJ. S. Shakal Citation: Review of Scientific Instruments 64, 946 (1993); doi: 10.1063/1.1144147 View online: http://dx.doi.org/10.1063/1.1144147 View Table of Contents: http://scitation.aip.org/content/aip/journal/rsi/64/4?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Using a High-Speed Camera to Measure the Speed of Sound Phys. Teach. 50, 45 (2012); 10.1119/1.3670086 Off the shelf inexpensive digital highspeed photography from CASIO Phys. Teach. 48, 559 (2010); 10.1119/1.3502522 The highspeed camera ULTRACAM AIP Conf. Proc. 848, 808 (2006); 10.1063/1.2348063 Highspeed infrared camera Rev. Sci. Instrum. 63, 3662 (1992); 10.1063/1.1143594 HighSpeed Framing Disk Camera Rev. Sci. Instrum. 29, 862 (1958); 10.1063/1.1716022

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lnexpensive high-speed intensified CID camera controller J. S. Shakala) Engine Research Center, Department of Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53 706

(Received 29 July 1992; accepted for publication 23 November 1992)

Image intensifiers are an essential part of many qualitative and quantitative imaging experiments. When temporal resolution is desired, continuous mode intensifiers such as first-generation intensifiers and ungated second-generation intensifiers are not suitable, and a gateable intensifier must be used. For laser fluorescence experiments, a controller providing synchronization on the order of nanoseconds between the microchannel plate of the intensifier and laser is usually needed. Such controllers are expensive and often designed for general purpose use, e.g., multichannel delay generators. However, by utilizing recently introduced integrated circuits, a low-cost, accurate, and versatile controller can be constructed. The device described in this article has an overall insertion delay of under 40 ns and jitter of under 3 ns. It can be controlled by front-panel switches or by a personal computer for automated operation. The device permits asynchronous triggering of a CID camera while leaving the camera-frame grabber timing cycle uninterrupted. Other uses are also suggested, and construction details are given.

1. INTRODUCTION

With the lower cost and increased performance of frame grabbers, pulsed lasers, solid-state cameras (CCD, CID, etc.), and gateable intensifiers, high-speed imaging experiments have become more popular. But to utilize the high-speed characteristics of these components, a way of synchronizing them is needed. In chemical kinetics studies, for example, an image of the fluorescing species is often desired. In this case the laser must be fired to excite the transition, followed by intensifier triggering (usually a fraction of a microsecond later) and then frame grabber triggering. For asynchronous applications, the camera also needs to be cleared, activated, and read out at the appro- priate time. A controller is thus needed to synchronize the laser, camera, intensifier, and frame grabber. The unit de- scribed in this article is designed to interface with an EOSI Model 91006 intensified CID camera (Electra-Optical Ser- vices Incorporated, Charlottesville, WV), an externally triggered frame grabber and a generic pulsed laser requir- ing “charge” and “fire” signals. The intensifier, a second- generation DEP Model XX145OCJ (Ziemer & Associates, Tempe, AZ) and CID camera (CID) Technologies Incor- porated, Liverpool, NY) could also be purchased sepa- rately and a custom system built.

The camera and gate controller (referred hereafter as CGC) described in this article could also be used for other purposes, such as (a) a stand-alone, computer-controlled, nanosecond level delay generator; (b) a stand-alone, computer-controlled high-speed pulse width modulator; (c) a stand-alone asynchronous CID camera and frame grabber controller. Design details will be discussed first, followed by operation characteristics, and then test results will be presented.

a)Permanent address: Internal Combustion Engine Laboratory, Univer- sity of Wisconsin-Madison, Madison, WI 53706.

II. CONTROLLER DESIGN

An ICID-based imaging system using the CGC de- scribed in this article is shown schematically in Fig. 1 and described briefly below. The ICID camera unit consists of a Model 3710 CIDTEC CID camera head coupled to an image intensifier and associated intensifier control electron- ics. The CIDTEC control unit provides the timing base for the camera and frame grabber, an ITEX VS-lOO-AT (Im- aging Technology Incorporated, Woburn, MA). It also multiplexes the video feed from the camera head into an RS-330 composite video signal, along with providing cer- tain timing wave forms to the frame grabber control cir- cuitry in the CGC. The EOSI gate drive box contains a high voltage dc power supply and switching element (op- tocoupler) for the intensifier gate.

The CGC contains a laser interface and frame grabber driver, a programmable delay generator, and a program- mable width generator. The laser interface contains a high- speed 50-Q driver and the frame grabber driver contains logic necessary to acquire an image from an asynchronous external trigger. The Programmable Delay Generator pro- vides three 255-ns ranges of trigger delay in 1-ns incre- ments and a total programmed delay of 755 ns. The Pro- grammable Width Generator provides incremental pulse width generation over a range of 12 bits or 4096 to 1. Two interchangeable ICs allow increments of 5 or 50 ns, result- ing in maximum programmed pulse widths of 20 475 and 204 750 ns, respectively. The CGC can be built with stan- dard “Vector Board” and conventional soldering tech- niques. The entire circuit was powered by a modular dc power supply, which was in turn supplied by a EMURFI filtered ac/ac converter with transient protection. A grounded metal enclosure was used for additional noise protection.

The PC is equipped with a frame grabber and with at least 14 channels of digital I/O. The frame grabber is op- erated as a slave to the CIDTEC control unit. The monitor

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- SHIELDED caky (BNC) CABLE - - - FLAT RIBRON DATA CAEtE - MlJLl l -CONDUCTOR CABLE

-----

PIG. 1. Imaging setup showing an example of how the camera and gate control circuit could be used.

is used to view the captured image before storing on the PC’s hard drive.

The CGC is a modular design, containing three units: (1) programmable width generator and data latch, (2) programmable delay generator, (3) high-speed camera, la- ser, and frame grabber interface.

Figure 2 shows a schematic corresponding to the three modules. An alternative design would place the width and delay generators together in unit 1 and the data latch alone in unit 2. The 14 lines of TTL level I/O from the PC consist of 12 data lines and two address lines. The control mode selector switches programming control between the hexadecimal switches (HW) and the PC. Figure 3 shows how this part is wired. The programmable width generator (Data Delay Devices, Clifton, NJ) requires a power-on- reset, which is provided by a momentary switch (manual reset) or by simultaneously addressing both devices with the PC. The circuit to do this is shown in Fig. 4. The hexadecimal DIP switches (AMP Incorporated, Harris- burg, PA) have screwdriver slots and are mounted on sep- arate boards to allow front-panel access. Wiring diagrams for these two small boards shown in Figs. S(a) and 5(b). The DIP switches are referred to as DSl, DS2, and for the 12-bit case, DS3, while DC14 is a 14-pin DIP ribbon wire connector. Thumbwheel switches could also be used here, provided they are hexadecimal coded.

A low insertion delay was the primary design objective of the CGC. Noise immunity was also a key objective as

PIG. 2. Schematic of the programmable width generator, data latch, programmable delay generator, camera control, and frame grabber and laser trigger. For use without a laser, the gate is self-triggered by con- necting the Laser and Trigger-In signals.

TO PIN Q

TO PIN 8 TO HEX DIP SWITCH COM TO PIN 3

TO PIN 4 (PWG) AND PIN 43 (PDG) -I

NOTE: CARD PLUGS INTO THIS SIDE OF SOCKET CONTACTS ARE NUMBERED AS SHOWN

44 . r. 25 24 23 ---------------mm----- ----------------------

1 e 3 4 B... 22

FIG. 3. Wiring diagram for the control mode switch, a double-pole double-throw device. Pin numbers refer to the width generator/data latch card. Card sockets are numbered according to the sequence in the lower diagram. The card would plug in component-side up, so contacts(pins) 1 through 22 are on the bottom and 23 through 44 on the top.

was the minimization of signal cross talk, especially in the camera control section. Large ground planes and oversized power and ground buses were designed into the circuits. Decoupling capacitors (0.1 pF) are used on the voltage supply line(s) of every IC, these are not shown in the accompanying diagrams. All resistance values are given in Ohms.

.

The delay generator will now be described in more detail. As shown in Fig. 6, the Sync-In line (pin 28) is from a laser or from the Fire-Out line if no laser is used. Switch DS2 inserts 100-n termination resistors into the Sync-In line to match the source impedance. Termination resistances of TTL, 100, 50, 33, and 25 0 are thus avail- able, for zero, one, two, three, or four elements turned on., The Sync-In line triggers the delay generator through a retriggerable monostable multivibrator (Ul ) and OR gate

MOLEX CONNECTOR

/ Ik t-h 101?~~“~

FIG. 4. Programmable width generator reset circuit diagram. A momen- tary contact switch shorts pins 1 and 5 to reset. The reset signal appears on pin 2, which is connected to pin 35 of the width generator/latch card. The two address bits enter via pins 6 and 7.

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12 BIT DIP SWITCH BgARD

PINOUT 1 DATA BIT 12 8 COMMON 2 DATA BIT 11 9 DATA BIT 6 3 DATA BIT 10 10 DATA BIT 5 4 DATA BIT 9 11 DATA BIT 4 6 DATA BIT 8 12 DATA BIT 3 8 DATA BIT 7 13 DATA BIT 2 7 COMMON

4 14 DATA BIT 1

.

8 BIT DIP SWITCH BOARD

PINOUT 1 N/C 8 COMMON 2 N/c

2 iis: 5 DATA BIT 8 3 DATA BIT 7 7 COMMON

b)

9 DATA BIT 6 10 DATA BIT5 11 DATA BIT 4 12 DATA BIT 3 13 DATA BIT 2 14 DATA BIT 1

FIG. 5. Hexadecimal DIP switch units for hardware control of the gate width (a) and gate delay (b). Each hexadecimal digit corresponds to four programming bits. The commons are all connected to the control mode switch, shown in Fig. 3. These switches are most useful for quickly “dialing in” a particular operating condition.

(U2). This is needed because the delay generator requires a trigger at least as long as the maximum programmable delay time, 255 ns in this case. Using the OR gate, the propagation delay of the relatively slow multivibrator does not add to the overall insertion delay, and about 20 ns is saved. The minimum duration for the Sync-In signal is 20 ns. The delay generator section is based on the Data Delay Devices PDU- 18F- 1 programmable delay generator (U4). This unit has eight bits of input to permit delays of 0 to 255 ns in increments of 1 ns and its output appears at pin 34.

For longer total delays, a fixed delay unit (U3 ) can be activated to insert a 250~ns or a 500~ns delay in series with the delay provided by the delay generator. This unit, a DDU-7F-500 (Data Delay Devices) is activated by adjust- ing the setting of switch DSl. The settings are described

FIG. 6. Wiring diagram of the programmable delay generator circuit card.

948 Rev. Sci. Instrum., Vol. 84, No. 4, April 1993 Camera controller 948

below in Table I. This simple design does not allow more than one element of DS 1 “on” at the same time without risking damage to the circuit. The power should therefore be turned off when adjusting this switch.

The delay generator may be programmed manually with the pair of DIP switches [in Fig. 5(b)] or remotely by a PC and digital I/O board, as described later. The eight data lines, from the g-bit hex DIP switch and the width generator/data latch card, enter via pins 35 through 42, and pin 43 is connected tom the control mode switch as noted in Fig. 4.

When controlled by the PC, the front panel mode switch must first be set to the “PC” position. Failure to do this may result in damage to the computer’s I/O board. To set a delay with the PC, the user inputs the desired delay, i.e., some integer number of nanoseconds from 0 to 755. For values above 255 ns the table below should be con- sulted to determine the correct setting for DSl. The soft- ware will convert this integer value to its binary equivalent and add 4096 to make bit number 13 high in order to address the delay unit. The final.value is written out and held for a minimum of 0.1 ms with a’software delay loop to allow time for latching. The programmed delay value may be changed during operation, while writing an image to the hard disk for example.

The camera control section, shown in Fig. 7, will now be described in more detail. The notation used here follows

TABLE I. DSl settings for use of the fixed delay unit.

Element of DSI “ON”

1 2 3 4

Result

(Not Connected) 250-ns delay activated 500-m delay activated

Disable FDU

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FIG. 7. Wiring diagram of the camera/frame grabber/laser interface circuit card.

that of the CIDTEC User’s Manual.’ An overbar or [ ] indicates the logical inverse, i.e., active low. The camera control circuit has two basic functions: One is to clear the imager by issuing a “dump,” and the second is to suspend readout, i.e., “inject inhibit,” until the even field will be read out next. To generate the dump signal, U5 latches the asynchronous external trigger (the “Fire” input, at pin 14) with the horizontal drive (HD) signal to generate the dump signal. [HD], which enters via pin 16 is inverted by Ul. Figure 8 shows the relative positions and durations of these waveforms. Note the difference in scale between the top three and the lower five waveforms. The circuit triggers off the rising edge of the external trigger, which needs to be at least 5 ns in duration. This duration is short enough to make the circuit sensitive to noise, especially that due to solenoid activity and pulsed laser operation. When [dump] goes high, at point B in Fig. 8, the laser is fired and simul-

FIG. 8. CID camera, laser trigger (Fine-Out), and external trigger wave forms showing the timing relationships.

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TABLE II. Jumper Jo settings for selecting the frame grabber trigger waveform.

Jumper selected

1 2 3 4

Frame grabber trigger wave form

Inject Inhibit Strobe

Strobe-Active Low Inject Inhibit-Active Low

taneously, [Inject Inhibit] is activated. U2 simply ORs the charge input, entering via pin 12, with the output of flip- flops U5 and U6. The high-speed laser driver section uses the Am9614 dual differential 50-a line driver from Ad- vanced Micro Devices. The laser Fire-Out signal exits via pin 6. The laser trigger is shown as three progressively longer intervals in Fig. 8 corresponding to jumper Jl po- sitions 1, 2, and 3, respectively. There is an uncertainty or “latency” of up to one line time, i.e., one cycle of HD, in the dump signal. Therefore the time between laser charge and laser fire will vary by up to 63.5 ps from shot to shot. The shaded region of [Inject Inhibit] represents intervals where the state of this signal is immaterial, i.e., it could be low or high. The top of Fig. 8 shows relevant events sur- rounding the rising edge of [Inject Inhibit], which is simul- taneous with frame grabber triggering. Most frame grab- bers require the even field followed by the odd field when they are triggered, because neither the RS-170 nor the RS- 330 composite video formats contain information about what field is present. The field identifier (FID) line, which enters via pin 20, is high when the even field is being read out and during the following vertical blanking interval. The FID is inverted by Ul and NANDed with the end of field (EOF) signal, which enters via pin 21. The resulting signal serves as a clock for U7, which triggers the frame grabber. The E and 0 beneath the FID waveform in Fig. 8 indicate when even and odd fields are read out, respec- tively. At point -4, EOF goes high, which brings [Inject Inhibit] high and triggers the frame grabber. A variety of waveforms is available at the “FG Trigger” output con- nector depending on the position of JO. These are summa- rized above in Table II. For frame grabbers with no hard- ware trigger, an input channel on an I/O card is easily used for generating a software trigger.

The programmable width generator contains two ma- jor components: ( 1) 20-bit edge triggered latch and (2) la-bit programmable pulse width generator. The edge trig- gered data latch is addressable by the PC to program either the delay generator or the width generator. As shown in Fig. 9, the lower 8 bits enter via pins 33 through 40, and lead to pins 10 through 18 of both Ul and U2, respectively. The high 4 bits enter via pins 41 through 44 and lead to pins I1 through I4 of U3. The resistor network “common” exits via pin 4 and is connected to the control mode switch (Fig. 3). The address lines A0 and A 1 enter via pins 3 1 and 32. (The reset circuit also uses these two lines.) When the delay generator is addressed, for example, by setting A0 (bit 13) high, eight bits on the data line are clocked through to the programmable delay generator. The format

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FIG. 9. Wiring diagram of the programmable width generator/data latch circuit card. For clarity, the remaining I/O lines are shown in the next figure.

of the control word would be (bits numbered 14 to 1, left to right):

01XXXXD8D7D6D5D4D3D2D1 -- - - -- -- -- -- -- -- -- -- --3 where X indicates “do not care” and 01-08 indicates the data bits from least significant to most significant. These data bits exit via pins 23 through 30 to the delay generator card. The width generator is programmed in an analogous manner using Al (bit 14), except 12 bits of data are clocked through instead of eight. In this case the control word would be

lOD12DllD1OD9D8D7D6DSD4D3D2D1 -- --- --- --- -- -- -- -- -- -- -- -- --f where now there are 12 data bits instead of 8. The state of the eight data lines at the delay generator and width gen- erator do not change again until another clock pulse is placed on the appropriate address line.

The output gate width to is a simple function of the programmed value and is therefore easily set by a com- puter program. Specifically:

to=tp+tr, (1)

where tp is the programmed value and tl is an inherent pulse width, which was found to be 25.9 ns for the S-ns pulse generator and 29.8 ns for the SO-ns pulse generator.

The programmable width generator uses the PPG- 3 12F-5 or PPG-312F-50, or any PPG-312F series, (Data Delay Devices) 12-bit FAST logic pulse generators. This IC, U4 in Figs. 9 and 10, is mounted in a zero insertion force socket, which makes interchanging this IC very easy. U4 is triggered via pin 6 by the delay generator and reset on powering up via pin 2 and the reset circuit. Latch out- puts 01-08 on U2 and 01-04 on U3 are connected to data inputs 01-012 on U4. The resistor networks supply pull-down resistors for the 12 data lines when operated in the HW mode. Their commons are connected to the con- trol mode switch via pin 4. The remaining I/O.lines are

950 Rev. Sci. Instrum., Vol. 64, No. 4, April 1993

FIG. 10. Wiring diagram of the programmable width generator/data latch-circuit card. The Z/O lines shown here were not shown in the previous figure.

shown in Fig. 10. The output signal exits via pin 5, and the delay and width LED indicators shown in Fig. 4 connect via pins 8 and 9. These indicate when the PC is actually programming the delay and width generators. U5 and U6 provide a clock signal for the latches. The output of Ul exits via pins 23 through 30 to the delay generator card. The 12 data lines, data bit 1 through data bit 12, from the DIP switch card are connected via pins 21-10.

III. TEST RESULTS

Tests were-run at 20 Hz to determine the overall sys- tem insertion delay, from the rising edge of the Sync-In signal to the falling edge of Gate-Out. The delay generator was set to 0, and the pulse width was set to 25 ns for the 5-ns unit and 0 for the 50-ns unit. 256 consecutive cycles were digitized and averaged on a Tektronix 2430A oscil- loscope and stored on a Tektronix 2402A, and cable effects were accounted for. A Hewlett-Packard 3314A digital function generator provided the Sync-In signal. The delay was defined as the interval between the point at which the Sync-In line reached 2 V and the first half-max of the Gate-Out line. The 5-ns unit produced a 39-ns overall de- lay, and the 25-ns unit produced a 3%ns overall delay. This means, for example, if we neglect additional cable and in- tensifier turn-on delays, that the system could capture an intensified image as near as 38 ns after a laser begins lasing (depending on how its sync-out is generated).

Also of importance is the jitter of the system output, especially when gating an intensifier close to firing a laser. If the intensifier were gated on at the wrong time, not only could the intensifier be burned out, the CID imager could also be destroyed. The system was set up with the same function generator as above, but a Tektronix 2465 300- MHz oscilloscope with the model 09 counter/timer/trigger option was used. Both the 5-ns and the 50-ns programma- ble width generators were set to 50 ns. The programmable

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delay generator was set to 0 and the fixed delay unit was set to 250 ns. The oscilloscope was triggered at 2.00 V on the Sync-In line (A trigger), the same as the low-to-high threshold of FAST logic used in the circuit. Averages (of 100 events) of the interval between the A trigger and the 2.00-V point of the Gate-Out signal (B trigger) were mea- sured and computed by the oscilloscope. These averages varied by no more than 2 ns over 1000 events for both width generators. The inherent jitter in the oscilloscope was estimated to be less than 100 ps. Tests were then re- peated with the programmable delay generator set to 0 and the fixed delay unit disabled. The results were identical; a variation of 2 ns was observed in the averages. The oscil- loscope cursors were then used at 5 ns/div (in a “live”

951 Rev. Sci. Instrum., Vol. 64, No. 4, April 1993

display mode) to measure the same A and B interval in order to verify the above observations. Over a period of 2400 events, the B trigger point did not vary by more than 2.0 ns for both width generators.

ACKNOWLEDGMENTS

The advice provided by Mr. Fred Moore is deeply ap- preciated. Acknowledgment is made to the Army Research Office through the designation of the University of Wisconsin-Madison as the Center of Excellence for Ad- vanced Propulsion Systems.

‘CID Technologies, Solid State CID Camera Users Manual-Models 3710D/E, Rev. B, (unpublished).

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