Infineon XC164-16 User's Manual (Peripheral Units) · User’s Manual, V2.1, March 2004 Microcontrollers Never stop thinking. XC164-16 16-Bit Single-Chip Microcontroller with C166SV2

User ’s Manual, V2.1, March 2004

Microcontrol lers

N e v e r s t o p t h i n k i n g .

XC164-1616-Bit Single-Chip Microcontrol ler wi th C166SV2 Core

Volume 2 (of 2) : Per ipheral Uni ts

Edition 2004-03

Published by Infineon Technologies AG,St.-Martin-Strasse 53,81669 München, Germany

© Infineon Technologies AG 2004.All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

User ’s Manual, V2.1, March 2004

Microcontrol lers

N e v e r s t o p t h i n k i n g .

XC164-1616-Bit Single-Chip Microcontrol ler wi th C166SV2 Core

Volume 2 (of 2) : Per ipheral Uni ts

Template: mc_tmplt_a5.fm / 3 / 2003-09-01

Controller Area Network (CAN): License of Robert Bosch GmbH

XC164 Volume 2 (of 2): Peripheral Units Revision History: V2.1, 2004-03

Previous Version: V2.0, 2003-12 (Pre-Release)V1.1, 2002-02 (Draft Manual)V1.0, 2001-04 (Draft Manual)

Page Subjects (major changes since last revision)

all The layout of several graphics and text structures has been adapted to company documentation rules, obvious typographical errors have been corrected.

16-17 ADC reset calibration note added

19-17 IrDA pulse width table corrected

We Listen to Your CommentsAny information within this document that you feel is wrong, unclear or missing at all?Your feedback will help us to continuously improve the quality of this document.Please send your proposal (including a reference to this document) to:[email protected]

XC164-16 DerivativesPeripheral Units (Vol. 2 of 2)

Table of Contents Page

This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. Foryour convenience this table of contents (and also the keyword index) lists both volumes,so you can immediately find the reference to the desired section in the correspondingdocument ([1] or [2]).

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]1.1 Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1]1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1]1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1]1.4 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1]

2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]2.1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1]2.1.1 High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . 2-4 [1]2.1.2 Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1]2.1.3 High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1]2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1]2.1.5 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1]2.1.6 Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1]2.2 On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1]2.3 On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 [1]2.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]2.5 Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]2.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1]2.7 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]

3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]3.1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]3.3 Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1]3.4 Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]3.5 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1]3.6 IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1]3.7 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1]3.8 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1]3.9 The On-Chip Program Flash Module . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1]3.9.1 Flash Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]3.9.2 Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1]3.9.3 Error Correction and Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . 3-25 [1]3.9.4 Protection and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 [1]3.9.5 Flash Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 [1]3.9.6 Operation Control and Error Handling . . . . . . . . . . . . . . . . . . . . . . 3-35 [1]

User’s Manual I-1 V2.1, 2004-03



3.10 The On-Chip Program Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1]3.10.1 Protection and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1]3.10.2 Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 [1]3.11 Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 [1]3.11.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1]3.11.2 Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 [1]3.11.3 User ROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 [1]3.11.4 IMB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 [1]

4 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]4.1 Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1]4.2 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1]4.2.1 Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1]4.2.2 Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]4.2.3 Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1]4.3 Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]4.3.1 Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1]4.3.2 Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1]4.3.3 Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1]4.3.4 Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1]4.4 CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1]4.5 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1]4.5.1 GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1]4.5.2 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1]4.6 Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1]4.7 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]4.7.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]4.7.2 Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1]4.7.3 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1]4.7.4 DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1]4.7.5 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1]4.8 Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1]4.8.1 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . 4-61 [1]4.8.2 Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1]4.8.3 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1]4.9 DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1]4.9.1 Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . 4-66 [1]4.9.2 The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . 4-67 [1]4.9.3 Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]4.9.4 One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]4.9.5 The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]4.9.6 The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]4.9.7 The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]




4.9.8 The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . 4-69 [1]4.9.9 The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1]4.9.10 The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1]4.10 Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 [1]

5 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]5.1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]5.2 Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1]5.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1]5.4 Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-18 [1]5.4.1 The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-22 [1]5.4.2 PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 [1]5.4.3 Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-26 [1]5.4.4 PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 [1]5.5 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-29 [1]5.6 Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-31 [1]5.7 Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 [1]5.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]5.9 OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 [1]5.10 Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1]5.11 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 [1]

6 General System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1]6.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]6.1.1 Reset Sources and Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]6.1.2 Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]6.1.3 Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . 6-11 [1]6.1.4 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 [1]6.1.5 Hardware Configuration in External Start Mode . . . . . . . . . . . . . . 6-18 [1]6.1.6 Default Configuration in Single-Chip Mode . . . . . . . . . . . . . . . . . . 6-23 [1]6.1.7 Reset Behavior Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1]6.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 [1]6.2.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1]6.2.2 Clock Generation and Frequency Control . . . . . . . . . . . . . . . . . . . 6-29 [1]6.2.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 [1]6.2.4 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1]6.2.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1]6.2.6 Generation of an External Clock Signal . . . . . . . . . . . . . . . . . . . . 6-38 [1]6.3 Central System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 [1]6.3.1 Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 [1]6.3.2 Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 [1]6.3.3 Peripheral Shutdown Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 [1]6.3.4 Debug System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1]




6.3.5 Register Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 [1]6.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 [1]6.4.1 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 [1]6.4.2 Reduction of Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 [1]6.4.3 Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 [1]6.5 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 [1]6.6 Identification Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 [1]

7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]7.1 Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]7.2 Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1]7.3 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1]7.4 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]7.5 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1]7.6 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 [1]7.7 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 [1]7.8 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 [1]7.9 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1]7.10 Port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60 [1]

8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]

9 The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]9.1 External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1]9.2 Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]9.2.1 Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]9.2.1.1 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1]9.2.1.2 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]9.2.2 Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]9.2.2.1 A Phase - CS Change Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]9.2.2.2 B Phase - Address Setup/ALE Phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1]9.2.2.3 C Phase - Delay Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]9.2.2.4 D Phase - Write Data Setup/MUX Tristate Phase . . . . . . . . . . . . 9-7 [1]9.2.2.5 E Phase - RD/WR Command Phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]9.2.2.6 F Phase - Address/Write Data Hold Phase . . . . . . . . . . . . . . . . . 9-8 [1]9.2.3 Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-8 [1]9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]9.3.1 Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]9.3.2 The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1]9.3.3 The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1]9.3.4 The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-15 [1]9.3.5 The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-16 [1]9.3.6 The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-18 [1]9.3.6.1 Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1]




9.3.6.2 Address Window Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1]9.3.7 Access Control to TwinCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1]9.3.8 Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 [1]9.4 LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . 9-23 [1]9.5 EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 [1]

10 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]10.1 Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]10.2 Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]10.3 Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]10.4 Choosing the Baudrate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]

11 Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]11.2 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1]11.3 OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 [1]11.3.1 Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 [1]11.3.2 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 [1]11.4 Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]11.4.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]11.5 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 [1]

12 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]

13 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]

14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2]14.1 Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 [2]14.1.1 GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 [2]14.1.2 GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . . 14-8 [2]14.1.3 GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . . 14-15 [2]14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . . 14-18 [2]14.1.5 GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [2]14.1.6 GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 [2]14.1.7 Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . 14-30 [2]14.2 Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 [2]14.2.1 GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 [2]14.2.2 GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . . 14-37 [2]14.2.3 GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . . 14-40 [2]14.2.4 GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . . 14-42 [2]14.2.5 GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . . 14-46 [2]14.2.6 GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51 [2]14.2.7 GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54 [2]14.2.8 Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . 14-55 [2]




14.3 Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-56 [2]

15 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2]15.1 Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2]15.2 RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2]15.3 RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2]15.3.1 48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]15.3.2 System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]15.3.3 Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2]15.4 RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2]

16 The Analog/Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]16.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]16.1.1 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]16.1.2 Enhanced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2]16.2 ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [2]16.2.1 Fixed Channel Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2]16.2.2 Auto Scan Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 [2]16.2.3 Wait for Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [2]16.2.4 Channel Injection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [2]16.3 Automatic Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 [2]16.4 Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [2]16.5 A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 [2]16.6 Interfaces of the ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [2]

17 Capture/Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2]17.1 The CAPCOM Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2]17.2 CAPCOM Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [2]17.3 Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2]17.4 Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [2]17.5 Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2]17.5.1 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]17.5.2 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]17.5.3 Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]17.5.4 Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]17.5.5 Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-22 [2]17.6 Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 17-25 [2]17.7 Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2]17.8 Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . 17-29 [2]17.9 CAPCOM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 [2]17.10 External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2]17.11 Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 [2]

18 Capture/Compare Unit 6 (CAPCOM6) . . . . . . . . . . . . . . . . . . . . . . 18-1 [2]




18.1 Timer T12 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 [2]18.1.1 Timer T12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [2]18.1.2 T12 Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2]18.1.3 Dead-Time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 [2]18.1.4 T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 [2]18.1.5 Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 [2]18.2 Timer T13 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 [2]18.2.1 T13 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32 [2]18.2.2 T13 Compare Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 [2]18.3 Timer Block Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 [2]18.4 Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 [2]18.5 Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50 [2]18.5.1 Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 [2]18.5.2 Sampling of the Hall Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-52 [2]18.5.3 Brushless DC-Motor Control with Timer T12 Block . . . . . . . . . . . 18-53 [2]18.5.4 Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55 [2]18.6 Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 [2]18.7 Output Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-65 [2]18.8 Shadow Register Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . 18-69 [2]18.9 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71 [2]18.10 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80 [2]18.11 Interfaces of the CAPCOM6 Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-81 [2]

19 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . 19-1 [2]19.1 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2]19.2 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 [2]19.2.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [2]19.2.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2]19.2.3 Transmit FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 [2]19.2.4 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]19.2.5 Receive FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]19.2.6 FIFO Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 [2]19.2.7 IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [2]19.2.8 RxD/TxD Data Path Selection in Asynchronous Modes . . . . . . . 19-17 [2]19.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 [2]19.3.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 [2]19.3.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 [2]19.3.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 [2]19.4 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 [2]19.4.1 Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 [2]19.4.2 Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 [2]19.5 Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 [2]19.5.1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 [2]




19.5.2 Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . 19-28 [2]19.5.3 Baudrate Selection and Calculation . . . . . . . . . . . . . . . . . . . . . . . 19-29 [2]19.5.4 Overwriting Registers on Successful Autobaud Detection . . . . . 19-33 [2]19.6 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 19-34 [2]19.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35 [2]19.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 [2]19.9 Interfaces of the ASC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-56 [2]

20 High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . 20-1 [2]20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]20.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]20.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 [2]20.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 [2]20.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 [2]20.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]20.2.5 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]20.2.6 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2]20.2.7 SSC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 [2]20.2.8 Port Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . 20-17 [2]20.3 Interfaces of the SSC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 [2]

21 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]21.1 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]21.1.2 TwinCAN Control Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]21.1.2.1 Initialization Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]21.1.2.2 Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2]21.1.2.3 Global Control and Status Logic . . . . . . . . . . . . . . . . . . . . . . . . 21-6 [2]21.1.3 CAN Node Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]21.1.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]21.1.3.2 Timing Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 [2]21.1.3.3 Bitstream Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]21.1.3.4 Error Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]21.1.3.5 Node Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2]21.1.3.6 Message Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]21.1.3.7 Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]21.1.4 Message Handling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [2]21.1.4.1 Arbitration and Acceptance Mask Register . . . . . . . . . . . . . . . 21-16 [2]21.1.4.2 Handling of Remote and Data Frames . . . . . . . . . . . . . . . . . . 21-17 [2]21.1.4.3 Handling of Transmit Message Objects . . . . . . . . . . . . . . . . . . 21-18 [2]21.1.4.4 Handling of Receive Message Objects . . . . . . . . . . . . . . . . . . 21-21 [2]21.1.4.5 Single Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 [2]21.1.5 CAN Message Object Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . 21-24 [2]




21.1.5.1 Buffer Access by the CAN Controller . . . . . . . . . . . . . . . . . . . 21-26 [2]21.1.5.2 Buffer Access by the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 [2]21.1.6 Gateway Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 [2]21.1.6.1 Normal Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 [2]21.1.6.2 Normal Gateway with FIFO Buffering . . . . . . . . . . . . . . . . . . . 21-33 [2]21.1.6.3 Shared Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 [2]21.1.7 Programming the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]21.1.7.1 Configuration of CAN Node A/B . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]21.1.7.2 Initialization of Message Objects . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]21.1.7.3 Controlling a Message Transfer . . . . . . . . . . . . . . . . . . . . . . . 21-41 [2]21.1.8 Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 [2]21.1.9 Single Transmission Try Functionality . . . . . . . . . . . . . . . . . . . . 21-45 [2]21.1.10 Module Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 [2]21.2 TwinCAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]21.2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]21.2.2 CAN Node A/B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 [2]21.2.3 CAN Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21-64 [2]21.2.4 Global CAN Control/Status Registers . . . . . . . . . . . . . . . . . . . . . 21-80 [2]21.3 XC164 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]21.3.1 Interfaces of the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]21.3.2 TwinCAN Module Related External Registers . . . . . . . . . . . . . . . 21-83 [2]21.3.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-84 [2]21.3.2.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-85 [2]21.3.2.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-89 [2]21.3.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-90 [2]

22 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]22.1 PD+BUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]22.2 LXBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2]

Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 [1+2]



The General Purpose Timer Units

14 The General Purpose Timer UnitsThe General Purpose Timer Unit blocks GPT1 and GPT2 have very flexiblemultifunctional timer structures which may be used for timing, event counting, pulsewidth measurement, pulse generation, frequency multiplication, and other purposes.They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 andGPT2. Each timer in each block may operate independently in a number of differentmodes such as gated timer or counter mode, or may be concatenated with another timerof the same block. Each block has alternate input/output functions and specific interruptsassociated with it.

Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliarytimers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 mayoptionally be configured as reload or capture registers for the core timer. These registersare listed in Section 14.1.6.

• fGPT/4 maximum resolution• 3 independent timers/counters• Timers/counters can be concatenated• 4 operating modes:

– Timer Mode– Gated Timer Mode– Counter Mode– Incremental Interface Mode

• Reload and Capture functionality• Separate interrupt lines

Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5.The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL)supports capture and reload operation with extended functionality. These registers arelisted in Section 14.2.7. The core timer T6 may be concatenated with timers of theCAPCOM units (T0, T1, T7, and T8).

The following list summarizes the features which are supported:

• fGPT/2 maximum resolution• 2 independent timers/counters• Timers/counters can be concatenated• 3 operating modes:

– Timer Mode– Gated Timer Mode– Counter Mode

• Extended capture/reload functions via 16-bit capture/reload register CAPREL• Separate interrupt lines

User’s Manual 14-1 V2.1, 2004-03GPT_X41, V2.0



14.1 Timer Block GPT1

From a programmer’s point of view, the GPT1 block is composed of a set of SFRs assummarized below. Those portions of port and direction registers which are used foralternate functions by the GPT1 block are shaded.

Figure 14-1 SFRs Associated with Timer Block GPT1

All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode,Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can countup or down. Each timer of GPT1 is controlled by a separate control register TxCON.

Each timer has an input pin TxIN (alternate pin function) associated with it, which servesas the gate control in gated timer mode, or as the count input in counter mode. The countdirection (up/down) may be programmed via software or may be dynamically altered bya signal at the External Up/Down control input TxEUD (alternate pin function). Anoverflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL,whose state may be output on the associated pin T3OUT (alternate pin function). Theauxiliary timers T2 and T4 may additionally be concatenated with the core timer T3(through T3OTL) or may be used as capture or reload registers for the core timer T3.

The current contents of each timer can be read or modified by the CPU by accessing thecorresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFRspace (see Section 14.1.6). When any of the timer registers is written to by the CPU inthe state immediately preceding a timer increment, decrement, reload, or captureoperation, the CPU write operation has priority in order to guarantee correct results.

m c_gp t0100_reg is te rs .vsd

D ata R eg is te rs C ontro l R eg is ters P ort R eg is ters

T2 T2CON T2IC

T3 T3CON T3IC

T4 T4CON T4IC

ODP3

DP3

P3

E

P5

P5DIDIS

ALTSEL0P3 E

Inte rrup t C ontro l

SYSCON3

Tx G P T1 T im er x R eg is terTxC O N G P T1 T im er x C ontro l R eg is terTx IC G P T1 T im er x In terrup t C trl. R eg.S Y S C O N 3 S ystem C trl. R eg. 3 (P er. M gm t.)

O D P 3 P ort 3 O pen D ra in C ontro l R eg is terD P 3 P ort 3 D irec tion C ontro l R eg is terP 3 P ort 3 D ata R eg is terA LTS E L0P 3 P ort 3 A lte rna te O utput S e lec t R eg.P 5 P ort 5 D ata R eg is terP 5D ID IS P ort 5 D ig ita l Input D isab le R eg.




The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC.These registers are not part of the GPT1 block. The input and output lines of GPT1 areconnected to pins of ports P3 and P5. The control registers for the port functions arelocated in the respective port modules.

Note: The timing requirements for external input signals can be found in Section 14.1.5,Section 14.3 summarizes the module interface signals, including pins.

Figure 14-2 GPT1 Block Diagram (n = 2 … 5)

T3Mode

Control

2n: 1fGPT

T2Mode

Control

Aux. Timer T2

ReloadCapture

T4Mode

Control Aux. Timer T4

Reload

Capture

Core Timer T3 T3OTL

U/D

T2EUD

T2IN

T3IN

T3EUD

T4IN

T4EUD

Toggle Latch

U/D

U/D

InterruptRequest(T2IRQ)



mc_gpt0101_bldiax1.vsd

T3OUT

Basic clock

T3CON.BPS1




14.1.1 GPT1 Core Timer T3 Control

The current contents of the core timer T3 are reflected by its count register T3. Thisregister can also be written to by the CPU, for example, to set the initial start value.

The core timer T3 is configured and controlled via its bitaddressable control registerT3CON.

GPT12E_T3CON Timer 3 Control Register SFR (FF42H/A1H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T3R

DIR

T3CHDIR

T3EDGE

BPS1T3

OTLT3OE

T3UDE

T3UD

T3R T3M T3I

rh rwh rwh rw rwh rw rw rw rw rw rw

Field Bits Type Description

T3RDIR 15 rh Timer T3 Rotation Direction Flag0 Timer T3 counts up1 Timer T3 counts down

T3CHDIR 14 rwh Timer T3 Count Direction Change FlagThis bit is set each time the count direction of timer T3 changes. T3CHDIR must be cleared by SW.0 No change of count direction was detected1 A change of count direction was detected

T3EDGE 13 rwh Timer T3 Edge Detection FlagThe bit is set each time a count edge is detected. T3EDGE must be cleared by SW.0 No count edge was detected1 A count edge was detected

BPS1 [12:11] rw GPT1 Block Prescaler ControlSelects the basic clock for block GPT1(see also Section 14.1.5)00 fGPT/801 fGPT/410 fGPT/3211 fGPT/16

T3OTL 10 rwh Timer T3 Overflow Toggle LatchToggles on each overflow/underflow of T3. Can be set or reset by software (see separate description)




T3OE 9 rw Overflow/Underflow Output Enable0 Alternate Output Function Disabled1 State of T3 toggle latch is output on pin T3OUT

T3UDE 8 rw Timer T3 External Up/Down Enable1)

0 Input T3EUD is disconnected1 Direction influenced by input T3EUD

T3UD 7 rw Timer T3 Up/Down Control1)

0 Timer T3 counts up1 Timer T3 counts down

T3R 6 rw Timer T3 Run Bit0 Timer T3 stops1 Timer T3 runs

T3M [5:3] rw Timer T3 Mode Control (Basic Operating Mode)000 Timer Mode001 Counter Mode010 Gated Timer Mode with gate active low011 Gated Timer Mode with gate active high100 Reserved. Do not use this combination.101 Reserved. Do not use this combination.110 Incremental Interface Mode

(Rotation Detection Mode)111 Incremental Interface Mode

(Edge Detection Mode)

T3I [2:0] rw Timer T3 Input Parameter SelectionDepends on the operating mode, see respective sections for encoding:Table 14-7 for Timer Mode and Gated Timer ModeTable 14-2 for Counter ModeTable 14-3 for Incremental Interface Mode

1) See Table 14-1 for encoding of bits T3UD and T3UDE.





Timer T3 Run Control

The core timer T3 can be started or stopped by software through bit T3R (Timer T3 RunBit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer,clearing bit T3R stops the timer.

In gated timer mode, the timer will only run if T3R = 1 and the gate is active (high or low,as programmed).

Note: When bit T2RC or T4RC in timer control register T2CON or T4CON is set, bit T3Rwill also control (start and stop) the auxiliary timer(s) T2 and/or T4.

Count Direction Control

The count direction of the GPT1 timers (core timer and auxiliary timers) can be controlledeither by software or by the external input pin TxEUD (Timer Tx External Up/DownControl Input). These options are selected by bits TxUD and TxUDE in the respectivecontrol register TxCON. When the up/down control is provided by software (bitTxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bitTxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction.However, bit TxUD can still be used to reverse the actual count direction, as shown inTable 14-1. The count direction can be changed regardless of whether or not the timeris running.

Note: When pin TxEUD is used as external count direction control input, it must beconfigured as input (its corresponding direction control bit must be cleared).

Table 14-1 GPT1 Timer Count Direction Control

Pin TxEUD Bit TxUDE Bit TxUD Count Direction Bit TxRDIR

X 0 0 Count Up 0

X 0 1 Count Down 1

0 1 0 Count Up 0

1 1 0 Count Down 1

0 1 1 Count Down 1

1 1 1 Count Up 0




Timer 3 Output Toggle Latch

The overflow/underflow signal of timer T3 is connected to a block named ‘Toggle Latch’,shown in the timer mode diagrams. Figure 14-3 illustrates the details of this block. Anoverflow or underflow of T3 will clock two latches: The first latch represents bit T3OTL incontrol register T3CON. The second latch is an internal latch toggled by T3OTL’s output.Both latch outputs are connected to the input control blocks of the auxiliary timers T2 andT4. The output level of the shadow latch will match the output level of T3OTL, but isdelayed by one clock cycle. When the T3OTL value changes, this will result in atemporarily different output level from T3OTL and the shadow latch, which can triggerthe selected count event in T2 and/or T4.

When software writes to T3OTL, both latches are set or cleared simultaneously. In thiscase, both signals to the auxiliary timers carry the same level and no edge will bedetected. Bit T3OE (overflow/underflow output enable) in register T3CON enables thestate of T3OTL to be monitored via an external pin T3OUT. When T3OTL is linked to anexternal port pin (must be configured as output), T3OUT can be used to control externalHW. If T3OE = 1, pin T3OUT outputs the state of T3OTL. If T3OE = 0, pin T3OUToutputs a high level (as long as the T3OUT alternate function is selected for the port pin).

The trigger signals can serve as an input for the counter function or as a trigger sourcefor the reload function of the auxiliary timers T2 and T4.

As can be seen from Figure 14-3, when latch T3OTL is modified by software todetermine the state of the output line, also the internal shadow latch is set or clearedaccordingly. Therefore, no trigger condition is detected by T2/T4 in this case.

Figure 14-3 Block Diagram of the Toggle Latch Logic of Core Timer T3

m c_gpt0106_otl.vsd

Togg le La tch Log ic

TxO U T

S et/C lear (S W )

C ore T im er

O verflow /U nderflow Shadow

Latch

1

0

MU

X

1

TxO E

TxOTLTo P ort Log ic

To A ux. T im erInput Log ic




14.1.2 GPT1 Core Timer T3 Operating Modes

Timer 3 in Timer Mode

Timer mode for the core timer T3 is selected by setting bitfield T3M in register T3CONto 000B. In timer mode, T3 is clocked with the module’s input clock fGPT divided by twoprogrammable prescalers controlled by bitfields BPS1 and T3I in register T3CON.Please see Section 14.1.5 for details on the input clock options.

Figure 14-4 Block Diagram of Core Timer T3 in Timer Mode

Prescaler Core Timer T3 Toggle Latch

MCB05391

BPS1 T3I

MUX Up/Down0

1

T3EUD

fGPT

=1

T3UD

fT3

T3R

CountT3OUT

T3IRQ

toT2/T4

T3UDE




Gated Timer Mode

Gated timer mode for the core timer T3 is selected by setting bitfield T3M in registerT3CON to 010B or 011B. Bit T3M.0 (T3CON.3) selects the active level of the gate input.The same options for the input frequency are available in gated timer mode as in timermode (see Section 14.1.5). However, the input clock to the timer in this mode is gatedby the external input pin T3IN (Timer T3 External Input).To enable this operation, the associated pin T3IN must be configured as input, that is,the corresponding direction control bit must contain 0.

Figure 14-5 Block Diagram of Core Timer T3 in Gated Timer Mode

If T3M = 010B, the timer is enabled when T3IN shows a low level. A high level at this linestops the timer. If T3M = 011B, line T3IN must have a high level in order to enable thetimer. Additionally, the timer can be turned on or off by software using bit T3R. The timerwill only run if T3R is 1 and the gate is active. It will stop if either T3R is 0 or the gate isinactive.

Note: A transition of the gate signal at pin T3IN does not cause an interrupt request.

Prescaler GateCtrl. Core Timer T3 Toggle Latch

MCB05392

BPS1 T3I

MUX Up/Down0

1

T3EUD

fGPT

=1

T3UD

fT3

T3R

CountT3OUT

T3IRQ

toT2/T4

T3UDE

T3IN




Counter Mode

Counter Mode for the core timer T3 is selected by setting bitfield T3M in register T3CONto 001B. In counter mode, timer T3 is clocked by a transition at the external input pinT3IN. The event causing an increment or decrement of the timer can be a positive, anegative, or both a positive and a negative transition at this line. Bitfield T3I in controlregister T3CON selects the triggering transition (see Table 14-2).

Figure 14-6 Block Diagram of Core Timer T3 in Counter Mode

For counter mode operation, pin T3IN must be configured as input (the respectivedirection control bit DPx.y must be 0). The maximum input frequency allowed in countermode depends on the selected prescaler value. To ensure that a transition of the countinput signal applied to T3IN is recognized correctly, its level must be held high or low fora minimum number of module clock cycles before it changes. This information can befound in Section 14.1.5.

Table 14-2 GPT1 Core Timer T3 (Counter Mode) Input Edge Selection

T3I Triggering Edge for Counter Increment/Decrement

0 0 0 None. Counter T3 is disabled

0 0 1 Positive transition (rising edge) on T3IN

0 1 0 Negative transition (falling edge) on T3IN

0 1 1 Any transition (rising or falling edge) on T3IN

1 X X Reserved. Do not use this combination

MCB05393

Core Timer T3 Toggle Latch

MUX Up/Down0

1

T3EUD

T3IN

=1

T3UD

T3R

CountT3OUT

T3IRQ

toT2/T4

T3UDE

T3I

Edge

Select




Incremental Interface Mode

Incremental interface mode for the core timer T3 is selected by setting bitfield T3M inregister T3CON to 110B or 111B. In incremental interface mode, the two inputsassociated with core timer T3 (T3IN, T3EUD) are used to interface to an incrementalencoder. T3 is clocked by each transition on one or both of the external input pins toprovide 2-fold or 4-fold resolution of the encoder input.

Figure 14-7 Block Diagram of Core Timer T3 in Incremental Interface Mode

Bitfield T3I in control register T3CON selects the triggering transitions (see Table 14-3).The sequence of the transitions of the two input signals is evaluated and generates countpulses as well as the direction signal. So T3 is modified automatically according to thespeed and the direction of the incremental encoder and, therefore, its contents alwaysrepresent the encoder’s current position.

The interrupt request (T3IRQ) generation mode can be selected: In Rotation DetectionMode (T3M = 110B), an interrupt request is generated each time the count direction ofT3 changes. In Edge Detection Mode (T3M = 111B), an interrupt request is generatedeach time a count edge for T3 is detected. Count direction, changes in the countdirection, and count requests are monitored by status bits T3RDIR, T3CHDIR, andT3EDGE in register T3CON.

MCB05394

Count

T3EUD

T3EDGE

T3RDIR

MUX0

1=1

T3UD

T3UDE

ChangeDetect

T3CHDIR

T3M

T3M

>1_

PhaseDetect

T3R

T3IN

T3I

T3IRQ

CoreTimer T3

ToggleLatch T3OUT

toT2/T4

Edge

Select




The incremental encoder can be connected directly to the XC164 without externalinterface logic. In a standard system, however, comparators will be employed to convertthe encoder’s differential outputs (such as A, A) to digital signals (such as A). This greatlyincreases noise immunity.

Note: The third encoder output T0, which indicates the mechanical zero position, maybe connected to an external interrupt input and trigger a reset of timer T3 (forexample via PEC transfer from ZEROS).

Figure 14-8 Connection of the Encoder to the XC164

For incremental interface operation, the following conditions must be met:

• Bitfield T3M must be 110B or 111B.• Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction

control bits must be 0.• Bit T3UDE must be 1 to enable automatic external direction control.

The maximum count frequency allowed in incremental interface mode depends on theselected prescaler value. To ensure that a transition of any input signal is recognizedcorrectly, its level must be held high or low for a minimum number of module clock cyclesbefore it changes. This information can be found in Section 14.1.5.

Table 14-3 Core Timer T3 (Incremental Interface Mode) Input Edge Selection


0 0 0 None. Counter T3 stops.

0 0 1 Any transition (rising or falling edge) on T3IN.

0 1 0 Any transition (rising or falling edge) on T3EUD.

0 1 1 Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD).

1 X X Reserved. Do not use this combination.

MCS04372

Encoder ControllerA

B

T0

T3Input

T3Input

Interrupt

A

BB

T0T0

A

SignalConditioning




As in incremental interface mode two input signals with a 90° phase shift are evaluated,their maximum input frequency can be half the maximum count frequency.

In incremental interface mode, the count direction is automatically derived from thesequence in which the input signals change, which corresponds to the rotation directionof the connected sensor. Table 14-4 summarizes the possible combinations.

Figure 14-9 and Figure 14-10 give examples of T3’s operation, visualizing count signalgeneration and direction control. They also show how input jitter is compensated, whichmight occur if the sensor rests near to one of its switching points.

Figure 14-9 Evaluation of Incremental Encoder Signals, 2 Count Inputs

Table 14-4 GPT1 Core Timer T3 (Incremental Interface Mode) Count Direction

Level on Respective other Input

T3IN Input T3EUD Input

Rising Falling Rising Falling

High Down Up Up Down

Low Up Down Down Up

MCT04373

Forward Jitter Backward Jitter Forward

T3IN

T3EUD

Contentsof T3

Up Down Up

Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input, i.e. T3I = '011 B'.




Figure 14-10 Evaluation of Incremental Encoder Signals, 1 Count Input

Note: Timer T3 operating in incremental interface mode automatically providesinformation on the sensor’s current position. Dynamic information (speed,acceleration, deceleration) may be obtained by measuring the incoming signalperiods. This is facilitated by an additional special capture mode for timer T5 (seeSection 14.2.5).

MCT04374

Forward Jitter Backward Jitter Forward

T3IN

Up Down Up

T3EUD

Contentsof T3

Note: This example shows the timer behaviour assuming that T3 counts upon any transition on input T3IN, i.e. T3I = '001 B'.




14.1.3 GPT1 Auxiliary Timers T2/T4 Control

Auxiliary timers T2 and T4 have exactly the same functionality. They can be configuredfor timer mode, gated timer mode, counter mode, or incremental interface mode with thesame options for the timer frequencies and the count signal as the core timer T3. Inaddition to these 4 counting modes, the auxiliary timers can be concatenated with thecore timer, or they may be used as reload or capture registers in conjunction with thecore timer. The start/stop function of the auxiliary timers can be remotely controlled bythe T3 run control bit. Several timers may thus be controlled synchronously.

The current contents of an auxiliary timer are reflected by its count register T2 or T4,respectively. These registers can also be written to by the CPU, for example, to set theinitial start value.

The individual configurations for timers T2 and T4 are determined by their bitaddressablecontrol registers T2CON and T4CON, which are organized identically. Note thatfunctions which are present in all 3 timers of block GPT1 are controlled in the same bitpositions and in the same manner in each of the specific control registers.

Note: The auxiliary timers have no output toggle latch and no alternate output function.


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T2R

DIR

T2CHDIR

T2EDGE

T2IR

DIS- -

T2RC

T2UDE

T2UD

T2R T2M T2I

rh rwh rwh rw - - rw rw rw rw rw rw


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T4R

DIR

T4CHDIR

T4EDGE

T4IR

DIS- -

T4RC

T4UDE

T4UD

T4R T4M T4I

rh rwh rwh rw - - rw rw rw rw rw rw


TxRDIR 15 rh Timer Tx Rotation Direction0 Timer x counts up1 Timer x counts down




TxCHDIR 14 rwh Timer Tx Count Direction ChangeThis bit is set each time the count direction of timer Tx changes. TxCHDIR must be cleared by SW.0 No change in count direction was detected1 A change in count direction was detected

TxEDGE 13 rwh Timer Tx Edge DetectionThe bit is set each time a count edge is detected. TxEDGE must be cleared by SW.0 No count edge was detected1 A count edge was detected

TxIRDIS 12 rw Timer Tx Interrupt Request Disable0 Interrupt generation for TxCHDIR and

TxEDGE interrupts in Incremental Interface Mode is enabled

1 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled

TxRC 9 rw Timer Tx Remote Control0 Timer Tx is controlled by its own run bit TxR1 Timer Tx is controlled by the run bit T3R of core

timer 3, not by bit TxR

TxUDE 8 rw Timer Tx External Up/Down Enable1)

0 Input TxEUD is disconnected1 Direction influenced by input TxEUD

TxUD 7 rw Timer Tx Up/Down Control1)

0 Timer Tx counts up1 Timer Tx counts down

TxR 6 rw Timer Tx Run Bit0 Timer Tx stops1 Timer Tx runs

Note: This bit only controls timer Tx if bit TxRC = 0.





Timer T2/T4 Run Control

Each of the auxiliary timers T2 and T4 can be started or stopped by software in twodifferent ways:

• Through the associated timer run bit (T2R or T4R). In this case it is required that therespective control bit TxRC = 0.

• Through the core timer’s run bit (T3R). In this case the respective remote control bitmust be set (TxRC = 1).

The selected run bit is relevant in all operating modes of T2/T4. Setting the bit will startthe timer, clearing the bit stops the timer.

In gated timer mode, the timer will only run if the selected run bit is set and the gate isactive (high or low, as programmed).

Note: If remote control is selected T3R will start/stop timer T3 and the selected auxiliarytimer(s) synchronously.


The count direction of the GPT1 timers (core timer and auxiliary timers) is controlled inthe same way, either by software or by the external input pin TxEUD. Please refer to thedescription in Table 14-1.

Note: When pin TxEUD is used as external count direction control input, it must beconfigured as input (its corresponding direction control bit must be cleared).

TxM [5:3] rw Timer Tx Mode Control (Basic Operating Mode)000 Timer Mode001 Counter Mode010 Gated Timer Mode with gate active low011 Gated Timer Mode with gate active high100 Reload Mode101 Capture Mode110 Incremental Interface Mode (Rotation Detect.)111 Incremental Interface Mode (Edge Detection)

TxI [2:0] rw Timer Tx Input Parameter SelectionDepends on the operating mode, see respective sections for encoding:Table 14-7 for Timer Mode and Gated Timer ModeTable 14-2 for Counter ModeTable 14-3 for Incremental Interface Mode

1) See Table 14-1 for encoding of bits TxUD and TxUDE.





14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes

The operation of the auxiliary timers in the basic operating modes is almost identical withthe core timer’s operation, with very few exceptions. Additionally, some combinedoperating modes can be selected.

Timers T2 and T4 in Timer Mode

Timer mode for an auxiliary timer Tx is selected by setting its bitfield TxM in registerTxCON to 000B.

Figure 14-11 Block Diagram of an Auxiliary Timer in Timer Mode

Prescaler AuxiliaryTimer Tx

BPS1 TxI

fGPT

fTx CountTxIRQ

MCB05395

MUX Up/Down0

1TxEUD

=1

TxUD

TxUDE

MUX

TxRC

TxR

T3R

x = 2, 4

0

1




Timers T2 and T4 in Gated Timer Mode

Gated timer mode for an auxiliary timer Tx is selected by setting bitfield TxM in registerTxCON to 010B or 011B. Bit TxM.0 (TxCON.3) selects the active level of the gate input.

Note: A transition of the gate signal at line TxIN does not cause an interrupt request.

Figure 14-12 Block Diagram of an Auxiliary Timer in Gated Timer Mode

Note: There is no output toggle latch for T2 and T4.Start/stop of an auxiliary timer can be controlled locally or remotely.

Prescaler GateCtrl.

AuxiliaryTimer Tx

BPS1 TxI

fGPTfTx Count

TxIRQ

TxM

MCB05396

MUX Up/Down0

1

TxEUD

=1

TxUD

TxUDE

MUX

TxRC

TxR

T3R

x = 2, 4

0

1

TxIN




Timers T2 and T4 in Counter Mode

Counter mode for an auxiliary timer Tx is selected by setting bitfield TxM in registerTxCON to 001B. In counter mode, an auxiliary timer can be clocked either by a transitionat its external input line TxIN, or by a transition of timer T3’s toggle latch T3OTL. Theevent causing an increment or decrement of a timer can be a positive, a negative, or botha positive and a negative transition at either the respective input pin or at the toggle latch.Bitfield TxI in control register TxCON selects the triggering transition (see Table 14-5).

Figure 14-13 Block Diagram of an Auxiliary Timer in Counter Mode

Note: Only state transitions of T3OTL which are caused by the overflows/underflows ofT3 will trigger the counter function of T2/T4. Modifications of T3OTL via softwarewill NOT trigger the counter function of T2/T4.

Table 14-5 GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection

T2I/T4I Triggering Edge for Counter Increment/Decrement

X 0 0 None. Counter Tx is disabled

0 0 1 Positive transition (rising edge) on TxIN

0 1 0 Negative transition (falling edge) on TxIN

0 1 1 Any transition (rising or falling edge) on TxIN

1 0 1 Positive transition (rising edge) of T3 toggle latch T3OTL

1 1 0 Negative transition (falling edge) of T3 toggle latch T3OTL

1 1 1 Any transition (rising or falling edge) of T3 toggle latch T3OTL

AuxiliaryTimer Tx

CountTxIRQ

MCB05397

MUX Up/Down0

1TxEUD

=1

TxUD

TxUDE

MUX

TxRC

TxR

T3R

x = 2, 4

TxI

MUX

TxI.2

TxIN

T3ToggleLatch

0

1

0

1

Edge

Select




For counter operation, pin TxIN must be configured as input (the respective directioncontrol bit DPx.y must be 0). The maximum input frequency allowed in counter modedepends on the selected prescaler value. To ensure that a transition of the count inputsignal applied to TxIN is recognized correctly, its level must be held high or low for aminimum number of module clock cycles before it changes. This information can befound in Section 14.1.5.

Timers T2 and T4 in Incremental Interface Mode

Incremental interface mode for an auxiliary timer Tx is selected by setting bitfield TxM inthe respective register TxCON to 110B or 111B. In incremental interface mode, the twoinputs associated with an auxiliary timer Tx (TxIN, TxEUD) are used to interface to anincremental encoder. Tx is clocked by each transition on one or both of the external inputpins to provide 2-fold or 4-fold resolution of the encoder input.

Figure 14-14 Block Diagram of an Auxiliary Timer in Incremental Interface Mode

The operation of the auxiliary timers T2 and T4 in incremental interface mode and theinterrupt generation are the same as described for the core timer T3. The descriptions,figures and tables apply accordingly.

MCB05398

CountOverflow

Underflow

TxEUD

TxEdge

TxRDIR

MUX0

1=1

TxUD

TxUDE

ChangeDetect

&

TxCHDIR

TxM

TxM

&

>1_

PhaseDetect

MUX

TxRC

TxR

T3R

TxIN

TxI

TxIRDIS

TxIRQ

AuxiliaryTimer Tx

0

1

Edge

Select




Timer Concatenation

Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter modeconcatenates the core timer T3 with the respective auxiliary timer. This concatenationforms either a 32-bit or a 33-bit timer/counter, depending on which transition of T3OTLis selected to clock the auxiliary timer.

• 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL are usedto clock the auxiliary timer, this timer is clocked on every overflow/underflow of thecore timer T3. Thus, the two timers form a 32-bit timer.

• 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL isselected to clock the auxiliary timer, this timer is clocked on every secondoverflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bitcore timer + T3OTL + 16-bit auxiliary timer).As long as bit T3OTL is not modified by software, it represents the state of the internaltoggle latch, and can be regarded as part of the 33-bit timer.

The count directions of the two concatenated timers are not required to be the same.This offers a wide variety of different configurations.

T3, which represents the low-order part of the concatenated timer, can operate in timermode, gated timer mode or counter mode in this case.

Figure 14-15 Concatenation of Core Timer T3 and an Auxiliary Timer

MCA05399

Toggle Latch T3OUT

T3IRQCount

T3R

Core Timer T3Operating

ModeControl

BPS1 TxI

T3INfGPT

AuxiliaryTimer Tx

TxI

0

1MUX

TxI.2

TxINTxIRQ

Up/Down

Up/Down

Count

MUX

TxRC

TxR

T3R

0

1

x = 2, 4

Edge

Select




Auxiliary Timer in Reload Mode

Reload Mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respectiveregister TxCON to 100B. In reload mode, the core timer T3 is reloaded with the contentsof an auxiliary timer register, triggered by one of two different signals. The trigger signalis selected the same way as the clock source for counter mode (see Table 14-5), i.e. atransition of the auxiliary timer’s input TxIN or the toggle latch T3OTL may trigger thereload.

Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stopsindependently of its run flag T2R or T4R.The timer input pin TxIN must be configured as input if it shall trigger a reloadoperation.

Figure 14-16 GPT1 Auxiliary Timer in Reload Mode

Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2or T4) and the respective interrupt request flag (T2IR or T4IR) is set.

Note: When a T3OTL transition is selected for the trigger signal, the interrupt requestflag T3IR will also be set upon a trigger, indicating T3’s overflow or underflow.Modifications of T3OTL via software will NOT trigger the counter function of T2/T4.

To ensure that a transition of the reload input signal applied to TxIN is recognizedcorrectly, its level must be held high or low for a minimum number of module clockcycles, detailed in Section 14.1.5.

The reload mode triggered by the T3 toggle latch can be used in a number of differentconfigurations. The following functions can be performed, depending on the selectedactive transition:

MCA05400

Toggle Latch T3OUT

T3IRQCount

T3R


ModeControl

BPS1 TxIUp/Down

T3INfGPT

AuxiliaryTimer Tx

TxI

Reload0

1MUX

TxI.2

TxINTxIRQ

x = 2, 4

Edge

Select




• If both a positive and a negative transition of T3OTL are selected to trigger a reload,the core timer will be reloaded with the contents of the auxiliary timer each time itoverflows or underflows. This is the standard reload mode (reload onoverflow/underflow).

• If either a positive or a negative transition of T3OTL is selected to trigger a reload, thecore timer will be reloaded with the contents of the auxiliary timer on every secondoverflow or underflow.

• Using this “single-transition” mode for both auxiliary timers allows to perform veryflexible Pulse Width Modulation (PWM). One of the auxiliary timers is programmed toreload the core timer on a positive transition of T3OTL, the other is programmed fora reload on a negative transition of T3OTL. With this combination the core timer isalternately reloaded from the two auxiliary timers.

Figure 14-17 shows an example for the generation of a PWM signal using the “single-transition” reload mechanism. T2 defines the high time of the PWM signal (reloaded onpositive transitions) and T4 defines the low time of the PWM signal (reloaded on negativetransitions). The PWM signal can be output on pin T3OUT if T3OE = 1. With this method,the high and low time of the PWM signal can be varied in a wide range.

Note: The output toggle latch T3OTL is accessible via software and may be changed, ifrequired, to modify the PWM signal.However, this will NOT trigger the reloading of T3.




Figure 14-17 GPT1 Timer Reload Configuration for PWM Generation

Note: Although possible, selecting the same reload trigger event for both auxiliary timersshould be avoided. In such a case, both reload registers would try to load the coretimer at the same time. If this combination is selected, T2 is disregarded and thecontents of T4 is reloaded.

MCA05401

T2IRQ

AuxiliaryTimer T2

Edge

Select

T2I

Reload0

1MUX

T2I.2

Toggle Latch T3OUT

T3IRQCount

T3R


ModeControl

BPS1 T3IUp/Down

T3INfGPT

T2IN

AuxiliaryTimer T4

Edge

Select

T4I

Reload0

1MUX

T4I.2

T4INT4IRQ




Auxiliary Timer in Capture Mode

Capture mode for an auxiliary timer Tx is selected by setting bitfield TxM in the respectiveregister TxCON to 101B. In capture mode, the contents of the core timer T3 are latchedinto an auxiliary timer register in response to a signal transition at the respective auxiliarytimer’s external input pin TxIN. The capture trigger signal can be a positive, a negative,or both a positive and a negative transition.

The two least significant bits of bitfield TxI select the active transition (see Table 14-5).Bit 2 of TxI is irrelevant for capture mode and must be cleared (TxI.2 = 0).

Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4)stops independently of its run flag T2R or T4R.

Figure 14-18 GPT1 Auxiliary Timer in Capture Mode

Upon a trigger (selected transition) at the corresponding input pin TxIN the contents ofthe core timer are loaded into the auxiliary timer register and the associated interruptrequest flag TxIR will be set.

For capture mode operation, the respective timer input pin TxIN must be configured asinput. To ensure that a transition of the capture input signal applied to TxIN is recognizedcorrectly, its level must be held high or low for a minimum number of module clockcycles, detailed in Section 14.1.5.

MCA05402

Toggle Latch T3OUT

T3IRQCount

T3R


ModeControl

BPS1 T3IUp/Down

T3INfGPT

AuxiliaryTimer Tx

TxI

CaptureTxIN TxIRQ

x = 2, 4y = 4, 2

to Ty

Edge

Select




14.1.5 GPT1 Clock Signal Control

All actions within the timer block GPT1 are triggered by transitions of its basic clock. Thisbasic clock is derived from the system clock by a basic block prescaler, controlled bybitfield BPS1 in register T3CON (see Figure 14-2). The count clock can be generated intwo different ways:

• Internal count clock, derived from GPT1’s basic clock via a programmableprescaler, is used for (gated) timer mode.

• External count clock, derived from the timer’s input pin(s), is used for counter mode.

For both ways, the basic clock determines the maximum count frequency and the timer’sresolution:

Internal Count Clock Generation

In timer mode and gated timer mode, the count clock for each GPT1 timer is derived fromthe GPT1 basic clock by a programmable prescaler, controlled by bitfield TxI in therespective timer’s control register TxCON.

The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lowerclock frequencies, as can be seen from the following formula:

(14.1)

The effective count frequency depends on the common module clock prescaler factorF(BPS1) as well as on the individual input prescaler factor 2<TxI>. Table 14-7 summarizesthe resulting overall divider factors for a GPT1 timer that result from these cascadedprescalers.

Table 14-8 lists a timer’s parameters (such as count frequency, resolution, and period)resulting from the selected overall prescaler factor and the applied system frequency.Note that some numbers may be rounded.

Table 14-6 Basic Clock Selection for Block GPT1

Block Prescaler1)

1) Please note the non-linear encoding of bitfield BPS1.

BPS1 = 01B BPS1 = 00B2)

2) Default after reset.

BPS1 = 11B BPS1 = 10B

Prescaling Factor for GPT1: F(BPS1)

F(BPS1)= 4

F(BPS1)= 8

F(BPS1)= 16

F(BPS1)= 32

Maximum External Count Frequency

fGPT/8 fGPT/16 fGPT/32 fGPT/64

Input SignalStable Time

4 × tGPT 8 × tGPT 16 × tGPT 32 × tGPT

fTxfGPT

F BPS1( ) 2<Txl>×---------------------------------------------= rTx µs[ ] F BPS1( ) 2<Txl>×

fGPT MHz[ ]---------------------------------------------=




Table 14-7 GPT1 Overall Prescaler Factors for Internal Count Clock

Individual Prescaler for Tx

Common Prescaler for Module Clock1)


BPS1 = 01B BPS1 = 00B BPS1 = 11B BPS1 = 10B

TxI = 000B 4 8 16 32

TxI = 001B 8 16 32 64

TxI = 010B 16 32 64 128

TxI = 011B 32 64 128 256

TxI = 100B 64 128 256 512

TxI = 101B 128 256 512 1024

TxI = 110B 256 512 1024 2048

TxI = 111B 512 1024 2048 4096

Table 14-8 GPT1 Timer Parameters

System Clock = 10 MHz Overall Divider Factor

System Clock = 40 MHz

Frequency Resolution Period Frequency Resolution Period

2.5 MHz 400 ns 26.21 ms 4 10.0 MHz 100 ns 6.55 ms

1.25 MHz 800 ns 52.43 ms 8 5.0 MHz 200 ns 13.11 ms

625.0 kHz 1.6 µs 104.9 ms 16 2.5 MHz 400 ns 26.21 ms

312.5 kHz 3.2 µs 209.7 ms 32 1.25 MHz 800 ns 52.43 ms

156.25 kHz 6.4 µs 419.4 ms 64 625.0 kHz 1.6 µs 104.9 ms

78.125 kHz 12.8 µs 838.9 ms 128 312.5 kHz 3.2 µs 209.7 ms

39.06 kHz 25.6 µs 1.678 s 256 156.25 kHz 6.4 µs 419.4 ms

19.53 kHz 51.2 µs 3.355 s 512 78.125 kHz 12.8 µs 838.9 ms

9.77 kHz 102.4 µs 6.711 s 1024 39.06 kHz 25.6 µs 1.678 s

4.88 kHz 204.8 µs 13.42 s 2048 19.53 kHz 51.2 µs 3.355 s

2.44 kHz 409.6 µs 26.84 s 4096 9.77 kHz 102.4 µs 6.711 s




External Count Clock Input

The external input signals of the GPT1 block are sampled with the GPT1 basic clock (seeFigure 14-2). To ensure that a signal is recognized correctly, its current level (high orlow) must be held active for at least one complete sampling period, before changing. Asignal transition is recognized if two subsequent samples of the input signal representdifferent levels. Therefore, a minimum of two basic clock periods are required for thesampling of an external input signal. Thus, the maximum frequency of an input signalmust not be higher than half the basic clock.

Table 14-9 summarizes the resulting requirements for external GPT1 input signals.

These limitations are valid for all external input signals to GPT1, including the externalcount signals in counter mode and incremental interface mode, the gate input signals ingated timer mode, and the external direction signals.

14.1.6 GPT1 Timer Registers

Table 14-9 GPT1 External Input Signal Limits

System Clock = 10 MHz Input Frequ. Factor

GPT1 Divider BPS1

Input Phase Duration


Max. Input Frequency

Min. Level Hold Time



1.25 MHz 400 ns fGPT/8 01B 4 × tGPT 5.0 MHz 100 ns

625.0 kHz 800 ns fGPT/16 00B 8 × tGPT 2.5 MHz 200 ns

312.5 kHz 1.6 µs fGPT/32 11B 16 × tGPT 1.25 MHz 400 ns

156.25 kHz 3.2 µs fGPT/64 10B 32 × tGPT 625.0 kHz 800 ns

GPT12E_Tx Timer x Count Register SFR (FE4xH/2yH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Txvalue

rwh

Table 14-10 GPT1 Timer Register Locations

Timer Register Physical Address 8-Bit Address

T3 FE42H 21H

T2 FE40H 20H

T4 FE44H 22H




14.1.7 Interrupt Control for GPT1 Timers

When a timer overflows from FFFFH to 0000H (when counting up), or when it underflowsfrom 0000H to FFFFH (when counting down), its interrupt request flag (T2IR, T3IR orT4IR) in register TxIC will be set. This will cause an interrupt to the respective timerinterrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respectiveinterrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interruptcontrol register for each of the three timers.

Note: Please refer to the general Interrupt Control Register description for anexplanation of the control fields.

GPT12E_T2ICTimer 2 Intr. Ctrl. Reg. SFR (FF60H/B0H) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - GPX T2IR T2IE ILVL GLVL

- - - - - - - rw rwh rw rw rw


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw




14.2 Timer Block GPT2

From a programmer’s point of view, the GPT2 block is represented by a set of SFRs assummarized below. Those portions of port and direction registers which are used foralternate functions by the GPT2 block are shaded.

Figure 14-19 SFRs Associated with Timer Block GPT2

Both timers of block GPT2 (T5, T6) can run in one of 3 basic modes: Timer Mode, GatedTimer Mode, or Counter Mode. All timers can count up or down. Each timer of GPT2 iscontrolled by a separate control register TxCON.

Each timer has an input pin TxIN (alternate pin function) associated with it, which servesas the gate control in gated timer mode, or as the count input in counter mode. The countdirection (up/down) may be programmed via software or may be dynamically altered bya signal at the External Up/Down control input TxEUD (alternate pin function). Anoverflow/underflow of core timer T6 is indicated by the Output Toggle Latch T6OTL,whose state may be output on the associated pin T6OUT (alternate pin function). Theauxiliary timer T5 may additionally be concatenated with core timer T6 (through T6OTL).

The Capture/Reload register CAPREL can be used to capture the contents of timer T5,or to reload timer T6. A special mode facilitates the use of register CAPREL for bothfunctions at the same time. This mode allows frequency multiplication. The capturefunction is triggered by the input pin CAPIN, or by GPT1 timer’s T3 input lines T3IN andT3EUD. The reload function is triggered by an overflow or underflow of timer T6.Overflows/underflows of timer T6 may also clock the timers of the CAPCOM units.

The current contents of each timer can be read or modified by the CPU by accessing thecorresponding timer count registers T5 or T6, located in the non-bitaddressable SFR

mc_gpt0107_registers.vsd

Data Registers Control Registers Port Registers

T5 T5CON T5IC

T6 T6CON T6IC

CAPREL CRIC

ODP3

DP3

P3

E

P5

P5DIDIS

ALTSEL0P3 E

Interrupt Control

SYSCON3

Tx GPT2 Timer x RegisterCAPREL GPT2 Capture/Reload RegisterTxCON GPT2 Timer x Control RegisterTxIC GPT2 Timer x Interrupt Ctrl. Reg.SYSCON3 System Ctrl. Reg. 3 (Per. Mgmt.)

ODP3 Port 3 Open Drain Control RegisterDP3 Port 3 Direction Control RegisterP3 Port 3 Data RegisterALTSEL0P3 Port 3 Alternate Output Select Reg.P5 Port 5 Data RegisterP5DIDIS Port 5 Digital Input Disable Reg.




space (see Section 14.2.7). When any of the timer registers is written to by the CPU inthe state immediately preceding a timer increment, decrement, reload, or captureoperation, the CPU write operation has priority in order to guarantee correct results.

The interrupts of GPT2 are controlled through the Interrupt Control Registers TxIC.These registers are not part of the GPT2 block. The input and output lines of GPT2 areconnected to pins of Ports P3 and P5. The control registers for the port functions arelocated in the respective port modules.

Note: The timing requirements for external input signals can be found in Section 14.2.6,Section 14.3 summarizes the module interface signals, including pins.

Figure 14-20 GPT2 Block Diagram

CAPRELModeControl

T5ModeControl

GPT2 Timer T5

T6ModeControl

GPT2 Timer T6

GPT2 CAPREL

T6OTL

T5IN

T3IN/T3EUD

CAPIN

T6IN

T6OUT

U/D

U/D

InterruptRequest(T5IR)

InterruptRequest(CRIR)

InterruptRequest(T6IR)

T6OUF

Clear

Capture

mc_gpt0108_bldiax4.vsd

Toggle FF

Clear

2n: 1fGPT Basic clock

T6CON.BPS2

Reload

T5EUD

T6EUD




14.2.1 GPT2 Core Timer T6 Control

The current contents of the core timer T6 are reflected by its count register T6. Thisregister can also be written to by the CPU, for example, to set the initial start value.

The core timer T6 is configured and controlled via its bitaddressable control registerT6CON.


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T6SR

T6CLR

- BPS2T6

OTLT6OE

T6UDE

T6UD

T6R T6M T6I

rw rw - rw rwh rw rw rw rw rw rw


T6SR 15 rw Timer 6 Reload Mode Enable0 Reload from register CAPREL Disabled1 Reload from register CAPREL Enabled

T6CLR 14 rw Timer T6 Clear Enable Bit0 Timer T6 is not cleared on a capture event1 Timer T6 is cleared on a capture event

BPS2 [12:11] rw GPT2 Block Prescaler ControlSelects the basic clock for block GPT2(see also Section 14.2.6)00 fGPT/401 fGPT/210 fGPT/1611 fGPT/8

T6OTL 10 rwh Timer T6 Overflow Toggle LatchToggles on each overflow/underflow of T6. Can be set or reset by software (see separate description)

T6OE 9 rw Overflow/Underflow Output Enable0 Alternate Output Function Disabled1 State of T6 toggle latch is output on pin T6OUT









T6M [5:3] rw Timer T6 Mode Control (Basic Operating Mode)000 Timer Mode001 Counter Mode010 Gated Timer Mode with gate active low011 Gated Timer Mode with gate active high100 Reserved. Do not use this combination.101 Reserved. Do not use this combination.110 Reserved. Do not use this combination.111 Reserved. Do not use this combination.

T6I [2:0] rw Timer T6 Input Parameter SelectionDepends on the operating mode, see respective sections for encoding:Table 14-16 for Timer Mode and Gated Timer ModeTable 14-12 for Counter Mode







The core timer T6 can be started or stopped by software through bit T6R (timer T6 runbit). This bit is relevant in all operating modes of T6. Setting bit T6R will start the timer,clearing bit T6R stops the timer.

In gated timer mode, the timer will only run if T6R = 1 and the gate is active (high or low,as programmed).

Note: When bit T5RC in timer control register T5CON is set, bit T6R will also control(start and stop) the Auxiliary Timer T5.


The count direction of the GPT2 timers (core timer and auxiliary timer) can be controlledeither by software or by the external input pin TxEUD (Timer Tx External Up/DownControl Input). These options are selected by bits TxUD and TxUDE in the respectivecontrol register TxCON. When the up/down control is provided by software (bitTxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bitTxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction.However, bit TxUD can still be used to reverse the actual count direction, as shown inTable 14-11. The count direction can be changed regardless of whether or not the timeris running.

Table 14-11 GPT2 Timer Count Direction Control

Pin TxEUD Bit TxUDE Bit TxUD Count Direction

X 0 0 Count Up

X 0 1 Count Down

0 1 0 Count Up

1 1 0 Count Down

0 1 1 Count Down

1 1 1 Count Up




Timer 6 Output Toggle Latch

The overflow/underflow signal of timer T6 is connected to a block named ‘Toggle Latch’,shown in the timer mode diagrams. Figure 14-21 illustrates the details of this block. Anoverflow or underflow of T6 will clock two latches: The first latch represents bit T6OTL incontrol register T6CON. The second latch is an internal latch toggled by T6OTL’s output.Both latch outputs are connected to the input control block of the auxiliary timer T5. Theoutput level of the shadow latch will match the output level of T6OTL, but is delayed byone clock cycle. When the T6OTL value changes, this will result in a temporarily differentoutput level from T6OTL and the shadow latch, which can trigger the selected countevent in T5.

When software writes to T6OTL, both latches are set or cleared simultaneously. In thiscase, both signals to the auxiliary timers carry the same level and no edge will bedetected. Bit T6OE (overflow/underflow output enable) in register T6CON enables thestate of T6OTL to be monitored via an external pin T6OUT. When T6OTL is linked to anexternal port pin (must be configured as output), T6OUT can be used to control externalHW. If T6OE = 1, pin T6OUT outputs the state of T6OTL. If T6OE = 0, pin T6OUToutputs a high level (while it selects the timer output signal).

As can be seen from Figure 14-21, when latch T6OTL is modified by software todetermine the state of the output line, also the internal shadow latch is set or clearedaccordingly. Therefore, no trigger condition is detected by T5 in this case.

Figure 14-21 Block Diagram of the Toggle Latch Logic of Core Timer T6

Note: T6 is also used to clock the timers in the CAPCOM units. For this purpose, thereis a direct internal connection between the T6 overflow/underflow line and theCAPCOM timers (signal T6OUF).

m c_gpt0106_otl.vsd

Togg le La tch Log ic

TxO U T

S et/C lear (S W )

C ore T im er

O verflow /U nderflow Shadow

Latch

1

0

MU

X

1

TxO E

TxOTLTo P ort Log ic

To A ux. T im erInput Log ic




14.2.2 GPT2 Core Timer T6 Operating Modes

Timer 6 in Timer Mode

Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CONto 000B. In this mode, T6 is clocked with the module’s input clock fGPT divided by twoprogrammable prescalers controlled by bitfields BPS2 and T6I in register T6CON.Please see Section 14.2.6 for details on the input clock options.

Figure 14-22 Block Diagram of Core Timer T6 in Timer Mode

Prescaler Core Timer T6 Toggle Latch

MCB05403_X4

BPS2 T6I

Up/Down

fGPT

fT6

T6R

CountT6OUT

T6IRQ

to T5/CAPREL

T6OUF

MUX0

1

T6EUD

=1

T6UD

T6UDE




Gated Timer Mode

Gated timer mode for the core timer T6 is selected by setting bitfield T6M in registerT6CON to 010B or 011B. Bit T6M.0 (T6CON.3) selects the active level of the gate input.The same options for the input frequency are available in gated timer mode as in timermode (see Section 14.2.6). However, the input clock to the timer in this mode is gatedby the external input pin T6IN (Timer T6 External Input).To enable this operation, the associated pin T6IN must be configured as input (thecorresponding direction control bit must contain 0).

Figure 14-23 Block Diagram of Core Timer T6 in Gated Timer Mode

If T6M = 010B, the timer is enabled when T6IN shows a low level. A high level at this linestops the timer. If T6M = 011B, line T6IN must have a high level in order to enable thetimer. Additionally, the timer can be turned on or off by software using bit T6R. The timerwill only run if T6R is 1 and the gate is active. It will stop if either T6R is 0 or the gate isinactive.

Note: A transition of the gate signal at pin T6IN does not cause an interrupt request.

Prescaler GateCtrl. Core Timer T6 Toggle Latch

MCB05404_X4

BPS2 T6I

Up/Down

fGPTfT6

T6R

CountT6OUT

T6IRQ

to T5,CAPRELClear

T6OUFT6IN

MUX0

1

T6EUD

=1

T6UD

T6UDE




Counter Mode

Counter mode for the core timer T6 is selected by setting bitfield T6M in register T6CONto 001B. In counter mode, timer T6 is clocked by a transition at the external input pinT6IN. The event causing an increment or decrement of the timer can be a positive, anegative, or both a positive and a negative transition at this line. Bitfield T6I in controlregister T6CON selects the triggering transition (see Table 14-12).

Figure 14-24 Block Diagram of Core Timer T6 in Counter Mode

For counter mode operation, pin T6IN must be configured as input (the respectivedirection control bit DPx.y must be 0). The maximum input frequency allowed in countermode depends on the selected prescaler value. To ensure that a transition of the countinput signal applied to T6IN is recognized correctly, its level must be held high or low fora minimum number of module clock cycles before it changes. This information can befound in Section 14.2.6.

Table 14-12 GPT2 Core Timer T6 (Counter Mode) Input Edge Selection


0 0 0 None. Counter T6 is disabled




1 X X Reserved. Do not use this combination

MCB05405_X4

Core Timer T6 Toggle Latch

Up/Down

T6IN

T6R

CountT6OUT

T6IRQ

to T5,CAPREL

T6IClear

T6OUF

Edge

Select

MUX0

1

T6EUD

=1

T6UD

T6UDE




14.2.3 GPT2 Auxiliary Timer T5 Control

Auxiliary timer T5 can be configured for timer mode, gated timer mode, or counter modewith the same options for the timer frequencies and the count signal as the core timerT6. In addition to these 3 counting modes, the auxiliary timer can be concatenated withthe core timer. The contents of T5 may be captured to register CAPREL upon an externalor an internal trigger. The start/stop function of the auxiliary timers can be remotelycontrolled by the T6 run control bit. Several timers may thus be controlled synchronously.

The current contents of the auxiliary timer are reflected by its count register T5. Thisregister can also be written to by the CPU, for example, to set the initial start value.

The individual configurations for timer T5 are determined by its bitaddressable controlregister T5CON. Some bits in this register also control the function of the CAPRELregister. Note that functions which are present in all timers of block GPT2 are controlledin the same bit positions and in the same manner in each of the specific control registers.

Note: The auxiliary timer has no output toggle latch and no alternate output function.


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T5SC

T5CLR

CIT5CC

CT3T5RC

T5UDE

T5UD

T5R T5M T5I

rw rw rw rw rw rw rw rw rw rw rw


T5SC 15 rw Timer 5 Capture Mode Enable0 Capture into register CAPREL Disabled1 Capture into register CAPREL Enabled

T5CLR 14 rw Timer T5 Clear Enable Bit0 Timer T5 is not cleared on a capture event1 Timer T5 is cleared on a capture event

CI [13:12] rw Register CAPREL Capture Trigger Selection(depending on bit CT3)00 Capture disabled01 Positive transition (rising edge) on CAPIN or

any transition on T3IN10 Negative transition (falling edge) on CAPIN or

any transition on T3EUD11 Any transition (rising or falling edge) on CAPIN

or any transition on T3IN or T3EUD




T5CC 11 rw Timer T5 Capture Correction0 T5 is just captured without any correction1 T5 is decremented by 1 before being captured

CT3 10 rw Timer T3 Capture Trigger Enable0 Capture trigger from input line CAPIN1 Capture trigger from T3 input lines T3IN and/or

T3EUD

T5RC 9 rw Timer T5 Remote Control0 Timer T5 is controlled by its own run bit T5R1 Timer T5 is controlled by the run bit T6R of

core timer 6, not by bit T5R






Note: This bit only controls timer T5 if bit T5RC = 0.

T5M [5:3] rw Timer T5 Mode Control (Basic Operating Mode)000 Timer Mode001 Counter Mode010 Gated Timer Mode with gate active low011 Gated Timer Mode with gate active high1XX Reserved. Do not use this combination

T5I [2:0] rw Timer T5 Input Parameter SelectionDepends on the operating mode, see respective sections for encoding:Table 14-16 for Timer Mode and Gated Timer Mode Table 14-12 for Counter Mode







The auxiliary timer T5 can be started or stopped by software in two different ways:

• Through the associated timer run bit (T5R). In this case it is required that therespective control bit T5RC = 0.

• Through the core timer’s run bit (T6R). In this case the respective remote control bitmust be set (T5RC = 1).

The selected run bit is relevant in all operating modes of T5. Setting the bit will start thetimer, clearing the bit stops the timer.

In gated timer mode, the timer will only run if the selected run bit is set and the gate isactive (high or low, as programmed).

Note: If remote control is selected T6R will start/stop timer T6 and the auxiliary timer T5synchronously.

14.2.4 GPT2 Auxiliary Timer T5 Operating Modes

The operation of the auxiliary timer in the basic operating modes is almost identical withthe core timer’s operation, with very few exceptions. Additionally, some combinedoperating modes can be selected.

Timer T5 in Timer Mode

Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in registerT5CON to 000B.

Figure 14-25 Block Diagram of Auxiliary Timer T5 in Timer Mode

Prescaler AuxiliaryTimer T5

BPS2 T5I

fGPT

fT5 CountT5IRQ

MCB05406_X4

Up/Down

MUX

T5RC

T5R

T6R

0

1

Clear

MUX0

1

T5EUD

=1

T5UD

T5UDE




Timer T5 in Gated Timer Mode

Gated timer mode for the auxiliary timer T5 is selected by setting bitfield T5M in registerT5CON to 010B or 011B. Bit T5M.0 (T5CON.3) selects the active level of the gate input.

Note: A transition of the gate signal at line T5IN does not cause an interrupt request.

Figure 14-26 Block Diagram of Auxiliary Timer T5 in Gated Timer Mode

Note: There is no output toggle latch for T5.Start/stop of the auxiliary timer can be controlled locally or remotely.

Timer T5 in Counter Mode

Counter mode for auxiliary timer T5 is selected by setting bitfield T5M in register T5CONto 001B. In counter mode, the auxiliary timer can be clocked either by a transition at itsexternal input line T5IN, or by a transition of timer T6’s toggle latch T6OTL. The eventcausing an increment or decrement of a timer can be a positive, a negative, or both apositive and a negative transition at either the respective input pin or at the toggle latch.Bitfield T5I in control register T5CON selects the triggering transition (see Table 14-13).

Prescaler GateCtrl.

AuxiliaryTimer T5

BPS2 T5IT5IN

fGPTfT5 Count

T5IRQ

MCB05407_X4

MUX

T5RC

T5R

T6R

Clear

Up/Down

0

1

MUX0

1

T5EUD

=1

T5UD

T5UDE




Figure 14-27 Block Diagram of Auxiliary Timer T5 in Counter Mode

Note: Only state transitions of T6OTL which are caused by the overflows/underflows ofT6 will trigger the counter function of T5. Modifications of T6OTL via software willNOT trigger the counter function of T5.

For counter operation, pin T5IN must be configured as input (the respective directioncontrol bit DPx.y must be 0). The maximum input frequency allowed in counter modedepends on the selected prescaler value. To ensure that a transition of the count inputsignal applied to T5IN is recognized correctly, its level must be held high or low for aminimum number of module clock cycles before it changes. This information can befound in Section 14.2.6.

Table 14-13 GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection


X 0 0 None. Counter T5 is disabled




1 0 1 Positive transition (rising edge) of T6 toggle latch T6OTL

1 1 0 Negative transition (falling edge) of T6 toggle latch T6OTL

1 1 1 Any transition (rising or falling edge) of T6 toggle latch T6OTL

AuxiliaryTimer T5

CountT5IRQ

MCB05408_X4

Up/Down

MUX

T5RC

T5R

T6R

T5I

MUX

T5I.2

T5IN

T6ToggleLatch

0

1

Clear

0

1

Edge

Select

MUX0

1

T5EUD

=1

T5UD

T5UDE




Timer Concatenation

Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter modeconcatenates the core timer T6 with the auxiliary timer T5. This concatenation formseither a 32-bit or a 33-bit timer/counter, depending on which transition of T6OTL isselected to clock the auxiliary timer.

• 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL are usedto clock the auxiliary timer, this timer is clocked on every overflow/underflow of thecore timer T6. Thus, the two timers form a 32-bit timer.

• 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL isselected to clock the auxiliary timer, this timer is clocked on every secondoverflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bitcore timer + T6OTL + 16-bit auxiliary timer).As long as bit T6OTL is not modified by software, it represents the state of the internaltoggle latch, and can be regarded as part of the 33-bit timer.

The count directions of the two concatenated timers are not required to be the same.This offers a wide variety of different configurations.

T6, which represents the low-order part of the concatenated timer, can operate in timermode, gated timer mode or counter mode in this case.

Figure 14-28 Concatenation of Core Timer T6 and Auxiliary Timer T5

MCA05409

Toggle Latch T6OUT

T6IRQCount

T6R


ModeControl

BPS2 T6IClear

T6INfGPT

AuxiliaryTimer T5

T5I

0

1MUX

T5I.2

T5INT5IRQ

Up/Down

Clear Up/Down

Count

MUX

T5RC

T5R

T6R

0

1

Edge

Select




14.2.5 GPT2 Register CAPREL Operating Modes

The Capture/Reload register CAPREL can be used to capture the contents of timer T5,or to reload timer T6. A special mode facilitates the use of register CAPREL for bothfunctions at the same time. This mode allows frequency multiplication. The capturefunction is triggered by the input pin CAPIN, or by GPT1 timer’s T3 input lines T3IN andT3EUD. The reload function is triggered by an overflow or underflow of timer T6.

In addition to the capture function, the capture trigger signal can also be used to clearthe contents of timers T5 and T6 individually.

The functions of register CAPREL are controlled via several bit(field)s in the timer controlregisters T5CON and T6CON.

GPT2 Capture/Reload Register CAPREL in Capture Mode

Capture mode for register CAPREL is selected by setting bit T5SC in control registerT5CON (set bitfield CI in register T5CON to a non-zero value to select a trigger signal).In capture mode, the contents of the auxiliary timer T5 are latched into register CAPRELin response to a signal transition at the selected external input pin(s). Bit CT3 selects theexternal input line CAPIN or the input lines T3IN and/or T3EUD of GPT1 timer T3 as thesource for a capture trigger. Either a positive, a negative, or both a positive and anegative transition at line CAPIN can be selected to trigger the capture function, ortransitions on input T3IN or input T3EUD or both inputs, T3IN and T3EUD. The activeedge is controlled by bitfield CI in register T5CON. Table 14-14 summarizes theseoptions.

Table 14-14 CAPREL Register Input Edge Selection

CT3 CI Triggering Signal/Edge for Capture Mode

X 0 0 None. Capture Mode is disabled.

0 0 1 Positive transition (rising edge) on CAPIN.

0 1 0 Negative transition (falling edge) on CAPIN.

0 1 1 Any transition (rising or falling edge) on CAPIN.

1 0 1 Any transition (rising or falling edge) on T3IN.

1 1 0 Any transition (rising or falling edge) on T3EUD.

1 1 1 Any transition (rising or falling edge) on T3IN or T3EUD.




Figure 14-29 GPT2 Register CAPREL in Capture Mode

When a selected trigger is detected, the contents of the auxiliary timer T5 are latchedinto register CAPREL and the interrupt request line CRIRQ is activated. The same eventcan optionally clear timer T5 and/or timer T6. This option is enabled by bit T5CLR inregister T5CON and bit T6CLR in register T6CON, respectively. If TxCLR = 0 thecontents of timer Tx is not affected by a capture. If TxCLR = 1 timer Tx is cleared afterthe current timer T5 value has been latched into register CAPREL.

Note: Bit T5SC only controls whether or not a capture is performed. If T5SC is clearedthe external input pin(s) can still be used to clear timer T5 and/or T6, or as externalinterrupt input(s). This interrupt is controlled by the CAPREL interrupt controlregister CRIC.

When capture triggers T3IN or T3EUD are enabled (CT3 = 1), register CAPREL capturesthe contents of T5 upon transitions of the selected input(s). These values can be usedto measure T3’s input signals. This is useful, for example, when T3 operates in

SignalSelect

AuxiliaryTimer T5 T5IRQ

MCA05410

Up/DownClear

T5CLR

T5SC

Capture

CAPRELRegister

T6CLR

0

1MUX

CT3

CI

CAPIN

T3IN

T3EUD

CountClock

T5CC

CRIRQ

CaptureCorrection

ClearT6

Edge

Select




incremental interface mode, in order to derive dynamic information (speed, acceleration)from the input signals.

For capture mode operation, the selected pins CAPIN, T3IN, or T3EUD must beconfigured as input. To ensure that a transition of a trigger input signal applied to one ofthese inputs is recognized correctly, its level must be held high or low for a minimumnumber of module clock cycles, detailed in Section 14.2.6.

GPT2 Capture/Reload Register CAPREL in Reload Mode

Reload mode for register CAPREL is selected by setting bit T6SR in control registerT6CON. In reload mode, the core timer T6 is reloaded with the contents of registerCAPREL, triggered by an overflow or underflow of T6. This will not activate the interruptrequest line CRIRQ associated with the CAPREL register. However, interrupt requestline T6IRQ will be activated, indicating the overflow/underflow of T6.

Figure 14-30 GPT2 Register CAPREL in Reload Mode

MCA05411

CAPRELRegister

T6SR

Core Timer T6

Reload

Up/Down

CountClock Toggle Latch T6OUT

T6IRQ

T6OUF

to T5




GPT2 Capture/Reload Register CAPREL in Capture-And-Reload Mode

Since the reload function and the capture function of register CAPREL can be enabledindividually by bits T5SC and T6SR, the two functions can be enabled simultaneously bysetting both bits. This feature can be used to generate an output frequency that is amultiple of the input frequency.

Figure 14-31 GPT2 Register CAPREL in Capture-And-Reload Mode

This combined mode can be used to detect consecutive external events which mayoccur aperiodically, but where a finer resolution, that means, more ‘ticks’ within the timebetween two external events is required.

For this purpose, the time between the external events is measured using timer T5 andthe CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g.fGPT/32. The external events are applied to pin CAPIN. When an external event occurs,

AuxiliaryTimer T5 T5IRQ

Up/DownClear

T5SC

Capture

CAPRELRegister

0

1MUX

CT3

CI

CAPIN

T3IN

T3EUD

CountClock

T5CC

CaptureCorrection

T5CLR

CRIRQ

MCA05412

T6SR

Core Timer T6

Clear

T6CLR

Reload

Up/Down

CountClock Toggle Latch T6OUT

T6IRQ

T6OUF

to T5

Edge

Select

Edge

Select




the contents of timer T5 are latched into register CAPREL and timer T5 is cleared(T5CLR = 1). Thus, register CAPREL always contains the correct time between twoevents, measured in timer T5 increments. Timer T6, which runs in timer mode countingdown with a frequency of e.g. fGPT/4, uses the value in register CAPREL to perform areload on underflow. This means, the value in register CAPREL represents the timebetween two underflows of timer T6, now measured in timer T6 increments. Since (in thisexample) timer T6 runs 8 times faster than timer T5, it will underflow 8 times within thetime between two external events. Thus, the underflow signal of timer T6 generates8 ‘ticks’. Upon each underflow, the interrupt request line T6IRQ will be activated and bitT6OTL will be toggled. The state of T6OTL may be output on pin T6OUT. This signal has8 times more transitions than the signal which is applied to pin CAPIN.

Note: The underflow signal of Timer T6 can furthermore be used to clock one or more ofthe timers of the CAPCOM units, which gives the user the possibility to setcompare events based on a finer resolution than that of the external events. Thisconnection is accomplished via signal T6OUF.

Capture Correction

A certain deviation of the output frequency is generated by the fact that timer T5 willcount actual time units (e.g. T5 running at 1 MHz will count up to the value 64H/100D fora 10 kHz input signal), while T6OTL will only toggle upon an underflow of T6 (i.e. thetransition from 0000H to FFFFH). In the above mentioned example, T6 would count downfrom 64H, so the underflow would occur after 101 timing ticks of T6. The actual outputfrequency then is 79.2 kHz, instead of the expected 80 kHz.

This deviation can be compensated for by activating the Capture Correction (T5CC = 1).If capture correction is active, the contents of T5 are decremented by 1 before beingcaptured. The described deviation is eliminated (in the example, T5 would count up tothe value 64H/100D, but the CAPREL register will capture the decremented value63H/99D, T6 would count exactly 100 ticks, and the output frequency is 80 kHz).




14.2.6 GPT2 Clock Signal Control

All actions within the timer block GPT2 are triggered by transitions of its basic clock. Thisbasic clock is derived from the system clock by a basic block prescaler, controlled bybitfield BPS2 in register T6CON (see Figure 14-20). The count clock can be generatedin two different ways:

• Internal count clock, derived from GPT2’s basic clock via a programmableprescaler, is used for (gated) timer mode.

• External count clock, derived from the timer’s input pin(s), is used for counter mode.

For both ways, the basic clock determines the maximum count frequency and the timer’sresolution:

Internal Count Clock Generation

In timer mode and gated timer mode, the count clock for each GPT2 timer is derived fromthe GPT2 basic clock by a programmable prescaler, controlled by bitfield TxI in therespective timer’s control register TxCON.

The count frequency fTx for a timer Tx and its resolution rTx are scaled linearly with lowerclock frequencies, as can be seen from the following formula:

(14.2)

The effective count frequency depends on the common module clock prescaler factorF(BPS2) as well as on the individual input prescaler factor 2<TxI>. Table 14-16summarizes the resulting overall divider factors for a GPT2 timer that result from thesecascaded prescalers.

Table 14-15 Basic Clock Selection for Block GPT2

Block Prescaler1)


BPS2 = 01B BPS2 = 00B2)

2) Default after reset.

BPS2 = 11B BPS2 = 10B

Prescaling Factor for GPT2: F(BPS2)

F(BPS2)= 2

F(BPS2)= 4

F(BPS2)= 8

F(BPS2)= 16

Maximum External Count Frequency

fGPT/4 fGPT/8 fGPT/16 fGPT/32

Input SignalStable Time

2 × tGPT 4 × tGPT 8 × tGPT 16 × tGPT

fTxfGPT

F BPS2( ) 2<Txl>×---------------------------------------------= rTx µs[ ] F BPS2( ) 2<Txl>×

fGPT MHz[ ]---------------------------------------------=




Table 14-17 lists a timer’s parameters (such as count frequency, resolution, and period)resulting from the selected overall prescaler factor and the applied system frequency.Note that some numbers may be rounded.

Table 14-16 GPT2 Overall Prescaler Factors for Internal Count Clock

Individual Prescaler for Tx

Common Prescaler for Module Clock1)

BPS2 = 01B BPS2 = 00B BPS2 = 11B BPS2 = 10B

TxI = 000B 2 4 8 16

TxI = 001B 4 8 16 32

TxI = 010B 8 16 32 64

TxI = 011B 16 32 64 128

TxI = 100B 32 64 128 256

TxI = 101B 64 128 256 512

TxI = 110B 128 256 512 1024

TxI = 111B 256 512 1024 20481) Please note the non-linear encoding of bitfield BPS2.

Table 14-17 GPT2 Timer Parameters

System Clock = 10 MHz Overall Divider Factor


Frequency Resolution Period Frequency Resolution Period

5.0 MHz 200 ns 13.11 ms 2 20.0 MHz 50 ns 3.28 ms

2.5 MHz 400 ns 26.21 ms 4 10.0 MHz 100 ns 6.55 ms

1.25 MHz 800 ns 52.43 ms 8 5.0 MHz 200 ns 13.11 ms

625.0 kHz 1.6 µs 104.9 ms 16 2.5 MHz 400 ns 26.21 ms

312.5 kHz 3.2 µs 209.7 ms 32 1.25 MHz 800 ns 52.43 ms

156.25 kHz 6.4 µs 419.4 ms 64 625.0 kHz 1.6 µs 104.9 ms

78.125 kHz 12.8 µs 838.9 ms 128 312.5 kHz 3.2 µs 209.7 ms

39.06 kHz 25.6 µs 1.678 s 256 156.25 kHz 6.4 µs 419.4 ms

19.53 kHz 51.2 µs 3.355 s 512 78.125 kHz 12.8 µs 838.9 ms

9.77 kHz 102.4 µs 6.711 s 1024 39.06 kHz 25.6 µs 1.678 s

4.88 kHz 204.8 µs 13.42 s 2048 19.53 kHz 51.2 µs 3.355 s




External Count Clock Input

The external input signals of the GPT2 block are sampled with the GPT2 basic clock (seeFigure 14-20). To ensure that a signal is recognized correctly, its current level (high orlow) must be held active for at least one complete sampling period, before changing. Asignal transition is recognized if two subsequent samples of the input signal representdifferent levels. Therefore, a minimum of two basic clock periods are required for thesampling of an external input signal. Thus, the maximum frequency of an input signalmust not be higher than half the basic clock.

Table 14-18 summarizes the resulting requirements for external GPT2 input signals.

These limitations are valid for all external input signals to GPT2, including the externalcount signals in counter mode and the gate input signals in gated timer mode.

Table 14-18 GPT2 External Input Signal Limits

System Clock = 10 MHz Input Frequ. Factor

GPT2 Divider BPS1

Input Phase Duration








625.0 kHz 800 ns fGPT/16 11B 8 × tGPT 2.5 MHz 200 ns

312.5 kHz 1.6 µs fGPT/32 10B 16 × tGPT 1.25 MHz 400 ns




14.2.7 GPT2 Timer Registers

GPT12E_Tx Timer x Count Register SFR (FE4xH/2yH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Txvalue

rwh

Table 14-19 GPT1 Timer Register Locations

Timer Register Physical Address 8-Bit Address

T5 FE46H 23H

T6 FE48H 24H

GPT12E_CAPREL Capture/Reload Register SFR (FE4AH/25H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Capture/Reloadvalue

rwh




14.2.8 Interrupt Control for GPT2 Timers and CAPREL

When a timer overflows from FFFFH to 0000H (when counting up), or when it underflowsfrom 0000H to FFFFH (when counting down), its interrupt request flag (T5IR or T6IR) inregister TxIC will be set. Whenever a transition according to the selection in bit field CIis detected at pin CAPIN, interrupt request flag CRIR in register CRIC is set. Setting anyrequest flag will cause an interrupt to the respective timer or CAPREL interrupt vector(T5INT, T6INT or CRINT) or trigger a PEC service, if the respective interrupt enable bit(T5IE or T6IE in register TxIC, CRIE in register CRIC) is set. There is an interrupt controlregister for each of the two timers and for the CAPREL register.



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw

GPT12E_CRICCAPREL Intr. Ctrl. Reg. SFR (FF6AH/B5H) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - GPX CRIR CRIE ILVL GLVL

- - - - - - - rw rwh rw rw rw




14.3 Interfaces of the GPT Module

Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2are connected to their environment in two basic ways (see Figure 14-32):

• Internal connections interface the timers with on-chip resources such as clockgeneration unit, interrupt controller, or other timers.

• External connections interface the timers with external resources via port pins.

Figure 14-32 GPT Module Interfaces

Port pins to be used for timer input signals must be switched to input, the respectivedirection control bits must be cleared (DPx.y = 0).

Port pins to be used for timer output signals must be switched to output, the respectivedirection control bits must be set (DPx.y = 1). The alternate timer output signal must beselected for these pins via the respective alternate select registers (see Chapter 7).

Interrupt nodes to be used for timer interrupt requests must be enabled and programmedto a specific interrupt level.

mc_gpt0105_modinterface_x.vsd

SystemControl

Unit

P5.15T2EUD

GeneralPurposeTimerUnits

fGPT

P5.14T4EUD

P3.7T2IN

P3.6T3IN

P3.5T4IN

P3.4T3EUD

P3.3T3OUT

P5.13T5IN

P5.12T6IN

P5.11T5EUD

P5.10T6EUD

P3.2CAPIN

P3.1T6OUT

T2IRQ

GPTDIS

T3IRQ

T4IRQ

T5IRQ

T6IRQ

CRIRQ

T6OUF

InterruptControl

Unit

CAPCOMUnits

Port

Logi

c fo

r P3

and

P5



Real Time Clock

15 Real Time Clock The Real Time Clock (RTC) module of the XC164 basically consists of a chain ofprescalers and timers. Its count clock is derived from the auxiliary oscillator or from theprescaled main oscillator. The RTC serves various purposes:

• 48-bit timer for long term measurements• System clock to determine the current time and date

(the RTC’s structure supports the direct representation of time and date)• Cyclic time based interrupt (can be generated by any timer of the chain)

A number of programming options as well as interrupt request signals adjust theoperation of the RTC to the application’s requirements. The RTC can continue itsoperation while the XC164 is in a power-saving mode, such that real time date and timeinformation is provided.

Figure 15-1 SFRs Associated with the RTC Module

The RTC module consists of a chain of 3 divider blocks:

• a selectable 8:1 divider (on - off)• the reloadable 16-bit timer T14• the 32-bit RTC timer block (accessible via RTC_RTCH and RTC_RTCL), made of:

– the reloadable 10-bit timer CNT0– the reloadable 6-bit timer CNT1– the reloadable 6-bit timer CNT2– the reloadable 10-bit timer CNT3

All timers count upwards. Each of the five timers can generate an interrupt request. Allrequests are combined to a common node request.

Note: The RTC registers are not affected by a system reset in order to maintain thecorrect system time even when intermediate resets are executed.

m ca04463_xc .vsd

R TC _C O N R TC _T14R E L R TC _T14 R TC _IS N C

C ontro l R eg is ters D ata R eg is ters C ounter R eg is ters In te rrup t C ontro l

R TC _T14 T im er T14 C ount R eg is terR TC _T14R E L T im er T14 R e load R eg is terR TC _R TC H /L R TC C ount R eg is ters , H igh/LowR TC _R E LH /L R TC R eload R eg., H igh /Low

R TC _IC

EE E

R TC _R TC H E

R TC _R TC L E

E

R TC _C O N R ea l T im e C lock C ontro l R eg is terS Y S C O N 0 G enera l S ys tem C ontro l R eg is terS Y S C O N 3 P ow er M anagem ent C ontro l R eg.R TC _IS N C Interrup t S ubnode C ontro l R eg is terR TC _IC R TC In terrup t C ontro l R eg is ter

E

R TC _R E LH E

R TC _R E LL ES Y S C O N 3 E

S Y S C O N 0 E

User’s Manual 15-1 V2.1, 2004-03RTC_X41, V2.1


Real Time Clock

15.1 Defining the RTC Time Base

The timer chain of the RTC is clocked with the count clock signal fRTC which is derivedfrom the prescaled main oscillator (see Figure 15-2 and Figure 15-3). Optionallyprescaled by a factor of 8, this is the basic RTC clock. Depending on the operating mode,timer T14 may provide the count increments used by the application and thus determinethe input frequency of the RTC timer, that is, the RTC time base (see also Table 15-3).

The RTC is also supplied with the system clock fSYS of the XC164. This clock signal isused to control the RTC’s logic blocks and its bus interface. To synchronize properly tothe count clock, the system clock must run at least four times faster than the count clock,this means fSYS ≥ 4 × fCNT.

Figure 15-2 RTC Clock Supply Block Diagram

For an example, Table 15-1 lists the interrupt period range and the T14 reload values(for a time base of 1 s and 1 ms):

Note: Select one value from the reload value pairs, depending if the 8:1 prescaler isdisabled/enabled.

Table 15-1 RTC Time Base Examples

Oscillator Frequency

T14 Intr. Period Reload Value A Reload Value B

Min. Max. T14REL Base T14REL Base

4 MHz 8.0 µs 4.194 s ------H/C2F7H

1.000 s FF83H/FFF0H

1.000 ms/ 1.024 ms

ClockGeneration

UnitMCB05413_X4

8:1 MUX

PRE

fCNTRTCCountClock

1

0

fSYS32:1

>1

fOSCmMainOSC

fRTC

RUN

MUX RTCModuleClock

RTCCMSYSCON0.14

1

0Sync Mode

Async Mode



Real Time Clock

Asynchronous Operation

When the system clock frequency becomes lower than 4 × fCNT proper synchronizationis not possible and count events may be missed. When the XC164 enters e.g. sleepmode the system clock stops completely and the RTC would stop counting.

In these cases the RTC can be switched to Asynchronous Mode (by setting bit RTCCMin register SYSCON0). In this mode the count registers are directly controlled by thecount clock independent of the system clock (hence the name). Asynchronous operationensures correct time-keeping even during sleep mode or powerdown mode.

However, as no synchronization between the count registers and the bus interface canbe maintained in asynchronous mode, the RTC registers cannot be written. Readaccesses may interfere with count events and, therefore, must be verified (e.g. byreading the same value with three consecutive read accesses).

Note: The access restrictions in asynchronous mode are only meaningful if the systemclock is not switched off, of course.

Switching Clocking Modes

The clocking mode of the RTC (synchronous or asynchronous) is selected via bitRTCCM in register SYSCON0. After reset, the RTC operates in Synchronous Mode(RTCCM = 0) with the 8:1 prescaler enabled.

The selected clocking mode also affects the access to RTC registers. Bit ACCPOS inregister RTC_CON indicates if full register access is possible (ACCPOS = 1, defaultafter reset) or not (ACCPOS = 0). This also indicates the current clocking mode.

Attention: Software should poll bit ACCPOS to determine the proper transition tothe intended clocking mode.

After switching to Asynchronous Mode (RTCCM = 1), bit ACCPOS = 0 indicates properoperation in Asynchronous Mode. In this case the system clock can be stopped orreduced.

After switching to Synchronous Mode, (RTCCM = 0), bit ACCPOS = 1 indicates properoperation in Synchronous Mode. In this case the RTC registers can again be accessedproperly (read and write).

Note: The RTC might lose a counting event (edge of fCNT) when switching fromsynchronous mode to asynchronous mode while the 8:1 prescaler is disabled. Forthese applications it is, therefore, recommended to set up the RTC with the 8:1prescaler enabled.



Real Time Clock

Increased RTC Accuracy through Software Correction

The accuracy of the XC164’s RTC is determined by the oscillator frequency and by therespective prescaling factor (excluding or including T14 and the 8:1 prescaler). Theaccuracy limit generated by the prescaler is due to the quantization of a binary counter(where the average is zero), while the accuracy limit generated by the oscillatorfrequency is due to the difference between the ideal and real frequencies (and thereforeaccumulates over time). This effect is predictable and can be compensated. The totalaccuracy of the RTC can be further increased via software for specific applications thatdemand a high time accuracy.

The key to the improved accuracy is knowledge of the exact oscillator frequency. Therelation of this frequency to the expected ideal frequency is a measure of the RTC’sdeviation. The number of cycles, N, after which this deviation causes an error of ±1 cyclecan be easily computed. So, the only action is to correct the count by ±1 after each seriesof N cycles. The correction may be made cyclically, for instance, within an interruptservice routine, or by evaluating a formula when the RTC registers are read (for this therespective “last” RTC value must be available somewhere).

Note: For the majority of applications, however, the standard accuracy provided by theRTC’s structure will be more than sufficient.

Adjusting the current RTC value would require reading and then writing the complete48-bit value. This can only be accomplished by three successive accesses each. Toavoid the hassle of reading/writing multi-word values, the RTC incorporates a correctionoption to simply add or suppress one count pulse.

This is done by setting bit T14INC or T14DEC, respectively, in register RTC_CON. Thiswill add an extra count pulse (T14INC) upon the next count event, or suppress the nextcount event (T14DEC). The respective bit remains set until its associated action hasbeen performed and is automatically cleared by hardware after this event.

Note: Setting both bits, T14INC and T14DEC, at the same time will have no effect on thecount values.



Real Time Clock

15.2 RTC Run Control

If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset).Bit RUN can be cleared, for example, to exclude certain operation phases from timekeeping. The RTC can be completely disabled by setting the corresponding bit RTCDISin register SYSCON3.

Note: A valid count clock is required for proper RTC operation, of course.

A reset for the RTC is triggered via software by setting bit RTCRST in registerSYSCON0. In this case all RTC registers are set to their initial values and bit RTCRSTis cleared automatically. A normal system reset does not affect the RTC registers and itsoperation (RTC_IC will be reset, however). The initialization software must ensure theproper RTC operating mode.

The RTC control register RTC_CON selects the basic operation of the RTC module.

RTC_CON Control Register ESFR (F110H/88H) Reset Value: 8003H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC POS

- - - - - - - - - - -T14 INC

T14 DEC

PRE RUN

rh - - - - - - - - - - - rwh rwh rw rw


ACCPOS 15 rh RTC Register Access Possible0 No write access is possible, only

asynchronous reads1 Registers can be read and written

T14INC 3 rwh Increment Timer T14 ValueSetting this bit to 1 adds one count pulse upon the next count event, thus incrementing T14.This bit is cleared by hardware after incrementation.

T14DEC 2 rwh Decrement Timer T14 ValueSetting this bit to 1 suppresses the next count event, thus decrementing T14.This bit is cleared by hardware after decrementation.



Real Time Clock

PRE 1 rw RTC Input Source Prescaler Enable0 Prescaler disabled, T14 clocked with fRTC1 Prescaler enabled, T14 clocked with fRTC/8

RUN 0 rw RTC Run Bit0 RTC stopped1 RTC runs




Real Time Clock

15.3 RTC Operating Modes

The RTC can be configured for several operating modes according to the purpose it ismeant to serve. These operating modes are configured by selecting appropriate reloadvalues and interrupt signals.

Figure 15-3 RTC Block Diagram

RTC Register Access

The actual value of the RTC is indicated by the three registers T14, RTCL, and RTCH.As these registers are concatenated to build the RTC counter chain, internal overflowsoccur while the RTC is running. When reading or writing the RTC value, such internaloverflows must be taken into account to avoid reading/writing corrupted values.

Care must be taken, when reading the timer(s), as this requires up to three readaccesses to the different registers with an inherent time delay between the accesses. Anoverflow from T14 to RTCL and/or from RTCL to RTCH might occur between theaccesses, which needs to be taken into account appropriately.

For example, reading/writing 0000H to RTCH and then accessing RTCL could producea corrupted value as RTCL may overflow before it can be accessed. In this case, RTCHwould be 0001H. The same precautions must be taken for T14 and T14REL.

m cb04805_xc.vsd

T14R E L

T14

T14-Register CNT-Register

REL-Register

10 B its 6 B its 6 B its 10 B its

10 B its 6 B its 6 B its 10 B its

In terrupt S ub N ode

C N TIN T0

C N TIN T1

C N TIN T2

C N TIN T3

R TC IN T1

0

8

R U N P R E

fR T C

M U X

fC N T



Real Time Clock

Timer T14 and its reload register are accessed via dedicated locations. The four RTCcounters CNT3 … CNT0 are accessed via the two 16-bit RTC timer registers, RTCH andRTCL. The associated four reload values REL3 … REL0 are accessed via the two 16-bitRTC reload registers, RELH and RELL.

Table 15-2 Register Locations for Timer T14

Register Name Long/Short Address

Reset Value

Notes

RTC_T14 F0D2H/69H 0000H 16-bit timer, can be used as prescaler for the RTC block

RTC_T14REL F0D0H/68H 0000H Timer T14 reload register

RTC_RTCH RTC Timer High Register ESFR (F0D6H/6BH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT3 CNT2

rwh rwh

RTC_RTCLRTC Timer Low Register ESFR (F0D4H/6AH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT1 CNT0

rwh rwh


CNTx(x = 3 … 0)

[15:6][5:0][15:10][9:0]

rwh RTC Timer Count Section CNTxAn overflow of this bitfield triggers a count pulse to the next count section CNTx+1 (except for CNT3) followed by a reload of CNTx from bitfield RELx.In addition, an interrupt request is triggered.



Real Time Clock

Note: The registers of the RTC receive their reset values only upon a specific RTC reset.This reset is not triggered upon a system reset, but via software.

RTC_RELH RTC Reload High Register ESFR (F0CEH/67H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REL3 REL2

rw rw

RTC_RELLRTC Reload Low Register ESFR (F0CCH/66H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REL1 REL0

rw rw


RELx(x = 3 … 0)

[15:6][5:0][15:10][9:0]

rw RTC Reload Value RELxThis bitfield is copied to bitfield CNTx upon an overflow of count section CNTx.



Real Time Clock

15.3.1 48-bit Timer Operation

The concatenation of timers T14 and COUNT0 … COUNT3 can be regarded as a 48-bittimer which is clocked with the RTC input frequency, optionally divided by the prescaler.The reload registers T14REL, RELL, and RELH must be cleared to produce a true binary48-bit timer. However, any other reload value may be used. Reload values other thanzero must be used carefully, due to the individual sections of the RTC timer with theirown individual overflows and reload values.

The maximum usable timespan is 248 (≈ 1014) T14 input clocks (assuming no prescaler),which would equal more than 200 years at an oscillator frequency of 32 kHz.

15.3.2 System Clock Operation

A real time system clock can be maintained that keeps on running also during powersaving modes (optionally) and indicates the current time and date. This is possiblebecause the RTC module is not affected by a system reset1).

The resolution for this clock information is determined by the input clock of timer T14. Byselecting appropriate reload values each cascaded timer can represent directly a part ofthe current time and/or date. Due to its width, T14 can adjust the RTC to the intendedrange of operation (time or date). The maximum usable timespan is achieved whenT14REL is loaded with 0000H and so T14 divides by 216.

System Clock Example

The RTC count clock is fOSCm/32 (8:1 prescaler off). With fOSCm = 4 MHz, the resultingcount clock is fCNT = 125 kHz. By selecting appropriate reload values the RTC timersdirectly indicate the current time (see Figure 15-4 and Table 15-3).

Figure 15-4 RTC Configuration Example

Note: This setup can generate an interrupt request every millisecond, every second,every minute, every hour, or every day.

1) After a power on reset, however, the RTC registers are undefined.

MCA05414_X4

Hours

REL3

3E8H

CNT3

Minutes

REL2

04H

CNT2

Seconds

REL1

04H

CNT1

1/1000Seconds

REL0

018H

CNT0

Prescaler

T14REL

FF83H

T14

fCNT =125 kHz



Real Time Clock

Each timer in the chain divides the clock by (2<timer_width> - <reload_value>) : 1, as thetimers count up. Table 15-3 shows the reload values which must be chosen for a specificscenario (i.e. operating mode of the RTC).

15.3.3 Cyclic Interrupt Generation

The RTC module can generate an interrupt request whenever one of the timersoverflows and is reloaded. This interrupt request may be used, for example, to providea system time tick independent of the CPU frequency without loading the generalpurpose timers, or to wake up regularly from sleep mode. The interrupt cycle time canbe adjusted by choosing appropriate reload values and by enabling the appropriateinterrupt request.

In this mode, the other operating modes can be combined. For example, a reload valueof T14REL = F9C0H (216 - 1600) generates a T14 interrupt request every 50 ms to wake-up the system regularly. Still the subsequent timers can be configured to represent thetime or build a binary counter, however with a different time base.

Table 15-3 Reload Value Scenarios

REL3 REL2 REL1 REL0 T14REL

Tim

e o

f D

ay(F

igu

re15

-4) Formula 210 - 24 26 - 60 26 - 60 210 - 1000 216 - 125

Rel. Value 3E8H 04H 04H 018H FF83H

Function h m s 1/1000 s Prescaler

Intr. Period day hour minute second millisec.

Day

of

the

Wee

k

Formula 210 - 7 26 - 24 26 - 60 210 - 600 216 - 12500

Rel. Value 3F9H 28H 04H 1A8H CF2CH

Function day h m 1/10 s Prescaler

Intr. Period week day hour minute 100 millisec



Real Time Clock

15.4 RTC Interrupt Generation

The overflow signals of each timer of the RTC timer chain can generate an interruptrequest. The RTC’s interrupt subnode control register ISNC combines these requests toactivate the common RTC interrupt request line RTC_IRQ.

Each timer overflow sets its associated request flag in register ISNC. Individual enablebits for each request flag determine whether this request also activates the commoninterrupt line. The enabled requests are ORed together on this line (see Figure 15-5).

The interrupt handler can determine the source of an interrupt request via the specificrequest flags and must clear them after appropriate processing (not cleared byhardware). The common node request bit is automatically cleared when the interrupthandler is vectored to.

Note: If only one source is enabled, no additional software check is required, of course.Both the individual request and the common interrupt node must be enabled.

Figure 15-5 Interrupt Block Diagram

MCB05415

>1_Interrupt RequestRTC_IRQ

&

&

&

&

&

Register RTC_ISNC

CNT3IR

CNT3IE

Set

SW Clear

CNT2IR

CNT2IE

Set

SW Clear

CNT1IR

CNT1IE

Set

SW Clear

CNT0IR

CNT0IE

Set

SW Clear

T14IR

T14IE

Set

SW Clear

CNT3 Overflow

CNT2 Overflow

CNT1 Overflow

CNT0 Overflow

T14 Overflow



Real Time Clock

Note: The interrupt request flags in register ISNC must be cleared by software. They arenot cleared automatically when the service routine is entered.

Note: Please refer to the general Interrupt Control Register description for anexplanation of the control fields.Register RTC_IC is not part of the RTC module and is reset with any system reset.

RTC_ISNC Interrupt Subnode Ctrl. Reg. ESFR (F10CH/86H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - -CNT3IR

CNT3IE

CNT2IR

CNT2IE

CNT1IR

CNT1IE

CNT0IR

CNT0IE

T14 IR

T14 IE

- - - - - - rwh rw rwh rw rwh rw rwh rw rwh rw


CNTxIR(x = 3 … 0)

9, 7, 5, 3

rwh Section CNTx Interrupt Request Flag0 No request pending1 This source has raised an interrupt request

CNTxIE(x = 3 … 0)

8, 6, 4, 2

rw Section CNTx Interrupt Enable Control Bit0 Interrupt request is disabled1 Interrupt request is enabled

T14IR 1 rwh T14 Overflow Interrupt Request Flag0 No request pending1 This source has raised an interrupt request

T14IE 0 rw T14 Overflow Interrupt Enable Control Bit0 Interrupt request is disabled1 Interrupt request is enabled

RTC_IC RTC Interrupt Ctrl. Reg. ESFR (F1A0H/D0H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - GPXRTCIR

RTCIE

ILVL GLVL

- - - - - - - rw rwh rw rw rw



The Analog/Digital Converter

16 The Analog/Digital Converter The XC164 provides an Analog/Digital Converter with 8-bit or 10-bit resolution and asample & hold circuit on-chip. An input multiplexer selects between up to 14 analog inputchannels (alternate functions of Port 5) either via software (fixed channel modes) orautomatically (auto scan modes).

To fulfill most requirements of embedded control applications the ADC supports thefollowing conversion modes:

• Fixed Channel Single Conversionproduces just one result from the selected channel

• Fixed Channel Continuous Conversionrepeatedly converts the selected channel

• Auto Scan Single Conversionproduces one result from each of a selected group of channels

• Auto Scan Continuous Conversionrepeatedly converts the selected group of channels

• Wait for ADDAT Read Modestart a conversion automatically when the previous result was read

• Channel Injection Modestart a conversion when a hardware trigger occurs,can insert the conversion of a specific channel into a group conversion (auto scan)

A set of SFRs and port pins provide access to control functions and results of the ADC.The enhanced-mode registers provide more detailed control functions for the ADC.

Figure 16-1 SFRs and Port Pins Associated with the A/D Converter

mc_adc0101_registers_x4.vsd

Data Registers Control Registers System Registers

ADC_DAT ADC_CON ADC_CIC

ADC_EIC

P5

P5DIDIS E

Interrupt Control

SYSCON3

Compatibility Mode:ADC_CON ADC Control RegisterADC_CON1 ADC Control Register 1Enhanced Mode:ADC_CTR0 ADC Control Register 0ADC_CTR2 ADC Control Register 2ADC_CTR2IN ADC Control Injection Register

ADC_DAT ADC Result RegisterADC_DAT2 ADC Injection Result RegisterADC_CIC ADC End-of-Conversion Intr. Reg.ADC_EIC ADC Conversion-Error Intr. Reg.P5 Port 5 Analog Input Port

(AN15...AN10, AN7...AN0)P5DIDIS Port 5 Digital Input Disable Reg.

ADC_DAT2 E ADC_CON1

ADC_CTR0

ADC_CTR2

ADC_CTR2IN

User’s Manual 16-1 V2.1, 2004-03ADC_X41, V2.1



The external analog reference voltages VAREF and VAGND are fixed. The separate supplyfor the ADC reduces the interference with other digital signals. The reference voltagesmust be stable during the reset calibration phase and during an entire conversion, toachieve a maximum of accuracy.

The sample time as well as the conversion time is programmable, so the ADC can beadjusted to the internal resistances of the analog sources and/or the analog referencevoltage supply (you may also want to refer to application note AP2428).

Figure 16-2 Analog/Digital Converter Block Diagram

The ADC is implemented as a capacitive network using successive approximationconversion. A conversion consists of 3 phases.

• During the sample phase, the capacitive network is connected to the selected analoginput and is charged or discharged to the voltage of the analog signal.

• During the actual conversion phase, the network is disconnected from the analoginput and is repeatedly charged or discharged via VAREF during the steps ofsuccessive approximation.

• After the (optional) post-calibration phase (to adjust the network to changingconditions such as temperature) the result is written to the result register and aninterrupt request is generated.

There are two sets of control, data, and status registers, one set for compatibility modeand one set for enhanced mode. Only one of these register sets may be active at a giventime. As most of the bits and bitfields of the registers of the two sets control the samefunctionality or control the functionality in a very similar way, the following description isorganized according to the functionality, not according to the two register sets.

MCB05416

Conversion ControlADC_CIRQ

Sample&

Hold

8/10-bitCapacitive Network

Conversion

ADC_EIRQ

MU

XCON1 CTR2INCON CTR2

CTR0

DAT

DAT2

MUXAN0

AN7

AN12

AN15

RequestsInjection




16.1 Mode Selection

The analog input channels AN15 … AN10, AN7 … AN0 are alternate functions of Port 5which is an input-only port. The Port 5 lines may either be used as analog or digitalinputs. For pins that shall be used as analog inputs it is recommended to disable thedigital input stage via register P5DIDIS. This avoids undesired cross currents andswitching noise while the (analog) input signal level is between VIL and VIH.

The functions of the A/D converter are controlled by two sets of bit-addressable controlregisters. In compatibility mode, registers ADC_CON and ADC_CON1 are used, inenhanced mode, registers ADC_CTR0, ADC_CTR2, and ADC_CTR2IN are used. Theirbitfields specify the analog channel to be acted upon, the conversion mode, and alsoreflect the status of the converter.

16.1.1 Compatibility Mode

In compatibility mode (MD = 0), registers ADC_CON and ADC_CON1 select the basicfunctions. The register layout is compatible with previous versions of the ADC module,while providing limited options.

ADC_CON ADC Control Register SFR (FFA0H/D0H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADCTC ADSTCAD

CRQAD CIN

AD WR

AD BSY

AD ST

- ADM ADCH

rw rw rwh rw rw rwh rwh - rw rw

Field Bits Type Function

ADCTC [15:14] rw ADC Conversion Time Control (Defines the ADC basic conversion clock fBC)00 fBC = fADC/401 fBC = fADC/210 fBC = fADC/1611 fBC = fADC/8

ADSTC [13:12] rw ADC Sample Time Control (Defines the ADC sample time in a certain range)00 tBC × 801 tBC × 1610 tBC × 3211 tBC × 64

ADCRQ 11 rwh ADC Channel Injection Request Flag

ADCIN 10 rw ADC Channel Injection Enable




ADWR 9 rw ADC Wait for Read Control

ADBSY 8 rh ADC Busy Flag0 ADC is idle1 A conversion is active

ADST 7 rwh ADC Start Bit0 Stop a running conversion1 Start conversion(s)

ADM [5:4] rw ADC Mode Selection00 Fixed Channel Single Conversion01 Fixed Channel Continuous Conversion10 Auto Scan Single Conversion11 Auto Scan Continuous Conversion

ADCH [3:0] rw ADC Analog Channel Input SelectionSelects the (first) ADC channel which is to be converted.

ADC_CON1 ADC Control Register 1 SFR (FFA6H/D3H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ICSTSAMPLE

CAL RES ADCTC ADSTC

rw rh rh rw rw rw


ICST 15 rw Improved Conversion and Sample TimingSelects the active timing control bitfields0 Standard conversion and sample time control,

2-bit fields in ADC_CON (default after reset)1 Improved conversion and sample time control,

6-bit fields in ADC_CON1

SAMPLE 14 rh Sample Phase Status Flag0 A/D Converter is not in sampling1 A/D Converter is currently in the sample phase

CAL 13 rh Reset Calibration Phase Status Flag0 A/D Converter is not in calibration phase1 A/D Converter is in calibration phase





Note: The limit values for fBC (see data sheet) must not be exceeded when selectingADCTC and fADC.

16.1.2 Enhanced Mode

In enhanced mode (MD = 1), registers ADC_CTR0, ADC_CTR2, and ADC_CTR2INselect the basic functions. The register layout differs from the compatibility-mode layout,but this mode provides more options.

Conversion timing is selected via registers ADC_CTR2(IN), where ADC_CTR2 controlsstandard conversions and ADC_CTR2IN controls injected conversions.

RES 12 rw Conversion Resolution Control0 10-bit resolution (default after reset)1 8-bit resolution

ADCTC [11:6] rw ADC Conversion Time ControlDefines the ADC basic conversion clock:fBC = fADC / (<ADCTC> + 1)

ADSTC [5:0] rw ADC Sample Time ControlDefines the ADC sample time:tS = tBC × 4 × (<ADSTC> + 1)

ADC_CTR0 ADC Control Register 0 SFR (FFBEH/DFH) Reset Value: 1000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MDSAMPLE

ADCTSAD

CRQADCIN

ADWR

ADBSY

ADST

ADMCAL OFF

ADCH

rw rh rw rwh rw rw rh rwh rw rw rw


MD 15 rw Mode Control0 Compatibility Mode1 Enhanced Mode

Note: Any modification of control bit MD is forbiddenwhile a conversion is currently running. Usersoftware must take care.

SAMPLE 14 rh Sample Phase Status Flag0 A/D Converter is not in sample phase1 A/D Converter in sample phase





ADCTS [13:12] rw Channel Injection Trigger Input Select00 Channel injection trigger input disabled01 Trigger input CAPCOM2 selected10 Trigger input CAPCOM6 selected11 Reserved

Note: Reset value of bitfield ADCTS is 01B forcompatibility purposes.

ADCRQ 11 rwh Channel Injection Request Flag

ADCIN 10 rw Channel Injection Enable Control

ADWR 9 rw Wait for Read Control

ADBSY 8 rh Busy Flag0 ADC is idle1 A conversion is active

ADST 7 rwh ADC Start/Stop Control0 Stop a running conversion1 Start conversion(s)

ADM [6:5] rw Mode Selection Control00 Fixed Channel Single Conversion01 Fixed Channel Continuous Conversion10 Auto Scan Single Conversion11 Auto Scan Continuous Conversion

CALOFF 4 rw Calibration Disable Control0 Calibration cycles are executed1 Calibration is disabled (off)

Note: This control bit is active in both compatibilityand enhanced mode.

ADCH [3:0] rw Analog Input Channel SelectionSelects the (first) ADC channel which is to be converted





Note: The limit values for fBC (see data sheet) must not be exceeded when selectingADCTC and fADC.

ADC_CTR2 ADC Control Register 2 ESFR (F09CH/4EH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- RES ADCTC ADSTC

- rw rw rw

ADC_CTR2IN Injection Control Register 2 ESFR (F09EH/4FH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- RES ADCTC ADSTC

r rw rw rw


RES [13:12] rw Converter Resolution Control00 10-bit resolution (default after reset)01 8-bit resolution1x Reserved

ADCTC [11:6] rw ADC Conversion Time ControlDefines the ADC basic conversion clock:fBC = fADC / (<ADCTC> + 1)

ADSTC [5:0] rw ADC Sample Time ControlDefines the ADC sample time:tS = tBC × 4 × (<ADSTC> + 1)




16.2 ADC Operation

Channel Selection, ADCH

Bitfield ADCH controls the input channel multiplexer logic. In the Single Channel Modes,it specifies the analog input channel which is to be converted. In the Auto Scan Modes,it specifies the highest channel number to be converted in the auto scan round.

ADCH may be changed while a conversion is in progress. The new value will go intoeffect after the current conversion is finished in the fixed channel modes, or after thecurrent conversion round is finished in the auto scan modes.

ADC Flags, ADBSY, SAMPLE

The ADC Busy Status Flag is set when the ADC is started (by setting ADST) and remainsset as long as the ADC performs conversions or calibration cycles.

ADBSY is cleared when the ADC is idle, meaning there are no conversion or calibrationoperations in progress.

Bit SAMPLE is set during the sample phase.

ADC Start/Stop Control, ADST

Bit ADST is used to start or to stop the ADC. A single conversion or a conversionsequence is started by setting bit ADST.

The busy flag ADBSY will be set and the converter then selects and samples the inputchannel, which is specified by the channel selection field ADCH. The sampled level willthen be held internally during the conversion. When the conversion of this channel iscomplete, the result together with the number of the converted channel is transferred intothe result register and the interrupt request is generated. The conversion result is placedinto bitfield ADRES.

ADST remains set until cleared either by hardware or by software. Hardware clears thebit dependent on the conversion mode:

• In Fixed Channel Single Conversion mode, ADST is cleared after the conversion ofthe specified channel is finished.

• In Auto Scan Single Conversion mode, ADST is cleared after the conversion ofchannel 0 is finished.

Note: In the continuous conversion modes, ADST is never cleared by hardware.

Stopping the ADC via software is performed by clearing bit ADST. The reaction of theADC depends on the conversion mode:

• In Fixed Channel Single Conversion mode, the ADC finishes the conversion and thenstops. There is no difference to the operation if ADST was not cleared by software.

• In Fixed Channel Continuous Conversion mode, the ADC finishes the currentconversion and then stops. This is the usual way to terminate this conversion mode.




• In Auto Scan Single Conversion mode, the ADC continues the auto scan round untilthe conversion of channel 0 is finished, then it stops. There is no difference to theoperation if ADST was not cleared by software.

• In Auto Scan Continuous Conversion mode, the ADC continues the auto scan rounduntil the conversion of channel 0 is finished, then it stops. This is the usual way toterminate this conversion mode.

A restart of the ADC can be performed by clearing and then setting bit ADST. Thissequence will abort the current conversion and restart the ADC with the new parametersgiven in the control registers.

Conversion Mode Selection, ADM

Bitfield ADM selects the conversion mode of the A/D converter, as listed in Table 16-1.

While a conversion is in progress, the mode selection field ADM and the channelselection field ADCH may be changed. ADM will be evaluated after the currentconversion. ADCH will be evaluated after the current conversion (fixed channel modes)or after the current conversion sequence (auto scan modes).

Conversion Resolution Control, RES

The ADC can produce either a 10-bit result (RES = 0) or an 8-bit result (RES = 1).Depending on the application’s needs a higher conversion speed (an 8-bit conversionrequires less conversion time) or a higher resolution can be chosen.

Table 16-1 A/D Converter Conversion Mode

ADM Description

00 Fixed Channel Single Conversion

01 Fixed Channel Continuous Conversion

10 Auto Scan Single Conversion

11 Auto Scan Continuous Conversion




Conversion Result

The result of a conversion is stored in the result register ADC_DAT, or in registerADC_DAT2 for an injected conversion.

The position of the result depends on the basic operating mode (compatibility orenhanced) and on the selected resolution (8-bit or 10-bit).

Note: Bitfield CHNR of register ADC_DAT is loaded by the ADC to indicate, whichchannel the result refers to. Bitfield CHNR of register ADC_DAT2 is loaded by theCPU to select the analog channel, which is to be injected.

ADC_DATADC Result Register SFR (FEA0H/50H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNR ADRES

rwh rwh

ADC_DAT2ADC Chan. Inj. Result Reg. ESFR (F0A0H/50H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHNR ADRES

rw rwh


CHNR [15:12] rw[h] Channel Number (identifies the converted analog channel)

ADRES [11:0] rwh A/D Conversion ResultThe digital result of the most recent conversion.In compatibility mode, the result is placed as follows:8-bit: ADRES[9:2]10-bit: ADRES[9:0]In enhanced mode, the result is placed as follows:8-bit: ADRES[11:4]10-bit: ADRES[11:2]

Note: Unused bits of ADRES are always set to 0.




16.2.1 Fixed Channel Conversion Modes

These modes are selected by programming the mode selection bitfield ADM to 00B(single conversion) or to 01B (continuous conversion). After starting the converterthrough bit ADST the busy flag ADBSY will be set and the channel specified in bitfieldADCH will be converted. After the conversion is complete, the interrupt request flagADCIR will be set.

In Single Conversion Mode the converter will automatically stop and reset bits ADBSYand ADST.

In Continuous Conversion Mode the converter will automatically start a newconversion of the channel specified in ADCH. ADCIR will be set after each completedconversion.

When bit ADST is reset by software, while a conversion is in progress, the converter willcomplete the current conversion and then stop and reset bit ADBSY.




16.2.2 Auto Scan Conversion Modes

These modes are selected by programming the mode selection field ADM to 10B (singleconversion) or to 11B (continuous conversion). Auto Scan modes automatically converta sequence of analog channels, beginning with the channel specified in bitfield ADCHand ending with channel 0, without requiring software to change the channel number.After starting the converter through bit ADST, the busy flag ADBSY will be set and thechannel specified in bitfield ADCH will be converted. After the conversion is complete,the interrupt request flag ADCIR will be set and the converter will automatically start anew conversion of the next lower channel. ADCIR will be set after each completedconversion. After conversion of channel 0 the current sequence is complete.

In Single Conversion Mode the converter will automatically stop and reset bits ADBSYand ADST.

In Continuous Conversion Mode the converter will automatically start a new sequencebeginning with the conversion of the channel specified in ADCH.

When bit ADST is reset by software, while a conversion is in progress, the converter willcomplete the current sequence (including conversion of channel 0) and then stop andreset bit ADBSY.

Figure 16-3 Auto Scan Conversion Mode Example

Note: Auto Scan sequences that begin with channel numbers above 7 will generate (upto) 2 invalid results from channels 9 and 8 which are not connected to input pins.Starting an Auto Scan sequence with ADCH = EH will generate the following15 results: 14, 13, 12, 11, 10, x, x, 7, 6, 5, 4, 3, 2, 1, 0.Starting a sequence with ADCH = 9H or 8H generates 2 or 1 invalid results at thebeginning of the sequence and therefore makes no sense in an application.

# 2

Result of Channel: # x # 3

Write ADC_DATADC_DAT Full

Conversionof Channel..

Read of ADC_DAT;

Generate InterruptRequest

# x

# 3

# 3

# 2

Interrupt RequestOverrun Error

# 2 # 1 Result Lost

MC_ADC0001_AUTOSCAN

# 3

# 1

# 1 # 0

ADC_DAT Full;Channnel 0

# 0 # 3

# 3 # 2




16.2.3 Wait for Read Mode

If in default mode of the ADC a previous conversion result has not been read out of theresult register by the time a new conversion is complete, the previous result is lostbecause it is overwritten by the new value, and the A/D overrun error interrupt requestflag ADEIR will be set.

In order to avoid error interrupts and the loss of conversion results especially when usingcontinuous conversion modes, the ADC can be switched to “Wait for Read Mode” bysetting bit ADWR.

If the result value has not been read by the time the current conversion is complete, thenew result is stored in a temporary buffer and the next conversion is suspended (ADSTand ADBSY will remain set in the meantime, but no end-of-conversion interrupt will begenerated). After reading the previous value the temporary buffer is copied intoADC_DAT (generating an ADCIR interrupt) and the suspended conversion is started.This mechanism applies to both single and continuous conversion modes.

Note: While in standard mode continuous conversions are executed at a fixed rate(determined by the conversion time), in “Wait for Read Mode” there may be delaysdue to suspended conversions. However, this only affects the conversions, if theCPU (or PEC) cannot keep track with the conversion rate.

Figure 16-4 Wait for Read Mode Example

Result of Channel:Read of ADC_DAT;

# x # 2# 3 # 1MC_ADC0002_WAITREAD

# 0

RequestGenerate Interrupt

Temp-Latch FullADC_DAT Full

Write ADC_DAT # x

of Channel..Conversion

# 3

# 2# 3

Temp-LatchHold Result in

1

# 2 # 1 wait

# 1 # 0 # 3

# 3# 0




16.2.4 Channel Injection Mode

Channel Injection Mode allows the conversion of a specific analog channel (also whilethe ADC is running in a continuous or auto scan mode) without changing the currentoperating mode. After the conversion of this specific channel the ADC continues with theoriginal operating mode.

Channel Injection mode is enabled by setting bit ADCIN and requires the Wait for ReadMode (ADWR = 1). The channel to be converted in this mode is specified in bitfieldCHNR of register ADC_DAT2.

Note: Bitfield CHNR in ADC_DAT2 is not modified by the A/D converter, but only theADRES bitfield. Since the channel number for an injected conversion is notbuffered, bitfield CHNR of ADC_DAT2 must never be modified during the samplephase of an injected conversion, otherwise the input multiplexer will switch to thenew channel. It is recommended to only change the channel number with noinjected conversion running.

Figure 16-5 Channel Injection Example

# x-2

Write ADC_DAT2

Int. Request

Conversionof Channel # y

ADC_DAT2 Full

Read ADC_DAT2

Request

Conversion

Write ADC_DAT;

Injected

Read ADC_DAT

ADC_DAT Full

of Channel..

Channel Injection

# x-1

# x+1

# x+1

# x

# x

# x

# x-1

# x-1

# x-2

MC_ADC0003_INJECT

ADEINT

# ...

# x-4

# y

# x-2

# x-3

# x-3

# x-3 # x-4

# x-4




A channel injection can be triggered in three ways:

• setting of the Channel Injection Request bit ADCRQ via software• a compare or a capture event of Capture/Compare register CC31 of the CAPCOM2

unit, which also sets bit ADCRQ• a period-match of timer T13 of the CAPCOM6 unit, which also sets bit ADCRQ.

The second method triggers a channel injection at a specific time, on the occurrence ofa predefined count value of the CAPCOM2 timers, stored in register CC31.

Note: The channel injection request bit ADCRQ will be set on any selected injectiontrigger (interrupt request of CAPCOM2 channel CC31 or period match ofCAPCOM6 timer T13), regardless whether the channel injection mode is enabledor not. It is recommended to always clear bit ADCRQ before enabling the channelinjection mode.

After the completion of the current conversion (if any is in progress) the converter willstart (inject) the conversion of the specified channel. When the conversion of thischannel is complete, the result will be placed into the alternate result registerADC_DAT2, and a Channel Injection Complete Interrupt request will be generated,which uses the interrupt request flag ADEIR (for this reason the Wait for Read Mode isrequired).

Note: The result of an injected conversion is directly written to ADC_DAT2. If theprevious result has not been read in the meantime, it is overwritten.Standard conversions are suspended if the temporary buffer is full.




Arbitration of Conversions

Conversion requests that are activated while the ADC is idle immediately trigger therespective conversion. If a conversion is requested while another conversion is currentlyin progress the operation of the A/D converter depends on the kind of the involvedconversions (standard or injected).

Note: A conversion request is activated if the respective control bit (ADST or ADCRQ)is toggled from 0 to 1, i.e. the bit must have been zero before being set.

Table 16-2 summarizes the ADC operation in the possible situations.

Table 16-2 Conversion Arbitration

Conversion in Progress

New Requested Conversion

Standard Injected

Standard Abort running conversion,and start requested new conversion.1)

1) If an injected conversion is pending when a standard conversion is re-started, the injected conversion isexecuted before the newly started standard conversion.

Complete running conversion,start requested conversion after that.

Injected Complete running conversion,start requested conversion after that.

Complete running conversion,start requested conversion after that.Bit ADCRQ will be 0 for the second conversion, however.




16.3 Automatic Calibration

The ADC of the XC164 features automatic self-calibration. This calibration corrects gainerrors, which are mainly due to process variation, and offset errors, which are mainly dueto temperature changes.

Two types of calibration are supported:

• Reset calibration performs a thorough basic calibration of the ADC after a reset. Inparticular this is required after a power-on reset.

• Post-calibration performs one small calibration step after each conversion.

Reset Calibration

After a reset, a thorough power-up calibration is performed automatically to correct gainand offset errors of the A/D converter. To achieve best calibration results, the referencevoltages as well as the supply voltages must be stable during the power-up calibration.During the calibration sequence a series of calibration cycles is executed, where the stepwidth for adjustments is reduced gradually. The total number of executed calibrationcycles depends on the actual properties of the respective ADC module. The maximumduration of the power-up calibration is 11,696 cycles of the basic clock fBC.

Status flag CAL is set as long as this power-up calibration takes place.

Note: The reset calibration must be completed (CAL = 0) before entering Sleep mode,Idle mode, or Powerdown mode. Otherwise, the analog comparator remainsactive and draws its supply current, which is undesired during power-saveconditions.

Post-Calibration

After each conversion a small calibration step can be executed. For 8-bit and 10-bitconversions post-calibration is not mandatory in order not to exceed the total unadjustederror (TUE) specified in the data sheet. Post-calibration can be disabled by setting bitCALOFF in register ADC_CTR0. When disabled, the post-calibration cycles are skippedwhich reduces the total conversion time.

Note: Calibration may be disabled only after the reset calibration is complete.




16.4 Conversion Timing Control

When a conversion is started, first the capacitances of the converter are loaded via therespective analog input pin to the current analog input voltage. The time to load thecapacitances is referred to as sample time. Next the sampled voltage is converted to adigital value in successive steps, which correspond to the resolution of the ADC. Duringthese phases (except for the sample time) the internal capacitances are repeatedlycharged and discharged via pins VAREF and VAGND.

The current that has to be drawn from the sources for sampling and changing chargesdepends on the time that each respective step takes, because the capacitors must reachtheir final voltage level within the given time, at least with a certain approximation. Themaximum current, however, that a source can deliver, depends on its internal resistance.

The time that the two different actions during conversion take (sampling, and converting)can be programmed within a certain range in the XC164 relative to the CPU clock. Theabsolute time that is consumed by the different conversion steps therefore isindependent from the general speed of the controller. This allows adjusting the A/Dconverter of the XC164 to the properties of the system:

Fast Conversion can be achieved by programming the respective times to theirabsolute possible minimum. This is preferable for scanning high frequency signals. Theinternal resistance of analog source and analog supply must be sufficiently low,however.

High Internal Resistance can be achieved by programming the respective times to ahigher value, or the possible maximum. This is preferable when using analog sourcesand supply with a high internal resistance in order to keep the current as low as possible.The conversion rate in this case may be considerably lower, however.

Control Bitfields

For the timing control of the conversion and the sample phase two mechanisms areprovided:

• Standard timing control uses two 2-bit fields in register ADC_CON to selectprescaler values for the general conversion timing and the duration of the samplephase. This provides compact control, while limiting the prescaler factors to a fewsteps.

• Improved timing control uses two 6-bit fields in register ADC_CON1 (compatibilitymode) or register ADC_CTR2/ADC_CTR2IN (enhanced mode). This provides a widerange of prescaler factors, so the ADC can be better adjusted to the internal andexternal system circumstances.

Improved timing control is selected by setting bit ICST in register ADC_CON1 incompatibility mode, or by selecting enhanced mode.




Standard Timing Control

Standard timing control is performed by using two 2-bit fields in register ADC_CON.Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), usedfor the operation of the A/D converter. The sample time is derived from this conversionclock and controlled by bitfield ADSTC. The sample time is always a multiple of 8 fBCperiods. Table 16-3 lists the possible combinations.

Improved Timing Control

To provide a finer resolution for programming of the timing parameters, wider bitfieldshave been implemented for timing control (the 2-bit bitfields in register ADC_CON aredisregarded in all cases).

In compatibility mode (with bit ICST = 1), the bitfields in register ADC_CON1 are usedfor all conversions.In enhanced mode (bit MD = 1), the bitfields in register ADC_CTR2 are used forstandard conversions. Injected conversions use the bitfields in register ADC_CTR2IN.

Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), usedfor the operation of the A/D converter. The sample time is derived from this conversionclock and controlled by bitfield ADSTC. The sample time is always a multiple of 4 fBCperiods. Table 16-4 lists the possible combinations.

Table 16-3 Standard Conversion and Sample Timing Control

ADC_CON.15|14 (ADCTC)

A/D Converter Basic Clock fBC

1)ADC_CON.13|12 (ADSTC)

Sample Time tS

00 fADC/4 00 tBC × 8

01 fADC/2 01 tBC × 16

10 fADC/16 10 tBC × 32

11 fADC/8 11 tBC × 64

Table 16-4 Improved Conversion and Sample Timing Control

ADCTC A/D Converter Basic Clock fBC

1)

1) The limit values for fBC (see data sheet) must not be exceeded when selecting ADCTC and fADC.

ADSTC Sample Time tS

00’0000B = 00H fADC/1 00’0000B = 00H tBC × 8

00’0001B = 01H fADC/2 00’0001B = 01H tBC × 12

00’0010B = 02H fADC/3 00’0010B = 02H tBC × 16

… fADC/(ADCTC + 1) … tBC × 4 × (ADSTC + 2)

11’1111B = 3FH fADC/64 11’1111B = 3FH tBC × 260




Total Conversion Time Examples

The time for a complete conversion includes the sample time tS, the conversion itself(successive approximation and calibration), and the time required to transfer the digitalvalue to the result register as shown in the example below (standard conversion timing).

The timings refer to module clock cycles, where tADC = 1/fADC.

• Assumptions: fADC = 40 MHz (i.e. tADC = 25 ns), ADCTC = 01B, ADSTC = 00B• Basic clock: fBC = fADC/2 = 20 MHz, i.e. tBC = 50 ns• Sample time: tS = tBC × 8 = 400 ns

Conversion 10-bit:

• With post-calibr.: tC10P = tS + 52 × tBC + 6 × tADC = (2600 + 400 + 150) ns = 3.15 µs• Post-calibr. off: tC10 = tS + 40 × tBC + 6 × tADC = (2000 + 400 + 150) ns = 2.55 µs

Conversion 8-bit:

• With post-calibr.: tC8P = tS + 44 × tBC + 6 × tADC = (2200 + 400 + 150) ns = 2.75 µs• Post-calibr. off: tC8 = tS + 32 × tBC + 6 × tADC = (1600 + 400 + 150) ns = 2.15 µs

Note: For the exact specification please refer to the data sheet of the selected derivative.




16.5 A/D Converter Interrupt Control

At the end of each conversion, interrupt request flag ADCIR in interrupt control registerADC_CIC is set. This end-of-conversion interrupt request may cause an interrupt tovector ADCINT, or it may trigger a PEC data transfer which reads the conversion resultfrom register ADC_DAT, e.g. to store it into a table in internal RAM for later evaluation.

The interrupt request flag ADEIR in register ADC_EIC will be set either, if a conversionresult overwrites a previous value in register ADC_DAT (error interrupt in standardmode), or if the result of an injected conversion has been stored into ADC_DAT2 (end-of-injected-conversion interrupt). This interrupt request may be used to cause aninterrupt to vector ADEINT, or it may trigger a PEC data transfer.


ADC_CICADC Conversion Intr. Ctrl. Reg. SFR (FF98H/CCH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- GPXADC

IRADC

IEILVL GLVL

- - - - - - - rw rwh rw rw rw

ADC_EICADC Error Intr. Ctrl. Reg. SFR (FF9AH/CDH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- GPXADE IR

ADE IE

ILVL GLVL

- - - - - - - rw rwh rw rw rw




16.6 Interfaces of the ADC Module

The ADC is connected to its environment in different ways.

Internal Connections

The capture/compare signal CC31IO of the CAPCOM2 unit and the timer T13 periodmatch signal of the CAPCOM6 unit are connected to the ADC, providing optional triggersources for injected conversions.

The 2 interrupt request lines of the ADC are connected to the interrupt control block.

External Connections

The analog input signals for the ADC are connected with Port 5 of the XC164 (inputonly). Two dedicated pins (VAREF and VAGND) provide the analog reference voltage for theconversion mechanism.




Figure 16-6 ADC Module IO Interface

ADCModule

VAREF

ADC_EIRQ

ADC_CIRQ

SystemControl

Unit (SCU)

InterruptControlBlock

fADC

ADCDIS

CC31_CITCAPCOM2Unit

VGND

Port P5Control

MCA05417_X4

P5.0/AN0

P5.1/AN1

P5.2/AN2

P5.3/AN3

P5.4/AN4

P5.5/AN5

P5.6/AN6

P5.7/AN7

P5.8

P5.9

P5.10/AN10

P5.11/AN11

P5.12/AN12

P5.13/AN13

P5.14/AN14

P5.15/AN15

GPT External Inputs

T13_PMCAPCOM6Unit



Capture/Compare Units

17 Capture/Compare UnitsThe XC164 provides two, almost identical, Capture/Compare (CAPCOM) units, whichonly differ in the way they are connected to the pins. Each CAPCOM unit provides16 capture/compare channels, which interact with 2 timers. A CAPCOM channel cancapture the contents of a timer on specific internal or external events, or it can comparea timer’s contents with given values, and modify output signals in case of a match.

Figure 17-1 SFRs Associated with the CAPCOM Units

mc_capcom120101_registers_x4.vsd

Data Registers Control Registers Port Registers

T0, T0REL T01CON T0IC

T1IC

T78CON

CC28IC-CC31IC

P9, DP9

ODP9

Interrupt Control

SYSCON3

CC0...15 CAPCOM1 Register 0...15CC0...15IC CAPCOM1 Intr. Ctrl. Reg. 0...15CCM0...3 CAPCOM1 Mode Ctrl. Reg. 0...3T01CON CAPCOM1 Timer Control Reg.T0, T1 CAPCOM1 Timer RegisterT0/1REL CAPCOM1 Timer Reload RegisterT0IC, T1IC CAPCOM1 Timer x Intr. Ctrl. Reg.CC1/2_SEE CAPCOM Single Event En. Reg.CC1/2_SEM CAPCOM Single Event Mode Reg.CC1/2_DRM CAPCOM Double Reg. Mode Reg.CC1/2_OUT CAPCOM Output RegisterCC1/2_IOC CAPCOM Input/Outp. Control Reg.

CC16...31 CAPCOM2 Register 16...31CC16...31IC CAPCOM2 Intr. Ctrl. Reg. 16...31CCM4...7 CAPCOM2 Mode Ctrl. Reg. 4...7T78CON CAPCOM2 Timer Control Reg.T7, T8 CAPCOM2 Timer RegisterT7/8REL CAPCOM2 Timer Reload RegisterT7IC, T8IC CAPCOM2 Timer x Intr. Ctrl. Reg.Px Port x Data RegisterDPx Port x Direction Control RegisterODPx Port x Open Drain Control RegisterALTSEL0Px Port x Alternate Outp. Select Reg.0SYSCON3 System Ctrl. Reg. 3 (Per. Mgmt.)

T1, T1REL

T7, T7REL

T8, T8REL

E

E

CC0-CC3

CC4-CC7

CC8-CC11

CC12-CC15

CC16-CC19

CC20-CC23

CC24-CC27

CC28-CC31 CC2_M7

CC2_M6

CC2_M5

CC2_M4

CC1_M3

CC1_M2

CC1_M1

CC1_M0

CC24IC-CC27IC

CC20IC-CC23IC

CC16IC-CC19IC

CC12IC-CC15IC

CC8IC-CC11IC

CC4IC-CC7IC

CC0IC-CC3IC

E

E

E

E

T7IC

T8IC

P1L, P1H

DP1L, DP1H E

ALTSEL0/1P9

ALTSEL0P1L/H E

E

CC1/2_OUT

CC1/2_SEE

CC1/2_SEM

CC1/2_DRM

CC1/2_IOC E

User’s Manual 17-1 V2.1, 2004-03CC12_X41, V2.1



With this mechanism, each CAPCOM unit supports generation and control of timingsequences on up to 16 channels with a minimum of software intervention.

From the programmer’s point of view, the term ‘CAPCOM unit’ refers to a set of registerswhich are associated with this peripheral, including the port pins which may be used foralternate input/output functions, and their direction control bits (see also Figure 17-1).

A CAPCOM unit is typically used to handle high speed IO tasks such as pulse andwaveform generation, pulse width modulation, or recording of the time when a specificevent occurs. It also supports the implementation of up to 16 software-controlledinterrupt events.

Each CAPCOM Unit consists of two 16-bit timers (T0/T1, T7/T8), each with its ownreload register (TxREL), and a bank of sixteen dual-purpose 16-bit capture/compareregisters (CCy).

The input clock for the CAPCOM timers is programmable to several prescaled values ofthe module input clock (fCC), or it can be derived from the overflow/underflow of timer T6.T0/T7 may also operate in counter mode (from an external input), clocked by externalevents.

Each capture/compare register may be programmed individually for capture or compareoperation, and each register may be allocated to either of the two timers. Eachcapture/compare register has one signal associated with it, which serves as an inputsignal for the capture operation or as an output signal for the compare operation.

The capture operation causes the current timer contents to be latched into the respectivecapture/compare register, triggered by an event (transition) on the associated inputsignal. This event also activates the associated interrupt request line.

The compare operation may cause an output signal transition on the associated outputsignal, when the allocated timer increments to the value stored in a capture/compareregister. The compare match event also activates the associated interrupt request line.In Double-register compare mode a pair of registers controls one common output signal.

The compare output signals are available via a dedicated output register, and may alsocontrol the output latches of the connected port pins. The output path can be selected.

For the switching of the output signals two timing schemes (see Section 17.8) can beselected:

In Staggered Mode1) the output signals are switched consecutively in 8 steps, whichdistributes the switching steps over a certain time. In staggered mode, the maximumresolution is 8 tCC.

In Non-Staggered Mode the output signals are switched immediately at the same time.In non-staggered mode, the maximum resolution is 1 tCC.

Figure 17-2 shows the basic structure of a CAPCOM unit.

1) Staggered mode is compatible with the CAPCOM units of previous 16-bit controllers.




Figure 17-2 CAPCOM Unit Block Diagram

Timer T0/T7

Sixteen16-bit

Capture/CompareRegisters

Timer T1/T8

Reload Reg.T1REL/T8REL

T0/T7Input

Control

ModeControl

(Captureor

Compare)

T1/T8Input

Control

MCB05418

Reload Reg.T0REL/T7REL

T0IRQ,T7IRQ

CCxIRQ

CCxIRQ

T1IRQ,T8IRQ

CCxIRQ

fCCT0IN/T7INT6OUF

CCxIOCCxIO

CCxIO

fCC

T6OUF

CAPCOM1 provides channels x = 0 … 15, CAPCOM2 provides channels x = 16 … 31.(see signals CCxIO and CCxIRQ)




17.1 The CAPCOM Timers

The primary use of the timers T0/T7 and T1/T8 is to provide two independent time basesfor the capture/compare channels of each unit. The maximum resolution is 8 tCC instaggered mode, and 1 tCC in non-staggered mode.

The basic structure of the two timers, illustrated in Figure 17-3, is identical, except forthe input pin (see mark).

Figure 17-3 Block Diagram of a CAPCOM Timer

Note: When an external input signal is connected to the input lines of both T0 and T7,these timers count the input signal synchronously. Thus, the two timers can beregarded as one timer whose contents can be compared with 32 compareregisters.

The functions of the CAPCOM timers are controlled via the bit-addressable controlregisters T01CON and T78CON. The high-byte of T01CON controls T1, the low-byte ofT01CON controls T0. The high-byte of T78CON controls T8, the low-byte of T78CONcontrols T7. The control options are identical for all four timers (except for external input).

In all modes, the timers are always counting upward. The current timer values areaccessible for the CPU in the timer registers Tx, which are non bit-addressable registers.When the CPU writes to a register Tx in the state immediately before the respective timerincrement or reload is to be performed, the CPU write operation has priority and theincrement or reload is disabled to guarantee correct timer operation.

MCB05419

TxIRQCount

TxR

ReloadReg. TxREL

Timer Tx

toCapure/Compare

Register Array

TxI

TxM

x = 0, 1, 7, 8

T6OUFMUX

TxI

TxIN

Prescaler

TxI

fTxfCC

Edge

Select




The timer run flags TxR allow the starting and stopping of the timers. The followingdescription of the timer modes and operation always applies to the enabled state of thetimers, i.e. the respective run flag is assumed to be set.

CC1_T01CON Timer 0/1 Control Register SFR (FF50H/A8H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- T1R - T1M T1I - T0R - T0M T0I

- rw - rw rw - rw - rw rw

CC2_T78CON Timer 7/8 Control Register SFR (FF20H/90H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- T8R - T8M T8I - T7R - T7M T7I

- rw - rw rw - rw - rw rw


TxR 14, 6 rw Timer/Counter Tx Run Control0 Timer/Counter Tx is disabled1 Timer/Counter Tx is enabled

TxM 11, 3 rw Timer/Counter Tx Mode Selection0 Timer Mode1 Counter Mode

TxI [10:8],[2:0]

rw Timer/Counter Tx Input SelectionTimer Mode (TxM = 0):Input frequency fTx = fCC/2(<TxI>+3) or fCC/2(<TxI>), depending on (non-)staggered mode, see Table 17-1Counter Mode (TxM = 1):000 Overflow/Underflow of GPT Timer T6001 Positive (rising) edge on pin TxIN010 Negative (falling) edge on pin TxIN011 Any edge (rising and falling) on pin TxIN1XX Reserved. Do not use this combination!

Note: For timers T1 and T8 the only option in countermode is 000B. T1 and T8 stop in other cases.




Timer Mode

In Timer Mode (TxM = 0), the input clock for a CAPCOM timer is derived from fCC,divided by a programmable prescaler. Each timer has its own individual prescaler,controlled through the individual bitfields TxI in the timer control registers T01CON andT78CON.

The input frequency fTx for a timer Tx and its resolution rTx are determined by thefollowing formulas:

Staggered Mode:

(17.1)

Non-Staggered Mode:

(17.2)

When a timer overflows from FFFFH to 0000H, it is reloaded with the value stored in itsrespective reload register TxREL. The reload value determines the period PTx betweentwo consecutive overflows of Tx as follows:

Staggered Mode:

(17.3)

Non-Staggered Mode:

(17.4)

After a timer has been started by setting its run flag (TxR), the first increment will occurwithin the time interval which is defined by the selected timer resolution. All furtherincrements occur exactly after the time defined by the timer resolution.

Examples for timer input frequencies, resolution and periods, which result from theselected prescaler option in TxI when using a 40 MHz clock, are listed in Table 17-1below. The numbers for the timer periods are based on a reload value of 0000H. Notethat some numbers may be rounded.

fTx MHz[ ] fCC MHz[ ]

2 <Txl> 3+( )--------------------------= rTx µs[ ] 2 <Txl> 3+( )

fCC MHz[ ]--------------------------=

fTx MHz[ ] fCC MHz[ ]

2<Txl>--------------------------= rTx µs[ ] 2<Txl>

fCC MHz[ ]--------------------------=

PTx µs[ ] 216 <TxREL>–( ) 2×<Txl> 3+( )

fCC MHz[ ]-------------------------------------------------------------------------=

PTx µs[ ] 216 <TxREL>–( ) 2×<Txl>

fCC MHz[ ]----------------------------------------------------------------=




Table 17-1 Timer Tx Input Clock Selection for Timer Mode, fCC = 40 MHz

TxI Prescaler Input Frequency

Resolution Period

Non-Staggered Mode

000B 8 5 MHz 200 ns 13.11 ms

001B 16 2.5 MHz 400 ns 26.21 ms

010B 32 1.25 MHz 800 ns 52.43 ms

011B 64 625 kHz 1.6 µs 104.86 ms

100B 128 312.5 kHz 3.2 µs 209.72 ms

101B 256 156.25 kHz 6.4 µs 419.43 ms

110B 512 78.125 kHz 12.8 µs 838.86 ms

111B 1024 39.0625 kHz 25.6 µs 1677.72 ms

Non-Staggered Mode

000B 1 40 MHz 25 ns 1.6384 ms

001B 2 20 MHz 50 ns 3.2768 ms

010B 4 10 MHz 100 ns 6.5536 ms

011B 8 5 MHz 200 ns 13.11 ms

100B 16 2.5 MHz 400 ns 26.21 ms

101B 32 1.25 MHz 800 ns 52.43 ms

110B 64 625 kHz 1.6 µs 104.86 ms

111B 128 312.5 kHz 3.2 µs 209.72 ms




Counter Mode

In Counter Mode (TxM = 1), the input clock of a CAPCOM timer is either derived from anassociated external input pin, T0IN/T7IN, or from the over-/underflows of GPT timer T6.

Using an external signal connected to pin TxIN as a counting signal is only possible fortimers T0 and T7. The only counter option for timers T1 and T8 is using the over-/underflows of the GPT timer T6 (selected by TxI = 000B).

Bitfields T0I/T7I are used to select either a positive, a negative, or both a positive and anegative transition of the external signal at pin T0IN/T7IN to trigger an increment of timerT0/T7. Please note that certain criteria must be met for the external signal and the portpin programming for this mode in order to operate properly. These conditions aredetailed in Chapter 17.10.

Timer Overflow and Reload

When a CAPCOM timer contains the value FFFFH at the time a new count trigger occurs,a timer interrupt request is generated, and the timer is loaded with the contents of itsassociated reload register TxREL. The timer then resumes incrementing with the nextcount trigger starting from the reloaded value.

The reload registers TxREL are not bitaddressable. After reset, they contain the value0000H.




17.2 CAPCOM Timer Interrupts

Upon a timer overflow the corresponding timer interrupt request flag TxIR for therespective timer will be set. This flag can be used to generate an interrupt or trigger aPEC service request, when enabled by the respective interrupt enable bit TxIE.

Each timer has its own bitaddressable interrupt control register and its own interruptvector. The organization of the interrupt control registers TxIC is identical with the otherinterrupt control registers.


CC1_T0IC CAPCOM T0 Intr. Ctrl. Reg. SFR (FF9CH/CEH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- GPX T0IR T0IE ILVL GLVL

- - - - - - - rw rwh rw rw rw

CC1_T1IC CAPCOM T1 Intr. Ctrl. Reg. SFR (FF9EH/CFH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw

CC2_T7IC CAPCOM T7 Intr. Ctrl. Reg. ESFR (F17AH/BEH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw

CC2_T8IC CAPCOM T8 Intr. Ctrl. Reg. ESFR (F17CH/BFH) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


- - - - - - - rw rwh rw rw rw




17.3 Capture/Compare Channels

The 16-bit capture/compare registers CC0 through CC15 (CC16 through CC31) areused as data registers for capture or compare operations with respect to timers T0/T7and T1/T8. The capture/compare registers are not bit-addressable.

The functions of the 16 capture/compare registers of a unit are controlled by 4 bit-addressable 16-bit mode control registers, named CC1_M0 … CC1_M3 (CC2_M4 …CC2_M7), which are all organized identically (see description below). Each registercontains the bits for mode selection and timer allocation for four capture/comp. registers.

Capture/Compare Registers for the CAPCOM1 Unit (CC15 … CC0)

CC1_M0 CAPCOM Mode Ctrl. Reg. 0 SFR (FF52H/A9H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC3

MOD3ACC

2MOD2

ACC1

MOD1ACC

0MOD0

rw rw rw rw rw rw rw rw

CC1_M1CAPCOM Mode Ctrl. Reg. 1 SFR (FF54H/AAH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC7

MOD7ACC

6MOD6

ACC5

MOD5ACC

4MOD4


CC1_M2CAPCOM Mode Ctrl. Reg. 2 SFR (FF56H/ABH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC11

MOD11ACC10

MOD10ACC

9MOD9

ACC8

MOD8


CC1_M3CAPCOM Mode Ctrl. Reg. 3 SFR (FF58H/ACH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC15

MOD15ACC14

MOD14ACC13

MOD13ACC12

MOD12





Capture/Compare Registers for the CAPCOM2 Unit (CC31 … CC16)

CC2_M4 CAPCOM Mode Ctrl. Reg. 4 SFR (FF22H/91H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC19

MOD19ACC18

MOD18ACC17

MOD17ACC16

MOD16


CC2_M5CAPCOM Mode Ctrl. Reg. 5 SFR (FF24H/92H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC23

MOD23ACC22

MOD22ACC21

MOD21ACC20

MOD20



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC27

MOD27ACC26

MOD26ACC25

MOD25ACC24

MOD24



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ACC31

MOD31ACC30

MOD30ACC29

MOD29ACC28

MOD28



ACCy 15, 11, 7, 3

rw Allocation Bit for CAPCOM Register CCy0 CCy allocated to Timer T0 or T7, respectively1 CCy allocated to Timer T1 or T8, respectively

MODy [14:12],[10:8],[6:4],[2:0]

rw Mode Selection for CAPCOM Register CCySee Table 17-2.




Each of the registers CCy may be individually programmed for capture mode or for oneof 4 different compare modes, and may be allocated individually to one of the two timersof the respective CAPCOM unit. A special double-register compare mode combines tworegisters to act on one common output signal. When capture or compare operations aredisabled for one of the CCy registers, it may be used for general purpose variablestorage.

The detailed discussion of the capture and compare modes is valid for all thecapture/compare channels, so registers, bits and pins are only referenced by aplaceholder.

Note: For channels not connected to a pin, only compare modes 0 and 2 make sense.A capture or compare event on channel 31 may be used to trigger a channelinjection on the XC164’s A/D converter if enabled.

Table 17-2 Selection of Capture Modes and Compare Modes

Mode MODy Selected Operating Mode

Disabled 0 0 0 Disable Capture and Compare ModesThe respective CAPCOM register may be used for general variable storage.

Capture 0 0 1 Capture on Positive Transition (Rising Edge) at Pin CCyIO

0 1 0 Capture on Negative Transition (Falling Edge) at Pin CCyIO

0 1 1 Capture on Positive and Negative Transition (Both Edges) at Pin CCyIO

Compare 1 0 0 Compare Mode 0: Interrupt OnlySeveral interrupts per timer period.Can enable double-register compare mode for Bank2 registers.

1 0 1 Compare Mode 1: Toggle Output Pin on each MatchSeveral compare events per timer period.Can enable double-register compare mode for Bank1 registers.

1 1 0 Compare Mode 2: Interrupt OnlyOnly one interrupt per timer period.

1 1 1 Compare Mode 3: Set Output Pin on each MatchReset output pin on each timer overflow; only one interrupt per timer period.




17.4 Capture Mode Operation

In Capture Mode, the current contents of a CAPCOM timer are latched (captured) intothe respective capture/compare register in response to an external event. This is used,for example, to record the time at which an external event has occurred, or to measurethe distance between two external events in timer increments.

The event to cause a capture of a timer’s contents can be programmed to be either thepositive, the negative, or both the positive and the negative transition of the externalsignal connected to the input pin. This triggering transition is selected by bitfield MODyin the respective mode control register. When the selected external signal transitionoccurs, the selected timer’s contents is latched into the capture/compare register and therespective interrupt request line CCyIRQ is activated. This can cause an interrupt or PECservice request, when enabled.

Note: A capture input can be used as an additional external interrupt input. The captureoperation can be disregarded in this case.

Either the contents of timer T0/T7 or T1/T8 can be captured, selected by the timerallocation control bit ACCy in the respective mode control register.

Figure 17-4 Capture Mode Block Diagram

For capture operation, the respective pin must be programmed for input. To ensure thata transition of the input signal is recognized correctly, its level must be held high or lowfor a minimum number of module clock cycles before it changes. This information canbe found in Section 17.10.

MCB05420

MU

X

Timer T0/T7

ACCy

Timer T1/T8

CaptureRegister CCy

InterruptRequests

MODy

CCyIO CCyIRQ

InputClock

Edge

Select




17.5 Compare Mode Operation

The compare modes allow triggering of events (interrupts and/or output signaltransitions) or generation of pulse trains with minimum software overhead. In all comparemodes, the 16-bit value stored in a capture/compare register CCy (in the following alsoreferred to as ‘compare value’) is continuously compared with the contents of theallocated timer (T0/T7 or T1/T8). If the current timer contents match the compare value,the interrupt request line associated with register CCy is activated and, depending on thecompare mode, an output signal can be generated at the corresponding output pinCCyIO.

Four different compare modes are available, which can be selected individually for eachof the capture/compare registers by bitfield MODy in the respective mode controlregister. Modes 0 and 2 do not influence the output signals. In the following, each modeis described in detail.

In addition to these ‘single-register’ modes, a ‘double-register’ compare mode enablestwo registers to operate on the same pin. This feature can further reduce softwareoverhead, as two different compare values can be programmed to control a sequence oftransitions for a signal. See Section 17.5.5 for details for this operation.

In all Compare Modes, the comparator performs an ‘equal to’ comparison. This means,a match is only detected when the timer contents are equal to the contents of a compareregister. In addition, the comparator is only enabled in the clock cycle directly after thetimer was incremented by hardware. This is done to prevent repeated matches if thetimer does not operate with the highest possible input clock (either in timer or countermode). In this case, the timer contents would remain at the same value for several or upto thousands of cycles. This operation has the side-effect, that software modifications ofthe timer contents will have no effect regarding the comparator. If a timer is set bysoftware to the same value stored in one of the compare registers, no match will bedetected. If a compare register is set to a value smaller than the current timer contents,no action will take place.

For the exact operation of the port output function, please see Section 17.6.

When two or more compare registers are programmed to the same compare value1),their corresponding interrupt request flags will be set and the selected output signals willbe generated after the allocated timer is incremented to this compare value. Furthercompare events on the same compare value are disabled2) until the timer is incrementedagain or written to by software. After a reset, compare events for register CCy will onlybecome enabled, if the allocated timer has been incremented or written to by softwareand one of the compare modes described in the following has been selected for thisregister.

1) In staggered mode these interrupts and output signals are generated sequentially (see Section 17.8).2) Even if more compare cycles are executed before the timer increments (lower timer frequency) a given

compare value only results in one single compare event.




17.5.1 Compare Mode 0

This is an interrupt-only mode which can be used for software timing purposes. In thismode, the interrupt request line CCyIRQ is activated each time a match is detectedbetween the contents of the compare register CCy and the allocated timer. A matchmeans, the contents of the timer are equal to (‘=’) the contents of the compare register.Several of these compare events are possible within a single timer period, if the comparevalue in register CCy is updated during the timer period. The corresponding port signalCCyIO is not affected by compare events in this mode and can be used as generalpurpose IO.

Note: If compare mode 0 is programmed for one of the bank2 registers the double-register compare mode may be enabled for this register (see Chapter 17.5.5).


This is a compare mode which influences the associated output signal. Besides this, thebasic operation is as in compare mode 0. Each time a match is detected between thecontents of the compare register CCy and the allocated timer, the interrupt request lineCCyIRQ is activated. In addition, the associated output signal is toggled. Several ofthese compare events are possible within a single timer period, if the compare value inregister CCy is updated during the timer period.

Note: If compare mode 1 is programmed for one of the bank1 registers the double-register compare mode may be enabled for this register (see Section 17.5.5).

For the exact operation of the port output signal, please see Section 17.6.




Figure 17-5 Compare Mode 0 and 1 Block Diagram

Note: The signal remains unaffected in compare mode 0.

Figure 17-6 illustrates a few example cases for compare modes 0 and 1.

In all examples, the reload value of the used timer is set to FFF9H. When the timeroverflows, it starts counting from this value upwards.

In Case 1, register CCy contains the value FFFCH. When the timer reaches this value,a match is detected, and the interrupt request line CCyIRQ is activated. In comparemode 0, this is all that will happen. In compare mode 1, additionally the associated portoutput is toggled, causing an inversion of the output signal. If the contents of register CCyare not changed, this operation will take place each time the timer reaches theprogrammed compare value.

In Case 2, software reloads the compare register CCy with FFFFH after the first matchwith FFFCH has occurred. As the timer continues to count up, it finally reaches this newcompare value, and a new match is detected, activating the interrupt request line (bothmodes) and toggling the output signal (compare mode 1). If then the compare value isleft unchanged, the next match will occur when the timer reaches FFFFH again.This example illustrates, that further compare matches are possible within the currenttimer period (this is in contrast to compare modes 2 and 3).

MCB05421

MU

X

Timer T0/T7

ACCy

Mode &Output Ctrl.

CCyIRQ

to PortLogic

Timer T1/T8

ModeControl

SEMySEEy CompareRegister CCy

Comparator= ?MODy

T0IRQ,T7IRQ

T1IRQ,T8IRQ

Mode 1 only!




Figure 17-6 Examples for Compare Modes 0 and 1

In Case 3, a new compare value, higher than the current timer contents, causes a newmatch within the current timer period. The compare register is reloaded with FFFAH afterthe first match (at FFFCH). However, the timer has already passed this value. Thus, it willtake until the timer reaches FFFAH in the following timer period to cause the desiredcompare match. Reloading register CCy now with a value higher than the current timercontents will cause the next match within this period.

In Case 4, the compare values are equal to the timer reload value or to the maximumcount value, FFFFH.

MCT05422

CCxIOCase 1

CCxIOCase 2

CC0 = FFFF

CCxIOCase 3

CCxIOCase 4

FFFCFFFD

FFFEFFFF

FFF9FFFA

FFFBFFFC

FFFDFFFE

FFFF

FFF9FFFA

FFFB

Timer Contents

CC0 = FFFA CC0 = FFFD CC0 = FFFC

CC0 = FFF9 CC0 =FFFA

CC0 =FFFC

CC0 =FFFF

CC0 =FFFB

Symbolizes activation of the interrupt request line CCyIRQ

Reload Value = FFF9





Compare mode 2 is an interrupt-only mode similar to compare mode 0. The maindifference is that only one compare match, corresponding to one interrupt request, ispossible within a given timer period.

when a match is detected in compare mode 2 for the first time within a count period ofthe allocated timer, the interrupt request line CCyIRQ is activated. In addition, all furthercompare matches within the current timer period are disabled, even if a new comparevalue, higher than the current timer contents, would be written to the register. Thisblocking is only released when the allocated timer overflows. A new compare valuewritten to the compare register after the first match will only go into effect within thefollowing timer period.


Compare mode 3 is based on compare mode 2, but additionally influences theassociated port pin. Only one compare event is possible within one timer period.

When a match is detected in compare mode 3 for the first time within a count period ofthe allocated timer, the interrupt request line CCyIRQ is activated, and the associatedoutput signal is set to 1. In addition, all further compare matches within the current timerperiod are disabled, even if a new compare value, higher than the current timer contents,would be written to the register. This blocking is only released when the allocated timeroverflows. A new compare value written to the compare register after the first match willonly go into effect within the following timer period.

The overflow signal is also used to reset the associated output signal to 0.

Special attention has to be paid when the compare value is set equal to the timer reloadvalue. In this case, the compare match signal would try to set the output signal, while thetimer overflow tries to reset the output signal. This conflict is avoided such that the stateof the output signal is left unchanged in this case.

Note: When the compare value is changed from a value above the current timercontents to a value below the current timer contents, the new value is notrecognized before the next timer period.

For the exact operation of the port output signal, please see Section 17.6.




Figure 17-7 Compare Mode 2 and 3 Block Diagram

Note: The port latch and signal remain unaffected in compare mode 2.

Figure 17-8 illustrates a few timing examples for compare modes 2 and 3.

In all examples, the reload value of the used timer is set to FFF9H. When the timeroverflows, it starts counting from this value upwards.

In Case 1, register CCy contains the value FFFCH. When the timer reaches this value,a match is detected, and the interrupt request line CCyIRQ is activated. In comparemode 2, this is all that will happen. In compare mode 3, additionally the associated portoutput is set to 1. The timer continues to count, and finally reaches its overflow. At thispoint, the port output is reset to 0 again. Note that, although not shown in the diagrams,the overflow signal of the timer also activates the associated interrupt request lineTxIRQ. If the contents of register CCy are not changed, the port output will be set againduring the following timer period, and reset again when the timer overflows. Thisoperation is ideal for the generation of a pulse width modulated (PWM) signal with aminimum of software overhead. The pulse width is varied by changing the comparevalue accordingly.

In Case 2, the compare operation is blocked after the first match within a timer period.After the first match at FFFCH, the interrupt request is generated and the port output isset. In addition, further compare matches are disabled. If now a new compare value iswritten to register CCy, no interrupt request and no port output influence will take place,although the new compare value is higher than the current timer contents. Only after theoverflow of the timer, the compare logic is enabled again, and the next match will be

MCB05423

MU

X

MU

X

Timer T0/T7

ACCy ACCy

Mode &Output Ctrl.

CCyIRQ

to PortLogic

Timer T1/T8

ModeControl

SEMySEEy CompareRegister CCy

Comparator= ?MODy

T0IRQ,T7IRQ

T1IRQ,T8IRQ

Mode 3 only!




detected at FFFFH. One can see, that this operation is ideal for PWM generation, assoftware can write a new compare value regardless of whether this value is higher orlower than the current timer contents. It is assured that the new value (usually written tothe compare register in the appropriate interrupt service routine) will only go into effectduring the following timer period.

Figure 17-8 Timing Example for Compare Modes 2 and 3

Note: In compare mode 2, only interrupt requests are generated, in mode 3, also theoutput signals are generated.

In Case 3, further examples for the operation of the compare match blocking areillustrated.

In Case 4, a new compare value is written to a compare register before the first matchwithin the timer period. One can see that, of course, the originally programmed comparematch (at FFFAH) will not take place. The first match will be detected at FFFCH. However,it is important to note that the reprogramming of the compare register took placeasynchronously - this means, the register was written to without any regard to the currentcontents of the timer. This is dangerous in the sense that the effect of such anasynchronous reprogramming is not easily predictable. If the timer would have alreadyreached the originally programmed compare value of FFFAH by the time the software

MCT05424

CCxIOCase 1

CCxIOCase 2

CC0 = FFFF

CCxIOCase 3

CCxIOCase 4

FFFCFFFD

FFFEFFFF

FFF9FFFA

FFFBFFFC

FFFDFFFE

FFFF

FFF9FFFA

FFFB

Timer Contents

CC0 = FFFA CC0 = FFFC

CC0 = FFFA CC0 = FFFC

Reload Value = FFF9




wrote to the register, a match would have been detected and the reprogramming wouldgo into effect during the next timer period.

The examples in Figure 17-9 show special cases for compare modes 2 and 3. Case 1illustrates the effect when the compare value is equal to the reload value of the timer. Aninterrupt is generated in both modes. In mode 3, the output signal is not affected - itremains at the high level. Setting the compare value equal to the reload value easilyenables a 100% duty cycle signal for PWM generation. The important advantage here isthat the compare interrupt is still generated and can be used to reload the next comparevalue. Thus, no special treatment is required for this case (see Case 3).

Cases 2, 4, and 5 show different options for the generation of a 0% duty cycle signal.Case 2 shows an asynchronous reprogramming of the compare value equal to thereload value. At the end of the current timer period, a compare interrupt will begenerated, which enables software to set the next compare value. The disadvantage ofthis method is that at least two timer periods will pass until a new regular compare valuecan go into effect. The compare match with the reload value FFF9H will block furthercompare matches during that timer period. This is additionally illustrated by Case 4.

Figure 17-9 Special Cases in Compare Modes 2 and 3

MCT05425

CC0 = FFF9 Int. Int.

CCxIOCase 1

Int.

CCxIOCase 2

Int.CC0 = FFF9 Int.

CCxIOCase 3

Int. CC0 = FFFB

CCxIOCase 4

Int.CC0 = FFF9 Int.

CC0 =FFFC

NoComp.

CCxIOCase 5

Int. CC0 =FFFC

Int.CC0 = FFF8

FFFCFFFD

FFFEFFFF

FFF9FFFA

FFFBFFFC

FFFDFFFE

FFFF

FFF9FFFA

FFFB

Timer Contents

Reload Value = FFF9

CC0 = FFF9 Int.




Case 5 shows an option to get around this problem. Here, the compare register isreloaded with FFF8H, a value which is lower than the timer reload value. Thus, the timerwill never reach this value, and no compare match will be detected. The output signal willbe set to 0 after the first timer overflow. However, after the second overflow, softwarenow reloads the compare register with a regular compare value. As no compare blockinghas taken place (since there was no compare match), the newly written compare valuewill go into effect during the current timer period.

17.5.5 Double-Register Compare Mode

The Double-Register Compare Mode makes it possible to further reduce softwareoverhead for a number of applications. In this mode, two compare registers worktogether to control one output. This mode is selected via the DRM register, or by aspecial combination of compare modes for the two registers.

For double-register compare mode, the 16 capture/compare registers of a CAPCOM unitare regarded as two banks of 8 registers each. The lower eight registers form bank1,while the upper eight registers form bank2. For double-register mode, a bank1 registerand a bank2 register form a register pair. Both registers of this register pair operate onthe pin associated with the bank1 register.

The relationship between the bank1 and bank2 register of a pair and the effected outputpins for double-register compare mode is listed in Table 17-3.

The double-register compare mode can be programmed individually for each registerpair. Double-register compare mode can be selected via a certain combination of

Table 17-3 Register Pairs for Double-Register Compare Mode

CAPCOM1 Unit1)

1) CAPCOM1 is not connected to pins. Therefore, double-register compare mode makes no sense here.

CAPCOM2 Unit

Register Pair Used Output Pin

Control Bitfield in CC1DRM

Register Pair Used Output Pin

Control Bitfield in CC2DRM

Bank 1 Bank 2 Bank 1 Bank 2

CC0 CC8 – DR0M CC16 CC24 CC16IO DR0M











compare modes for the two registers of a pair. The bank1 register must be programmedfor mode 1 (with port influence), while the bank2 register must be programmed formode 0 (interrupt-only).

Double-register compare mode can be controlled (this means, enabled or disabled) foreach register pair via the associated control bitfield DRxM in register CC1_DRM orCC2_DRM, respectively.

Double-register compare mode can be controlled individually for each of the registerpairs.

In the block diagram of the double-register compare mode (Figure 17-10), a bank2register will be referred to as CCz, while the corresponding bank1 register will be referredto as CCy.

CC1_DRM Double-Reg. Cmp. Mode Reg. SFR (FF5AH/ADH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR7M DR6M DR5M DR4M DR3M DR2M DR1M DR0M


CC2_DRMDouble-Reg. Cmp. Mode Reg. SFR (FF2AH/95H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR7M DR6M DR5M DR4M DR3M DR2M DR1M DR0M



DRxM [1:0], [3:2], [5:4], [7:6], [9:8], [11:10], [13:12], [15:14]

rw Double Register x Compare Mode Selection00 DRM is controlled via the combination of compare

modes 1 and 0 (compatibility mode)01 DRM disabled regardless of compare modes10 DRM enabled regardless of compare modes11 Reserved

Note: “x” indicates the register pair index in a bank.




Figure 17-10 Double-Register Compare Mode Block Diagram

When a match is detected for one of the two registers in a register pair (CCy or CCz),the associated interrupt request line (CCyIRQ or CCzIRQ) is activated, and pin CCyIO,corresponding to the bank1 register CCy, is toggled. The generated interrupt alwayscorresponds to the register that caused the match.

Note: If a match occurs simultaneously for both register CCy and register CCz of theregister pair, pin CCyIO will be toggled only once, but two separate compareinterrupt requests will be generated.

Each of the two registers of a pair can be individually allocated to one of the two timersin the CAPCOM unit. This offers a wide variety of applications, as the two timers can runin different modes with different resolution and frequency. However, this might requiresophisticated software algorithms to handle the different timer periods.

Note: The signals CCzIO (which do not serve for double-register compare mode) maybe used for general purpose IO.

ModeControl

SEMySEEy

Comp.= ?

MU

X

Timer T0/T7 Timer T1/T8

ACCy ACCz

DRyMMODy

CCyIRQ

MU

XMode &

Output Ctrl.to PortLogic

MCB05426

Comparator= ?

CompareRegister CCz

CCzIRQ

z = y + 8

ModeControl

SEMzSEEz

DRyMMODz

CompareRegister CCy




17.6 Compare Output Signal Generation

This section discusses the interaction between the CAPCOM Unit and the Port Logic.The block diagram illustrated in Figure 17-11 details the logic of the block “Mode &Output Control”, shown in Figure 17-5, Figure 17-7, and Figure 17-10.

Each output signal is latched in its associated bit of the respective output latch registerCCx_OUT. The individual bits are updated each time an associated compare eventoccurs. The bits of these registers are connected to the respective port pins as analternate output function of a port line.

Compare signals can also directly affect the associated port output latch Px. In this case,the port latch must be selected for the respective pin. The direct port latch option isdisabled in non-staggered mode or it can be disabled by setting bit PL in registerCCx_IOC.

Register CCx_OUT is always updated in parallel to the update of the port output latch.

CC1_OUT Compare Output Reg. SFR (FF5CH/AEH) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC15IO

CC14IO

CC13IO

CC12IO

CC11IO

CC10IO

CC9IO

CC8IO

CC7IO

CC6IO

CC5IO

CC4IO

CC3IO

CC2IO

CC1IO

CC0IO

rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh

CC2_OUTCompare Output Reg. SFR (FF2CH/96H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC15IO

CC14IO

CC13IO

CC12IO

CC11IO

CC10IO

CC9IO

CC8IO

CC7IO

CC6IO

CC5IO

CC4IO

CC3IO

CC2IO

CC1IO

CC0IO



CCyIO 15 … 0 rwh Compare Output for Channel yAlternative port output for the associated port pin.




Figure 17-11 Port Output Block Diagram for Compare Modes

Note: A compare output signal is visible at the pin only in compare modes 1 or 3.

The output signal of a compare event can either be a 1, a 0, the complement of thecurrent level, or the previous level. The block ‘Output Value Control’ determines thecorrect new level based on the compare event, the timer overflow signal, and the currentstates of the Port and OUT latches. For the output toggle function (e.g. in comparemode 1), the state of the output latch is read, inverted, and then written back.

The associated output pins either drives the port latch signal or the OUT signal, selectedby register ALTSEL (see Figure 17-11).

Note: If the port output latch is written to by software at the same time it would be alteredby a compare event, the software write will have priority. In this case the hardware-triggered change will not become effective.

MCB05427

TxOV

MUX

ALTSEL0Pn

0

1

Port Latch

&

OUT Latch

>1_

OutputValue

Control

MODy

CompareMatch

STAG

PL

Direction

Driver Port PinPm.n

CAPCOM Logic Port Logic




17.7 Single Event Operation

If an application requires that one and only one compare event needs to take place(within a certain time frame), single event operation helps to reduce software overheadand to eliminate the need for fast reaction upon events.

In order to achieve a single event operation without this feature, software would have toeither disable the compare mode or write a new value, which is outside of the countrange of the timer, into the compare register, after the programmed compare match hastaken place. Thus, usually an interrupt service routine is required to perform thisoperation. Interrupt response time may be critical if the timer period is very short - thedisable operation needs to be completed before the timer would reach the same valueagain.

The single event operation eliminates the need for software to react after the firstcompare match. The complete operation can be set up before the event, and no actionis required after the event. The hardware takes care of generating only one event, andthen disabling all further compare matches.

This option is programmed via the Single Event Mode register CCx_SEM and the SingleEvent Enable register CCx_SEE. Each register provides one bit for each CCy register ofa unit.

CC1_SEM Single Event Mode Ctrl. Reg. SFR (FE28H/14H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEM15

SEM14

SEM13

SEM12

SEM11

SEM10

SEM9

SEM8

SEM7

SEM6

SEM5

SEM4

SEM3

SEM2

SEM1

SEM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CC2_SEMSingle Event Mode Ctrl. Reg. SFR (FE2CH/16H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEM15

SEM14

SEM13

SEM12

SEM11

SEM10

SEM9

SEM8

SEM7

SEM6

SEM5

SEM4

SEM3

SEM2

SEM1

SEM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw


SEMy 15 … 0 rw Single Event Mode Control0 Single Event Mode disabled for channel y1 Single Event Mode enabled for channel y




To setup a single event operation for a CCy register, software first programs the desiredcompare operation and compare value, and then sets the respective bit in registerCCx_SEM to enable the single event mode. At last, the respective event enable bit inregister CCx_SEE is set.

When the programmed compare match occurs, all operations of the selected comparemode take place. In addition, hardware automatically disables all further comparematches and reset the event enable bit in register CCx_SEE to 0. As long as this bit iscleared, any compare operation is disabled. To setup a new event, this bit must first beset again.

CC1_SEE Single Event Enable Reg. SFR (FE2EH/17H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEE15

SEE14

SEE13

SEE12

SEE11

SEE10

SEE9

SEE8

SEE7

SEE6

SEE5

SEE4

SEE3

SEE2

SEE1

SEE0


CC2_SEESingle Event Enable Reg. SFR (FE2AH/15H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEE15

SEE14

SEE13

SEE12

SEE11

SEE10

SEE9

SEE8

SEE7

SEE6

SEE5

SEE4

SEE3

SEE2

SEE1

SEE0



SEEy 15 … 0 rwh Single Event Enable Control0 Single Event disabled for channel y1 Single Event enabled for channel y

Note: This bit is cleared by hardware after the event.




17.8 Staggered and Non-Staggered Operation

The CAPCOM units can run in one of two basic operation modes: Staggered Mode andNon-Staggered Mode. The selection between these modes is performed via registerIOC.

Note: Whenever Non-Staggered Mode is enabled (STAG = 1) or Port Lock is activated(PL = 1), the port output registers are not changed by the CAPCOM unit.

In staggered mode, a CAPCOM operation cycle consists of 8 module clock cycles, andthe outputs of the compare events of the different registers are staggered, that is, theoutputs for compare matches with the same compare value are not switched at the sametime, but with a fixed time delay. This operation helps to reduce noise and peak powerconsumption caused by simultaneous switching outputs.

In non-staggered Mode, a CAPCOM operation cycle is equal to one module clock cycle,and all compare outputs for compare events with the same compare value are switched

CC1_IOC I/O Control Register ESFR (F062H/31H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- -ST AG

PL -

- - rw rw -

CC2_IOCI/O Control Register ESFR (F066H/33H) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- -ST AG

PL -

- - rw rw -


STAG 2 rw Staggered Mode Control0 CAPCOM operates in Staggered Mode1 CAPCOM operates in Non-Staggered Mode

PL 1 rw Port Lock Control1)

0 Compare output signals affect the associated port output latch

1 Direct influence of the port output latch by the compare output signals is disabled

1) CAPCOM1 is not connected to pins. Therefore, port control options make no sense here.




in the same clock cycle. This mode offers a faster operation and increased resolution ofthe CAPCOM unit, 8 times higher than in staggered mode.

Staggered Mode

Figure 17-12 illustrates the staggered mode operation. In this example, all CCy registersare programmed for compare mode 3.

Registers CC0, CC1, and CC2 are all programmed for a compare value of FFFEH. Whenthe timer increments to FFFEH, the comparator detects a match for all of the threeregisters. The output CC0IO of register CC0 is switched to 1 one cycle after thecomparator match. However, the outputs CC1IO and CC2IO are not switched at thesame time, but one, respectively two cycles later. This staggering of the outputscontinues for all registers including register CC7. The number of the register indicatesthe delay of the output signal in clock cycles - the output of register CC7 is switched7 cycles later than the one of register CC0. In the example, the compare value forregister CC7 is set to FFFDH. Thus, the output is switched in the last clock cycle of theCAPCOM cycle in which the timer reached FFFDH.

When the timer overflows, all compare outputs are reset to 0 (compare mode 3). Again,the staggering of the output signals can be seen from Figure 17-12.

Looking at registers CC8 through CC15 shows that their outputs are switched in parallelto the respective outputs of registers CC0 through CC15. In fact, the staggering isperformed in parallel for the upper and the lower register bank. In this way, it is assured,that both compare signals of a register pair in double-register compare mode operatesimultaneously.

In staggered mode direct port latch switching (see Section 17.6) is possible. However,it is possible to use the alternate output function option of the associated port pins tooutput the compare signals.

Note: This is a general description and only refers to channels connected to pins.




Figure 17-12 Staggered Mode Operation

MCT05428

CC0 = FFFE

Timercontents= FFFD

Timer increments toFFFE

Timer increments toFFFF

Timer is reloadedwith FFFC

Timer overflow

1 CAPCOM Cycle= 8 fCC Clock Cycles

1 CAPCOM Cycle= 8 fCC Clock Cycles

CC1 = FFFE

CC2 = FFFE

CC3 = FFFF

CC4 = FFFE

CC5 = FFFF

CC6 = FFFF

CC7 = FFFD

CC8 = FFFE

CC9 = FFFE

CC10 = FFFE

CC11 = FFFF

CC12 = FFFE

CC13 = FFFF

CC14 = FFFF

CC15 = FFFD




Non-Staggered Mode

To gain maximum speed and resolution with the CAPCOM unit, it can be switched tonon-staggered mode. In this mode, one CAPCOM operation cycle is equal to onemodule clock cycle. Timer increment and the comparison of its new contents with thecontents of the compare register takes place within one clock cycle. The appropriateoutput signals are switched in the following clock cycle (in parallel to the next possibletimer increment and comparison).

Figure 17-13 illustrates the non-staggered mode. Note that when the timer overflows, italso takes one additional clock cycle to switch the output signals.

Note: In non-staggered mode, direct port latch switching is disabled.This is a general description and only refers to channels connected to pins.




Figure 17-13 Non-Staggered Mode Operation

MCT05429

CC0 = FFFE

Timercontents= FFFD

Timer increments toFFFE

Timer increments toFFFF

Timer is reloadedwith FFFC

Timer overflow

1 CAPCOM Cycle= 1 fCC Clock Cycle

1 CAPCOM Cycle= 1 fCC Clock Cycle

CC1 = FFFE

CC2 = FFFE

CC3 = FFFF

CC4 = FFFE

CC5 = FFFF

CC6 = FFFF

CC7 = FFFD

CC8 = FFFE

CC9 = FFFE

CC10 = FFFE

CC11 = FFFF

CC12 = FFFE

CC13 = FFFF

CC14 = FFFF

CC15 = FFFD




17.9 CAPCOM Interrupts

Upon a capture or compare event, the interrupt request flag CCxIR for the respectivecapture/compare register CCx is automatically set. This flag can be used to generate aninterrupt or trigger a PEC service request when enabled by the interrupt enable bitCCxIE. Capture interrupts can be regarded as external interrupt requests with theadditional feature of recording the time at which the triggering event occurred.

Each of the capture/compare registers has its own bitaddressable interrupt controlregister and its own interrupt vector allocated. These registers are organized in the sameway as all other interrupt control registers. The basic register layout is shown below,Table 17-4 lists the associated addresses.


CCx_CCyIC CAPCOM Intr. Ctrl. Reg. (E)SFR (Table 17-4) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- GPXCCyIR

CCyIE

ILVL GLVL

- - - - - - - rw rwh rw rw rw




Table 17-4 CAPCOM Unit Interrupt Control Register Addresses

CAPCOM1 Unit CAPCOM2 Unit

Register Name Address Reg. Space

Register Name Address Reg. Space

CC1_CC0IC FF78H/BCH SFR CC2_CC16IC F160H/B0H ESFR

CC1_CC1IC FF7AH/BDH SFR CC2_CC17IC F162H/B1H ESFR

CC1_CC2IC FF7CH/BEH SFR CC2_CC18IC F164H/B2H ESFR

CC1_CC3IC FF7EH/BFH SFR CC2_CC19IC F166H/B3H ESFR

CC1_CC4IC FF80H/C0H SFR CC2_CC20IC F168H/B4H ESFR

CC1_CC5IC FF82H/C1H SFR CC2_CC21IC F16AH/B5H ESFR

CC1_CC6IC FF84H/C2H SFR CC2_CC22IC F16CH/B6H ESFR

CC1_CC7IC FF86H/C3H SFR CC2_CC23IC F16EH/B7H ESFR

CC1_CC8IC FF88H/C4H SFR CC2_CC24IC F170H/B8H ESFR

CC1_CC9IC FF8AH/C5H SFR CC2_CC25IC F172H/B9H ESFR

CC1_CC10IC FF8CH/C6H SFR CC2_CC26IC F174H/BAH ESFR

CC1_CC11IC FF8EH/C7H SFR CC2_CC27IC F176H/BBH ESFR

CC1_CC12IC FF90H/C8H SFR CC2_CC28IC F178H/BCH ESFR

CC1_CC13IC FF92H/C9H SFR CC2_CC29IC F184H/C2H ESFR

CC1_CC14IC FF94H/CAH SFR CC2_CC30IC F18CH/C6H ESFR

CC1_CC15IC FF96H/CBH SFR CC2_CC31IC F194H/CAH ESFR




17.10 External Input Signal Requirements

The external input signals of a CAPCOM unit are sampled by the CAPCOM logic basedon the module clock and the basic operation mode (staggered or non-staggered mode).To assure that a signal level is recognized correctly, its high or low level must be heldactive for at least one complete sampling period.

The duration of a sampling period is one module clock cycle in non-staggered mode, and8 module clock cycles in staggered mode. To recognize a signal transition, the signalneeds to be sampled twice. If the level of the first sampling is different to the leveldetected during the second sampling, a transition is recognized. Therefore, a minimumof two sampling periods are required for the sampling of an external input signal. Thus,the maximum frequency of an input signal must not be higher than half the module clockfrequency in non-staggered mode, and a 1/16th of the module clock frequency instaggered mode.

Table 17-5 summarizes the requirements and limits for external input signals.

In order to use an external signal as a count or capture input, the port pin to which it isconnected must be configured as input.

Note: For example for test purposes a pin used as a count or capture input may beconfigured as output. Software or an other peripheral may control the respectivesignal and thus trigger count or capture events.

In order to cause a compare output signal to be seen by the external world, theassociated port pin must be configured as output. Compare output signals can eitherdirectly switch the port latch, or the output of the CCx_OUT latch is used as an alternateoutput function of a port.

Table 17-5 CAPCOM External Input Signal Limits

Non-Staggered Mode Staggered Mode

Maximum Input Frequency fCC/2 fCC/16

Minimum Input Signal Level Duration

1/fCC 8/fCC




17.11 Interfaces of the CAPCOM Units

The CAPCOM units CAPCOM1 (see Figure 17-14) and CAPCOM2 (see Figure 17-15)are connected to their environment in different ways.


The overflow/underflow signal T6OUF of GPT2 timer T6 is connected to the CAPCOMunits, providing an optional clock source for the CAPCOM timers.

The 18 interrupt request lines of each CAPCOM unit are connected to the interruptcontrol block.

Note: The upper 8 input lines from PORT1, connected with the CAPCOM2 unit, can alsobe used as individual external interrupt inputs.

The interrupt request line of channel 31 is connected to the ADC, as a possible triggersource for injected conversions.


Twelve capture/compare signals of the CAPCOM2 unit are connected with input/outputports of the XC164. Depending on the selected direction, these ports may providecapture trigger signals from the external system or issue compare output signals toexternal circuitry.

Note: Capture trigger signals may also be derived from output pins. In this case,software can generate the trigger edges, for example.

Timer T0 can be clocked by an external signal.




Figure 17-14 CAPCOM1 Unit Interfaces

MCA05430_X4

Alternate ExternalInterrupt Input

CC14IO

CAPCOM1Module

fCC

CC1DIS

T6OUF

InterruptControl

SystemControl

Unit (SCU)

GPT12Unit

P1H.0/EX0IN

P1H.1/EX1IN

P1H.2/EX2IN

P1H.3/EX3IN

P1H.4/EX4IN

P1H.5/EX5IN

P1H.6/EX6IN

P1H.7/EX7IN

CC15IRQ

CC14IRQ

CC13IRQ

CC12IRQ

CC11IRQ

CC10IRQ

CC9IRQ

CC8IRQ

CC7IRQ

CC6IRQ

CC5IRQ

CC4IRQ

CC3IRQ

CC2IRQ

CC1IRQ

CC0IRQ

T1IRQ

T0IRQ

CC15IO

T0IN

CC13IO

CC12IO

CC11IO

CC10IO

CC9IO

CC8IO

CC7IO

CC6IO

CC5IO

CC4IO

CC3IO

CC2IO

CC1IO

CC0IO

AlternateInput Select

ExternalInterruptInputs EXnIN





MCA05431_X4

CC30IO

CAPCOM2Module

fCC

CC2DIS

T6OUF

InterruptControl

SystemControl

Unit (SCU)

GPT12Unit

P9.0/CC16IO

P9.1/CC17IO

P9.2/CC18IO

P9.3/CC19IO

P9.4/CC20IO

P9.5/CC21IO

P1H.3/T7INCC31IRQ

CC30IRQ

CC29IRQ

CC28IRQ

CC27IRQ

CC26IRQ

CC25IRQ

CC24IRQ

CC23IRQ

CC22IRQ

CC21IRQ

CC20IRQ

CC19IRQ

CC18IRQ

CC17IRQ

CC16IRQ

T8IRQ

T7IRQ

CC31IO

T7IN

CC29IO

CC28IO

CC21IO

CC20IO

CC19IO

CC18IO

CC17IO

CC16IO

ADCInjectionTrigger

P1H.0/CC23IO

P1L.7/CC22IO

P1H.4/CC24IO

P1H.5/CC25IO

P1H.6/CC26IO

P1H.7/CC27IOCC27IO

CC26IO

CC25IO

CC24IO

CC23IO

CC22IO

Port P2Control

Port P9Control

Port P1Control



Capture/Compare Unit 6 (CAPCOM6)

18 Capture/Compare Unit 6 (CAPCOM6)The CAPCOM6 unit is made up of a Timer T12 Block with three capture/comparechannels and a Timer T13 Block with one compare channel. The T12 channels canindependently generate PWM signals or accept capture triggers, or they can jointlygenerate control signal patterns to drive AC-motors or inverters. Special operatingmodes support the control of Brushless DC-motors using Hall sensors or Back-EMFdetection. Furthermore, block commutation and control mechanisms for multi-phasemachines are supported.

Figure 18-1 SFRs Associated with the CAPCOM6 Unit

mc_capcom60100_registers.vsd

Data Registers Control Registers System Registers

T12 CMPSTAT

CCU6_T12IC

CCU6_T13IC

CMPMODIF

P1L

DP1L

Interrupt Control

T12/T13 CAPCOM6 Timer T12/T13 RegisterT12PR/T13PR CAPCOM6 T12/T13 Period RegisterT12DTC CAPCOM6 T12 Deadtime Control Reg.TCTRx CAPCOM6 Timer Control RegisterT12MSEL T12 Capture/Compare Mode Select Reg.CC6xR CAPCOM6 Capture/Compare RegisterCC6xSR CAPCOM6 Capt./Comp. Shadow Reg.CMPSTAT Capture/Compare State RegisterCMPMODIF Capture/Comp. State Modification Reg.MODCTR Modulation Control RegisterMCMOUT Multi-Channel Mode Output RegisterMCMOUTS Multi-Ch. Mode Output Shadow Reg.MCMCTR Multi-Channel Mode Control Register

TRPCTR Trap Control RegisterPSLR Passive State Level RegisterIS Interrupt Status RegisterISS/ISR Interrupt Status Set/Reset RegisterIEN Interrupt Enable RegisterINP Interrupt Node Pointer RegisterT12IC/T13IC CAPCOM6 Timer Interrupt Control Reg.CCU6_IC CAPCOM6 Interrupt Control RegisterCCU6_EIC CAPCOM6 Error Interrupt Control Reg.P1L/P1H PORT1 Data RegisterDP1L/DP1H PORT1 Direction Control RegisterALTSEL0P1x PORT1 Alternate Outp. Select Reg. 0SYSCON3 System Control Reg. 3 (Per. Mgmt.)

T12PR

T12DTC

CC60R

X

X

CC60SR

CC61R

CC61SR

CC62R

CC62SR

T13

T13PR

CC63R

MCMOUT

MCMOUTS

PSLR

TRPCTR

MODCTR

TCTR4

TCTR2

TCTR0

CCU6_IEN

CCU6_INP

CCU6_ISR

CCU6_ISS

CCU6_IS

CCU6_EIC

CCU6_IC

P1H

DP1H E

ALTSEL0P1H E

CC63SR

MCMCTR

T12MSEL

SYSCON3

ALTSEL0P1L E

E

E

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

E

E

E

E

User’s Manual 18-1 V2.1, 2004-03CAPCOM6_X, V2.0



A rich set of status bits, synchronized updating of parameter values via shadowregisters, and flexible generation of interrupt request signals provide means for efficientsoftware-control.

Timer 12 Block Features

• Three capture/compare channels, each channel can be used either as capture or ascompare channel

• Generation of a three-phase PWM supported (six outputs, individual signals forhighside and lowside switches)

• 16-bit resolution, maximum count frequency = peripheral clock• Dead-time control for each channel to avoid short-circuits in the power stage• Concurrent update of the required T12/T13 registers• Center-aligned and edge-aligned PWM can be generated• Single-shot mode supported• Many interrupt request sources• Hysteresis-like control mode

Timer 13 Block Features

• One independent compare channel with one output• 16-bit resolution, maximum count frequency = peripheral clock• Can be synchronized to T12• Interrupt generation at period-match and compare-match• Single-shot mode supported

Additional Features

• Block commutation for Brushless DC-drives implemented• Position detection via Hall-sensor pattern• Hall-Effect noise filter• Automatic rotational speed measurement for block commutation• Integrated error handling• Fast emergency stop without CPU load via external signal (CTRAP)• Control modes for multi-channel AC-drives• Output levels can be selected and adapted to the power stage




Figure 18-2 CAPCOM6 Block Diagram

The Timer T12 can work in capture and/or compare mode for its three channels. Themodes can also be combined. The Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by T12 and/orT13. The modulation sources can be selected and combined for the signal modulation.

Module Kemel

MCB05506

Input / Output Control

Port Control

Com

pare

Com

pare

2 2

Com

pare

Out

put S

elec

t

3

Hal

l Inp

ut

Out

put S

elec

t

1

Trap

Inpu

t

3+3

Cap

ture

CC

62

T13 Channel 3

Start

21

Compare

Multi-channelControl

TrapControl

Dead-Time

Control

Channel 0

Channel 1

Compare1

1

1

T12

Channel 2

CO

UT6

2

CC

61

CO

UT6

1

CC

60

CO

UT6

0

CO

UT6

3

T13R

H

T12H

R

CC

POS0

CC

POS1

CC

POS2

CTR

AP

AddressDecoder

ClockControl

InterruptControl




18.1 Timer T12 Block

The timer T12 block is the main unit to generate the 3-phase PWM. A 16-bit counter isconnected to 3 channel registers via comparators, which generate a signal when thecounter contents match one of the channel register contents. A variety of controlfunctions facilitate the adaptation of the T12 structure to different application needs.

Besides the 3-phase PWM generation, the T12 block offers options for individualcompare and capture functions, as well as dead-time control and hysteresis-likecompare mode.

Figure 18-3 Overview Diagram of the Timer T12 Block

Figure 18-4 shows a detailed block diagram of Timer T12. It receives its input clock, fT12,from the module clock fCC6 via a programmable prescaler and an optional 1/256 divider.These options are controlled via bitfields T12CLK and T12PRE (see Table 18-1). T12can count up or down, depending on the selected operation mode. A direction flag,CDIR, indicates the current counting direction.

Via a comparator, T12 is connected to a Period Register, T12PR. This registerdetermines the maximum count value for T12. In Edge-Aligned mode, T12 is reset to0000H after it has reached the period value. In Center-Aligned mode, the count directionof T12 is set from ‘up’ to ‘down’ after it has reached the period value (please note that inthis mode, T12 exceeds the period value by one before counting down). In both cases,signal T12_PM (T12 Period Match) is generated. The Period Register receives a newperiod value from its Shadow Period Register, T12PS, which is loaded via software. Thetransfer of a new period value from the shadow register into T12PR (see Section 18.8)is controlled via the ‘T12 Shadow Transfer’ control signal, T12_ST. The generation ofthis signal depends on the operating mode and on control bit STE12. Providing a shadowregister for the period value as well as for other values related to the generation of thePWM signal facilitates a concurrent update by software for all relevant parameters.

MCA05507

Timer T12Logic

Capture/CompareChannel 61



CC61ST

CC60ST

CC62ST

State Bits

To Dead-TimeControland OutputModulation

Input and Control/Status LogicExt.Inputs




Two further signals indicate whether the counter contents are equal to 0000H (T12_ZM)or 0001H (T12_OM). These signals control the counting and switching behavior of T12.

The basic operating mode of T12, either Edge-Aligned mode (Figure 18-5) or Center-Aligned mode (Figure 18-6), is selected via bit CTM. A Single-Shot control bit, T12SSC,enables an automatic stop of the timer when the current counting period is finished (seeFigure 18-7 and Figure 18-8).

Figure 18-4 Timer T12 Logic and Period Comparators

The start or stop of T12 is controlled by the Run bit, T12R. This control bit can be set bysoftware via the associated set/reset bits T12RS or T12RR, or it is reset by hardwareaccording to preselected conditions.

Timer T12 can be cleared via control bit T12RES. Setting this write-only bit does onlyclear the timer contents, but has no further effects, for example, it does not stop the timer.

The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bitSTE12. This bit can be set or reset by software indirectly through its associated set/resetcontrol bits T12STR and T12STD.

Note: The control registers to select the T12 operating mode are described inSection 18.3.

MCA05508

Comp.= ?

Period RegisterT12PR

Period ShadowRegister T12PR

T12_PM

Counter RegisterT12

fCC6

Write-Only

Read-Only

T12Control

& Status

T12RCDIRSTE12T12REST12SSC

T12_OMT12_ZM

CTMT12STRT12STD

T12RRT12RS

= 0000H

= 0001H

T12_SSEP

T12_ST

fT12

T12PRE

MUX256n

T12CLK




Register T12 represents the counting value of Timer T12. It can only be written whileTimer T12 is stopped. Write actions while T12 is running are not taken into account.Register T12 can always be read by software.

Register T12PR contains the period value for Timer T12. The period value is comparedto the actual count value of T12 and the resulting actions depend on the defined countingrules.

This register has a shadow register (using the same address) and the shadow transferis controlled by bit STE12. A read action by SW delivers the value which is currently usedfor the period compare, whereas a write action targets the shadow register. The shadowregister structure allows concurrent updating of all T12-related values.

CCU6_T12 Timer T12 Count Register XSFR (E890H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T12CV

rwh


T12CV [15:0] rwh T12 Count ValueRepresents the 16-bit count value of Timer T12

CCU6_T12PR Timer T12 Period Register XSFR (E892H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T12PV

rwh


T12PV [15:0] rwh T12 Period ValueWhen T12 equals value T12PV a period-match is triggered. When reaching this value, Timer T12 is set to zero (edge-aligned mode) or changes its count direction to down counting (center-aligned mode).




18.1.1 Timer T12 Operation

The input clock fT12 of Timer T12 is derived from the module clock fCC6 through aprogrammable prescaler and an optional 1/256 divider. The resulting prescale factorsare listed in Table 18-1. The prescaler of T12 is reset while T12 is not running to ensurereproducible timings and delays.

The period of the timer is determined by the value in the period Register T12PR and bythe timer mode.

In Edge-Aligned mode, the timer period is:

T12PER = <Period-Value> + 1; in T12 clocks (fT12) (18.1)

In Center-Aligned mode, the timer period is:

T12PER = (<Period-Value> + 1) × 2; in T12 clocks (fT12) (18.2)

While Timer T12 is running, write accesses to the count register T12 are not taken intoaccount. If T12 is stopped and the Dead-Time counters are 0, write actions to registerT12 are immediately taken into account.

Table 18-1 Timer T12 Input Clock Options

T12CLK Resulting Input ClockPrescaler Off (T12PRE = 0)

Resulting Input ClockPrescaler On (T12PRE = 1)

000B fCC6 fCC6/256

001B fCC6/2 fCC6/512

010B fCC6/4 fCC6/1024

011B fCC6/8 fCC6/2048

100B fCC6/16 fCC6/4096

101B fCC6/32 fCC6/8192

110B fCC6/64 fCC6/16384

111B fCC6/128 fCC6/32768




As described above, T12 can operate in Edge-Aligned mode or Center-Aligned mode. Inboth modes, a certain set of ‘counting rules’ determine the behavior of the T12 counter.

The counting rules lead to a behavior in Edge-Aligned mode as illustrated inFigure 18-5.

In the Center-Aligned mode (T12 counts up and down), the counting rules lead to thebehavior shown in Figure 18-6.

T12 in Edge-Aligned Mode:

• With the next clock of fT12 the counter is reset to zero when a Period-Match isdetected. The counting direction is always upwards (CDIR = 0).

Figure 18-5 T12 Operation in Edge-Aligned Mode

MCT05509

fT12

Zero

CC6x

Shadow Transfer

T12 Count

PeriodValue

PeriodMatch

ZeroMatch

Value n+1 Value n+2

CDIRUp Up




T12 in Center-Aligned mode:

• With the next clock of fT12 the count direction is set to counting up (CDIR = 0) whenthe counter reaches 0001H while counting down.

• With the next clock of fT12 the count direction is set to counting down (CDIR = 1) whenthe Period-Match is detected while counting up.

• With the next clock of fT12 the counter counts up while CDIR = 0 and it counts downwhile CDIR = 1.

Note: Bit CDIR changes with the next timer clock after the one-match or the period-match. Therefore, the timer continues counting in the previous direction for onecycle before actually changing its direction (see Figure 18-6).

Figure 18-6 T12 Operation in Center-Aligned Mode

MCT05510

fT12

CC6x

Shadow Transfer

T12 Count PeriodMatch

ZeroMatch

Value n Value n+1

CDIRDown Up

Shadow Transfer

Value n+1 Value n+2

Up Down

PeriodMatch

<Period Value> + 1

Zero

PeriodValue




T12 Shadow Transfer Signal, T12_ST

A special shadow transfer signal (T12_ST) can be generated to facilitate updating theperiod and compare values synchronously to the operation of T12. The generation of thissignal is requested by software via bit STE12 (set by writing 1 to the write-only bitT12STR, cleared by writing 1 to the write-only bit T12STD).

If requested (STE12 = 1), signal T12_ST is generated when:

• a Period-Match is detected while counting up, or• the counter reaches 0001H while counting down, or• timer T12 is not running (T12R = 0)

When signal T12_ST is active, a shadow register transfer is triggered with the next cycleof the T12 clock. A new period value is loaded from the shadow register into the actualperiod register T12PR, and new compare values are transferred from their shadowregisters into the actual compare registers (see Section 18.1.2). With the shadowregister transfer bit STE12 is automatically cleared.

T12 Start/Stop and Reset Control

Timer T12 is counting while bit T12R is set. Software can control the timer’s countoperation via bit T12R (set by writing 1 to the write-only bit T12RS, cleared by writing 1to the write-only bit T12RR). T12R can also be cleared by hardware in Single Shot mode.

Software can clear timer T12 by writing 1 to the write-only bit T12RES. This operationonly sets the timer contents to 0000H. No further actions will take place, for example, thetimer run bit is not cleared.




Single-Shot Mode

The run bit T12R is also influenced by hardware in Single-Shot mode. This mode isenabled through bit T12SSC. When this bit is set, the timer will stop when the currenttimer period is finished. In Edge-Aligned mode, this is when the timer is cleared to 0000Hafter having reached the period value. In Center-Aligned mode, the period is finishedwhen the timer has counted down to 0000H. See Figure 18-7 and Figure 18-8.

Figure 18-7 Single-Shot Operation in Edge-Aligned Mode

Figure 18-8 Single-Shot Operation in Center-Aligned Mode

Zero

Compare-Match

MCT05511

CompareValue

PeriodValue

fT12

CC6xST

T12SSC

T12 Count

MCT05512

Zero

Compare-Match Compare-Match

CompareValue

PeriodValue

fT12

CC6xST

T12SSC

T12 Count




18.1.2 T12 Compare Modes

Associated with Timer T12 are three individual capture/compare channels, which canperform compare or capture operations with regard to the contents of the T12 counter.The capture functions are explained in Section 18.1.4.

In Compare Mode (see Figure 18-9), the three channels can operate eitherindependently as individual channels, or generate a three-phase PWM pattern.

Figure 18-9 T12 Channel Comparators

Each channel is connected to the T12 counter register via its individual equal-tocomparator, which generates a match signal when the contents of the counter matchesthe contents of the associated compare register. Each channel consists of thecomparator and a double register structure - the actual compare register CC6xR, feedingthe comparator, and an associated shadow register CC6xSR, which is preloaded bysoftware and transferred into the compare register when signal T12 shadow transfer,T12_ST, gets active. Providing a shadow register for the compare value as well as forother values related to the generation of the PWM signal facilitates a concurrent updateby software for all relevant parameters (see also Section 18.8).

MCA05513

Comp.= ?

Compare RegisterCC61R

Compare ShadowRegister CC61SR

Comp.= ?



Comp.= ?



&

&

CompareMatch CM_61CompareMatch CM_62CompareMatch CM_60

CM_61_DN

CM_61_UP

T12_ST

Counter RegisterT12fT12

CDIR




Associated with each channel is a State Bit, CC6xST, which holds the status of thecompare (or capture) operation (see Figure 18-10).

Figure 18-10 Compare State Bits Block Diagram for Compare Mode

The inputs to the set/reset logic for the CC6xST bits are the timer direction (CDIR), thetimer run bit (T12R), the timer zero-match signal (T12_ZM), the end-of-single-shot modesignal (T12_SSEP), and the actual individual compare-match signals CM_6x as well asthe mode control bits, MSEL6x. In addition, each state bit can be set or reset by softwarevia the appropriate set and reset bits, MCC6xS and MCC6xR.

Note: In Hall Sensor mode, additional inputs are taken into account (see Section 18.5).

MCB05514

Set/ResetControlLogic

MCC60S/R

CDIR

CompareState BitCC60ST

CM_60 CC60ST

CC60ST

MSEL60

T12R

To InterruptControl

Rising EdgeFalling Edge

DTC0_INCC60ST Change


MCC61S/R


CM_61 CC61ST

CC61ST

MSEL61

To InterruptControl




MCC62S/R


CC62ST

CC62ST

MSEL62

To InterruptControl



CM_62

T12_ZM

T12_SSEP




A hardware-modification of a State Bit CC6xST is only possible while Timer T12 isrunning (T12R = 1). If this is the case, the following rules apply for setting and resettingthe State Bits in Compare Mode (illustrated in Figure 18-11 and Figure 18-12):

A State Bit CC6xST is set to 1

• with the next T12 clock (fT12) after a compare-match when T12 is counting up(i.e., when the counter is incremented above the compare value);

• with the next T12 clock (fT12) after a zero-match AND a parallel compare-match whenT12 is counting up.

A State Bit CC6xST is reset to 0

• with the next T12 clock (fT12) after a compare-match when T12 is counting down(i.e., when the counter is decremented below the compare value);

• with the next T12 clock (fT12) after a zero-match AND NO parallel compare-matchwhen T12 is counting up.

Figure 18-11 Compare Operation, Edge-Aligned Mode

Figure 18-12 Compare Operation, Center-Aligned Mode

MCT05515

fT12

Zero

CompareValue

CC6xST

Compare-Match Compare-Match PeriodValue

T12 Count

MCT05516

fT12

Zero

CompareValue

CC6xST

PeriodValue

Compare-Match Compare-Match

T12 Count




Figure 18-13 illustrates some more examples for compare waveforms. It is important tonote that in these examples, it is assumed that some of the compare values are changedwhile the timer is running. This change is performed via a software preload of theShadow Register, CC6xSR. The value is transferred to the actual Compare RegisterCC6xR with the T12 Shadow Transfer signal, T12_ST, which is assumed to be enabled.

Figure 18-13 Compare Waveform Examples

Example b) illustrates the transition to a duty cycle of 100%. First, a compare value of0001H is used, then changed to 0000H. Please note that a low pulse with the length ofone T12 clock is still produced in the cycle where the new value 0000H is in effect; thispulse originates from the previous value 0001H. In the following timer cycles, the StateBit CCxST remains at 1, producing a 100% duty cycle signal. In this case, the comparerule ‘zero-match AND compare-match’ is in effect.

MCT05517

fT12

CDIR

CC6x Value n Value n+1 Value n+2 Value n+3

T12 Count

PeriodValue = 5

Zero

CC6x = 2

Down DownUp Up

CC6x = 2 CC6x = 1 CC6x = 1a)

CC6x = 1b)

CC6x = 0 CC6x = 0 CC6x = 0

CC6x = 3 CC6x = 3 CC6x = 3 CC6x = 3c)

CC6x = 4 CC6x = 4 CC6x = 4 CC6x = 4d)

CC6x = 5 CC6x = 5 CC6x = 5 CC6x = 5e)

CC6x = 3 CC6x = 6 CC6x = 6 CC6x = 6f)




Example f) shows the transition to a duty cycle of 0%. The new compare value is set to<Period-Value> + 1, and the State Bit CC6ST remains cleared.

Figure 18-14 illustrates an example for the waveforms of all three channels. With theappropriate dead-time control and output modulation, a very efficient 3-phase PWMsignal can be generated.

Figure 18-14 Three-Channel Compare Waveforms

MCT05518

PeriodValue

UpDown Down Up DownZeroCC61R

CC60R

CC62R

CC62ST

CC61ST

CC60ST

ShadowTransfer

CDIR

T12 Count




Compare Mode Output Path

Figure 18-15 gives an overview on the signal path from a channel State Bit to its outputpin in its simplest form. As illustrated, a user has a variety of controls to determine thedesired output signal switching behavior in relation to the current state of the State Bit,CC6xST. Please refer to Chapter 18.7 for details on the output modulation.

Figure 18-15 Compare Mode Simplified Output Path Diagram

MCA05519

State BitCC6xST

T12MODENyCOUT6xPS

LevelSelect

PSLy

LevelSelect

T12MODENx PSLx

CC6x

COUT6x

To Output Pins

Output Modulation

COUT6x_O

CC6x_O

Dead-TimeGeneration

CC6xPS

DTCx_IN

CC6xST

State Selection

CC6xST& DTRx

CC6xST& DTRx




Compare Mode Registers

In compare mode, registers CC6xR (x = 0, 1, 2) are the actual compare registers for T12.The values stored in CC6xR are compared (all three channels in parallel) to the countvalue of T12. Registers CC6xR can only be read by SW, the modification of the value isdone by a shadow register transfer from the corresponding shadow registers CC6xSR.These registers can be read and written by SW.

In capture mode, the current value of the T12 counter register is captured into registersCC6xR or CC6xSR when the corresponding capture event is detected (depending on theselected mode).

CCU6_CC60R Channel 0 Capt./Comp. Reg. XSFR (E898H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC60V

rh

CCU6_CC61RChannel 1 Capt./Comp. Reg. XSFR (E89AH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC61V

rh

CCU6_CC62RChannel 2 Capt./Comp. Reg. XSFR (E89CH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC62V

rh


CC6xV(x = 0, 1, 2)

[15:0] rh Channel x Compare ValueIn compare mode, the bitfields CC6xV contain the values that are compared to the T12 count value. In capture mode, the captured value of T12 can be read from these registers.




CCU6_CC60SR Ch. 0 Capt./Cmp. Shadow Reg. XSFR (E8A0H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC60S

rwh

CCU6_CC61SRCh. 1 Capt./Cmp. Shadow Reg. XSFR (E8A2H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC61S

rwh

CCU6_CC62SRCh. 2 Capt./Cmp. Shadow Reg. XSFR (E8A4H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC62S

rwh


CC6xS(x = 0, 1, 2)

[15:0] rwh Shadow Register for Channel x Compare ValueIn compare mode, the contents of bitfields CC6xS are transferred to bitfields CC6xV in registers CC6xR during a shadow transfer. In capture mode, the captured value of T12 can be read from these registers.




Register T12MSEL contains control bits to select the capture/compare functionality ofthe three channels of Timer T12.

Note: Channel status information is available through the channel state (modification)registers, described in Section 18.3.

CCU6_T12MSEL T12 Mode Select Register XSFR (E8C6H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - MSEL62 MSEL61 MSEL60

- - - - rw rw rw


MSEL62MSEL61MSEL60

[11:8][7:4][3:0]

rw Capture/Compare Mode SelectionThese bitfields select the operating mode of the three T12 capture/compare channels. Each channel (x = 0, 1, 2) can be programmed individually for one of these modes (except for Hall Sensor Mode). See Table 18-2.

Table 18-2 Capture/Compare Modes Overview

MSEL6x Selected Operating Mode

0000B Compare outputs disabled, pins CC6x and COUT6x can be used for IO.

0001B Compare output on pin CC6x, pin COUT6x can be used for IO.

0010B Compare output on pin COUT6x, pin CC6x can be used for IO.

0011B Compare output on pins COUT6x and CC6x.

01XXB Double-Register Capture modes, see Chapter 18.1.4 and Table 18-3.

1000B Hall Sensor Mode, see Chapter 18.5. In order to properly enable this mode, all three MSEL6x fields have to be programmed to Hall Sensor mode.

1001B Hysteresis-like mode, see Chapter 18.1.5.

101XB11XXB

Multi-Input Capture modes, see Chapter 18.1.4 and Table 18-4.




18.1.3 Dead-Time Generation

The generation of (complementary) signals for the highside and the lowside switches ofone power inverter phase is based on the same compare channel. For example, if thehighside switch should be active while the T12 counter value is above the compare value(State Bit = 1), then the lowside switch should be active while the counter value is belowthe compare value (State Bit = 0).

In most cases, the switching behavior of the connected power switches is notsymmetrical concerning the switch-on and switch-off times. A general problem arises ifthe time for switch-on is smaller than the time for switch-off of the power device. In thiscase, a short-circuit can occur in the inverter bridge leg, which may damage thecomplete system. In order to solve this problem by HW, this capture/compare unitcontains a programmable Dead-Time Generation Block, which is able to delay thepassive to active edge of the switching signals (the active to passive edge is notdelayed).

The Dead-Time Generation Block, illustrated in Figure 18-16, is built in a similar way forall three channels of T12. Any change of a CC6xST bit triggers the corresponding Dead-Time Counter, a single-shot 6-bit down counter which is clocked with the same inputclock as T12 (fT12). A trigger pulse DTCx_IN, activated by the change of the State BitCC6xST, leads to a reload of the dead-time counter with the value DTM stored in registerT12DTC and starts the counter.

Figure 18-16 Dead-Time Generation Block Diagram

Reload ValueDTM

&DTC1_IN

DTE1

6-bitDown Counter

&DTC0_IN

DTE0

6-bitDown Counter

fT12

DTRES

MCB05520

DTR2

&DTC2_IN

DTE2

6-bitDown Counter

DTR1DTR0




While counting down, the output line DTRx is 0. Thus, the reload value determines thelength of the low phase (the passive state) of the output signal, and therefore the delayof the 0-to-1 transition of the State Bit outputs. The active state of the output signal isrepresented by a 1.

The programmable reload value DTM applies to all three channels.

When the counter reaches zero, the counter is stopped and output line DTRx is set to 1.While DTRx is 0 both outputs are forced into passive state. While DTRx is 1 the outputscan go to active state.

Each of the three dead-time counters has its individual enable control bit, DTEx, for thetrigger input, DTCx_IN. A reload of a counter is only possible while the counter is notrunning. This avoids a possible retriggering of the dead-time if a change in the State BitCC6xST is detected. Figure 18-17 illustrates the waveforms of the dead-time generation(passive state = 0). The associated registers are detailed below.

Figure 18-17 Dead-Time Generation Waveforms

MCT05521

CC6xST &DTRx

CC6xST &DTRx

DTRx

DownCounter

DTCx_IN

CC6xST

CC6xST

CompareT12 Count




Register T12DTC controls the dead-time generation for the T12 compare channels.Each channel can be independently enabled/disabled for dead-time generation. Ifenabled, the transition from passive state to active state is delayed by the value definedby bitfield DTM.

Note: The Dead-Time Counters can be cleared by setting bit DTRES in register TCTR4.

CCU6_T12DTC T12 Dead-Time Control Reg. XSFR (E894H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-DTR

2DTR

1DTR

0-

DTE2

DTE1

DTE0

- - DTM

- rh rh rh - rw rw rw - - rw


DTR2DTR1DTR0

14,13,12

rh Dead Time Run Indication FlagsIndicate the status of the dead-time generation for each corresponding compare channel (0, 1, 2)0 The dead-time counter is stopped1 The dead-time counter is running (delay is

active)

DTE2DTE1DTE0

10,9,8

rw Dead-Time Generation Enable BitsEnable/disable the dead-time generation for each corresponding compare channel (0, 1, 2)0 Dead-time generation is disabled1 Dead-time generation is enabled

DTM [5:0] rw Dead-Time ValueDTM specifies the programmable delay between switching from the passive state to the active state of the selected outputs




18.1.4 T12 Capture Modes

Each of the three channels of the T12 Block can also be used to capture T12 timeinformation in response to an external signal.

There are a number of different modes for capture operation. In all modes, both of theregisters of a channel are used. This can reduce the interrupt rate to the CPU, as it needsto react only to every second event. The selection of the capture modes is done via theMSEL6x bitfields in register T12MSEL and can be selected individually for each of thechannels.

Figure 18-18 illustrates Capture Mode 1. When a rising edge (0-to-1 transition) isdetected at the corresponding input pin CC6x, the current contents of Timer T12 arecaptured into register CC6xR. When a falling edge (1-to-0 transition) is detected at pinCC6x, the contents of Timer T12 are captured into register CC6xSR.

Figure 18-18 Capture Mode 1 Block Diagram

Table 18-3 Capture Modes Overview

MSEL6x Mode Pin Active Edge CC6nSR Stored in T12 Stored in

0100B 1 CC6x Rising – CC6xR

CC6x Falling – CC6xSR

0101B 2 CC6x Rising CC6xR CC6xSR

0110B 3 CC6x Falling CC6xR CC6xSR

0111B 4 CC6x Any CC6xR CC6xSR

MCB05522

fT12

Edge

Detect

Select

State BitCC6xST

MSEL6x

CC6x

To Interrupt Logic

MSEL6x

Set

Rising Falling

Shadow RegisterCC6xSRRegister CC6xR

Counter RegisterT12




Capture Modes 2, 3 and 4 are shown in Figure 18-19. They differ only in the active edgecausing the capture operation. In each of the three modes, when the selected edge isdetected at the corresponding input pin CC6x, the current contents of the shadowregister CC6xSR are latched into register CC6xR, and the current Timer T12 contentsare captured in register CC6xSR (simultaneous transfer). The active edge is a risingedge at pin CC6x for Capture Mode 2, a falling edge for Mode 3, and both, a rising or afalling edge for Capture Mode 4, as shown in Table 18-3. These capture modes are veryuseful in cases where there is little time between two consecutive edges of the inputsignal.

Figure 18-19 Capture Modes 2, 3 and 4 Block Diagram

MCB05523

fT12

Edge

Detect

Select

State BitCC6xST

MSEL6x

CC6x

To Interrupt Logic

MSEL6x

RisingFalling

Set

Shadow RegisterCC6xSR

Register CC6xR

Counter RegisterT12




Five further capture modes are called Multi-Input Modes, as they use two differentexternal inputs, pin CC6x and pin CC6POSx.

Figure 18-20 Multi-Input Capture Modes Block Diagram

In each of these modes, the current T12 contents are latched in register CC6xR inresponse to a selected event at pin CC6x, and in register CC6xSR in response to aselected event at pin CC6POSx. The possible events can be opposite input transitions,or the same transitions, or any transition at the two input pins. The different options aredetailed in Table 18-4.

In each of the various capture modes, the Channel State Bit, CC6xST, is set to 1 whenthe selected capture trigger event at pin CC6x or CC6POSx has occurred. The State Bitmust be reset by software.

In addition, appropriate signal lines to the interrupt logic are activated, which cangenerate an interrupt request to the CPU. Regardless of the selected active edge, alledges detected at pin CC6x lead to the activation of the appropriate interrupt request line(see also Section 18.9).

MCB05524

fT12

Edge

Detect

Select

State BitCC6xST

MSEL6x

CC6x

To Interrupt Logic

MSEL6x

Set

RisingFalling

Shadow RegisterCC6xSRRegister CC6xR

Counter RegisterT12

Set

Select

MSEL6x

Edge

Detect

CC6POSx

MSEL6x




Table 18-4 Multi-Input Capture Modes Overview

MSEL6x Mode Pin Active Edge T12 Stored in

1010B 5 CC6x Rising CC6xR

CCPOSx Falling CC6xSR

1011B 6 CC6x Falling CC6xR

CCPOSx Rising CC6xSR

1100B 7 CC6x Rising CC6xR

CCPOSx Rising CC6xSR

1101B 8 CC6x Falling CC6xR

CCPOSx Falling CC6xSR

1110B 9 CC6x Any CC6xR

CCPOSx Any CC6xSR

1111B – reserved (no capture or compare action)




18.1.5 Hysteresis-Like Control Mode

The hysteresis-like control mode (MSEL6x = 1001B) offers the possibility to switch off thePWM output if the input CCPOSx becomes 0 by resetting bit CC6xST. This can be usedas a simple motor control feature by using a comparator indicating, e.g., overcurrent.While CCPOSx = 0, the PWM outputs of the corresponding channel are driving theirpassive levels. The setting of bit CC6xST is only possible while CCPOSx = 1.

Figure 18-21 Hysteresis-Like Control Mode Logic

In this mode, the State Bit CC6xST is reset when pin CC6POSx shows a negative edge.As long as input CC6POSx is 0, the outputs of the State Bit are in passive state. WhenCC6POSx is at high level, the outputs can be in active state and are determined by bitCC6xST (see Figure 18-10 for the state bit logic and Figure 18-15 for the output paths).

This mode can be used to introduce a timing-related behavior to a hysteresis controller.A standard hysteresis controller detects if a value exceeds a limit and switches its outputaccording to the compare result. Depending on the operating conditions, the switchingfrequency and the duty cycle are not fixed, but change permanently.

If (outer) time-related control loops based on a hysteresis controller (inner loop) shouldbe implemented, the outer loops show a better behavior if they are synchronized to theinner loops. Therefore, the hysteresis-like mode can be used, which combines timer-related switching with a hysteresis controller behavior. For example, in this mode, anoutput can be switched on according to a fixed time base, but it is switched off as soonas a falling edge is detected at input CCPOSx.

This mode can be used for standard PWM with overcurrent protection. As long as thereis no low level signal at pin CC6POSx, the output signals are generated in the normalmanner as described in the previous sections. Only if input CC6POSx shows a low level,e.g. due to the detection of overcurrent, the outputs are shut off to avoid harmful stressto the system.

MCA05525

CDIR

COUT6xO

Set/Reset

ControlLogic

MCC6xS/R

Edge

Detect

CC6POSxT12R

MSELx2

CM_6xT12_ZM

T12_SSEP

Bit CC6xST+ Dead-TimeGeneration

StateSelectLogic

CC6xO




18.2 Timer T13 Block

Timer T13 is implemented similarly to Timer T12, but only with one channel in comparemode. A 16-bit up-counter is connected to a channel register via a comparator, whichgenerates a signal when the counter contents match the contents of the channel register.A variety of control functions facilitate the adaptation of the T13 structure to differentapplication needs. In addition, T13 can be triggered synchronously to timer T12 events.

Figure 18-22 Overview Diagram of the Timer T13 Block

Figure 18-23 shows a detailed block diagram of Timer T13. It receives its input clock,fT13, from the module clock fCC6 via a programmable prescaler and an optional 1/256divider. T13 can only count up (similar to the Edge-Aligned mode of T12).

Via a comparator, T13 is connected to a Period Register, T13PR. This registerdetermines the maximum count value for T13. When T13 reaches the period value,signal T13_PM (T13 Period Match) is generated and T13 is reset to 0000H with the nextT13 clock edge. The Period Register receives a new period value from its ShadowPeriod Register, T13PS, which is loaded via software. The transfer of a new period valuefrom the shadow register into T13PR is controlled via the ‘T13 Shadow Transfer’ controlsignal, T13_ST. The generation of this signal depends on the associated control bitSTE13. Providing a shadow register for the period value as well as for other valuesrelated to the generation of the PWM signal facilitates a concurrent update by softwarefor all relevant parameters (see also Section 18.8).

Another signal indicates whether the counter contents are equal to 0000H (T13_ZM).

A Single-Shot control bit, T13SSC, enables an automatic stop of the timer when thecurrent counting period is finished (see Figure 18-25).

MCA05526

Timer T13Logic

CompareChannel 63 CC63ST

State Bit

To OutputModulation

Control/Status Logic




Figure 18-23 T13 Counter Logic and Period Comparators

The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set bysoftware via the associated set/reset bits T13RS or T13RR, or it is reset by hardwareaccording to preselected conditions.

Timer T13 can be cleared to 0000H via control bit T13RES. Setting this write-only bit onlyclears the timer contents, but has no further effects, e.g., it does not stop the timer.

The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bitSTE13. This bit can be set or reset by software indirectly through its associated set/resetcontrol bits T13STR and T13STD.

Two bitfields, T13TEC and T13TED, control the synchronization of T13 to Timer T12events. T13TEC selects the trigger event, while T13TED determines for which T12 countdirection the trigger should be active.

Note: The T13 Period Register and its associated shadow register are located at thesame physical address. A write access to this address targets the ShadowRegister, while a read access reads from the actual period register.

MCA05527

Comp.= ?


Period ShadowRegister T13PS

T13_PM

Counter RegisterT13

fCC6

Write-Only

Read-Only

T13Control

& Status

T13RSTE13T13REST13SSC

T13_ZM

T13STRT13STD

T13RRT13RS

= 0000H

T13_ST

fT13

T13PRE

MUX256n

T13CLK

T13TECT13TED




Register T13 represents the counting value of Timer T13. It can only be written whileTimer T13 is stopped. Write actions while T13 is running are not taken into account.Register T13 can always be read by SW.

Register T13PR contains the period value for Timer T13. The period value is comparedto the actual count value of T13 and T13 is reset when the two values match. Thisregister has a shadow register and the shadow transfer is controlled by bit STE13. A readaction by SW delivers the value which is currently used for the period compare, whereasa write action targets the shadow register. The shadow register structure allows aconcurrent update of all T13-related values.

CCU6_T13 Timer T13 Count Register XSFR (E8B0H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T13CV

rwh


T13CV [15:0] rwh Timer T13 Count ValueRepresents the 16-bit count value of Timer T13

CCU6_T13PR Timer T13 Period Register XSFR (E8B2H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T13PV

rwh


T13PV [15:0] rwh T13 Period ValueT13PV defines the count value for T13 which leads to a Period-Match. When reaching this value, Timer T13 is set to zero.




18.2.1 T13 Operation

The input clock fT13 of Timer T13 is derived from the module clock fCC6 through aprogrammable prescaler and an optional 1/256 divider. The resulting prescale factorsare listed in Table 18-5. The prescaler of T13 is reset while T13 is not running to ensurereproducible timings and delays.

The period of the timer is determined by the value in the period Register T13PRaccording to the following formula:

T13PER = <Period-Value> + 1; in T13 clocks (fT13) (18.3)

While Timer T13 is running, write accesses to the count register T13 are not taken intoaccount. If T13 is stopped, write actions to register T13 are immediately taken intoaccount.

As described above, T13 can only count up, comparable to the Edge-Aligned mode ofT12. This leads to very simple ‘counting rules’ for the T13 counter:

• The counter is reset to zero with the next T13 clock edge if a Period-Match isdetected. The counting direction is always upwards.

The behavior of T13 is illustrated in Figure 18-24.

Table 18-5 Timer T13 Input Clock Options

T13CLK Resulting Input ClockPrescaler Off (T13PRE = 0)

Resulting Input ClockPrescaler On (T13PRE = 1)

000B fCC6/1 fCC6/256

001B fCC6/2 fCC6/512

010B fCC6/4 fCC6/1024

011B fCC6/8 fCC6/2048

100B fCC6/16 fCC6/4096

101B fCC6/32 fCC6/8192

110B fCC6/64 fCC6/16384

111B fCC6/128 fCC6/32768




Figure 18-24 T13 Operation

T13 Shadow Transfer Signal, T13_ST

A special shadow transfer signal (T13_ST) can be generated to facilitate updating theperiod and compare values synchronously to the operation of T13. The generation of thissignal is requested by software via bit STE13 (set by writing 1 to the write-only bitT13STR, cleared by writing 1 to the write-only bit T13STD).

If requested (STE13 = 1), signal T13_ST is generated when:

• the counter is reset to 0000H after the Period-Match, or• timer T13 is not running (T13R = 0)

With signal T13_ST, a new period value is loaded from the shadow register into theactual period register T13PR, and a new compare value is transferred from its shadowregister into the actual compare register (see Section 18.1.2).

T13 Start/Stop and Reset Control

Timer T13 is started through software by setting the write-only bit T13RS. This operationsets the timer run bit T13R, and the timer starts counting. To stop the timer, the write-only bit T13RR needs to be set to 1. The run bit T13R is cleared to 0, and the timer stopscounting.

The run bit can also be cleared by hardware in Single Shot mode. In addition, T13 canbe started by events generated by the T12 Block, which set the run bit T13R. Please seethe next sections for details on these modes.

Software can clear timer T13 by writing 1 to the write-only bit T13RES. This operationonly sets the timer contents to 0000H. No further actions will take place, for example, thetimer run bit is not cleared.

MCT05528

fT13

Zero

CC63

Shadow Transfer

T13 Count

PeriodValue

PeriodMatch

ZeroMatch

Value n+1 Value n+2




Single-Shot Mode

The run bit T13R is also influenced by hardware in Single-Shot mode. This mode isenabled through bit T13SSC. When this bit is set, the timer will stop when the currenttimer period is finished (see Figure 18-25). This is when the timer is cleared to 0000Hafter having reached the period value.

Figure 18-25 Single-Shot Operation of Timer T13

Zero

CompareValue

Compare-Match PeriodValue

MCT05529

fT13

CC63ST

T13SSC

T13 Count




Synchronization of T13 to T12

Timer T13 can be synchronized to a T12 event. Bitfields T13TEC and T13TED select theevent which is used to start Timer T13. The selected event sets bit T13R via HW, andT13 starts counting. Combined with the Single-Shot mode, this feature can be used togenerate a programmable delay after a T12 event.

Figure 18-26 shows an example for the synchronization of T13 to a T12 event. Here, theselected event is a compare-match (compare value = 2) while counting up. The clocksof T12 and T13 can be different (other prescaler factor); the figure shows an example inwhich T13 is clocked with half the frequency of T12.

Figure 18-26 Synchronization of T13 to T12

Bitfield T13TEC selects the trigger event to start T13 (automatic set of T13R forsynchronization to T12 compare signals) according to the combinations shown inTable 18-6. Bitfield T13TED additionally specifies for which count direction of T12 theselected trigger event should be regarded (see Table 18-7).

Zero

CompareValue

Compare-Match PeriodValue

MCT05530

fT12

T13R

T13 Count

fT13

T12 Count




Table 18-6 T12 Trigger Event Selection

T13TEC Selected Event

000B None.

001B T12 Compare Event on Channel 0.



100B T12 Compare Event on any Channel (0, 1, 2).

101B T12 Period-Match.

110B T12 Zero-Match while counting up.

111B Any Hall State Change.

Table 18-7 T12 Trigger Event Additional Specifier

T13TED Selected Event Specifier

00B Reserved, no action.

01B Selected event is active while T12 is counting up.

10B Selected event is active while T12 is counting down.

11B Selected event is active independently of the count direction of T12.




18.2.2 T13 Compare Modes

Associated with Timer T13 is one compare channel, which can perform compareoperations with regard to the contents of the T13 counter.

Figure 18-27 gives an overview on the T13 channel in Compare Mode. The channel isconnected to the T13 counter register via an Equal-to comparator, which generates amatch signal when the contents of the counter matches the contents of the compareregister. The channel consists of the comparator and a double register structure - theactual compare register, CC63R, feeding the comparator, and an associated shadowregister, CC63SR, which is preloaded by software and transferred into the compareregister when signal T13 shadow transfer, T13_ST, gets active. Providing a shadowregister for the compare value as well as for other values related to the generation of thePWM signal facilitates a concurrent update by software for all relevant parameters. Seealso Section 18.8, which provides an overview on this functionality.

Figure 18-27 T13 Channel Comparator

Associated with the channel is a State Bit, CC63ST, which holds the status of thecompare operation. This bit is set and reset according to certain conditions, which areexplained in more detail in the following sections. Figure 18-28 gives an overview on thelogic for the State Bit.

MCA05531

Comp.= ?



Compare Match CM_63

T13_ST

Counter RegisterT13

fT13




Figure 18-28 T13 State Bit Block Diagram

The inputs to the set/reset logic for the CC6xST bits are the timer run bit (T13R), thetimer zero-match signal (T13_ZM), the end-of-single-shot mode signal (T13_SSEP), andthe actual individual compare-match signal CM_63. In addition, the state bit can be setor reset by software via the set and reset bits, MCC63S and MCC63R.

A modification of the State Bit CC63ST by hardware is only possible while Timer T13 isrunning (T13R = 1). If this is the case, the following rules apply for setting and resettingthe State Bit in Compare Mode:

State Bit CC63ST is set to 1

• with the next T13 clock (fT13) after a compare-match (T13 is always counting up)(i.e., when the counter is incremented above the compare value);

• with the next T13 clock (fT13) after a zero-match AND a parallel compare-match.

State Bit CC63ST is reset to 0

• with the next T13 clock (fT13) after a zero-match AND NO parallel compare-match.

Figure 18-29 T13 Compare Operation

Note: The waveforms in Figure 18-29 correspond to the T12-waveforms inFigure 18-11.

MCB05532


MCC63S/R

State BitCC63ST

T13_SSEP

T13_ZM

CM_63 CC63ST

CC63ST

T13R

MCT05533

fT13

Zero

CompareValue

CC63ST

Compare-Match Compare-Match PeriodValue

T13 Count




T13 Compare Mode Output Path

Figure 18-30 gives an overview on the signal path from the channel State Bit to its outputpin in its simplest form. As illustrated, a user has a variety of controls to determine thedesired output signal switching behavior in relation to the current state of the State Bit,CC63ST. Please refer to Section 18.7 for detailed information on the output modulationcontrol.

Figure 18-30 CC63 Output Path

The output line COUT63_O can generate a T13 PWM at the output pin COUT63. Thesignal CC63_O can be used to modulate the T12-related output signals with a T13 PWM.In order to decouple COUT63 from the internal modulation, the compare state leading toan active signal can be selected independently by bits T13IM and COUT63PS.

MCA05534

State BitCC63ST

COUT63PS

LevelSelect

PSL63

To Output PinCOUT63

COUT63_O

CC63_O

T13IM

CC63ST

CC63ST

ECT13O

State Selection

OutputModulation




T13 Compare Mode Registers

Register CC63R is the actual compare registers for T13. The value stored in CC63R iscompared to the count value of T13. Register CC63R can only be read by SW, themodification of the value is done by a shadow register transfer from the correspondingshadow register CC63SR. This register can be read and written by SW.

CCU6_CC63R Channel 3 Compare Register XSFR (E8B4H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC63V

rh


CC63V [15:0] rh Channel 3 Compare ValueBitfield CC6xV contains the value that is compared to the T13 count value

CCU6_CC63SR Channel 3 Comp. Shadow Reg. XSFR (E8B6H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC63S

rwh


CC63S [15:0] rwh Shadow Register for Channel 3 Compare ValueThe contents of CC63S are transferred to bitfield CC63V in register CC63R during a shadow transfer




18.3 Timer Block Control

Most features of timers T12 and T13 are controlled via the timer control registers TCTR0,TCTR2, and TCTR4.

Register TCTR0 controls the basic functionality of both timers, T12 and T13.

CCU6_TCTR0 Timer Control Register 0 XSFR (E8ACH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- -STE13

T13RT13PRE

T13CLK CTM CDIRSTE12

T12RT12PRE

T12CLK

- - rh rh rw rw rw rh rh rh rw rw


STE131) 13 rh Timer T13 Shadow Transfer Enable0 The shadow register transfer is not requested1 The shadow register transfer is requested

T13R2) 12 rh Timer T13 Run BitT13R starts and stops timer T13. It is set/reset by SW via bits T13RR or T13RS or it is reset by HW according to the function defined by bitfield T13SSC.0 Timer T13 is stopped1 Timer T13 is running

T13PRE 11 rw Timer T13 Prescaler Enable BitEnables the additional 1/256-prescaler of T130 The additional prescaler is disabled1 The additional prescaler is enabled

T13CLK [10:8] rw Timer T13 Input Clock SelectSelects the input clock for Timer T13 which is derived from the CAPCOM6 input clock according to the equation:fT13 = fCC6/2

<T13CLK>. See Table 18-5.

CTM 7 rw T12 Operating Mode0 Edge-Aligned Mode1 Center-Aligned Mode

CDIR 6 rh Count Direction of Timer T12Displays the current counting direction of T120 T12 counts up1 T12 counts down




Note: A write action to the bitfields T12CLK/T13CLK or T12PRE/T13PRE is only takeninto account while timer T12/T13 is not running (T12/T13R = 0).

STE121) 5 rh Timer T12 Shadow Transfer Enable0 The shadow register transfer is not requested1 The shadow register transfer is requested

T12R2) 4 rh Timer T12 Run BitT12R starts and stops Timer T12. It is set/reset by SW via bits T12RR or T12RS, or it is reset by HW according to the function defined by bitfield T12SSC.0 Timer T12 is stopped1 Timer T12 is running

T12PRE 3 rw Timer T12 Prescaler Enable BitEnables the additional 1/256-prescaler of T120 The additional prescaler is disabled1 The additional prescaler is enabled

T12CLK [2:0] rw Timer T12 Input Clock SelectSelects the input clock for Timer T12 which is derived from the CAPCOM6 input clock according to the equation:fT12 = fCC6/2

<T12CLK>. See Table 18-1.1) Bit STE12/STE13 is cleared when the shadow transfer takes place.

2) A concurrent set/reset action on T13R/T12R (from TxSSC, TxRR or TxRS) will have no effect. Bit T13R/T12Rwill remain unchanged.





Register TCTR2 controls the single-shot and the synchronization functionality of bothtimers T12 and T13.

Register TCTR4 provides software-control (independent set and clear conditions) for therun bits T12R and T13R. Furthermore, the timers can be reset (while running) and bitsSTE12 and STE13 can be controlled by software. Reading these bits always returns 0s.

CCU6_TCTR2 Timer Control Register 2 XSFR (E8AEH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - - -T13TED

T13TEC

T13SSC

T12SSC

- - - - - - - - - rw rw rw rw


T13TED [6:5] rw Trigger Event Direction ControlBitfield T13TED additionally specifies for which count direction of T12 the selected trigger event should be regarded (see Table 18-7).

T13TEC [4:2] rw Trigger Event SelectionBitfield T13TEC selects the trigger event to start T13 (automatic set of T13R for synchronization to T12 compare signals) according to Table 18-6.

T13SSCT12SSC

10

rw Timer T13/T12 Single Shot ControlThis bit enables the Single-Shot Mode of T13/T120 Single-Shot Mode is disabled1 Single-Shot Mode is enabled




CCU6_TCTR4 Timer Control Register 4 XSFR (E8A6H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T13STD

T13STR

- - -T13RES

T13RS

T13RR

T12STD

T12STR

- -DT

REST12RES

T12RS

T12RR

w w - - - w w w w w - - w w w w


T13STDT12STD

157

w Timer T13/T12 Shadow Transfer Disable0 No action1 STE13/STE12 is cleared without triggering the

shadow transfer

T13STRT12STR

146

w Timer T13/T12 Shadow Transfer Request0 No action1 STE13/STE12 is set, requesting the shadow

transfer

T13REST12RES

102

w Timer T13/T12 Reset0 No effect on T13/T121 The T13/T12 counter register is reset to zero.

The switching of the output signals is according to the switching rules. Setting of T13RES/T12RES has no impact on bit T13R/T12R.

T13RST12RS

91

w Timer T13/T12 Run Bit Set Control1)

Software can set bit T13R/T12R (start timer T13/T12) by writing to bit T13RS/T12RS.0 T13R/T12R is not set1 T13R/T12R is set, T13/T12 starts counting

T13RRT12RR

80

w Timer T13/T12 Run Bit Reset Control1)

Software can clear bit T13R/T12R (stop timer T13/T12) by writing to bit T13RR/T12RR.0 T13R/T12R is not cleared1 T13R/T12R is cleared, T13/T12 stops counting

DTRES 3 w Dead-Time Counter Reset0 No effect on the Dead-Time counters1 All three Dead-Time counters are cleared and

stopped1) Setting the respective set- and reset-control bits together will not influence the associated timer.




The channel state register CMPSTAT contains status bits displaying the current captureor compare state and control bits defining the active/passive state of a compare channel.

CCU6_CMPSTAT Compare State Register XSFR (E8A8H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T13IM

COUT63PS

COUT62PS

CC62PS

COUT61PS

CC61PS

COUT60PS

CC60PS

-CC

63ST

CCPOS

2

CCPOS

1

CCPOS

0

CC62ST

CC61ST

CC60ST

rwh rwh rwh rwh rwh rwh rwh rwh - rh rh rh rh rh rh rh


T13IM 15 rwh T13 Inverted Modulation ControlBit T13IM inverts signal CC63_O for the modulation of the CC6x and COUT6x (x = 0, 1, 2) signals0 CC63_O is not inverted1 CC63_O is inverted for further modulation

COUT63PS1)

COUT62PSCC62PSCOUT61PSCC61PSCOUT60PSCC60PS

1) These bits have shadow bits and are updated in parallel to the capture/compare registers of T12 or T13,respectively. A read action targets the actually used values, whereas a write action targets the shadow bits.

141312111098

rwh Passive State Select for Compare OutputBit COUT6xPS/CC6xPS selects the state of the compare channel, considered as the passive state. During the passive state, the passive level (defined in register PSLR) is driven by the output pin.0 The compare output drives passive level while

CC6xST is 01 The compare output drives passive level while

CC6xST is 1

Note: In capture mode, these bits are not used.

CC63ST2)

CC62STCC61STCC60ST

2) These bits are set and reset according to the T12, T13 switching rules.

6210

rh T13/T12 Compare State BitBits CC6xST monitor the state of the capture/ compare channels.Compare mode:0 The timer count is less than the compare value1 The timer count is greater than the comp. valueCapture mode (channels 0 … 2 only):0 The selected edge has not yet been detected1 The selected edge has been detected

CCPOSx 5, 4, 3 rh Sampled Hall Pattern Bits




The Compare Status Modification Register CMPMODIF provides software-control(independent set and clear conditions) for the channel state bits CC6xST. This featureenables the user to individually change the status of the output lines by software, forexample when the corresponding compare timer is stopped.

CCU6_CMPMODIF Comp. State Modification Reg. XSFR (E8AAH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-MCC63R

- - -MCC62R

MCC61R

MCC60R

-MCC63S

- - -MCC62S

MCC61S

MCC60S

- w - - - w w w - w - - - w w w


MCC63RMCC62RMCC61RMCC60R

141098

w Capture/Compare Channel x Status Reset Bit0 No action1 Bit CC6xST is cleared1)

1) Setting the respective set- and reset-control bits together will toggle the associated status bit.

MCC63SMCC62SMCC61SMCC60S

6210

w Capture/Compare Channel x Status Set Bit0 No action1 Bit CC6xST is set1)




18.4 Multi-Channel Mode

The Multi-Channel mode offers the possibility to modulate all six T12-related outputsignals with one instruction. The bits in bitfield MCMOUT.MCMP are used to specify theoutputs which may become active. If Multi-Channel mode is enabled (bitMODCTR.MCMEN = 1), only those outputs may become active, which have a 1 at thecorresponding bit position in bitfield MCMP.

This bitfield has its own shadow bitfield, MCMPS, which can be written by software. Thetransfer of the new value in MCMPS to the bitfield MCMP can be triggered by, andsynchronized to, T12 or T13 events. This structure permits the software to write the newvalue, which is then taken into account by the hardware at a well-defined moment andsynchronized to a PWM signal. This avoids unintended pulses due to unsynchronizedmodulation sources (T12, T13, software).

Figure 18-31 Multi-Channel Mode Block Diagram

Figure 18-31 shows the modulation selection for the Multi-Channel mode. The eventthat triggers the update of bitfield MCMP is chosen by SWSEL. In order to synchronizethe update of MCMP to a PWM generated by T12 or T13, bitfield SWSYN allows theselection of the synchronization event, which leads to the transfer from MCMPS toMCMP. Due to this structure, an update takes place with a new PWM period. A reminderflag, bit R, is set when the selected switching event occurs, and is reset when the transfertakes place. This flag can be monitored by software to check for the status of this logic.

MCB05535

SwitchingSynchro-nization

Shadow RegisterMCMOUTS.MCMPS

Shadow TransferMCM_ST

RegisterMCMOUTS.MCMP

Modulation Control

Output Pins CC6x/COUT6x

State BitOutputs

SW Update, STRMCMT12_ZMT13_ZM

MUX

T12_PMCM_61_UP

T12_OMT13_PM

Corr. Hall Evt. CM_CHE0

SWSEL

SWSYN




If it is explicitly desired, the update takes place immediately with the occurrence of theselected event when the direct synchronization mode is selected. The update can alsobe requested by software by writing to bitfield MCMPS with the shadow transfer requestbit STRMCM set. By using the direct mode and bit STRMCM, the update takes placecompletely under software control. The event selection and synchronization options aresummarized in Table 18-8 and Table 18-9.

Table 18-8 Multi-Channel Mode Trigger Event Selection

SWSEL Selected Event (see register CCU6_MCMCTR)1)

1) Software control is always possible.

000B None

001B Correct Hall Event (CM_CHE) at pins CCPOS6x

010B T13 Period-Match (T13_PM)

011B T12 One-Match while counting down (T12_OM)

100B T12 Compare Event of Channel 1 while counting up (CM_61_UP; see Section 18.5 and Figure 18-34). Phase delay function

101B T12 Period-Match while counting up (T12_PM)

11xB Reserved, no action

Table 18-9 Multi-Channel Mode Trigger Event Synchronization

SWSYN Synchronization Event (see register CCU6_MCMCTR)

00B Direct Mode: the trigger event directly causes the shadow transfer

01B T13 Zero-Match

10B T12 Zero-Match while counting up

11B Reserved, no action




Register MODCTR contains control bits enabling the modulation of the correspondingoutput signal by PWM patterns generated by timers T12 and T13. Furthermore, theMulti-Channel mode can be enabled as additional modulation source for the outputsignals.

Note: Registers MCMOUT, MCMOUTS, and MCMCTR are also related to Multi-Channel Mode operation.

CCU6_MODCTR Modulation Control Register XSFR (E8C0H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECT13O

- T13MODENMCMEN

- T12MODEN

rw - rw rw - rw


ECT13O 15 rw Enable Compare Timer T13 Output0 Signal COUT63 is forced to 01 Signal COUT63 can switch as programmed

T13MODENT12MODEN

[13:8][5:0]

rw T13/T12 Modulation EnableThese bits enable the modulation of the corresponding compare channel(s) by a PWM pattern generated by timer T13 or T12.0 No modulation by T13/T121 Corresponding output is modulated by a

T13/T12 PWM patternT13MODEN[5:0] and T12MODEN[5:0] correspond (left to right) to:COUT62, CC62, COUT61, CC61, COUT60, CC60.

MCMEN 7 rw Multi-Channel Mode EnableEnables the modulation of the output signals by a multi-channel pattern according to bitfield MCMOUT0 The modulation is disabled1 The modulation is enabled




18.5 Hall Sensor Mode

For Brushless DC-Motors, usually the Multi-Channel Mode is used, as the modulationpatterns need to be output to properly control the motor. These patterns need to beoutput in relation to the angular position of the motor. For this, usually Hall sensors orBack-EMF sensing are used to determine the angular rotor position. The CAPCOM6provides three inputs, CC6POS0 … CC6POS2, which can be used as inputs for the Hallsensors or the Back-EMF detection signals.

There is a strong correlation between the motor position and the output modulationpattern. When a certain position of the motor has been reached, indicated by thesampled Hall sensor inputs (the Hall pattern), the next, pre-determined Modulationpattern has to be output. Because of different machine types, the modulation pattern fordriving the motor can vary. Therefore, it is wishful to have a wide flexibility in defining thecorrelation between the Hall pattern and the corresponding Modulation pattern.

The CAPCOM6 offers this by having a register which contains the actual current Hallpattern (CURH), the next expected Hall pattern (EXPH) and the corresponding outputpattern (MCMP). A new Modulation pattern is output when the sampled Hall inputsmatch the expected ones (EXPH). To detect the next rotation phase (segment for blockcommutation), the CAPCOM6 monitors the Hall inputs for changes. When the nextexpected Hall pattern is detected, the next corresponding Modulation pattern is output.

To provide for noise immunity (to a certain extend), the CAPCOM6 offers the possibilityto introduce a sampling delay for the Hall inputs. In addition, it compares the sampledHall signals to the current Hall pattern (CURH) to provide for some tolerance in case ofshort spikes.

For the Hall and Modulation patterns, a double-register structure is implemented. Whileregister MCMOUT holds the actually used values, its shadow register MCMOUTS canbe loaded by software from a pre-defined table, holding the appropriate Hall andModulation patterns for the given motor control.

A transfer from the shadow register into register MCMOUT can take place when acorrect Hall pattern change is detected, that is, when the sampled Hall pattern matchesthe expected one. Software can then load the next values into register MCMOUTS. It isalso possible by software to force a transfer from MCMOUTS into MCMOUT.




18.5.1 Hall Pattern Compare Logic

Figure 18-32 gives an overview on the double-register structure and the patterncompare logic. Software writes the next modulation pattern (MCMPS) and thecorresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadowregister MCMOUTS. Register MCMOUT holds the actually used values. The modulationpattern MCMP is provided to the Output Modulation Control block. The current (CURH)and expected (EXPH) Hall patterns are compared to the sampled Hall sensor inputs(pins CC6POSx) by comparators. Sampling of the inputs and the evaluation of thecomparator outputs is controlled by signal HCRDY (Hall Compare Ready), which isdetailed in the next section.

Figure 18-32 Hall Pattern Compare Logic

When the sampled Hall pattern matches the expected one (EXPH), signal CM_CHE(Correct Hall Event) is generated. When the sampled Hall pattern matches the currentone (CURH), no signal is generated, as this is a normal case after a spike on the inputline. If the sampled pattern matches neither EXPH nor CURH, signal CM_WHE isgenerated, which indicates a wrong Hall event.

At every correct Hall event (CM_CHE), the next Hall patterns are transferred from theshadow register MCMOUTS into MCMOUT, and a new Hall pattern with itscorresponding output pattern can be loaded (from a predefined table) by software intoMCMOUTS. For the Modulation patterns, signal MCM_ST is used to trigger the transfer.This signal can be generated through signal CM_CHE (see Figure 18-31). Loading this

MCA05536

Comp.= ?

Comp.= ?

Comb.Logic

HCRDY

Correct Hall EventCM_CHE

Wrong Hall EventCM_WHE

MCMPS

To OutputModulation

RegisterMCMOUT

RegisterMCMOUTS

EXPHCURH

Sam

ple

HCRDY

CC

6PO

S0.

.2

CURHS EXPHS

ShadowTransferCM_CHE

ShadowTransferMCM_ST

SW Write SW Write SW Write

MCMP




shadow register can also be done by a write action on MCMOUTS with bit STRHP = 1.In case of a phase delay (generated by T12 channel 1), a new pattern is applied whenthe Multi-Channel mode shadow transfer MCM_ST (indicated by bit STR) occurs.

18.5.2 Sampling of the Hall Pattern

The Hall sensor inputs (CC6POSx) are monitored with the module clock (fCC6) via anedge detection block. When a level change is detected on any one of the three inputs, asignal is generated. In order to suppress spikes on the Hall inputs due to high di/dt inrugged inverter environment, a hardware noise filter can be used.

This noise filtering is performed using the Dead-Time Counter DTC0. For this function,the mode control bitfields MSELx for the T12 Channels must all be programmed to‘1000’. The output signal of the edge detection block is used to trigger DTC0. It isreloaded, starts counting, and thus generates a delay. An output signal, DTC0_O, isgenerated when the counter reaches the value one. This signal is used as the inputsampling and compare evaluation signal HCRDY (see Figure 18-32).

This feature provides a noise filter by delay. Most disturbances, such as switching spikesand signal bouncing, can be eliminated this way. When an input signal change wasdetected, the inputs are sampled a certain time later, determined by the reload value ofDTC0. They are then compared to the current and expected Hall patterns. If the sampledpattern matches the current pattern (CURH), the detected input signal change was dueto a noise spike (which is not visible anymore), and no further action will be triggered. Ifthe sampled pattern matches the expected one (EXPH), the signal change was a correctHall event, and signal CM_CHE is generated to trigger further actions.

However, when the sampled pattern matches none of CURH and EXPH, the detectedinput change lead to a wrong Hall pattern. Signal CM_WHE is generated to indicate thisfault and to allow further appropriate actions.

Figure 18-33 illustrates the noise filter logic.

Figure 18-33 Hall Trigger Logic Block Diagram

MCB05537CC

PO

S60

..62

Edge

Detect

Dead-TimeGen. Block

DTC0

HallCompare

Logic

DTC0_O HCRDY




18.5.3 Brushless DC-Motor Control with Timer T12 Block

The CAPCOM6 provides a mode for the Timer T12 Block especially targeted forconvenient control of Brushless DC-Motors. This mode is selected by setting all MSELxbitfields of the three T12 Channels to 1000B.

In this mode, illustrated in Figure 18-34, channel 0 is placed in capture mode, whilechannels 1 and 2 are in compare mode.

Figure 18-34 T12 Block in Hall Sensor Mode

The signal to transfer the new compare values from the shadow registers (CC6xSR) intothe actual compare registers (CC6xR) is now taken from the Correct Hall EventCompare, CM_CHE. In addition, this signal triggers a capture of the current T12 contentsinto register CC60R, and then forces a reset of T12 to 0000H. The same signal is alsoused to perform the shadow transfer of the new T12 period value.

Note: In this mode, the shadow transfer signal T12_ST is not generated. Shadow bits,such as the PSLy bits, will not be transferred to their main registers. To programthe main registers, SW needs to write to these registers while Timer T12 isstopped. In this case, a SW write actualizes both registers.

MCA05538

Comp.= ?



Comp.= ?



CM_CHE

Counter RegisterT12fT12 CM_CHE

Reset

CM_61

CM_62CM_CHE

Capture RegisterCC60R




Figure 18-35 Brushless DC-Motor Control Example (all MSEL6x = 1000B)

After the detection of a valid expected Hall pattern, the T12 count value is captured intochannel 0 (representing the actual motor speed), and T12 is reset. When the timerreaches the compare value in channel 1, the next multi-channel state is switched bytriggering the shadow transfer of bitfield MCMP (if enabled in bitfield SWEN). This triggerevent can be combined with several conditions which are necessary to implement anoise filtering (correct Hall event) and to synchronize the next multi-channel state to themodulation sources (avoiding spikes on the output lines). This compare function ofchannel 1 can be used as a phase delay from the position sensor input signals to theswitching of the output signals, which is necessary if a sensorless back-EMF techniqueis used instead of Hall sensors. The compare value in channel 2 can be used as a time-out trigger (interrupt), indicating that the motor’s actual speed is far below the desireddestination value, which can be caused by an abnormal load change. In this mode, themodulation of the outputs by T12 needs to be disabled (T12MODENx = 0).

MCT05539

COUT6x

CC62 Comp.

CC6x

MCMP

EXPH

CURH

= 011= 001 = 110= 010 = 100 = ???

= 001= 101 = 010= 011 = 110 = 100

CC6POS2 1 0 0 0 1 1

CC6POS1 0 0 1 1 1 0

CC6POS0 1 1 1 0 0 0

0000H

CC61 Comp.

T12 Count

Hall Event capturesand resets T12

CC62 Comparefor Time-Out

CC61 Comparefor Phase Delay




The capturing of the timer value in register CC60R, the shadow transfer from registersCC61SR to CC61R, from CC62SR to CC62R, and for the T12 period value, is donetogether with the reset event for T12.

18.5.4 Hall Mode Flags

Depending on the Hall pattern compare operation, a number of flags are set in order toindicate the status of the module and to trigger further actions and interrupt requests.

Flag CHE (Correct Hall Event) in register IS is set via signal CM_CHE when the sampledHall pattern matches the expected one (EXPH). This flag can also be set by SW viasetting bit SCHE in register ISS. If enabled through bit ENCHE (in register IEN), the setsignal for CHE can also generate an interrupt request to the CPU. To clear flag CHE, SWneeds to write a 1 to bit RCHE in register ISR.

Flag WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as wellas interrupt request generation is the same as described above for flag CHE.

The implementation of flag STR is done in the same way as for CHE and WHE. This flagis set by HW via the shadow transfer signal MCM_ST (see also Figure 18-31).




Figure 18-36 Hall Mode Flag Logic

Please note that for flags CHE, WHE, and STR, the interrupt request generation istriggered by the set signal for the flag. That means, a request can be generated even ifthe flag is already set. There is no need to reset the flag in order to enable furtherinterrupt requests.

The implementation for the IDLE flag is different. It is set by HW through signal CM_WHEif enabled by bit ENIDLE. Software can also set the flag via bit SIDLE. As long as bit IDLEis set, the modulation pattern field MCMP is cleared to force the outputs to the passivestate. Flag IDLE must be reset by software through bit RIDLE in order to return to normaloperation. To fully restart from IDLE mode, the transfer requests for the bitfields inregister MCMOUTS to register MCMOUT have to be initiated by software via bitsSTRMCM and STRHP in register MCMOUTS. In this way, the release from IDLE modeis under software control, but can be performed synchronously to the PWM signal.

&

MCA05540

>1_SCHE

Set

CM_CHE

>1_SWHE

Set

CM_WHE

RWHE

&>1_

ENIDLE

SIDLE

IDLE

CHE ResetRCHE

WHE Reset

Set

Reset

RIDLE

&

ENCHE

&

ENWHE

Interrupt Req.

Interrupt Req.

STR

>1_

SetRSTR

Reset

ENSTRInterrupt Req.

SSTR

MCM_ST

Clear MCMP




Hall Mode Registers

Register MCMOUTS contains the shadow bitfields for the modulation and Hall patternsas well as control bits for a software-initiated shadow transfer. The contents of bitfieldsMCMPS, EXPHS, and CURHS are transferred into the corresponding fields of registerMCMOUT when the associated shadow transfer signals are activated.

CCU6_MCMOUTS Multi-Ch. Mode Outp. Shad. R. XSFR (E8CAH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STRHP

- CURHS EXPHSSTRMCM

- MCMPS

w - rw rw w - rw


STRHP 15 w Shadow Transfer Request for the Hall PatternsSetting this bit during a write action leads to an immediate update of bitfields CURH and EXPH by the value written to CURHS and EXPHS. This functionality permits an update triggered by SW. When read, this bit always delivers 0.0 CURH and EXPH are updated according to the

defined HW action. The write access to CURHS and EXPH does not modify bitfields CURH and EXPH.

1 CURH and EXPH are updated by the value written to bitfields CURHS and EXPHS.

CURHS [13:11] rw Current Hall Pattern Shadow FieldCURHS is the shadow field for bitfield CURH. The bitfield is transferred to CURH when a correct Hall event is detected.

EXPHS [10:8] rw Expected Hall Pattern Shadow FieldEXPHS is the shadow field for bitfield EXPH. The bitfield is transferred to EXPH when a correct Hall event is detected.




Register MCMOUT holds the Modulation and Hall patterns that are currently used.

STRMCM 7 w Shadow Transfer Request for MCMPSSetting this bit during a write action leads to an immediate update of bitfield MCMP by the value written to MCMPS. This functionality permits an update triggered by SW. When read, this bit always delivers 0.0 MCMP is updated according to the defined HW

action. The write access to MCMPS does not modify MCMP.

1 MCMP is updated by the value written to MCMPS.

MCMPS [5:0] rw Multi-Channel PWM Pattern Shadow FieldMCMPS is the shadow field for bitfield MCMP. The Multi-Channel shadow transfer is triggered according to the transfer conditions defined by register MCMCTR.

CCU6_MCMOUT Multi-Ch. Mode Output Reg. XSFR (E8CCH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - CURH EXPH - R MCMP

- - rh rh - rh rh


CURH1) [13:11] rh Current Hall PatternCURH is written by a shadow transfer from bitfield CURHS. Bitfield CURH is compared to the sampled Hall pattern after every detected edge at the Hall sensor inputs CC6POSx. If the pattern match, the detected edge has been an invalid transition (e.g. due to a spike), and no further action is performed. If the sampled pattern do not either match CURH or EXPH, a Wrong Hall Event signal is set, which can trigger further actions.





EXPH1) [10:8] rh Expected Hall PatternEXPH is written by a shadow transfer from bitfield EXPHS. Bitfield EXPH is compared to the sampled Hall pattern after every detected edge at the Hall sensor inputs CC6POSx. If the pattern match, a Correct Hall Event signal is generated, which triggers further actions.

R 6 rh Reminder FlagIndicates that the shadow transfer from bitfield MCMPS to MCMP has been requested by the selected trigger source. This bit is cleared while MCMEN = 0 and when the shadow transfer takes place.0 No shadow transfer is requested1 A shadow transfer from MCMPS to MCMP has

been requested but not yet executed

MCMP2) [5:0] rh Multi-Channel Modulation PatternMCMP contains the output modulation pattern for the Multi-Channel mode, which can set the corresponding output to the passive state. It is written by a shadow transfer from bitfield MCMPS.0 The output is set to the passive state.1 The output can deliver the PWM generated by

T12 or T13 (according to register MODCTR).MCMP[5:0] corresponds to (left to right):COUT62, CC62, COUT61, CC61, COUT60, CC60.

1) The bits in the bitfields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x = 0, 1,2) in the order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS.1, CCPOS0).

2) While bit IS.IDLE = 1, bitfield MCMP is cleared.





Register MCMCTR contains control bits for the Multi-Channel mode, controlling theoutput modulation pattern.

Note: The generation of the shadow transfer request by HW is only enabled if bitMCMEN = 1.

CCU6_MCMCTR Multi-Ch. Mode Control Reg. XSFR (E8CEH/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - - - - SWSYN - SWSEL

- - - - - - - - - - rw - rw


SWSYN [5:4] rw Switching SynchronizationSWSYN triggers the shadow transfer from MCMPS to MCMP, if it has been requested before (flag R set) by an event selected by SWSEL. This permits the synchronization of the outputs to the source which is used for modulation (T12 or T13). See Table 18-9.

SWSEL [2:0] rw Switching SelectionSWSEL selects the trigger source (next multi-channel event) for the shadow transfer from MCMPS to MCMP. The transfer takes place synchronously with the selected event. See Table 18-8.




18.6 Trap Handling

The trap functionality permits the PWM outputs to react on the state of the input pinCTRAP. This functionality can be used to switch off the power devices if the trap inputbecomes active (e.g. to perform an emergency stop).

The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State. Itcan also be set by SW. The Trap State Bit TRPS determines the effect on the outputsand controls the exit of the Trap State.

When a trap condition is detected, both, the Trap Flag TRPF and the Trap State BitTRPS, are set to 1. The Trap State is entered immediately. The output of the Trap StateBit TRPS leads to the Output Modulation Block and can there deactivate the outputs (setthem to the passive state). Individual enable control bits for each of the six T12-relatedoutputs and the T13-related output facilitate a flexible adaptation to the application needs(see Section 18.7).

There are a number of different ways to exit the Trap State. This offers SW the option toselect the operation which is best for the given application. Exiting the Trap State can bedone either immediately when the trap condition is removed, or under software control,or synchronously to the PWM generated by either Timer T12 or Timer T13.

Figure 18-37 gives an overview on the trap function. Both, the Trap Flag TRPF and theTrap State Bit TRPS, located in register IS, are set to 1 when input CTRAP is activated.The Trap Flag TRPF can also be set by SW via bit STRPF. In turn, the Trap State BitTRPS will also be set through its Set/Reset Control block. As long as pin CTRAP = 0,TRPF and TRPS remain set and can not be cleared (assuming TRPPEN = 1).

Figure 18-37 Trap Logic Block Diagram

MCB05541TRPM1 TRPM0

TRPPEN

STRPF RTRPF

TRPM2

Set/ResetControl

Set/ResetControl

TrapStateTRPS

TrapFlag

TRPF

Reg. IS

Reg. IS

Set

Reset

Set

ResetTo OutputModulationT12_ZM

T13_ZM

CTRAP




The reset of TRPF is controlled by the mode control bit TRPM2 (located in the TrapControl Register TRPCTR). When TRPM2 = 0, TRPF is automatically cleared by HWwhen CTRAP returns to the inactive level (CTRAP = 1). When TRPM2 = 1, TRPF mustbe reset by SW after CTRAP has become inactive.

The reset of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located inthe Trap Control Register TRPCTR). A reset of TRPS terminates the Trap State andreturns to normal operation. There are three options selected by TRPM1 and TRPM0.One is that the Trap State is left immediately when the Trap Flag TRPF is cleared,without any synchronization to timers T12 or T13. The other two options facilitate thesynchronization of the termination of the Trap State to the count periods of either TimerT12 or Timer T13. Figure 18-38 gives an overview on the associated operation.

Figure 18-38 Trap State Synchronization (with TRM2 = 0)

MCT05542

T12 Count

T13 Count

TRPF

TRPS

TRPS

TRPS

CTRAP active

Sync. to T12

Sync. to T13

No sync.




Trap Handling Registers

Register TRPCTR controls the trap functionality. It contains independent enable bits foreach output signal and control bits to select the behavior in case of a trap condition.

CCU6_TRPCTR Trap Control Register XSFR (E8C2H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRPPEN

TRPEN13

TRPEN - - - - -TRPM2

TRPM1

TRPM0

rw rw rw - - - - - rw rw rw


TRPPEN 15 rw Trap Pin Enable Control0 The trap input pin CTRAP is disabled.

Software can generate a trap by setting bit TRPF.

1 The trap input pin CTRAP is enabled. A trap can be generated by SW by setting bit TRPF or by CTRAP = 0.

TRPEN13 14 rw Trap Enable Control for T13 OutputEnables the trap functionality for the T13 output signal CC63.0 The trap functionality is disabled. The output

state is independent from bit TRPS.1 The trap functionality is enabled. The output is

set to the passive state while TRPS = 1.

TRPEN [13:8] rw Trap Enable Control for T12 OutputsEnables the trap functionality for the individual output signals CC6x and COUT6x.0 The trap functionality is disabled. The output

state is independent from bit TRPS.1 The trap functionality is enabled. The output is

set to the passive state while TRPS = 1.TRPEN[5:0] corresponds to (left to right):COUT62, CC62, COUT61, CC61, COUT60, CC60.




TRPM2 2 rw Trap Mode Control Bit 2This bit controls whether the Trap State Exit is initiated by hardware or by software.0 Trap State Exit initiated by HW. Bit TRPF is

automatically cleared by HW if the input pin CTRAP becomes inactive (CTRAP = 1).

1 Trap State Exit initiated by SW. Bit TRPF must be reset by SW after the input CTRAP becomes inactive (CTRAP = 1).

TRPM1,TRPM0

[1:0] rw Trap Mode Control Bits 1, 0These two bits control the termination of the Trap State. When the Trap Flag TRPF is reset to 0, the Trap State Bit TRPS is reset and the Trap State is left according to the following options:00 T12 Synchronization: Reset of TRPS and Trap

State Exit on a T12 Zero-Match (T12_ZM).01 T13 Synchronization: Reset of TRPS and Trap

State Exit on a T13 Zero-Match (T13_ZM).10 Reserved, no action.11 No Synchronization: Reset of TRPS and Trap

State Exit immediately after reset of the Trap Flag TRPF.





18.7 Output Modulation Control

The last block of the data path is the Output Modulation Control Logic. Here, all themodulation sources are combined and control the actual level of the output pins.

In the following, the six T12-related outputs (CC6x, COUT6x) are discussed separatelyfrom the T13-related output CC63.

Figure 18-39 gives an overview on the six control blocks and control signals regardingthe T12-related outputs. Four individual modulation signals and their associated enablecontrols lead to each one of the blocks. The modulation signals CC6x_O andCOUT6x_O come from the State Selection logic (see Figure 18-15) at the outputs of thethree State Bits CC6xST. Signals MCMPy are the six outputs of the Multi-Channel Moderegister MCMOUT (see Figure 18-31). Signal CC63_O is the T13-generated signal fromthe State Selection logic at the output of the State Bit CC63_ST (see Figure 18-30), andleads in parallel to all 6 blocks. The trap signal TRPS also is connected to all six blocks,and is the output of the Trap State bit (see Figure 18-37).

While signals CC6x_O/COUT6x_O, CC63_O, and TRPS have individual enable controlsfor each of the six blocks, there is only one general enable signal, MCMEN, for theMCMPy signals.

The output of each of the modulation control blocks is connected to a level select block,which offers the option to determine the actual output level of a pin, depending on thestate of the output line.

Figure 18-40 provides a closer look at one of the modulation and level select blocks. Thelogic, which combines the various signals, is designed such that only signals which areenabled by their respective enable signal can influence the output line, MCL_OUT. If oneof the modulation signals CC6x_O/COUT6x_O, CC63_O, or MCMPx is enabled and isat passive state, output MCL_OUT is also in passive state, regardless of the state of theother enabled signals. Only if all enabled signals are in active state output MCL_OUTshows an active state.

If the Trap State is active (TRPS = 1), then all outputs for which the trap signal is enabled(TRPENy = 1) are set to the passive state.

The output MCL_OUT of the modulation control block is then used to select the actuallevel of the output, specified through the Passive State Select bit PSLy. WhenMCL_OUT is in the passive state, the level specified directly by PSLy is output. WhenMCL_OUT is in the active state, the inverted level of PSLy is output.

The PSLy bits have shadow registers to allow for updates without undesired pulses onthe output lines. The bits are updated with the T12 shadow transfer signal (T12_ST). Aread action returns the actually used values, whereas a write action targets the shadowbits. Providing a shadow register for the PSL value as well as for other values related tothe generation of the PWM signal facilitates a concurrent update by software for allrelevant parameters (see also Section 18.8).




Figure 18-39 Output Modulation Overview

ToOutputPins

MCA05543

T12MODEN.0MCMENT13MODEN.0TRPEN.0

LevelSelect

PSL0

MCL_OUT0CC60

T12MODEN.1

T13MODEN.1TRPEN.1

LevelSelect

PSL1

MCL_OUT1COUT60

T12MODEN.2

T13MODEN.2TRPEN.2

LevelSelect

PSL2

MCL_OUT2CC61

T12MODEN.3

T13MODEN.3TRPEN.3

LevelSelect

PSL3

MCL_OUT3COUT61

T12MODEN.4

T13MODEN.4TRPEN.4

LevelSelect

PSL4

MCL_OUT4CC62

T12MODEN.5

T13MODEN.5TRPEN.5

LevelSelect

PSL5

MCL_OUT5COUT62

ModulationControlCC60

ModulationControl

COUT60


ModulationControl

COUT61


ModulationControl

COUT62

CC60_OMCMP.0CC63_O

TRPS

COUT60_OMCMP.1

CC61_OMCMP.2

COUT61_OMCMP.3

CC62_OMCMP.4

COUT62_OMCMP.5




Figure 18-40 Output Modulation, Timer T12 Block

Figure 18-41 Output Modulation, Timer T13 Block

MCA05544

PSLyShadow

PSLy

T12_ST

Read-Only

Write-Only

1

0MUX

MCL_OUTy

ModulationControlLogicCC6x/

COUT6xCC6xCOUT6x

ToOutputPins

0: Passive State1: Active State

x = 0, 1, 2y = 0..5To Other Blocks

CC6x_OCOUT6x_O

T12MODENy

MCMEN

MCMPy

T13MODENy

CC63_O

TRPENy

TRPS

MCA05545

PSL63Shadow

PSL63

T13_ST

Read-Only

Write-Only

1

0MUX

MCL_OUT63

ModulationControlLogic

COUT63

To Output PinCOUT63

0: Passive State1: Active State

To Other Blocks

ECT13O

COUT63_O

TRPEN13

TRPS




Register PSLR defines the passive state level driven by the output pins of the module.The passive state level is the value that is driven by the port pin during the passive stateof the output. During the active state, the corresponding output pin drives the active statelevel, which is the inverted passive state level. The passive state level permits to adaptthe driven output levels to the driver polarity (inverted, not inverted) of the connectedpower stage.

CCU6_PSLR Passive State Level Register XSFR (E8C4H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- - - - - - - -PSL63

- PSL

- - - - - - - - rwh - rwh


PSL63 7 rwh T13 Output COUT63 Passive State Level ControlThis bitfield defines the passive level of the output pin COUT63.0 The passive level is 01 The passive level is 1

PSL [5:0] rwh T12 Outputs Passive State Level ControlDefines the passive level driven by the module outputs during the passive state.0 The passive level is 01 The passive level is 1PSL[5:0] corresponds to (left to right):COUT62, CC62, COUT61, CC61, COUT60, CC60.




18.8 Shadow Register Transfer Control

Figure 18-42 and Figure 18-43 give an overview on the shadow register structure andthe shadow transfer signals, as well as on the read/write accessibility of the variousregisters. Providing a shadow register for values describing one PWM period facilitatesa concurrent update by software for all relevant parameters. The next PWM period canrun with a new set of parameters.

Figure 18-42 T12 Shadow Register and Transfer Signal Overview

MCA05546

Compare RegisterCC6xR

Compare ShadowRegister CC6xSR

>1_

Other Modes(Hall, Capture, etc.)



COUT6xPS

COUT6xPSShadow

(T12)PSLy

(T12) PSLyShadow

CC6xPS

CC6xPSShadow

T12_ST

Read

ReadWrite

Write

Read

Write

Read

Read

Read

Write

Write




Figure 18-43 T13 Shadow Register and Transfer Signal Overview

MCA05547





PSL63

PSL63Shadow

T13IM

T13IMShadow

T13_ST

Read

ReadWrite

Write

Read

Write

Read Read

Write




18.9 Interrupt Generation

The interrupt structure is shown in Figure 18-44. The HW interrupt event or the SWsetting of the corresponding interrupt set bit (in register ISS) can trigger the interruptgeneration. The interrupt pulse is generated independently from the interrupt flag inregister IS. The interrupt flag can be reset by SW by writing to the corresponding bit inregister ISR.

If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can begenerated on one of the four interrupt output lines, I0 … I3, of the module. If more thanone interrupt source is connected to the same interrupt node pointer (in register INP), therequests are combined to one common line.

Figure 18-44 Interrupt Structure Overview

MCA05548

Interrupt Control Logic

CC60 Cap./Com. RisingCC60 Cap./Com. FallingCC61 Cap./Com. RisingCC61 Cap./Com. FallingCC62 Cap./Com. RisingCC62 Cap./Com. Falling

T12 One-MatchT12 Period-Match

T13 Compare-MatchT13 Period-MatchCorrect Hall Event

MCM Shadow TransferTrap Condition

Wrong Hall Event

14 Node PointerRegister INP

I0

I1

I2

I3

CC6_INT

CC6_EINT

CC6_T12INT

CC6_T13INT

Interrupt SetRegister ISS

Interrupt ResetRegister ISR

Interrupt EnableRegister IEN

Interrupt StatusRegister IS

16 16

1616




Figure 18-45 Interrupt Structure Detail

Interrupt Registers

Register IS contains the individual interrupt request and status bits. This register canonly be read, write actions have no impact on the contents of this register. Software canset or reset the bits individually by writing to register ISS (to set the bits) or to registerISR (to reset the bits).

CCU6_IS Interrupt Status Register XSFR (E8D0H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- IDLE WHE CHETRP

STRP

FT13PM

T13CM

T12PM

T12OM

ICC62F

ICC62R

ICC61F

ICC61R

ICC60F

ICC60R

- rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh


IDLE 14 rh IDLE State FlagIf enabled (ENIDLE = 1), this bit is set together with bit WHE (Wrong Hall Event). It has to be reset by SW.0 No action1 Bitfield MCMP is cleared, the selected outputs

are set to passive state

MCA05549

>1_

>1_SW Request SetHW InterruptEvent a

Int.FlagSW Request Reset

Set

>1_HW InterruptEvent bSW Request Set

Int.FlagSW Request Reset

Set

From OtherInterrupt Sources

INPx

>1_

>1_

>1_

>1_

6

6

6

6

I0

I1

I2

I3

&

&

InterruptEnable

InterruptEnable




WHE 13 rh Wrong Hall Event Flag0 No wrong hall pattern yet1 A transition to a wrong hall pattern (not the

expected one) has occurred

CHE 12 rh Correct Hall Event Flag0 No correct (= expected) hall pattern yet1 A transition to an expected hall pattern has

occurred

TRPS1) 11 rh Trap State Bit0 The Trap State is not active1 The Trap State is active. Bit TRPS is set while

bit TRPF = 1. It is reset according to the mode selected in register TRPCTR.

TRPF 10 rh Trap FlagThe trap flag TRPF is set either by HW, if TRPPEN = 1 and CTRAP = 0, or by SW. If TRPM2 = 0, bit TRPF is reset by HW if the input CTRAP becomes inactive (TRPPEN = 1). If TRPM2 = 1, bit TRPF has to be reset by SW in order to leave the trap state.0 The trap condition has not occurred1 The trap condition has occurred (CTRAP = 0

or by SW)

T13PM 9 rh Timer T13 Period-Match Flag0 No T13 Period-Match yet1 A T13 Period-Match has occurred

T13CM 8 rh Timer T13 Compare-Match Flag0 No T13 Compare-Match yet1 A T13 Compare-Match has occurred

T12PM 7 rh Timer T12 Period-Match Flag0 No T12 Period-Match yet1 A T12 Period-Match has occurred while

counting up

T12OM 6 rh Timer T12 One-Match Flag0 No T12 One-Match yet1 A T12 One-Match has been detected while

counting down





Note: Not all bits in register IS can generate an interrupt. Other status bits have beenadded, which have a similar structure for their set and reset actions.

Note: In compare mode (and hall mode), the timer-related interrupts are only generatedwhile the timer is running (TxR = 1). In capture mode, the capture interrupts arealso generated while the Timer T12 is stopped.

ICC62FICC61FICC60F

531

rh Capture, Compare-Match Falling Edge FlagIn compare mode, a Compare-Match has been detected while T12 was counting down. In capture mode, a falling edge has been detected at the input CC6x (x = 0, 1, 2).0 The event has not yet occurred1 The event described above has occurred

ICC62RICC61RICC60R

420

rh Capture, Compare-Match Rising Edge FlagIn compare mode, a compare-match has been detected while T12 was counting up. In capture mode, a rising edge has been detected at the input CC6x (x = 0, 1, 2).0 The event has not yet occurred1 The event described above has occurred

1) During the trap state, the selected outputs are set to the passive state.





Registers ISS and ISR contain write-only bits corresponding to the interrupt and statusflags in register IS (except for bit 11). By writing 1s to these bits, software can set (ISS)or clear (ISR) the associated flag(s). Reading these bits always returns 0s.

Setting a bit in register ISS will set the corresponding flag in register IS and may triggeran interrupt request (if enabled and if available for that function).

Setting a bit in register ISR will clear the corresponding flag in register IS.

CCU6_ISS Interrupt Status Set Register XSFR (E8D2H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-S

IDLES

WHES

CHE-

STRP

F

ST13PM

ST13CM

ST12PM

ST12OM

SCC62F

SCC62R

SCC61F

SCC61R

SCC60F

SCC60R

- w w w - w w w w w w w w w w w

Field Bits Type Description1)

1) Writing 1 to one of these bits will set the associated flag. Writing 0 has no effect.

SIDLE 14 w Set IDLE Flag

SWHE 13 w Set Wrong Hall Event Flag

SCHE 12 w Set Correct Hall Event Flag

STRPF 10 w Set Trap Flag

ST13PM 9 w Set Timer T13 Period-Match Flag

ST13CM 8 w Set Timer T13 Compare-Match Flag

ST12PM 7 w Set Timer T12 Period-Match Flag

ST12OM 6 w Set Timer T12 One-Match Flag

SCC62FSCC61FSCC60F

531

w Set Capture, Compare-Match Falling Edge Flag

SCC62RSCC61RSCC60R

420

w Set Capture, Compare-Match Rising Edge Flag




Note: The set/clear bits in registers ISS and ISR can be written (set) via bit-operations(e.g. BSET), logical operations (e.g. OR), or single MOV-operations (e.g.executed via PEC).

CCU6_ISR Interrupt Status Reset Reg. XSFR (E8D4H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-R

IDLER

WHER

CHE-

RTRP

F

RT13PM

RT13CM

RT12PM

RT12OM

RCC62F

RCC62R

RCC61F

RCC61R

RCC60F

RCC60R

- w w w - w w w w w w w w w w w

Field Bits Type Description1)

RIDLE 14 w Reset IDLE Flag

RWHE 13 w Reset Wrong Hall Event Flag

RCHE 12 w Reset Correct Hall Event Flag

RTRPF 10 w Reset Trap Flag

RT13PM 9 w Reset Timer T13 Period-Match Flag

RT13CM 8 w Reset Timer T13 Compare-Match Flag

RT12PM 7 w Reset Timer T12 Period-Match Flag

RT12OM 6 w Reset Timer T12 One-Match Flag

RCC62FRCC61FRCC60F

531

w Reset Capture, Compare-Match Falling Edge Flag

RCC62RRCC61RRCC60R

420

w Reset Capture, Compare-Match Rising Edge Flag

1) Writing 1 to one of these bits will clear the associated flag. Writing 0 has no effect.




Register IEN contains the interrupt enable bits and a control bit to enable the automaticidle function in the case of a wrong hall pattern. Setting a bit in this register will enablethe interrupt request (or defined function for a bit). Clearing a bit disables the interruptrequest (or defined other function).

CCU6_IEN Interrupt Enable Register XSFR (E8D8H/--) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-EN

IDLEEN

WHEEN

CHE-

ENTRP

F

ENT13PM

ENT13CM

ENT12PM

ENT12OM

ENCC62F

ENCC62R

ENCC61F

ENCC61R

ENCC60F

ENCC60R

- rw rw rw - rw rw rw rw rw rw rw rw rw rw rw


ENIDLE 14 rw Enable Idle Flag Set Function

ENWHE 13 rw Enable Wrong Hall Event Interrupt

ENCHE 12 rw Enable Correct Hall Event Interrupt

ENTRPF 10 rw Enable Trap Flag Interrupt

ENT13PM 9 rw Enable T13 Period-Match Interrupt

ENT13CM 8 rw Enable T13 Compare-Match Interrupt

ENT12PM 7 rw Enable T12 Period-Match Interrupt

ENT12OM 6 rw Enable T12 One-Match Interrupt

ENCC62FENCC61FENCC60F

531

rw Enable Capture, Compare-Match Interruptupon Falling Edge

ENCC62RENCC61RENCC60R

420

rw Enable Capture, Compare-Match Interruptupon Rising Edge




The interrupt sources of the CAPCOM6 module can be mapped to four interrupt nodesby programming the interrupt node pointer register CC6_INP. The encoding valid for allbitfields is shown in Table 18-10.

The default assignment of the interrupt sources to the nodes and their correspondingcontrol registers are listed in Table 18-11.

CCU6_INP Interrupt Node Pointer Reg. XSFR (E8D6H/--) Reset Value: 3940H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- -INPT13

INPT12

INPERR

INPCHE

INPCC62

INPCC61

INPCC60

- - rw rw rw rw rw rw rw


INPT13 [13:12] rw Interrupt Node Pointer for Timer13 InterruptThis bitfield selects the interrupt request line for source T13CM and/or source T13PM.

INPT12 [11:10] rw Interrupt Node Pointer for Timer12 InterruptsThis bitfield selects the interrupt request line for source T12OM and/or source T12PM.

INPERR [9:8] rw Interrupt Node Pointer for Error InterruptsThis bitfield selects the interrupt request line for source TRPF and/or source WHE.

INPCHE [7:6] rw Interrupt Node Pointer for the CHE InterruptThis bitfield selects the interrupt request line for source CHE and/or source STR.

INPCC62INPCC61INPCC60

[5:4][3:2][1:0]

rw Interrupt Node Pointer for Channel x InterruptsThis bitfield selects the interrupt request line for source CC6xR and/or source CC6xF.

Table 18-10 Encoding of Interrupt Node Pointer Bitfields

Bitfield INPxx Interrupt Output Line to be Activated

00B I0

01B I1

10B I2

11B I3




All interrupt control registers have the same structure. The basic register layout is shownbelow, Table 18-11 lists the associated addresses.


CCU6_xIC CAPCOM6 Intr. Ctrl. Reg. ESFR (Table 18-11) Reset Value: - - 00H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- GPXCCyIR

CCyIE

ILVL GLVL

- - - - - - - rw rwh rw rw rw

Table 18-11 CAPCOM6 Default Interrupt Node Register Assignment

Source of Interrupt Interrupt Request Nr.

Interrupt Control Register

Register Address

Channel 0 Interrupts I0 CCU6_IC F140H

Channel 1 Interrupts I0

Channel 2 Interrupts I0

Correct Hall Pattern Interrupt

I1 CCU6_EIC F188H

Emergency Interrupts I1

Timer T12 Interrupts I2 CCU6_T12IC F190H

Timer T13 Interrupts I3 CCU6_T13IC F198H




18.10 Suspend Mode

In suspend mode, the functional clock fCC6 of the module kernel is stopped. The registerscan still be accessed by the CPU (read only). This mode is useful for debuggingpurposes, e.g. where the current device status should be ‘frozen’ in order to get asnapshot of the internal values. In suspend mode, the timers T12 and T13 are notrunning. The suspend mode is non-intrusive concerning the register bits. This means,register bits are not changed by hardware when entering or leaving the suspend mode.Software actions are also not required. In suspend mode, all registers can be accessedby read instructions for debugging purposes.

The suspend mode can be entered when the suspend mode is requested, the suspendmode is enabled and the module has reached a safe, deterministic state (like the timerstop conditions in single shot mode). This behavior avoids critical situations if a powerinverter is connected to the module’s outputs.

The suspend state has no direct influence on the output signals.




18.11 Interfaces of the CAPCOM6 Unit

The CAPCOM6 units is connected to its environment in different ways.


The 4 interrupt request lines of the CAPCOM6 unit are connected to the interrupt controlblock.

The period match signal of timer T13 (T13_PM) is connected to the ADC, as a possibletrigger source for injected conversions.


The signals of the CAPCOM6 unit are connected with input/output ports of the XC164.These ports may provide capture trigger signals from the external system, issuecompare output signals to external circuitry, or accept control input signals.


MCA05550

SystemControl

Unit (SCU)

fCC6

CC6DIS

CAPCOM6Module

P1L.0

P1L.1

P1L.2

P1L.3

P1L.4

P1L.5

P1L.6

P1L.7

P1H.0

P1H.1

P1H.2

CC60

COUT60

CC61

CCOUT61

CC62

CCOUT62

CCOUT63

CTRAP

CC6POS0

CC6POS1

CC6POS2

CCU6T12IRQInterruptControl

CCU6IRQ

CCU6EIRQ

CCU6T13IRQ

CCU6T13PMADC

I0

I1

I2

I3



Asynchronous/Synchronous Serial Interface (ASC)

19 Asynchronous/Synchronous Serial Interface (ASC) The XC164 contains two Asynchronous/Synchronous Serial Interfaces, ASC0 andASC1. The following sections present the general features and operations of such anASC module. The final section describes the actual implementation of the two ASCmodules including their interconnections with other on-chip modules.

The ASC supports full-duplex asynchronous communication and half-duplexsynchronous communication. The ASC provides the following features and functions.

Features and Functions

• Full-duplex asynchronous operating modes– 8- or 9-bit data frames, LSB first– Parity bit generation/checking– One or two stop bits– Baudrate from 2.5 Mbit/s to 50 bit/s (@ 40 MHz module clock fASC)

• Multiprocessor Mode for automatic address/data byte detection• Loopback capability• Support for IrDA data transmission up to 115.2 kbit/s maximum• Half-duplex 8-bit synchronous operating mode

– Baudrate from 5 Mbit/s to 202 bit/s (@ 40 MHz module clock fASC)• Double buffered transmitter/receiver• Interrupt generation

– On a transmitter buffer empty condition– On a transmit last bit of a frame condition– On a receiver buffer full condition– On an error condition (frame, parity, overrun error)

• Autobaud detection unit for asynchronous operating modes– Detection of standard baudrates

1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, and 230400 bit/s– Detection of non-standard baudrates– Detection of Asynchronous Modes– 7 bit, even parity; 7 bit, odd parity; 8 bit, even parity; 8 bit, odd parity; 8 bit, no parity– Automatic initialization of control bits and baudrate generator after detection– Detection of a serial two-byte ASCII character frame

• FIFO– 8-stage receive FIFO (RXFIFO), 8-stage transmit FIFO (TXFIFO)– Independent control of RXFIFO and TXFIFO– 9-bit FIFO data width– Programmable Receive/Transmit Interrupt Trigger Level– Receive and transmit FIFO filling level indication – Overrun and Underflow error generation

Figure 19-1 shows all functional relevant interfaces associated with the ASC Kernel.

User’s Manual 19-1 V2.1, 2004-03ASC_X, V2.0



Figure 19-1 ASC Interface Diagram

ASCModule(Kernel)

ModuleBus Interface

MCA05432

PortControl

Product Interface

ClockControl

AddressDecoder

InterruptControl

TIR

ASCxDIS

ABDETIR

TBIR

RIR

EIR

ABSTIR

fASC

TxD

RxD




19.1 Operational Overview

Figure 19-2 shows a block diagram of the ASC with its operating modes (Asynchronousand Synchronous Mode).

Figure 19-2 Block Diagram of the ASC

The ASC supports full-duplex asynchronous communication with up to 2.5 Mbit/s andhalf-duplex synchronous communication with up to 5 Mbit/s (@ 40 MHz module clock).In Synchronous Mode, data are transmitted or received synchronous to a shift clock thatis generated by the microcontroller. In Asynchronous Mode, either 8- or 9-bit datatransfer, parity generation, and the number of stop bits can be selected. Parity, framing,and overrun error detection is provided to increase the reliability of data transfers.Transmission and reception of data is double-buffered. For multiprocessorcommunication, a mechanism is provided to distinguish address bytes from data bytes.

Receive / TransmitBuffers and

Shift Registers

MCB05433

MUX

Serial PortControl

BaudrateTimer

fDIVPrescaler /Fractional

Divider

AutobaudDetection

IrDADecoding

fASC

RxD

IrDADecoding

MUXTxD

Asynchronous Mode


Shift Registers

Serial PortControl

BaudrateTimer

fASC

TxDRxD

RxD

Shift Clock

2or 3

Synchronous Mode




Testing is supported by a loop-back option. A 13-bit baudrate timer with a versatile inputclock divider circuitry provides the serial clock signal. In a Special Asynchronous Mode,the ASC supports IrDA data transmission up to 115.2 kbit/s with fixed or programmableIrDA pulse width. Autobaud Detection allows to detect asynchronous data frames withits baudrate and mode with automatic initialization of the baudrate generator and themode control bits.

A transmission is started by writing to the transmit buffer register TBUF. The selectedoperating mode determines the number of data bits that will actually be transmitted, sothat, bits written to positions 9 through 15 of register TBUF are always insignificant. Datatransmission is double-buffered, so a new character may be written to the transmit bufferregister before the transmission of the previous character is complete. This allows thetransmission of characters back-to-back without gaps.

Data reception is enabled by the Receiver Enable Bit REN. After reception of a characterhas been completed, the received data can be read from the (read-only) receive bufferregister RBUF; the received parity bit can also be read if provided by the selectedoperating mode. Bits in the upper half of RBUF that are not valid in the selected operatingmode will be read as zeros.Data reception is double-buffered, so that reception of a second character may alreadybegin before the previously received character has been read out of the receive bufferregister. In all modes, receive overrun error detection can be selected through bit OEN.When enabled, the overrun error status flag OE and the error interrupt request line EIRwill be activated when the receive buffer register has not been read by the time receptionof a ninth character is complete. The previously received character in the receive bufferis overwritten.

The Loopback Mode (selected by bit LB) allows the data currently being transmitted tobe received simultaneously in the receive buffer. This may be used to test serialcommunication routines at an early stage without having to provide an external network.

Note: In Loopback Mode, the alternate input/output functions of the associated port pinsare not necessary.

Note: Serial data transmission or reception is only possible when the BaudrateGenerator Run bit R is set. Otherwise, the serial interface is idle.

Note: Do not program the Mode Control bitfield M to one of the reserved combinationsto avoid unpredictable behavior of the serial interface.

The operating mode of the serial channel ASC is controlled by its control registerASCx_CON. This register contains control bits for mode and error check selection, andstatus flags for error identification.




19.2 Asynchronous Operation

Asynchronous Mode supports full-duplex communication in which both transmitter andreceiver use the same data frame format and the same baudrate. Data is transmitted online TxD and received on line RxD. IrDA data transmission/reception is supported up to115.2 kbit/s. Figure 19-3 shows the block diagram of the ASC when operating inAsynchronous Mode.

Figure 19-3 Asynchronous Mode of Serial Channel ASC

Serial Port Control

MCA05434

13-bit Reload Register

13-bit Baudrate Timer 16

fBRT

fBRfDIV

CON.FDE

MUX

CON.BRS

FractionalDivider

2

3CON.R

fASC

Autobaud Detection

AutobaudStart Int.AutobaudDetect Int.

ABSTIR

ABDETIR

CON.RENCON.FENCON.PENCON.OENCON.LB

Shift ClockFIFO

Control

Shift Clock

CON.OE

TIR

TBIR

EIR

Receive Int.Request

Transmit BufferInt. Request

CON.PECON.FE

CON.STPCON.M

CON.ODD

RIR

Transmit Int.Request

Error Int.Request

Receive Buffer Reg.RBUF

Transmit Buffer Reg.TBUF

Receive ShiftRegister

Transmit ShiftRegister

IrDACoding

MU

X

SamplingMUX

MU

X

IrDADecoding

Internal Bus

MUX 1 TxD1RxD




19.2.1 Asynchronous Data Frames

8-Bit Data Frames

8-bit data frames consist of either eight data bits D7 … D0 (M = 001B), or seven data bitsD6 … D0 plus an automatically generated parity bit (M = 011B). Parity may be odd oreven, depending on bit ODD. An even parity bit will be set if the modulo-2-sum of the7 data bits is 1. An odd parity bit will be cleared in this case. Parity checking is enabledvia bit PEN (always OFF in 8-bit data mode). The parity error flag PE will be set, alongwith the error interrupt request flag, if a wrong parity bit is received. The parity bit itselfwill be stored in bit RBUF.7.

Figure 19-4 Asynchronous 8-Bit Frames

MCT05435

D0LSB

StartBit0

(2nd)StopBit

(1st)StopBit

D1 D2 D3 D4 D5 D6 D7MSB

8 Data Bits

10-/11-bit UART Frame

1 1

M = 001B

D0LSB

StartBit0

D1 D2 D3 D4 D5 D6MSB

ParityBit

7 Data Bits


1 1

M = 011B

(2nd)StopBit

(1st)StopBit




9-Bit Data Frames

9-bit data frames consist of either nine data bits D8 … D0 (M = 100B), eight data bitsD7 … D0 plus an automatically generated parity bit (M = 111B), or eight data bitsD7 … D0 plus wake-up bit (M = 101B). Parity may be odd or even, depending on bitODD. An even parity bit will be set if the modulo-2-sum of the 8 data bits is 1. An oddparity bit will be cleared in this case. Parity checking is enabled via bit PEN (always OFFin 9-bit data and wake-up mode). The parity error flag PE will be set, along with the errorinterrupt request flag, if a wrong parity bit is received. The parity bit itself will be storedin bit RBUF.8.

Figure 19-5 Asynchronous 9-Bit Frames

In wake-up mode, received frames are transferred to the receive buffer register only ifthe 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request will beactivated and no data will be transferred.

This feature may be used to control communication in a multi-processor system:When the master processor wants to transmit a block of data to one of several slaves, itfirst sends out an address byte to identify the target slave. An address byte differs froma data byte in that the additional 9th bit is a 1 for an address byte, but is a 0 for a databyte; so, no slave will be interrupted by a data ‘byte’. An address ‘byte’ will interrupt allslaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eightLSBs of the received character (the address). The addressed slave will switch to 9-bitdata mode (such as by clearing bit M[0]), to enable it to also receive the data bytes thatwill be coming (having the wake-up bit cleared). The slaves not being addressed remainin 8-bit data + wake-up bit mode, ignoring the following data bytes.

MCT05436

D0LSB

StartBit0

(2nd)StopBit

(1st)StopBit

D1 D2 D3 D4 D5 D7 Bit 9

9 Data Bits


1 1

D6

CON.M = 100B : Bit 9 = Data Bit D8CON.M = 101B : Bit 9 = Wake-up BitCON.M = 111B : Bit 9 = Parity Bit




IrDA Frames

The modulation schemes of IrDA are based on standard asynchronous datatransmission frames. The asynchronous data format in IrDA Mode (M = 010B) is definedas follows:

1 start bit/8 data bits/1 stop bit

The coding/decoding of/to the asynchronous data frames is shown in Figure 19-6. Ingeneral, during IrDA transmissions, UART frames are encoded into IR frames and viceversa. A low level on the IR frame indicates an “LED off” state. A high level on the IRframe indicates an “LED on” state.

For a 0-bit in the UART frame, a high pulse is generated. For a 1-bit in the UART frame,no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixedwidth of 3/16 of the bit time. The ASC also allows the length of the IrDA high pulse to beprogrammed. Further, the polarity of the received IrDA pulse can be inverted in IrDAMode. Figure 19-6 shows the non-inverted IrDA pulse scheme.

Figure 19-6 IrDA Frame Encoding/Decoding

The ASC IrDA pulse mode/width register PMW contains the 8-bit IrDA pulse width valueand the IrDA pulse width mode select bit. This register is required in the IrDA operatingmode only.

MCT05437

0 1 0 1 0 0 1 1 0 1

0 1 0 1 0 0 1 1 0 1

StartBit

StopBit

8 Data Bits

UART Frame

StartBit

StopBit

8 Data Bits

IR Frame

Pulse Width =3/16-bit Time(or variable length)

Bit Time 1/2-bit Time




19.2.2 Asynchronous Transmission

Asynchronous transmission begins at the next overflow of the divide-by-16 baudratetimer (transition of the baudrate clock fBR), if bit R is set and data has been loaded intoTBUF. The transmitted data frame consists of three basic elements:

• Start bit• Data field (eight or nine bits, LSB first, including a parity bit, if selected)• Delimiter (one or two stop bits)

Data transmission is double-buffered. When the transmitter is idle, the transmit dataloaded in the transmit buffer register is immediately moved to the transmit shift register,thus freeing the transmit buffer for the next data to be sent. This is indicated by thetransmit buffer interrupt request line TBIR being activated. TBUF may now be loadedwith the next data, while transmission of the previous data continues.

The transmit interrupt request line TIR will be activated before the last bit of a frame istransmitted, that is, before the first or the second stop bit is shifted out of the transmitshift register.

Note: The transmitter output pin TxD must be configured for alternate data output.

19.2.3 Transmit FIFO Operation

The transmit FIFO (TXFIFO) provides the following functionality:

• Enable/disable control• Programmable filling level for transmit interrupt generation• Filling level indication• FIFO clear (flush) operation• FIFO overflow error generation

The 8-stage transmit FIFO is controlled by the TXFCON control register. When bitTXFEN is set, the transmit FIFO is enabled. The interrupt trigger level defined by TXFITLdefines the filling level of the TXFIFO at which a transmit buffer interrupt TBIR or atransmit interrupt TIR is generated. These interrupts are always generated when thefilling level of the transmit FIFO is equal to or less than the value stored in TXFITL.

Bitfield TXFFL in the FIFO status register ASCx_FSTAT indicates the number of entriesthat are actually written (valid) in the TXFIFO. Therefore, the software can verify, in theinterrupt service routine, for instance, how many bytes can still be written into thetransmit FIFO via register TBUF without getting an overrun error.

The transmit FIFO cannot be accessed directly. All data write operations into the TXFIFOare executed by writing into the TBUF register.




Figure 19-7 Transmit FIFO Operation Example

The example in Figure 19-7 shows a typical 8-stage transmit FIFO operation. In thisexample seven bytes are transmitted via the TxD output line. The transmit FIFO interrupttrigger level TXFITL is set to 0011B. The first byte written into the empty TXFIFO viaTBUF is directly transferred into the transmit shift register and is not written into the FIFO.A transmit buffer interrupt will be generated in this case. After byte 1, bytes 2 to 6 arewritten into the transmit FIFO.

After the transfer of byte 3 from the TXFIFO into the transmit shift register of the ASC,3 bytes remain in the TXFIFO. Therefore, the value of TXFITL is reached and a transmitbuffer interrupt will be generated at the beginning and a transmit interrupt at the end ofthe byte 3 serial transmission. During the serial transmission of byte 4, another byte(byte 7) is written into the TXFIFO (TBUF write operation). Finally, after the start of theserial transmission of byte 7, the TXFIFO is again empty.

MCT05438

Byte 6Byte 5Byte 4Byte 3

0101

Byte 2

TBIR

0100

Byte 3

TIRTBIR

0011

TIRTBIR

0010

Byte 5

TIRTBIR

0010

Byte 7Byte 6

TIRTIRTBIR

0001 00000000

TxD

FSTAT.TXFFL

Byte 6Byte 5Byte 4

Byte 6Byte 5

Byte 6Byte 5

Byte 7Byte 6Byte 7

Byte 7

TXFIFOEmpty

Byte 6Byte 5Byte 4Byte 3Byte 2

Byte 5Byte 4Byte 3Byte 2

Byte 4Byte 3Byte 2

Byte 3Byte 2Byte 2

Writing Byte 1Writing Byte 2Writing Byte 3Writing Byte 4Writing Byte 5Writing Byte 6

Writing Byte 7

TXFCON.TXFITL = 0011B

Byte 1 Byte 4

TBIR




If the TXFIFO is full and additional bytes are written into TBUF, the error interrupt will begenerated with bit OE set. In this case, the data byte that was last written into the transmitFIFO is overwritten and the transmit FIFO filling level TXFFL is set to maximum.

The TXFIFO can be flushed or cleared by setting bit TXFFLU in registerASCx_TXFCON. After this TXFIFO flush operation, the TXFIFO is empty and thetransmit FIFO filling level TXFFL is set to 0000B. A running serial transmission is notaborted by a receive FIFO flush operation

Note: The TXFIFO is flushed automatically with a reset operation of the ASC moduleand if the TXFIFO becomes disabled (resetting bit TXFEN) after it was previouslyenabled.




19.2.4 Asynchronous Reception

Asynchronous reception is initiated by a falling edge (1-to-0 transition) on line RxD,provided that bits R and REN are set. The receive data input line RxD is sampled at16 times the rate of the selected baudrate. A majority decision of the 7th, 8th, and 9th

sample determines the effective bit value. This avoids erroneous results that may becaused by noise.

If the detected value is not a 0 when the start bit is sampled, the receive circuit is resetand waits for the next 1-to-0 transition at line RxD. If the start bit proves valid, the receivecircuit continues sampling and shifts the incoming data frame into the receive shiftregister.

When the last stop bit has been received, the content of the receive shift register aretransferred to the receive data buffer register RBUF. Simultaneously, the receiveinterrupt request line RIR is activated after the 9th sample in the last stop bit time slot (asprogrammed), regardless of whether valid stop bits have been received or not. Thereceive circuit then waits for the next start bit (1-to-0 transition) at the receive data inputline.

Note: The receiver input pin RxD must be configured for input.

Asynchronous reception is stopped by clearing bit REN. A currently received frame iscompleted including the generation of the receive interrupt request and an error interruptrequest, if appropriate. Start bits that follow this frame will not be recognized.

Note: In wake-up mode, received frames are transferred to the receive buffer registeronly if the 9th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt requestwill be activated and no data will be transferred.

19.2.5 Receive FIFO Operation

The receive FIFO (RXFIFO) provides the following functionality:

• Enable/disable control• Programmable filling level for receive interrupt generation• Filling level indication• FIFO clear (flush) operation• FIFO overflow error generation

The 8-stage receive FIFO is controlled by the RXFCON control register. When bitRXFEN is set, the receive FIFO is enabled. The interrupt trigger level defined by RXFITLdefines the filling level of RXFIFO at which a receive interrupt RIR is generated. RIR isalways generated when the filling level of the receive FIFO is equal to or greater than thevalue stored in RXFITL.

Bitfield RXFFL in the FIFO status register ASCx_FSTAT indicates the number of bytesthat have been actually written into the FIFO and can be read out of the FIFO by a userprogram.




The receive FIFO cannot be accessed directly. All data read operations from theRXFIFO are executed by reading the RBUF register.

Figure 19-8 Receive FIFO Operation Example

The example in Figure 19-8 shows a typical 8-stage receive FIFO operation. In thisexample, six bytes are received via the RxD input line. The receive FIFO interrupt triggerlevel RXFITL is set to 0011B. Therefore, the first receive interrupt RIR is generated afterthe reception of byte 3 (RXFIFO is filled with three bytes).

After the reception of byte 4, three bytes are read out of the receive FIFO. After this readoperation, the RXFIFO still contains one byte. RIR becomes again active after two morebytes (byte 5 and 6) have been received (RXFIFO filled again with 3 bytes). Finally, theFIFO is cleared after three read operation.

If the RXFIFO is full and additional bytes are received, the receive interrupt RIR and theerror interrupt EIR will be generated with bit OE set. In this case, the data byte last writteninto the receive FIFO is overwritten. With the overrun condition, the receive FIFO fillinglevel RXFFL is set to maximum. If a RBUF read operation is executed with the RXFIFO

MCT05439

Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

0000 0001 0010 0011 0100 0001 0010 0100 0000

Byte 1 Byte 1Byte 2

Byte 1Byte 2Byte 3

Byte 1Byte 2Byte 3Byte 4 Byte 4 Byte 4

Byte 5Byte 6

RXFIFOEmpty

RIRRIRRIR

Read RBUF (Byte 1)Read RBUF (Byte 2)Read RBUF (Byte 3)Read RBUF (Byte 4)Read RBUF (Byte 5)Read RBUF (Byte 6)

RxD

Content ofFSTAT.RXFFL

RXFCON.RXFITL = 0011B

Byte 4Byte 5




enabled but empty, an error interrupt EIR will be generated as well with bit OE set. In thiscase, the receive FIFO filling level RXFFL is set to 0000B.

If the RXFIFO is available but disabled (RXFEN = 0) and the receive operation is enabled(REN = 1), the asynchronous receive operation is functionally equivalent to theasynchronous receive operation of the ASC module.

The RXFIFO can be flushed or cleared by setting bit RXFFLU in register RXFCON. Afterthis RXFIFO flush operation, the RXFIFO is empty and the receive FIFO filling levelRXFFL is set to 0000B.

The RXFIFO is flushed automatically with a reset operation of the ASC module and if theRXFIFO becomes disabled (resetting bit RXFEN) after it was previously enabled.Resetting bit REN without resetting RXFEN does not affect (reset) the RXFIFO state.This means that the receive operation of the ASC is stopped, in this case, withoutchanging the content of the RXFIFO. After setting REN again, the RXFIFO with itscontent is again available.

Note: After a successful autobaud detection sequence (if implemented), the RXFIFOshould be flushed before data is received.




19.2.6 FIFO Transparent Mode

In Transparent Mode, a specific interrupt generation mechanism is used for receive andtransmit buffer interrupts. In general, in Transparent Mode, receive interrupts are alwaysgenerated if data bytes are available in the RXFIFO. Transmit buffer interrupts arealways generated if the TXFIFO is not full. The relevant conditions for interruptgeneration in Transparent Mode are:

• FIFO filling levels• Read/write operations on the RBUF/TBUF data register

Interrupt generation for the receive FIFO depends on the RXFIFO filling level and theexecution of read operations of register RBUF (see Figure 19-9). Transparent Mode forthe RXFIFO is enabled when bits RXTMEN and RXFEN in register ASCx_RXFCON areset.

Figure 19-9 Transparent Mode Receive FIFO Operation

If the RXFIFO is empty, a receive interrupt RIR is always generated when the first byteis written into an empty RXFIFO (RXFFL changes from 0000B to 0001B). If the RXFIFOis filled with at least one byte, the occurrence of further receive interrupts depends on theread operations of register RBUF. The receive interrupt RIR will always be activated aftera RBUF read operation if the RXFIFO still contains data (RXFFL is not equal to 0000B).If the RXFIFO is empty after a RBUF read operation, no further receive interrupt will begenerated.

If the RXFIFO is full (RXFFL = maximum) and additional bytes are received, an errorinterrupt EIR will be generated with bit OE set. In this case, the data byte last written intothe receive FIFO is overwritten. If a RBUF read operation is executed with the RXFIFOenabled but empty (underflow condition), an error interrupt EIR will be generated as well,with bit OE set.

If the RXFIFO is flushed in Transparent Mode, the software must take care that aprevious pending receive interrupt is ignored.

MCT05440

Byte 1 Byte 2 Byte 3 Byte 4

0000 0001 0010 0011 0100

RxD

RIR (1)

Content ofRXFCON.RXFFL

0011 0010 0001 0001

ReadRBUF

RIR (2) RIR (3) RIR (4)

ReadByte 1

ReadByte 2

ReadByte 3

ReadByte 4




Note: The Receive FIFO Interrupt Trigger Level bitfield RXFITL is a don’t care inTransparent Mode.

Interrupt generation for the transmit FIFO depends on the TXFIFO filling level and theexecution of write operations to the register TBUF. Transparent Mode for the TXFIFO isenabled when bits TXTMEN and TXFEN are set.

A transmit buffer interrupt TBIR is always generated when the TXFIFO is not full (TXFFLnot equal to maximum) after a byte has been written into register ASCx_TBUF. TBIR isalso activated after a TXFIFO flush operation or when the TXFIFO becomes enabled(TXTMEN and TXFEN set) when it was previously disabled. In these cases, the TXFIFOis empty and ready to be filled with data.

If the TXFIFO is full (TXFFL = maximum) and an additional byte is written into TBUF, nofurther transmit buffer interrupt will be generated after the TBUF write operation. In thiscase the data byte last written into the transmit FIFO is overwritten and an overrun errorinterrupt (EIR) will be generated with bit OE set.

Note: The Transmit FIFO Interrupt Trigger Level bitfield TXFITL is a don’t care inTransparent Mode.

19.2.7 IrDA Mode

The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard alsoallows the pulse duration to be independent of the baudrate or bit period. In this case,the width of the transmitted pulse always corresponds to the 3/16 pulse width at115.2 kbit/s, which is 1.627 µs. Either fixed or bit-period-dependent IrDA pulse widthgeneration can be selected. The IrDA pulse width mode is selected by bit IRPW.

In case of fixed IrDA pulse width generation, the lower eight bits in register PMW areused to adapt the IrDA pulse width to a fixed value such as 1.627 µs. The fixed IrDApulse width is generated by a programmable timer as shown in Figure 19-10.

Figure 19-10 Fixed IrDA Pulse Generation

The IrDA pulse width can be calculated according the formulas given in Table 19-1.

Note: The name PMW in the formulas of Table 19-1 represents the contents of the pulsemode/width register PMW (PW_VALUE), taken as an unsigned 8-bit integer.

MCA05441

PWM

8-bit TimerfASC IrDA Pulse

StartTimer

tIPW




The contents of PW_VALUE further define the minimum IrDA pulse width (tIPW min) thatis still recognized as a valid IrDA pulse during a receive operation. This function isindependent of the selected IrDA pulse width mode (fixed or variable) which is definedby bit IRPW. The minimum IrDA pulse width is calculated by a shift right operation ofPMW bit 7-0 by one bit divided by the module clock fASC.

Note: If IRPW is cleared (fixed IrDA pulse width), PW_VALUE must be a value whichassures that tIPW > tIPW min.

Table 19-2 gives examples for typical frequencies of fASC.

19.2.8 RxD/TxD Data Path Selection in Asynchronous Modes

The data paths for the serial input and output data in Asynchronous Mode are affectedby several control bits in the registers CON and ABCON as shown in Figure 19-11. TheSynchronous Mode operation is not affected by these data path selection capabilities.

The input signal from RxD passes an inverter which is controlled by bit RXINV. Theoutput signal of this inverter is used for the Autobaud Detection and may bypass the logicin the Echo Mode (controlled by bit ABEM). Further, two multiplexers are in the RxD inputsignal path for providing the Loopback Mode capability (controlled by bit LB) and theIrDA receive pulse inversion capability (controlled by bit RxDI).

Depending on the Asynchronous Mode (controlled by bitfield M), output signal or theRxD input signal in Echo Mode (controlled by bit ABEM) is switched to the TxD outputvia an inverter (controlled by bit TXINV).

Table 19-1 Formulas for IrDA Pulse Width Calculation

PMW PMW_IPMW Formulas

1 … 255 0

1

Table 19-2 IrDA Pulse Width Adaption to 1.627 µs

fASC PMW tIPW Error tIPW min

20 MHz 33 1.650 µs +1.4% 0.8 µs

40 MHz 65 1.625 µs -0.1% 0.8 µs

tIPW3

16 Baudrate×---------------------------------------= tIPW min

PMW >> 1( )fASC

---------------------------------=

tIPWPMWfASC

---------------=




Figure 19-11 RxD/TxD Data Path in Asynchronous Modes

Note: In Echo Mode the transmit output signal is blocked by the Echo Mode outputmultiplexer. Figure 19-11 shows that it is not possible to use an IrDA codedreceiver input signal for Autobaud Detection.

ASCAsynch. Mode Logic

MCA05442

IrDACoding

IrDADecode

CON

MUXMUX

MUXRxD

MUXMUX

Autobaud Detection

ABCON

RxDILB

M

MUXTxD

RXINV TXINV

ABEM




19.3 Synchronous Operation

Synchronous Mode supports half-duplex communication, basically for simple I/Oexpansion via shift registers. Data is transmitted and received via line RxD while line TxDoutputs the shift clock.

Synchronous Mode is selected with bitfield M = 000B.

Eight data bits are transmitted or received synchronous to a shift clock generated by theinternal baudrate generator. The shift clock is active only as long as data bits aretransmitted or received.

Figure 19-12 Synchronous Mode of Serial Channel ASC

Serial Port Control

MCA05443


13-bit Baudrate TimerfBRT

fBRfDIV

MUX2

3R

fASC

Shift ClockFIFO

Control

Shift Clock

TIR

TBIR

EIR

Receive Int.Request

Transmit BufferInt. Request

M = 000B

RIR

Transmit Int.Request

Error Int.Request

Receive FIFO Reg.RBUF

Transmit FIFO Reg.TBUF

Receive ShiftRegister

Transmit ShiftRegister

MUX

Internal Bus

BRS

OE

RENOENLB

RxD

TxD

4

0

1




19.3.1 Synchronous Transmission

Synchronous transmission begins within four state times after data has been loaded intoTBUF, provided that bit R is set and bit REN is cleared (half-duplex, no reception).Exception: in Loopback Mode (bit LB set), REN must be set for reception of thetransmitted byte. Data transmission is double-buffered. When the transmitter is idle, thetransmit data loaded into TBUF is immediately moved to the transmit shift register, thusfreeing TBUF for more data. This is indicated by the transmit buffer interrupt request lineTBIR being activated. TBUF may now be loaded with the next data, while transmissionof the previous continuous. The data bits are transmitted synchronous with the shiftclock. After the bit time for the eighth data bit, both the TxD and RxD lines will go high,the transmit interrupt request line TIR is activated, and serial data transmission stops.

Note: Pin TxD must be configured for alternate data output in order to provide the shiftclock. Pin RxD must also be configured for output during transmission.

19.3.2 Synchronous Reception

Synchronous reception is initiated by setting bit REN. If bit R is set, the data applied atRxD is clocked into the receive shift register synchronous to the clock that is output atTxD. After the eighth bit has been shifted in, the contents of the receive shift register aretransferred to the receive data buffer RBUF, the receive interrupt request line RIR isactivated, the receiver enable bit REN is reset, and serial data reception stops.

Note: Pin TxD must be configured for alternate data output in order to provide the shiftclock. Pin RxD must be configured as alternate data input.

Synchronous reception is stopped by clearing bit REN. A currently received byte iscompleted, including the generation of the receive interrupt request and an error interruptrequest, if appropriate. Writing to the transmit buffer register while a reception is inprogress has no effect on reception and will not start a transmission.

If a previously received byte has not been read out of a full receive buffer at the time thereception of the next byte is complete, both the error interrupt request line EIR and theoverrun error status flag OE will be activated/set, provided the overrun check has beenenabled by bit OEN.

19.3.3 Synchronous Timing

Figure 19-13 shows timing diagrams of the ASC Synchronous Mode data reception anddata transmission. In idle state, the shift clock level is high. With the beginning of asynchronous transmission of a data byte, the data is shifted out at RxD with the fallingedge of the shift clock. If a data byte is received through RxD, data is latched with therising edge of the shift clock.

Between two consecutive receive or transmit data bytes, one shift clock cycle (fBR) delayis inserted.




Figure 19-13 ASC Synchronous Mode Waveforms

MCT05444

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3

Shift Clock(TxD)

Transmit Data(RxD)

Receive Data(RxD)

Continuous Transmit Timing

1. Byte 2. Byte

1. Byte 2. Byte

Valid Datan + 1

Valid Datan + 2

Valid Datan

Data Bitn + 1

Data Bitn + 2

Data Bitn

Latch

Shift Shift Shift

Shift Clock(TxD)

Transmit Data(RxD)

Receive Data(RxD)

Receive/Transmit Timing




19.4 Baudrate Generation

The serial channel ASC has its own dedicated 13-bit baudrate generator with reloadcapability, allowing baudrate generation independent of other timers.

The baudrate generator is clocked with a clock (fDIV) derived via a prescaler from theASC input clock fASC. The baudrate timer counts downwards and can be started orstopped through the baudrate generator run bit R. Each underflow of the timer providesone clock pulse to the serial channel. The timer is reloaded with the value stored in its13-bit reload register each time it underflow. The resulting clock fBRT is again divided bya factor for the baudrate clock (16 in Asynchronous Modes and 4 in Synchronous Mode).The prescaler is selected by the bits BRS and FDE. In addition to the two fixed dividers,a fractional divider prescaler unit is available in the Asynchronous Modes that allowsselection of prescaler divider ratios of n/512 with n = 0 … 511. Therefore, the baudrateof ASC is determined by the module clock, the content of FDV, the reload value of BG,and the operating mode (asynchronous or synchronous).

Register ASCx_BG is the dual-function Baudrate Generator/Reload register. ReadingASCx_BG returns the contents of the timer BR_VALUE (bits 15 … 13 return zero), whilewriting to BG always updates the reload register (bits 15 … 13 are insignificant).

An autoreload of the timer with the contents of the reload register is performed each timeASCx_BG is written to. However, if bit R is cleared at the time a write operation toASCx_BG is performed, the timer will not be reloaded until the first instruction cycle afterbit R was set. For a clean baudrate initialization, ASCx_BG should be written only ifR = 0. If ASCx_BG is written while R = 1, unpredictable behavior of the ASC may occurduring running transmit or receive operations.

The ASC baudrate timer reload register ASCx_BG contains the 13-bit reload value forthe baudrate timer in Asynchronous and Synchronous modes.

19.4.1 Baudrate in Asynchronous Mode

For Asynchronous Mode, the baudrate generator provides a clock fBRT with sixteen timesthe rate of the established baudrate. Every received bit is sampled at the 7th, 8th, and 9th

cycle of this clock. The clock divider circuitry, which generates the input clock for the13-bit baudrate timer, is extended by a fractional divider circuitry that allows adjustmentfor more accurate baudrate and the extension of the baudrate range.

The baudrate of the baudrate generator depends on the following bits and registervalues:

• Input clock fASC• Selection of the baudrate timer input clock fDIV by bits FDE and BRS• If bit FDE is set (fractional divider): value of register ASCx_FDV• Value of the 13-bit reload register ASCx_BG




The output clock of the baudrate timer with the reload register is the sample clock in theAsynchronous Modes of the ASC. For baudrate calculations, this baudrate clock fBR isderived from the sample clock fDIV by a division by 16.

The ASC fractional divider register ASCx_FDV contains the 9-bit divider value for thefractional divider (Asynchronous Mode only). It is also used for reference clockgeneration of the autobaud detection unit.

Figure 19-14 ASC Baudrate Generator Circuitry in Asynchronous Modes

Using the Fixed Input Clock Divider

The baudrate for asynchronous operation of serial channel ASC when using the fixedinput clock divider ratios (FDE = 0) and the required reload value for a given baudratecan be determined by the following formulas:

BG represents the contents of the reload bitfield BR_VALUE, taken as unsigned 13-bitinteger.

The maximum baudrate that can be achieved for the Asynchronous Modes when usingthe two fixed clock divider and a module clock of 40 MHz is 1.25 Mbit/s. Table 19-4 listsvarious commonly used baudrates together with the required reload values and thedeviation errors compared to the intended baudrate.

Note: FDE must be 0 to achieve the baudrates in Table 19-3. The deviation errors givenin the table are rounded. Using a baudrate crystal will provide correct baudrateswithout deviation errors.

MCA05445


13-bit Baudrate Timer

16

fBRT

fBR

fDIV

MUXFractionalDivider

2

3R

fASC

BRS

FDE

BaudrateClock

SampleClock

BRS

0

1

X

Selected Divider

2

3

Fractional Divider

FDE

0

0

1




Using the Fractional Divider

When the fractional divider is selected, the input clock fDIV for the baudrate timer isderived from the module clock fASC by a programmable divider. If bit FDE is set, thefractional divider is activated. It divides fASC by a fraction of n/512 for any value of n from0 to 511. If n = 0, the divider ratio is 1, which means that fDIV = fASC. In general, thefractional divider allows the baudrate to be programmed with much more accuracy thanwith the two fixed prescaler divider stages.

Note: BG represents the contents of the reload bitfield BR_VALUE, taken as anunsigned 13-bit integer.

Note: FDV represents the contents of the fractional divider register FD_VALUE taken asan unsigned 9-bit integer.

Table 19-3 Asynchronous Baudrate Formulas Using the Fixed Input Clock Dividers

FDE BRS BG Formula

0 0 0 … 8191

1

Table 19-4 Typical Asynchronous Baudrates Using the Fixed Input Clock Dividers

Baudrate BRS = 0, fASC = 40 MHz BRS = 1, fASC = 40 MHz

Deviation Error Reload Value Deviation Error Reload Value

1.25 Mbit/s --- 0000H NA NA

19.2 kbit/s +0.1% / -1.3% 0040H / 0041H +0.9% / -1.3% 002AH / 002BH

9600 bit/s +0.1% / -0.6% 0081H / 0082H +0.9% / -0.2% 0055H / 0056H

4800 bit/s +0.1% / -0.2% 0103H / 0104H +0.3% / -0.2% 00ACH / 00ADH

2400 bit/s +0.1% / -0.0% 0207H / 0208H +0.0% / -0.2% 015AH / 015BH

1200 bit/s +0.0% / -0.0% 0410H / 0411H +0.0% / -0.0% 02B5H / 02B6H

BaudratefASC

32 BG 1+( )×------------------------------------=

BGfASC

32 Baudrate×--------------------------------------- 1–=

BaudratefASC

48 BG 1+( )×------------------------------------=

BGfASC

48 Baudrate×--------------------------------------- 1–=




Table 19-5 Async. Baudrate Formulas Using the Fractional Input Clock Divider

FDE BRS BG FDV Formula

1 – 1 … 8191 1 … 511

0

Table 19-6 Typical Asynchronous Baudrates Using the Fractional Input Clock Divider

fASC Desired Baudrate

BG FDV Resulting Baudrate

Deviation

40 MHz 115.2 kbit/s 04H 076H 115.234 kbit/s 0.02%

57.6 kbit/s 04H 03BH 57.617 kbit/s 0.02%

38.4 kbit/s 0EH 076H 38.411 kbit/s 0.02%

19.2 kbit/s 0EH 03BH 19.206 kbit/s 0.02%

Baudrate FDV512------------

fASC

16 BG 1+( )×------------------------------------×=

BaudratefASC

16 BG 1+( )×------------------------------------=




19.4.2 Baudrate in Synchronous Mode

For synchronous operation, the baudrate generator provides a clock with four times therate of the established baudrate (see Figure 19-15).

Figure 19-15 ASC Baudrate Generator Circuitry in Synchronous Mode

The baudrate for synchronous operation of serial channel ASC can be determined by theformulas as shown in Table 19-7.

Note: BG represents the contents of the reload bitfield BR_VALUE, taken as anunsigned 13-bit integers.

The maximum baudrate that can be achieved in Synchronous Mode when using amodule clock of 40 MHz is 5 Mbit/s.

Table 19-7 Synchronous Baudrate Formulas

BRS BG Formula

0 0 … 8191

1

MCA05446


13-bit Baudrate TimerfBRT

fDIV

MUX2

3

R

fASC

BRS

Shift /SampleClock

Selected Divider

2

3

BRS

0

1

4

BaudratefASC

8 BG 1+( )×---------------------------------= BG

fASC

8 Baudrate×------------------------------------ 1–=

BaudratefASC

12 BG 1+( )×------------------------------------= BG

fASC

12 Baudrate×--------------------------------------- 1–=




19.5 Autobaud Detection

19.5.1 General Operation

Autobaud Detection provides a capability to recognize the mode and the baudrate of anasynchronous input signal at RxD. Generally, the baudrates to be recognized must beknown by the application. With this knowledge always a set of nine baudrates can bedetected. The Autobaud Detection is not designed to calculate a baudrate of an unknownasynchronous frame.

Figure 19-16 shows how the Autobaud Detection is integrated into its AsynchronousMode configuration. The RxD data line is an input to the autobaud detection unit. Theclock fDIV, generated by the fractional divider, is used by the autobaud detection unit astime base. After successful recognition of baudrate and Asynchronous Mode of the RxDdata input signal, bits in register ASCx_CON and the value of register ASCx_BG in thebaudrate timer are set to the appropriate values, and the ASC can start immediately withthe reception of serial input data.

Figure 19-16 Asynchronous Mode Block Diagram

Note: Autobaud detection is not available in Synchronous Mode.

The following sequence must be executed to start the autobaud detection unit:

• Definition of the baudrates to be detected: standard or non-standard baudrates• Programming of the prescaler/fractional divider to select a specific value of fDIV• Starting the prescaler/fractional divider (setting bit R)• Preparing the interrupt system• Enabling the autobaud detection (setting bit EN and the interrupt enable bits in

ABCON for interrupt generation, if required)• Polling interrupt request flag or waiting for the autobaud detection interrupt


Shift RegistersMCA05447

MUX

Serial PortControl

BaudrateTimer

fDIVPrescaler /Fractional

Divider

AutobaudDetection

IrDADecoding

fASC

RxD

IrDADecoding

MUXTxD

Asynchronous Mode




19.5.2 Serial Frames for Autobaud Detection

The Autobaud Detection is based on the serial reception of a specific two-byte serialframe. This serial frame is build up by the two ASCII bytes “at” or “AT” (“aT” or “At” arenot allowed). Both byte combinations can be detected in five types of asynchronousframes. Figure 19-17 and Figure 19-18 show the serial frames which are detected atleast.

Note: Some other two-byte combinations will be defined too.

Figure 19-17 Two-Byte Serial Frames with ASCII ‘at’

MCT05448

1 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1

‘a’ = 61H

7 Bit, Even Parity

Start

‘t’ = 74H

1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 1

‘a’ = 61H

7 Bit, Odd Parity‘t’ = 74H

1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1

‘a’ = 61H

8 Bit, No Parity‘t’ = 74H

1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 0

‘a’ = 61H

8 Bit, Even Parity‘t’ = 74H

1 1

1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 1

‘a’ = 61H

8 Bit, Odd Parity‘t’ = 74H

1 1

Parity Stop Start Parity Stop

Start Parity Stop Start Parity Stop

Start Stop Start Stop


Parity StopStartParity StopStart




Figure 19-18 Two-Byte Serial Frames with ASCII ‘AT’

19.5.3 Baudrate Selection and Calculation

Autobaud Detection requires some calculations concerning the programming of thebaudrate generator and the baudrates to be detected. Two steps must be considered:

• Defining the baudrate(s) to be detected• Programming of the baudrate timer prescaler - setup of the clock rate of fDIV

MCT05449

1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1

‘A’ = 41H

7 Bit, Even Parity‘T’ = 54H

1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1

‘A’ = 41H

7 Bit, Odd Parity‘T’ = 54H

1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1

‘A’ = 41H

8 Bit, No Parity‘T’ = 54H

1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1

‘A’ = 41H

8 Bit, Even Parity‘T’ = 54H

1 1

1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0

‘A’ = 41H

8 Bit, Odd Parity‘T’ = 54H

1 1



Start Stop Start Stop






In general, the baudrate generator in Asynchronous Mode is build up by two parts (seealso Figure 19-14):

• The clock prescaler part which derives fDIV from fASC• The baudrate timer part which generates the sample clock fBRT and the baudrate

clock fBR

Prior to an Autobaud Detection the prescaler part has to be set up by the CPU while thebaudrate timer (register ASCx_BG) is initialized with a 13-bit value (BR_VALUE)automatically after a successful autobaud detection. For the following calculations, thefractional divider is used (FDE = 1).

Note: It is also possible to use the fixed divide-by-2 or divide-by-3 prescaler. But thefractional divider allows the much more precise adaption of fDIV to the requiredvalue.

Standard Baudrates

For standard baudrate detection the baudrates as shown in Table 19-8 can be e.g.detected. Therefore, the output frequency fDIV of the baudrate generator must be set toa frequency derived from the module clock fASC in a way that it is equal to 11.0592 MHz.The value to be written into register FDV is the nearest integer value which is calculatedaccording the following formula:

(19.1)

Table 19-8 defines the nine standard baudrates (Br0 - Br8) which can be detected forfDIV = 11.0592 MHz.

Table 19-8 Autobaud Detection Using Standard Baudrates (fDIV = 11.0592 MHz)

Baudrate Numbering

Detectable Standard Baudrate

Divide Factor df BG is Loaded after Detection with Value

Br0 230.400 kbit/s 48 2 = 002H

Br1 115.200 kbit/s 96 5 = 005H

Br2 57.600 kbit/s 192 11 = 00BH

Br3 38.400 kbit/s 288 17 = 011H

Br4 19.200 kbit/s 576 35 = 023H

Br5 9600 bit/s 1152 71 = 047H

Br6 4800 bit/s 2304 143 = 08FH

Br7 2400 bit/s 4608 287 = 11FH

Br8 1200 bit/s 9216 575 = 23FH

FDV 512 11.0592 MHz×fASC

----------------------------------------------------=




According to Table 19-8 a baudrate of 9600 bit/s is achieved when register ASCx_BG isloaded with a value of 047H, assuming that fDIV has been set to 11.0592 MHz.Table 19-8 also lists a divide factor df which is defined with the following formula:

(19.2)

This divide factor df defines a fixed relationship between the prescaler output frequencyfDIV and the baudrate to be detected during the Autobaud Detection operation. Thismeans, changing fDIV results in a totally different baudrate table in means of baudratevalues. For the baudrates to be detected, the following relations are always valid:

Br0 = fDIV/48D, Br1 = fDIV/96D, … up to Br8 = fDIV/9216D

A requirement for detecting standard baudrates up to 230.400 kbit/s is the fDIV minimumvalue of 11.0592 MHz. With the value FD_VALUE the fractional divider fDIV is adapted tothe module clock frequency fASC. Table 19-9 defines the deviation of the standardbaudrates when using autobaud detection depending on the module clock fASC.

Note: If the deviation of the baudrate after autobaud detection is to high, the baudrategenerator (fractional divider FDV and reload register ASCx_BG) can bereprogrammed if required to get a more precise baudrate with less error.

Table 19-9 Standard Baudrates - Deviations and Errors for Autobaud Detection

fASC FDV Error in fDIV

10 MHz not possible

12 MHz 472 +0.03%

13 MHz 436 +0.1%

16 MHz 354 +0.03%

18 MHz 315 +0.14%

18.432 MHz 307 -0.07%

20 MHz 283 -0.04%

24 MHz 236 +0.03%

25 MHz 226 -0.22%

30 MHz 189 +0.14%

33 MHz 172 +0.24%

40 MHz 142 +0.31%

BaudratefDIV

df---------=




Non-Standard Baudrates

Due to the relationship between Br0 to Br8 in Table 19-8 concerning the divide factor dfother baudrates than the standard baudrates can be also selected. E.g. if a baudrate of50 kbit/s has to be detected, Br2 is e.g. defined as baudrate for the 50 kbit/s selection.This further results in:

fDIV = 50 kbit/s × df@Br2 = 50 kbit/s × 192 = 9.6 MHz

Therefore, depending on the module clock frequency fASC, the value of the fractionaldivider (register FDV) must be set in this example according to the formula:

with fDIV = 9.6 MHz (19.3)

Using this selection (fDIV = 9.6 MHz), the detectable baudrates start at 200 kbit/s (Br0)down to 1042 bit/s (Br8). Table 19-10 shows the baudrate table for this example.

Table 19-10 Autobaud Detection Using Non-Standard Baudrates (fDIV = 9.6 MHz)

Baudrate Numbering

Detectable Non-Standard Baudrates

Divide Factor df BG is Loaded after Detection with Value

Br0 200.000 kbit/s 48 2 = 002H

Br1 100.000 kbit/s 96 5 = 005H

Br2 50 kbit/s 192 11 = 00BH

Br3 33.333 kbit/s 288 17 = 011H

Br4 16.667 kbit/s 576 35 = 023H

Br5 8333 bit/s 1152 71 = 047H

Br6 4167 bit/s 2304 143 = 08FH

Br7 2083 bit/s 4608 287 = 11FH

Br8 1047 bit/s 9216 575 = 23FH

FDV512 f× DIV

fASC

-------------------------=




19.5.4 Overwriting Registers on Successful Autobaud Detection

With a successful Autobaud Detection some bits in registers ASCx_CON and ASCx_BGare automatically set to a value which corresponds to the mode and baudrate of thedetected serial frame conditions (see Table 19-11). In control register ASCx_CON themode control bits M and the parity select bit ODD are overwritten. Register ASCx_BG isloaded with the 13-bit reload value for the baudrate timer.

Note: The autobaud detection interrupts are described in Section 19.7.

Table 19-11 Autobaud Detection Overwrite Values for the CON Register

Detected Parameters M ODD BR_VALUE

Operating Mode 7 bit, even parity7 bit, odd parity8 bit, even parity8 bit, odd parity8 bit, no parity

0 1 10 1 11 1 11 1 10 0 1

01010

–

Baudrate Br0Br1Br2Br3Br4Br5Br6Br7Br8

– – 2 = 002H5 = 005H11 = 00BH17 = 011H35 = 023H71 = 047H143 = 08FH287 = 11FH575 = 23FH




19.6 Hardware Error Detection Capabilities

To improve the safety of serial data exchange, the serial channel ASC provides an errorinterrupt request flag to indicate the presence of an error, and three (selectable) errorstatus flags in register ASCx_CON to indicate which error has been detected duringreception. Upon completion of a reception, the error interrupt request line EIR will beactivated simultaneously with the receive interrupt request line RIR, if one or more of thefollowing conditions are met:

• If the framing error detection enable bit FEN is set and any of the expected stop bitsis not high, the framing error flag FE is set, indicating that the error interrupt requestis due to a framing error (Asynchronous Mode only).

• If the parity error detection enable bit PEN is set in the modes where a parity bit isreceived, and the parity check on the received data bits proves false, the parity errorflag PE is set, indicating that the error interrupt request is due to a parity error(Asynchronous Mode only).

• If the overrun error detection enable bit OEN is set and the last character receivedwas not read out of the receive buffer by software or by a DMA transfer at the timethe reception of a new frame is complete, the overrun error flag OE is set indicatingthat the error interrupt request is due to an overrun error (Asynchronous andSynchronous Mode).




19.7 Interrupts

Six interrupt sources are provided for serial channel ASC. Line TIR indicates a transmitinterrupt, TBIR indicates a transmit buffer interrupt, RIR indicates a receive interrupt andEIR indicates an error interrupt of the serial channel. The autobaud detection unitprovides two additional interrupts, the ABSTIR start of autobaud operation interrupt andthe ABDETIR autobaud detected interrupt. The interrupt output lines TBIR, TIR, RIR,EIR, ABSTIR, and ABDETIR are activated (active state) for two periods of the moduleclock fASC.

The cause of an error interrupt request (framing, parity, overrun error) can be identifiedby the error status flags FE, PE, and OE. For the two autobaud detection interruptsregister ABSTAT provides status information.

Note: In contrary to the error interrupt request line EIR, the error status flags FE/PE/OEare not reset automatically but must be cleared by software.

For normal operation (i.e. besides the error interrupt) the ASC provides three interruptrequests to control data exchange via this serial channel:

• TBIR is activated when data is moved from TBUF to the transmit shift register.• TIR is activated before the last bit of an asynchronous frame is transmitted, or after

the last bit of a synchronous frame has been transmitted.• RIR is activated when the received frame is moved to RBUF.

Note: While the receive task is handled by a single interrupt handler, the transmitter isserviced by two interrupt handlers. This provides advantages for the servicingsoftware.

For single transfers it is sufficient to use the transmitter interrupt (TIR), which indicatesthat the previously loaded data has been transmitted, except for the last bit of anasynchronous frame. For multiple back-to-back transfers it is necessary to load thefollowing piece of data at last until the time the last bit of the previous frame has beentransmitted. In Asynchronous Mode this leaves just one bit-time for the handler torespond to the transmitter interrupt request, in Synchronous Mode it is impossible at all.

Using the transmit buffer interrupt (TBIR) to reload transmit data gives the time totransmit a complete frame for the service routine, as TBUF may be reloaded while theprevious data is still being transmitted.

The start of autobaud operation interrupt ABSTIR is generated whenever the autobauddetection unit is enabled (ABEN and ABDETEN and ABSTEN are set), and a start bithas been detected at RxD. In this case ABSTIR is generated during Autobaud Detectionwhenever a start bit is detected.

The autobaud detected interrupt ABDETIR is always generated after recognition of thesecond character of the two-byte frame, this means after a successful AutobaudDetection. If FCDETEN is set the autobaud detected interrupt ABDETIR is alsogenerated after the recognition of the first character of the two-byte frame.




Figure 19-19 ASC Interrupt Generation

As shown in Figure 19-19, TBIR is an early trigger for the reload routine, while TIRindicates the completed transmission. Therefore, software using handshake should relyon TIR at the end of a data block to ensure that all data has actually been transmitted.

The six interrupts of the ASC0 and of the ASC1 module are controlled by the followingservice request control registers:

• ASC0_ABIC, ASC1_ABIC: control the autobaud interrupts• ASC0_TIC, ASC1_TIC: control the transmit interrupts• ASC0_RIC, ASC1_RIC: control the receive interrupts• ASC0_EIC, ASC1_EIC: control the error interrupts• ASC0_TBIC, ASC1_TBIC: control the transmit buffer empty interrupt


MCT05450

Sta

rt

Idle Sto

p

Sta

rt

Sto

p

Sta

rt

Sto

p

Idle

TBIR TBIR

TIR

RIR

TBIR

TIR

RIR

TIR

RIR

Asynchronous Mode

Idle Idle

TBIR TBIR

TIR

RIR

TBIR

TIR

RIR

TIR

RIR

Synchronous Mode

Asynchronous ModesAutobaud Detection

Star

t

Idle Sto

p

ABSTIR

1. Character

Star

t

ABDETIR

2. Character Sto

p

ABDETIR 1)

1) Only if FCDETEN = 1




The two autobaud interrupt request lines (start of autobaud detection and end ofautobaud detection) in each ASC module are ‘ORed’ together; the ‘ORed’ output signalis connected to the interrupt control register. This is shown in Figure 19-20.

Figure 19-20 Wiring of Autobaud Interrupts

Table 19-12 summarizes all interrupt sources:

Table 19-12 ASC Interrupt Sources

Interrupt Signal Description

TBUF Action TBIR A write action to the transmit shift register from the transmit buffer register ASCx_TBUF.If a FIFO is configured for the ASC and bit TXTMEN is cleared, TXFIFL defines when the interrupt is generated depending on the FIFO fill state.

Transmit Interrupt

TIR The interrupt is generated after the last (eight) data bit of a transmission frame is send via line TxD by the transmit shift register.

Note: Only for Synchronous Mode

Transmit Interrupt

TIR The interrupt is generated just before the last bit of a transmission frame is send via line TxD by the transmit shift register. If a FIFO is configured for the ASC and bit XTMEN is cleared, TXFIFL defines when the interrupt is generated depending on the FIFO fill state.

Note: Only for Asynchronous Modes

Receive Interrupt

RIR The interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register.


MCA05451

>1_start_autobaud_detect_irq

end_autobaud_detect_irqASCxKernel ASCx_ABIC

(x = 0 … 1)




Receive Interrupt

RIR The interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register. If a FIFO is configured for the ASC and bit RXTMEN is cleared, RXFIFL defines when the interrupt is generated depending on the FIFO fill state.

Note: Only for Asynchronous Modes

Receive Error Interrupt

RIR and EIR

The interrupt is generated when the received frame is copied from the receive shift register to the receive buffer register and the receive buffer contains already valid data.


Receive Overflow

RIR and EIR

If an additional frame is received when the FIFO is completely full an overflow error occurs. Both interrupts are generated and the previously received frame is overwritten in the FIFO and therefore lost.

Read to empty FIFO

EIR A read operation from the CPU to an empty receive FIFO generates this interrupt.

Transparent Read Operation

RIR In Transparent Mode a receive interrupt is always generated on a read operation from the CPU to the receive FIFO if the FIFO is not empty after this operation.

Flush Action TBIR A transmit buffer interrupt is generated when the transmit FIFO is flushed.

FIFO Enable TBIR A transmit buffer interrupt is generated when the transmit FIFO is enabled by setting bits TXTMEN and TXFEN when it was previously disabled in Transparent Mode.

Transmit Overflow

EIR If an additional frame is written to the transmit FIFO when it is completely full an overflow error occurred. The interrupt is generated and the previously written frame is overwritten and therefor lost in the FIFO.

Frame Error RIR and EIR

An expected stop bit is not high.

Note: Asynchronous Mode only

Parity Error RIR and EIR

When a parity bit is received that does not fit to the parity of the received data.

Note: Asynchronous Mode only

Table 19-12 ASC Interrupt Sources (cont’d)

Interrupt Signal Description




19.8 Registers

Table 19-13 shows all registers which are required for programming the ASC modules.It summarizes the ASC kernel registers and the interrupt control registers and lists theiraddresses.

Table 19-13 ASC Module Register Summary

Name Description ASC0 Addresses

Reg. Area

ASC1 Addresses

16-Bit 8-Bit 16-Bit 8-Bit

ASCx_CON Control Register FFB0H D8H SFR FFB8H DCH

ASCx_TBUF Transmit Buffer Register FEB0H 58H SFR FEB8H 5CH

ASCx_RBUF Receive Buffer Register FEB2H 59H SFR FEBAH 5DH

ASCx_ABCON Autobaud Control Register F1B8H DCH ESFR F1BCH DEH

ASCx_ABSTAT Autobaud Status Register F0B8H 5CH ESFR F0BCH 5EH

ASCx_BG Baudrate Timer Reload Register

FEB4H 5AH SFR FEBCH 5EH

ASCx_FDV Fractional Divider Register FEB6H 5BH SFR FEBEH 5FH

ASCx_PMW IrDA Pulse Mode and Width Register

FEAAH 55H SFR FEACH 56H

ASCx_RXFCON Receive FIFO Control Register

F0C6H 63H ESFR F0A6H 53H

ASCx_TXFCON Transmit FIFO Control Register

F0C4H 62H ESFR F0A4H 52H

ASCx_FSTAT FIFO Status Register F0BAH 5DH ESFR F0BEH 5FH

ASCx_ABIC Autobaud Interrupt Control Register

F15CH AEH ESFR F1BAH DDH

ASCx_TIC Transmit Interrupt Control Register

FF6CH B6H SFR/ESFR

F182H C1H

ASCx_RIC Receive Interrupt Control Register

FF6EH B7H SFR/ESFR

F18AH C5H

ASCx_EIC Error Interrupt Control Register

FF70H B8H SFR/ESFR

F192H C9H

ASCx_TBIC Transmit Buffer Interrupt Control Register

F19CH CEH ESFR F150H A8H




Control Register

The operating mode of the serial channel ASC is controlled by its control register CON.This register contains control bits for mode and error check selection, and status flagsfor error identification.

ASCx_CON Control Register SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R LB BRS ODD FDE OE FE PE OEN FENPEN/RxDI

REN STP M

rw rw rw rw rw rwh rwh rwh rw rw rw rwh rw rw


R 15 rw Baudrate Generator Run Control Bit0 Baudrate generator disabled (ASC inactive)1 Baudrate generator enabled

Note: BR_VALUE should only be written if R = 0.

LB 14 rw Loopback Mode Enabled0 Loopback Mode disabled. Standard

transmit/receive Mode1 Loopback Mode enabled

BRS 13 rw Baudrate Selection0 Baud rate timer prescaler divide-by-2 selected1 Baud rate timer prescaler divide-by-3 selected

Note: BRS is don’t care if FDE = 1 (fractional dividerselected).

ODD 12 rw Parity Selection0 Even parity selected (parity bit of 1 is included

in data stream on odd number of 1 and parity bit of 0 is included in data stream on even number of 1)

1 Odd parity selected (parity bit of 1 is included in data stream on even number of 1 and parity bit of 0 is included in data stream on odd number of 1)




FDE 11 rw Fractional Divider Enable0 Fractional divider disabled1 Fractional divider enabled and used as

prescaler for baudrate generator (bit BRS is don’t care)

OE 10 rwh Overrun Error FlagSet by hardware on an overrun/underflow error (OEN = 1). Must be cleared by software.

FE 9 rwh Framing Error FlagSet by hardware on a framing error (FEN = 1).Must be cleared by software.

PE 8 rwh Parity Error FlagSet by hardware on a parity error (PEN = 1).Must be cleared by software.

OEN 7 rw Overrun Check Enable0 Ignore overrun errors1 Check overrun errors

FEN 6 rw Framing Check Enable(Asynchronous Mode only)0 Ignore framing errors1 Check framing errors

PEN / RxDI 5 rw Parity Check Enable/RxDI Invert in IrDA ModeAll Asynchronous Modes without IrDA Mode (PEN):0 Ignore parity1 Check parityOnly in IrDA Mode (RxDI):0 RxD input is not inverted1 RxD input is inverted

REN 4 rwh Receiver Enable Bit0 Receiver disabled1 Receiver enabled

Note: REN is cleared by hardware after reception ofa byte in synchronous mode.

STP 3 rw Number of Stop Bits Selection0 One stop bit1 Two stop bits





Baudrate Register

The ASC baudrate timer reload register BG contains the 13-bit reload value for thebaudrate timer in Asynchronous and Synchronous Mode.

M [2:0] rw Mode Control000 8-bit-data for synchronous operation001 8-bit-data for asynchronous operation010 8-bit-data IrDA Mode for asynchronous

operation011 7-bit-data and parity for asynchronous

operation100 9-bit-data for asynchronous operation101 8-bit-data and wake up bit for asynchronous

operation110 Reserved. Do not use this combination111 8-bit-data and parity for asynchronous

operation

ASCx_BG Baudrate Timer/Reload Reg. SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- BR_VALUE

- rw


BR_VALUE [12:0] rw Baudrate Timer/Reload ValueReading returns the 13-bit content of the baudrate timer; writing loads the baudrate timer/reload value.

Note: BG should only be written if R = 0.





Fractional Divider Register

The ASC fractional divider register FDV contains the 9-bit divider value for the fractionaldivider (Asynchronous Mode only). It is also used for reference clock generation of theautobaud detection unit.

ASCx_FDV Fractional Divider Register SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- FD_VALUE

- rw


FD_VALUE [8:0] rw Fractional Divider Register ValueFD_VALUE contains the 9-bit value of the fractional divider which defines the fractional divider ration/512 (n = 0 … 511). With n = 0, the fractional divider is switched off (input = output frequency, fDIV = fASC, see Figure 19-14).




IrDA Pulse Mode/Width Register

The ASC IrDA pulse mode and width register PMW contains the 8-bit IrDA pulse widthvalue and the IrDA pulse width mode select bit. This register is only required in the IrDAoperating mode.

ASCx_PMW IrDA Pulse Mode/Width Reg. SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-IRPW

PW_VALUE

- rw rw


IRPW 8 rw IrDA Pulse Width Selection0 IrDA pulse width is 3/16 bit time1 IrDA pulse width is defined by PW_VALUE

PW_VALUE [7:0] rw IrDA Pulse Width ValuePW_VALUE is the 8-bit value n, which defines the variable pulse width of an IrDA pulse.Depending on the ASC input frequency fASC, this value can be used to adjust the IrDA pulse width to value which is not equal 3/16 bit time (e.g. 1.6 ms).




Transmitter Buffer Register

The ASC transmitter buffer register TBUF contains the transmit data value inAsynchronous and Synchronous Mode.

ASCx_TBUF Transmit Buffer Register SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- TD_VALUE

- rw


TD_VALUE [8:0] rw Transmit Data Register ValueTBUF contains the data to be transmitted in asynchronous and synchronous operating mode of the ASC. Data transmission is double buffered. Therefore, a new value can be written to TBUF before the transmission of the previous value is complete.




Receiver Buffer Register

The ASC Receiver buffer register RBUF contains the transmit data value inAsynchronous and Synchronous Modes.

ASCx_RBUF Receive Buffer Register SFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- RD_VALUE

- rw


RD_VALUE [8:0] rw Receive Data Register ValueRBUF contains the received data bits and, depending on the selected mode, the parity bit in asynchronous and synchronous operating mode of the ASC.In asynchronous operating mode with M = 011(7-bit data + parity) the received parity bit is written into RD7.In asynchronous operating mode with M = 111(8-bit data + parity) the received parity bit is written into RD8.




Autobaud Control Register

The autobaud control register ABCON of the ASC module is used to control theautobaud detection operation. It contains its general enable bit, the interrupt enablecontrol bits, and data path control bits.

ASCx_ABCON Autobaud Control Register ESFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-RXINV

TXINV

ABEM -FC

DETEN

ABDETEN

ABST

EN

AUREN

ABEN

- rw rw rw - rw rw rw rw rwh


RXINV 11 rw Receive Inverter Enable0 Receive inverter disabled1 Receive inverter enabled

TXINV 10 rw Transmit Inverter Enable0 Transmit inverter disabled1 Transmit inverter enabled

ABEM [9:8] rw Autobaud Echo Mode EnableIn Echo Mode the serial data at RxD is switched to TxD output.00 Echo Mode disabled01 Echo Mode is enabled during Autobaud

Detection10 Echo Mode is always enabled11 Reserved; do not use this combination

FCDETEN 4 rw First Character of Two-Byte Frame Detected Enable0 Autobaud Detection interrupt ABDETIR

becomes active after the two-byte frame recognition

1 Autobaud Detection interrupt ABDETIR becomes active after detection of the first and second byte of the two-byte frame

ABDETEN 3 rw Autobaud Detection Interrupt Enable0 Autobaud Detection interrupt disabled1 Autobaud Detection interrupt enabled




ABSTEN 2 rw Start of Autobaud Detection Interrupt Enable0 Start of Autobaud Detection interrupt disabled1 Start of Autobaud Detection interrupt enabled

AUREN 1 rw Automatic Autobaud Control of CON.REN0 CON.REN is not affected during autobaud

detection1 CON.REN is cleared (receiver disabled) when

ABEN and AUREN are set together. CON.REN is set (receiver enabled) after a successful Autobaud Detection (with the stop bit detection of the second character)

ABEN 0 rwh Autobaud Detection Enable0 Autobaud detection is disabled1 Autobaud detection is enabled

Note: ABEN is reset by hardware after a successfulAutobaud Detection; (with the stop bitdetection of the second character).Resetting ABEN by software if it was set abortsthe Autobaud Detection.





Autobaud Status Register

The autobaud status register ABSTAT of the ASC module indicates the status of theautobaud detection operation.

ASCx_ABSTAT Autobaud Status Register ESFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

-DETWAIT

SCCDET

SCSDET

FCCDET

FCSDET

- rwh rwh rwh rwh rwh


DETWAIT 4 rwh Autobaud Detection is Waiting0 Either character ‘a’, ‘A’, ‘t’, or ‘T’ has been

detected1 The autobaud detection unit waits for the first

‘a’ or ‘A’Bit is cleared when either FCSDET or FCCDET is set (‘a’ or ‘A’ detected). Bit can be also cleared by software. DETWAIT is set by hardware when ABEN is set.

SCCDET 3 rwh Second Character with Capital Letter Detected0 No capital ‘T’ character detected1 Capital ‘T’ character detectedBit is cleared by hardware when ABEN is set and if FCSDET or FCCDET or SCSDET is set. Bit can be also cleared by software.

SCSDET 2 rwh Second Character with Small Letter Detected0 No small ‘t’ character detected1 Small ‘t’ character detectedBit is cleared by hardware when ABEN is set and if FCSDET or FCCDET or SCCDET is set. Bit can be also cleared by software.




Note: SCSDET or SCCDET are set when the second character has been recognized.ABEN is reset and ABDETIR set after SCSDET or SCCDET have been set.

FCCDET 1 rwh First Character with Capital Letter Detected0 No capital ‘A’ character detected1 Capital ‘A’ character detectedBit is cleared by hardware when ABEN is set and if FCSDET or SCSDET or SCCDET is set. Bit can be also cleared by software.

FCSDET 0 rwh First Character with Small Letter Detected0 No small ‘a’ character detected1 Small ‘a’ character detectedBit is cleared by hardware when ABEN is set and if FCCDET or SCSDET or SCCDET is set. Bit can be also cleared by software.





Receive FIFO Control Register

ASCx_RXFCON Receive FIFO Control Reg. ESFR (Table 19-13) Reset Value: 0100H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- RXFITL -RXTMEN

RXFFLU

RXFEN

- rw - rw rw rw


RXFITL [11:8] rw Receive FIFO Interrupt Trigger LevelDefines a receive FIFO interrupt trigger level. A receive interrupt request (RIR) is generated after the reception of a byte when the filling level of the receive FIFO is equal to or greater than RXFITL.0000 Reserved. Do not use this combination0001 Interrupt trigger level is set to one0010 Interrupt trigger level is set to two… …0111 Interrupt trigger level is set to seven1000 Interrupt trigger level is set to eight

Note: In Transparent Mode this bitfield is don’t care.

Note: Combinations defining an interrupt trigger levelgreater than the FIFO size should not be used.

RXTMEN 2 rw Receive FIFO Transparent Mode Enable0 Receive FIFO Transparent Mode is disabled1 Receive FIFO Transparent Mode is enabled

Note: This bit is don’t care if the receive FIFO isdisabled (RXFEN = 0).




Note: After a successful autobaud detection sequence, the RXFIFO should be flushedbefore data is received.

RXFFLU 1 rw Receive FIFO Flush0 No operation1 Receive FIFO is flushed

Note: Setting RXFFLU clears bitfield RXFFL inregister FSTAT. RXFFLU is always read as 0.

RXFEN 0 rw Receive FIFO Enable0 Receive FIFO is disabled1 Receive FIFO is enabled

Note: Resetting RXFEN automatically flushes thereceive FIFO.





Transmit FIFO Control Register

ASCx_TXFCON Transmit FIFO Control Reg. ESFR (Table 19-13) Reset Value: 0100H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- TXFITL -TXTMEN

TXFFLU

TXFEN

- rw - rw rw rw


TXFITL [11:8] rw Transmit FIFO Interrupt Trigger LevelDefines a transmit FIFO interrupt trigger level. A transmit interrupt request (TIR) is generated after the transfer of a byte when the filling level of the transmit FIFO is equal to or lower than TXFITL.0000 Reserved. Do not use this combination0001 Interrupt trigger level is set to one0010 Interrupt trigger level is set to two… …0111 Interrupt trigger level is set to seven1000 Interrupt trigger level is set to eight

Note: In Transparent Mode this bitfield is don’t care.

Note: Combinations defining an interrupt trigger levelgreater than the FIFO size should not be used.

TXTMEN 2 rw Transmit FIFO Transparent Mode Enable0 Transmit FIFO Transparent Mode is disabled1 Transmit FIFO Transparent Mode is enabled

Note: This bit is don’t care if the receive FIFO isdisabled (TXFEN = 0).




TXFFLU 1 rw Transmit FIFO Flush0 No operation1 Transmit FIFO is flushed

Note: Setting TXFFLU clears bitfield TXFFL inregister ASCx_FSTAT. TXFFLU is alwaysread as 0.

TXFEN 0 rw Transmit FIFO Enable0 Transmit FIFO is disabled1 Transmit FIFO is enabled

Note: Resetting TXFEN automatically flushes thetransmit FIFO.





FIFO Status Register

ASCx_FSTAT FIFO Status Register ESFR (Table 19-13) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- TXFFL - RXFFL

- rh - rh


TXFFL [11:8] rh Transmit FIFO Filling Level0000 Transmit FIFO is filled with zero bytes0001 Transmit FIFO is filled with one byte… …0111 Transmit FIFO is filled with seven bytes1000 Transmit FIFO is filled with eight bytes

Note: TXFFL is cleared after a receive FIFO flushoperation.

RXFFL [3:0] rh Receive FIFO Filling Level0000 Receive FIFO is filled with zero bytes0001 Receive FIFO is filled with one byte… …0111 Receive FIFO is filled with seven bytes1000 Receive FIFO is filled with eight bytes

Note: RXFFL is cleared after a receive FIFO flushoperation.




19.9 Interfaces of the ASC Modules

In the XC164 the ASC modules are connected to IO ports and other internal modulesaccording to Figure 19-21 and Figure 19-22.

The input/output lines of ASC0 and ASC1 are connected to pins of Ports P3. The6 interrupt request lines of each module are connected to the Interrupt Control Block.

Clock control and emulation control of the SSC Module is handled by the System ControlUnit, SCU.

Figure 19-21 ASC0 Module Interfaces

Figure 19-22 ASC1 Module Interfaces


ASC0Module

MCA05452

Port P3Control

SystemControl

Unit (SCU)

P3.11/RxDA0

P3.10/TxDA0

S0TIRQ

S0ABIRQ2

S0RIRQ

S0EIRQ

S0TBIRQ

S0ABIRQ1

ASC0DIS

fASC

S0RxD

S0TxD


ASC1Module

MCA05453

Port P3Control

SystemControl

Unit (SCU)

P3.1/RxDA1

P3.0/TxDA1

S1TIRQ

S1ABIRQ2

S1RIRQ

S1EIRQ

S1TBIRQ

S1ABIRQ1

ASC1DIS

fASC

S1RxD

S1TxD




Note: In synchronous operating mode, the direction of the RxD pin is not automaticallyset by the ASC modules; it must be switched by software via the corresponding bitin register DP3, depending on the selected mode (receive or transmit data).

Note: To select RxDA1 as alternate output function for P3.1, it is sufficient to set bit 1 ofregister ALTSEL0P3, the corresponding bit in register ALTSEL1P3 is “don’t care”.



High-Speed Synchronous Serial Interface (SSC)

20 High-Speed Synchronous Serial Interface (SSC) The XC164 contains two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1.The following sections present the general features and operations of such an SSCmodule. The final section describes the actual implementation of the two SSC modulesincluding their interconnections with other on-chip modules.

20.1 Introduction

The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial synchronous communication up to 20 Mbit/s (@ 40 MHz module clock).The serial clock signal can be generated by the SSC itself (Master Mode) or can bereceived from an external master (Slave Mode). Data width, shift direction, clock polarity,and phase are programmable. This supports communication with SPI-compatibledevices. Transmission and reception of data is double-buffered. A 16-bit baudrategenerator provides the SSC with a separate serial clock signal.

Features and Functions

• Master and Slave Mode operation– Full-duplex or half-duplex operation

• Flexible data format– Programmable number of data bits: 2 to 16 bits– Programmable shift direction: LSB or MSB shift first– Programmable clock polarity: idle low or high state for the shift clock– Programmable clock/data phase:

data shift with leading or trailing edge of the shift clock• Baudrate generation from 20 Mbit/s to 306.6 bit/s (@ 40 MHz module clock)• Interrupt generation

– On a Transmitter-Empty condition– On a Receiver-Full condition– On an Error condition (receive, phase, baudrate, transmit error)

20.2 Operational Overview

The high-speed synchronous serial interface can be configured in a very flexible way, soit can be used with other synchronous serial interfaces, can serve for master/slave ormultimaster interconnections or can operate compatible with the popular SPI interface.Thus, the SSC can be used to communicate with shift registers (IO expansion),peripherals (e.g. EEPROMs, etc.) or other controllers (networking). The SSC supportshalf-duplex and full-duplex communication. Data is transmitted on lines MTX/STX orreceived on lines MRX/SRX, connected with pins MTSR (Master Transmit/SlaveReceive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line

User’s Manual 20-1 V2.1, 2004-03SSC_X, V2.0



MSCLK (Master Serial Shift Clock) or input via line SSCLK (Slave Serial Shift Clock).Both lines are connected to pin SCLK. These pins are alternate functions of port pins.

A block diagram of the SSC Module is shown in Figure 20-2.

From the programmer’s point of view, the term ‘SSC unit’ refers to a set of registers (seeFigure 20-1) which are associated with this peripheral, including the port pins which maybe used for alternate input/output functions, and including their direction control bits.

Figure 20-1 SFRs Associated with the SSC Unit

MCA05454

P1HDP1H

ALTSEL0P1H

SYSCON3OPSEN

P3DP3

ALTSEL0P3

SSC

0SS

C1

TICRICEIC

CONBR

TBRB

System RegistersInterrupt RegistersControl RegistersData Registers

Transmit / Receive Buffer RegisterSSC Control RegisterBaudrate Timer / Reload RegisterTransmit / Receive / Error Interrupt Control RegisterPort Py Data Register (y = 1H, 3)Port Py Direction Control Register (y = 1H, 3)Port Py Alternate Output Select Register 0 (y = 1H, 3)SCU System Control Register 3

TB / RBCONBRTIC / RIC / EICPyDPyALTSEL0PySYSCON3




Figure 20-2 Synchronous Serial Channel (SSC) Block Diagram

20.2.1 Operating Mode Selection

The operating mode of the SSC module is controlled by its control register SSCx_CON.This register has a double function:

• During programming (SSC disabled by SSCx_CON.EN = 0), it provides access to aset of control bits

• During operation (SSC enabled by SSCx_CON.EN = 1), it provides access to a setof status flags

In the following, the layout of register CON is shown for both functions.

MCB05455

BaudrateGenerator

ClockControl

SSCControl Block

TIRQRIRQEIRQ

Transmit InterruptReceive Interrupt RequestError Interrupt Request

Status Control

16-bit ShiftRegister



Input/OutputLine

Control

MTXMRX

STXSRX

fSSCto PinSCLK

to PinMTSR

to PinMRST

MSCLKSSCLK




SSC Control Register (SSCx_CON.EN = 0: Programming Mode)

SSCx_CON SSC Control Register SFR (Table 20-2) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN= 0

MS -A

RENBEN PEN REN TEN LB PO PH HB BM

rw rw - rw rw rw rw rw rw rw rw rw rw


EN 15 rw Enable Bit = 0Transmission and reception disabled. Access to control bits.

MS 14 rw Master Select0 Slave Mode. Operate on shift clock received

via SCLK.1 Master Mode. Generate shift clock and output

it via SCLK.

AREN 12 rw Automatic Reset Enable0 No additional action upon a baudrate error1 The SSC is automatically reset upon a

baudrate error

BEN 11 rw Baudrate Error Enable0 Ignore baudrate errors1 Check baudrate errors

PEN 10 rw Phase Error Enable0 Ignore phase errors1 Check phase errors

REN 9 rw Receive Error Enable0 Ignore receive errors1 Check receive errors

TEN 8 rw Transmit Error Enable0 Ignore transmit errors1 Check transmit errors

LB 7 rw Loop Back Control0 Normal output1 Receive input is connected with transmit

output (half-duplex mode)




SSC Control Register (SSCx_CON.EN = 1: Operating Mode)

PO 6 rw Clock Polarity Control0 Idle clock line is low, leading clock edge is low-

to-high transition.1 Idle clock line is high, leading clock edge is

high-to-low transition.

PH 5 rw Clock Phase Control0 Shift transmit data on the leading clock edge,

latch on trailing edge.1 Latch receive data on leading clock edge, shift

on trailing edge.

HB 4 rw Heading Control0 Transmit/Receive LSB First1 Transmit/Receive MSB First

BM [3:0] rw Data Width Selection0000 Reserved. Do not use this combination.0001 Transfer Data Width is 2 bits… Transfer Data Width is (<BM> + 1)1111 Transfer Data Width is 16 bits

SSCx_CON SSC Control Register SFR (Table 20-2) Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN= 1

MS - BSY BE PE RE TE - - - - BC

rw rw - rh rwh rwh rwh rwh - - - - rw


EN 15 rw Enable Bit = 1Transmission and reception enabled. Access to status flags and M/S control.

MS 14 rw Master/Slave Selection0 Slave Mode. Operate on shift clock received

via SCLK.1 Master Mode. Generate shift clock and output

it via SCLK.





Note: The target of an access to SSCx_CON (control bits or flags) is determined by thestate of bit EN prior to the access; that is, writing C057H to SSCx_CON inprogramming mode (EN = 0) will initialize the SSC (EN was 0) and then turn it on(EN = 1). When writing to SSCx_CON, ensure that reserved locations receivezeros.

Transmitter Buffer Register

The SSC Transmit Buffer Register SSCx_TB (see Table 20-2) contains the transmitdata value. Unselected bits of SSCx_TB are ignored during transmission. The transmitvalue must be right-aligned regardless of MSB or LSB first operation.

Receiver Buffer Register

The SSC Receive Buffer Register SSCx_RB (see Table 20-2) contains the receive datavalue. Unselected bits of SSCx_RB will be not valid and should be ignored. The receivedvalue is always right-aligned regardless of MSB or LSB first operation.

BSY 12 rh Busy FlagSet while a transfer is in progress. Do not write to!!!

BE 11 rwh Baudrate Error Flag0 No error1 More than factor 2 or 0.5 between slave’s

actual and expected baudrate

PE 10 rwh Phase Error Flag0 No error1 The received data has changed around

sampling clock edge

RE 9 rwh Receive Error Flag0 No error1 A reception was completed before the receive

buffer was read

TE 8 rwh Transmit Error Flag0 No error1 A transfer has started with the slave’s transmit

buffer not being updated

BC [3:0] rh Bit Count FieldShift counter is updated with every shifted bit.Do not write to!!!





The shift register of the SSC is connected to both, the transmit lines and the receive linesvia the pin control logic (see block diagram in Figure 20-2). Transmission and receptionof serial data are synchronized and take place at the same time, i.e. the same numberof transmitted bits is also received.

To prepare for a transfer, the transmit data is written into the Transmit Buffer (SSCx_TB)by software. It is moved to the shift register as soon as this is empty. An SSC master(CON.MS = 1) immediately begins transmitting, while an SSC slave (CON.MS = 0) willwait for an active shift clock. When the transfer starts, the busy flag CON.BSY is set andthe Transmit Interrupt Request line TIRQ will be activated to indicate that registerSSCx_TB may be reloaded again. When the programmed number of bits (2 … 16) hasbeen transferred, the contents of the shift register are moved to the Receive BufferSSCx_RB and the Receive Interrupt Request line RIRQ is activated. If no further transferis to take place (SSCx_TB is empty), CON.BSY will be cleared at the same time.Software should not modify CON.BSY, as this flag is hardware controlled.

Note: Only one SSC can be master at a given time in a serial system.

The transfer of serial data bits can be programmed in many respects:

• The data width can be specified from 2 bits to 16 bits• A transfer may start with either the LSB or the MSB• The shift clock may be idle low or idle high• The data bits may be shifted with the leading edge or the trailing edge of the shift

clock signal• The baudrate may be set from 306.6 bit/s up to 20 Mbit/s (@ 40 MHz module clock) • The shift clock can be generated (MSCLK) or can be received (SSCLK)

These features allow the adaptation of the SSC to a wide range of applications in whichserial data transfer is required.

The Data Width Selection supports the transfer of frames of any data length, from 2-bit“characters” up to 16-bit “characters”. Starting with the LSB (CON.HB = 0) enablescommunication with SSC devices in Synchronous Mode or with 8051-like serialinterfaces, for example. Starting with the MSB (CON.HB = 1) enables operationcompatible with the SPI interface.

Regardless of the data width selected and whether the MSB or the LSB is transmittedfirst, the transfer data is always right-aligned in registers SSCx_TB and SSCx_RB, withthe LSB of the transfer data in bit 0 of these registers. The data bits are rearranged fortransfer by the internal shift register logic. The unselected bits of SSCx_TB are ignored;the unselected bits of SSCx_RB will not be valid and should be ignored by the receiverservice routine.

The Clock Control allows the adaptation of transmit and receive behavior of the SSC toa variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shiftout transmit data, while the other shift clock edge is used to latch in receive data. Bit PHselects the leading edge or the trailing edge for each function. Bit PO selects the level of




the shift clock line in the idle state. Thus, for an idle-high clock, the leading edge is afalling edge, a 1-to-0 transition (see Figure 20-3).

Figure 20-3 Serial Clock Phase and Polarity Options

20.2.2 Full-Duplex Operation

In a Full-Duplex serial configuration, illustrated in Figure 20-4, the various devices areconnected via three lines. The definition of these lines is always determined by themaster: The line connected to the master’s data output line MTSR is the transmit line;the receive line is connected to its data input line MRST; the shift clock line is SCLK. Onlythe device selected for master operation generates and outputs the shift clock on lineSCLK. All slaves receive this clock; thus, their SCLK pin must be switched to input mode.The output of the master’s shift register is connected to the external transmit line, whichin turn is connected to the slaves’ shift register inputs. The outputs of the slaves’ shiftregister are connected to the external receive line in order to enable the master toreceive the data shifted out of the slaves. The external connections are hard-wired, thefunction and direction of these pins is determined by the master or slave operation of theindividual device.

Note: The shift direction shown in Figure 20-4 applies for MSB-first operation as well asfor LSB-first operation.

When initializing the devices in this configuration, one device must be selected formaster operation while all other devices must be programmed for slave operation.Initialization includes the operating mode of the device’s SSC and also the function ofthe respective port lines.

CON.PO

CON.PH

0 0

0 1

1 0

1 1

MCT05456

Shift ClockSCLK

PinsMTSR/MRST

FirstBit

Latch DataShift Data

Transmit Data LastBit




Figure 20-4 SSC Full-Duplex Configuration

The data output pins MRST of all slave devices are connected together onto the onereceive line in the configuration shown in Figure 20-4. During a transfer, each slaveshifts out data from its shift register. There are two ways to avoid collisions on the receiveline due to different slave data:

• Only one slave drives the line, i.e. enables the driver of its MRST pin. All the otherslaves must have their MRST pins programmed as input so only one slave can putits data onto the master’s receive line. Only receiving data from the master ispossible. The master selects the slave device from which it expects data either byseparate select lines, or by sending a special command to this slave. The selectedslave then switches its MRST line to output until it gets a de-selection signal orcommand.In the configuration depicted in Figure 20-4, Device #2 is the slave which has itsoutput driver enabled as push/pull output. Device #3 is an inactive slave, it needs todisable its output driver by programming the pin to input mode.

• The slaves use their MRST outputs in open-drain mode. This forms a wired-ANDconnection. The receive line needs an external pull-up in this case. Corruption of the

Clock

MCA05457

Master Device #1

Transmit

Receive

Clock

MTSR

SCLK

MRST

Shift Register

Clock

MTSR

SCLK

MRST

Shift Register

Clock

Device #2 Slave

MTSR

SCLK

MRST

Shift Register

Device #3 SlaveSymbols

Input

Push/Pull Output

Open-Drain Output

Tri-Stated = Input




data on the receive line sent by the selected slave is avoided when all slaves notselected for transmission to the master only send ones (1). Because this high level isnot actively driven onto the line, but only held through the pull-up device, the selectedslave can pull this line actively to a low level when transmitting a zero bit. The masterselects the slave device from which it expects data either by separate select lines orby sending a special command to this slave.

After performing the necessary initialization of the SSC, the serial interfaces can beenabled. For a master device, the clock line MSCLK will now go to its programmedpolarity. The output data line MTX will go to either 0 or 1 until the first transfer will start.After a transfer, the data line MTX will always remain at the logic level of the lasttransmitted data bit.

When the serial interfaces are enabled, the master device can initiate the first datatransfer by writing the transmit data into register SSCx_TB. This value is copied into theshift register (assumed to be empty at this time), and the selected first bit of the transmitdata will be placed onto the transmit line MTSR on the next clock from the baudrategenerator (transmission starts only if bit EN = 1). Depending on the selected clockphase, a clock pulse will also be generated on the SCLK line. At the same time, with theopposite clock edge, the master latches and shifts in the data detected at its input lineMRST. This “exchanges” the transmit data with the receive data. Because the clock lineis connected to all slaves, their shift registers will be shifted synchronously with themaster’s shift register, shifting out the data contained in the registers, and shifting in thedata detected at the input line. After the preprogrammed number of clock pulses (via thedata width selection), the data transmitted by the master is contained in all the slaves’shift registers, while the master’s shift register holds the data of the selected slave. In themaster and all slaves, the contents of the shift register are copied into the receive bufferSSCx_RB and the receive interrupt line RIRQ is activated.

A slave device will immediately output the selected first bit (MSB or LSB of the transferdata) at line MRST when the contents of the transmit buffer are copied into the slave’sshift register. Bit BSY is not set until the first clock edge at SCLK appears. The slavedevice will not wait for the next clock from the baudrate generator, as the master does.The reason for this is that, depending on the selected clock phase, the first clock edgegenerated by the master may already be used to clock in the first data bit. Thus, theslave's first data bit must already be valid at this time.

Note: On the SSC, a transmission and a reception takes place at the same time,regardless of whether valid data has been transmitted or received.

Note: The initialization of the CLK pin on the master requires some attention in order toavoid undesired clock transitions, which may disturb the other devices. Before theclock pin is switched to output via the related direction control register, the clockoutput level shall be selected in the control register SSCx_CON and the alternateoutput be prepared via the related ALTSEL register, or the output latch must beloaded with the clock idle level.




20.2.3 Half-Duplex Operation

In a Half-Duplex configuration, only one data line is necessary for both, receiving andtransmitting of data. The data exchange line is connected to both, the MTSR and MRSTpins of each device, the shift clock line is connected to the SCLK pin.

The master device controls the data transfer by generating the shift clock, while the slavedevices receive it. Due to the fact that all transmit and receive pins are connected to theone data exchange line, serial data may be moved between arbitrary stations.

Similar to Full-Duplex mode, there are two ways to avoid collisions on the data exchangeline:

• only the transmitting device may enable its transmit pin driver• the non-transmitting devices use open-drain outputs and send only ones (1s).

Because the data inputs and outputs are connected together, a transmitting device willclock in its own data at the input pin (MRST for a master device, MTSR for a slave). Bythis method, any corruptions on the common data exchange line are detected if thereceived data is not equal to the transmitted data.

Figure 20-5 SSC Half-Duplex Configuration

Clock

MCA05458

Master Device #1Transmit

Clock

MTSR

SCLK

MRST

Shift Register

Clock

MTSR

SCLK

MRST

Shift Register

Clock

Device #2 Slave

MTSR

SCLK

Shift Register

Device #3 SlaveSymbols

Input

Push/Pull Output

Open-Drain Output

Tri-Stated = Input

MRST




20.2.4 Continuous Transfers

When the transmit interrupt request flag is set, it indicates that the transmit bufferSSCx_TB is empty and ready to be loaded with the next transmit data. If SSCx_TB hasbeen reloaded by the time the current transmission is finished, the data is immediatelytransferred to the shift register and the next transmission will start without any additionaldelay. On the data line, there is no gap between the two successive frames. Forexample, two 8-bit transfers would look the same as one 16-bit transfer. This feature canbe used to interface with devices that can operate with or require more than 16 data bitsper transfer. It is just a matter of software, how long a total data frame length can be. Thisoption can also be used to interface to byte-wide and word-wide devices on the sameserial bus, for instance.

Note: Of course, this can happen only in multiples of the selected basic data width,because it would require disabling/enabling of the SSC to reprogram the basicdata width on-the-fly.

20.2.5 Baudrate Generation

The serial channel SSC has its own dedicated 16-bit Baudrate Generator with 16-bitreload capability, facilitating baudrate generation independent of the timers. Figure 20-6shows the baudrate generator of the SSC in more detail.

Figure 20-6 SSC Baudrate Generator

The Baudrate Generator is clocked with the module clock fSSC. The counter countsdownwards. Access to the Baudrate Generator is performed via one register, SSCx_BR,described below.

MCA05459


16-bit CounterfSCLK

2fSSC

fSCLKmax in Master Mode

fSCLKmax in Slave Mode

≤ fSSC / 2

≤ fSSC / 4




Baudrate Timer/Reload Register

The SSC Baudrate Timer/Reload Register SSCx_BR has a double function.

While the SSC is disabled, it serves as the reload register for the baudrate timer. Writingto it loads the timer reload register with the written reload value. Reading returns thecurrent reload value.

While the SSC is enabled, this register reflects the current baudrate timer contents.Writing to this register is not allowed while the SSC is enabled.

Baudrate Calculation

The timer is loaded with the reload value and starts counting immediately when the SSCis enabled. The formulas below calculate either the resulting baudrate for a given reloadvalue, or the required reload value for a given baudrate:

(20.1)

<BR> represents the contents of the reload register, taken as unsigned 16-bit integer;while baudrate is equal to fSCLK as shown in Figure 20-6.

The maximum baudrate that can be achieved when using a module clock of 40 MHz is20 Mbit/s in Master Mode (with <BR> = 0000H) or 10 Mbit/s in Slave Mode (with <BR> =0001H).

Table 20-1 lists some possible baudrates together with the required reload values andthe resulting bit times, assuming a module clock of 40 MHz.

Table 20-1 Typical Baudrates of the SSC (fSSC = 40 MHz)

Reload Value Baudrate (= fSCLK) Deviation

0000H 20 Mbit/s (only in Master Mode) 0.0%

0001H 10 Mbit/s 0.0%

0009H 2 Mbit/s 0.0%

0013H 1 Mbit/s 0.0%

001AH 750 kbit/s -1.25%

0027H 500 kbit/s 0.0%

0063H 200 kbit/s 0.0%

00C7H 100 kbit/s 0.0%

FFFFH 306.6 bit/s 0.0%

BaudratefSSC

2 <BR> 1+( )×---------------------------------------= BG

fSSC

2 Baudrate×------------------------------------ 1–=




20.2.6 Error Detection Mechanisms

The SSC is able to detect four different error conditions. Receive Error and Phase Errorare detected in all modes; Transmit Error and Baudrate Error only apply to Slave Mode.When an error is detected, the respective error flag in register SSCx_CON is set and anerror interrupt request will be generated by activating the EIRQ line (see Figure 20-7).The error interrupt handler may then check the error flags to determine the cause of theerror interrupt. The error flags are not reset automatically but rather must be cleared bysoftware after servicing. This allows servicing of some error conditions via interrupt,while the others may be polled by software.

Note: The error interrupt handler must clear the associated (enabled) error flag(s) toprevent repeated interrupt requests.

Figure 20-7 SSC Error Interrupt Control

A Receive Error (Master or Slave Mode) is detected when a new data frame iscompletely received but the previous data was not read out of the receive buffer registerSSCx_RB. This condition sets the error flag RE and, when enabled via bit REN, the errorinterrupt request line EIRQ. The old data in the receive buffer SSCx_RB will beoverwritten with the new value and is irretrievably lost.

A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module

MCA05460

&

&

&

&

Bits in RegisterCON

>1_Error InterruptRequest EIRQ

TEN

REN

PEN

BEN

TE

RE

PE

BE

ErrorTransmit

ErrorReceive

ErrorPhase

ErrorBaudrate




clock, changes between one cycle before and two cycles after the latching edge of theshift clock signal SCLK. This condition sets the error flag PE and, when enabled via bitPEN, the error interrupt request line EIRQ.

A Baudrate Error (Slave Mode) is detected when the incoming clock signal deviatesfrom the programmed baudrate by more than 100%, i.e. it either is more than double orless than half the expected baudrate. This condition sets the error flag BE and, whenenabled via bit BEN, the error interrupt request line EIRQ. Using this error detectioncapability requires that the slave’s baudrate generator is programmed to the samebaudrate as the master device. This feature detects false, additional or missing, pulseson the clock line (within a certain frame).

Note: If this error condition occurs and bit AREN = 1, an automatic reset of the SSC willbe performed in case of this error. This is done to re-initialize the SSC if too few ortoo many clock pulses have been detected.

A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master(SCLK gets active), but the transmit buffer SSCx_TB of the slave was not updated sincethe last transfer. This condition sets the error flag TE and, when enabled via bit TEN, theerror interrupt request line EIRQ. If a transfer starts while the transmit buffer is notupdated, the slave will shift out the ‘old’ contents of the shift register, which usually is thedata received during the last transfer. This may lead to corruption of the data on thetransmit/receive line in half-duplex mode (open-drain configuration) if this slave is notselected for transmission. This mode requires that slaves not selected for transmissiononly shift out ones; that is, their transmit buffers must be loaded with FFFFH prior to anytransfer.

Note: A slave with push/pull output drivers not selected for transmission will usually haveits output drivers switched off. However, in order to avoid possible conflicts ormisinterpretations, it is recommended to always load the slave's transmit bufferprior to any transfer.

The cause of an error interrupt request (receive, phase, baudrate, transmit error) can beidentified by the error status flags in control register SSCx_CON.

Note: The error status flags TE, RE, PE, and BE, are not reset automatically upon entryinto the error interrupt service routine, but must be cleared by software.




20.2.7 SSC Register Summary

Table 20-2 SSC Module Register Summary

Name Description SSC0 Addresses

Reg. Area

SSC1 Addresses

16-Bit 8-Bit 16-Bit 8-Bit

SSCx_CON Control Register FFB2H D9H SFR FF5EH AFH

SSCx_BR Baudrate Timer Reload Register

F0B4H 5AH ESFR F05EH 2FH

SSCx_TB Transmit Buffer Register F0B0H 58H ESFR F05AH 2DH

SSCx_RB Receive Buffer Register F0B2H 59H ESFR F05CH 2EH

SSCx_TIC Transmit Interrupt Control Register

FF72H B9H SFR/ESFR

F1AAH D5H

SSCx_RIC Receive Interrupt Control Register

FF74H BAH SFR/ESFR

F1ACH D6H

SSCx_EIC Error Interrupt Control Register

FF76H BBH SFR/ESFR

F1AEH D7H




20.2.8 Port Configuration Requirements

Table 20-3 shows the required register setting to configure the IO lines of the SSCmodules for master or slave mode operation.

Note: The direction control bits in registers DP3 or DP1H must be set or cleared bysoftware depending on the mode of operation selected (master or slave mode).They are not controlled automatically by the SSC modules.

Table 20-3 SSC0/SSC1 IO Selection and Setup

Module Mode Port Lines Alternate Select Register

Direction and Port Output Register

IO

SSC0 Master P3.8 / MRST0 ALTSEL0P3.P8 = 1 DP3.P8 = 0 Input

P3.9 / MTSR0 ALTSEL0P3.P9 = 1 DP3.P9 = 1and P3.P9 = 1

Output

P3.13 / SCLK0 ALTSEL0P3.P13 = 1 DP3.P13 = 1and P3.P13 = 1

Output

Slave P3.8 / MRST0 ALTSEL0P3.P8 = 1 DP3.P8 = 1and P3.P8 = 1

Output

P3.9 / MTSR0 ALTSEL0P3.P9 = 1 DP3.P9 = 0 Input

P3.13 / SCLK0 ALTSEL0P3.P13 = 1 DP3.P13 = 0 Input

SSC1 Master P1H.1 / MRST1 ALTSEL0P1H.P1 = 1 DP1H.P1 = 0 Input

P1H.2 / MTSR1 ALTSEL0P1H.P2 = 1 DP1H.P2 = 1 Output

P1H.3 / SCLK1 ALTSEL0P1H.P3 = 1 DP1H.P3 = 1 Output

Slave P1H.1 / MRST1 ALTSEL0P1H.P1 = 1 DP1H.P1 = 1 Output

P1H.2 / MTSR1 ALTSEL0P1H.P2 = 1 DP1H.P2 = 0 Input

P1H.3 / SCLK1 ALTSEL0P1H.P3 = 1 DP1H.P3 = 0 Input




20.3 Interfaces of the SSC Modules

In the XC164 the SSC modules are connected to IO ports and other internal modulesaccording to Figure 20-8 and Figure 20-9.

The input/output lines of SSC0 are connected to pins of Ports P3, while the input/outputlines of SSC1 are connected to pins of Ports P1H. The three interrupt request lines ofeach module are connected to the Interrupt Control Block.

Clock control and emulation control of the SSC Module is handled by the System ControlUnit, SCU.

Figure 20-8 SSC0 Module Interfaces

Figure 20-9 SSC1 Module Interfaces

SSC0Module

MCA05461

Port P3Control

SystemControl

Unit (SCU)SSC0DIS

fSSC


SSC0_TIRQ

SSC0_RIRQ

SSC0_EIRQ

P3.9/MTSR0

P3.8/MRST0MTX

MRX

STX

SRX

MSCLK

SSCLK P3.13/SCLK0

SSC1Module

MCA05462

Port P1HControl

SystemControl

Unit (SCU)SSC1DIS

fSSC


SSC1_TIRQ

SSC1_RIRQ

SSC1_EIRQ

P1H.2/MTSR1

P1H.1/MRST1MTX

MRX

STX

SRX

MSCLK

SSCLK P1H.3/SCLK1



TwinCAN Module

21 TwinCAN Module

21.1 Kernel Description

21.1.1 Overview

The TwinCAN module contains two Full-CAN nodes operating independently orexchanging data and remote frames via a gateway function. Transmission and receptionof CAN frames is handled in accordance to CAN specification V2.0 part B (active). Eachof the two Full-CAN nodes can receive and transmit standard frames with 11-bitidentifiers as well as extended frames with 29-bit identifiers.

Both CAN nodes share the TwinCAN module’s resources in order to optimize the CANbus traffic handling and to minimize the CPU load. The flexible combination of Full-CANfunctionality and FIFO architecture reduces the efforts to fulfill the real-time requirementsof complex embedded control applications. Improved CAN bus monitoring functionalityas well as the increased number of message objects permit precise and comfortableCAN bus traffic handling.

Depending on the application, each of the 32 message objects can be individuallyassigned to one of the two CAN nodes. Gateway functionality allows automatic dataexchange between two separate CAN bus systems, which reduces CPU load andimproves the real time behavior of the entire system.

The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and areprogrammable up to a data rate of 1 MBaud. A pair of receive and transmit pins connecteach CAN node to a bus transceiver.

Features

• CAN functionality according to CAN specification V2.0 B active.• Dedicated control registers are provided for each CAN node.• A data transfer rate up to 1 MBaud is supported.• Flexible and powerful message transfer control and error handling capabilities are

implemented.• Full-CAN functionality: 32 message objects can be individually

– assigned to one of the two CAN nodes,– configured as transmit or receive object,– participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm,– setup to handle frames with 11-bit or 29-bit identifiers,– provided with programmable acceptance mask register for filtering,– monitored via a frame counter,– configured to Remote Monitoring Mode.

• Up to eight individually programmable interrupt nodes can be used.• CAN Analyzer Mode for bus monitoring is implemented.

User’s Manual 21-1 V2.1, 2004-03TwinCAN_X41, V2.1


TwinCAN Module

Figure 21-1 General Block Diagram of the TwinCAN Module

The CAN kernel (Figure 21-2) is split into

• A global control shell, subdivided into the initialization logic, the global control andstatus logic and the interrupt request compressor.– The initialization logic sets up all submodules after power-on or reset. After

finishing the initialization of the node control logic and its associated messageobjects, the respective CAN node is synchronized with the connected CAN bus.

– The global control and status logic informs the CPU about pending object transmitand receive interrupts and about the recent transfer history.

– The interrupt request compressor condenses the interrupt requests from72 sources, belonging to CAN node A and B, to 8 interrupt nodes.

• A message buffer unit, containing the message buffers, the FIFO buffermanagement, the gateway control logic and a message-based interrupt requestgeneration unit.– The message buffer unit stores up to 32 message objects of 8 bytes maximum

data length. Each object has an identifier and its own set of control and status bits.After initialization, the message buffer unit can handle reception and transmissionof data without CPU supervision.

– The FIFO buffer management stores the incoming and outgoing messages in acircular buffer and determines the next message to be processed by the CANcontroller.

– The gateway control logic transfers a message from CAN node A to CAN node Bor vice versa.

– The interrupt request generation unit indicates message-specifically the receptionor transmission of an object.

TwinCAN Module Kernel

MCB05471

PortControl

TxDCA

RxDCA

TxDCB

RxDCB

CANNode A

CANNode B

CANMessage Object Buffer

TwinCAN Control

ClockControl

fCAN

InterruptControl

AddressDecoder

TwinCAN Control



TwinCAN Module

• Two separate CAN nodes, subdivided into a bit stream processor, a bit timing controlunit, an error handling logic, an interrupt request generation unit and a node controllogic:– The bit stream processor performs data, remote, error and overload frames

according to the ISO-DIS 11898 standard. The serial data flow between the CANbus line, the input/output shift register and the CRC register is controlled as wellas the parallel data flow between the I/O shift register and the message buffer unit.

– The bit timing control unit defines the sampling point in respect to propagation timedelays and phase shift errors and performs the resynchronization.

– The error handling control logic manages the receive and the transmit errorcounter. According the contents in both timers, the CAN controller is set into anerror-active, error-passive or bus-off state.

– The interrupt request generation unit signals globally the successful end of amessage transmit or receive operation, all kinds of transfer problems like bitstuffing errors, format, acknowledge, CRC or bit state errors, every change of theCAN bus warning level or of the bus-off state.

– The node control logic enables and disables the node specific interrupt sources,enters the CAN analyzer mode and administrates a global frame counter.

Figure 21-2 Detailed Block Diagram of the TwinCAN Kernel

MCB05472

Interrupt RequestCompressor

Global Status andControl Logic Initialization Logic

TwinCAN Conrtol

FIFO ControlInterrupt RequestGeneration Gateway Control

Message Object Buffers

Interrupt RequestGeneration

Node AControlLogic Error Handling

Bit Timing Control

Bit StreamProcessor

To CAN Bus A

Interrupt RequestGeneration

Error Handling

Bit Timing Control

Bit StreamProcessor

To CAN Bus B

Node BControlLogic



TwinCAN Module

21.1.2 TwinCAN Control Shell

21.1.2.1 Initialization Processing

After an external hardware reset or while it is bus-off, the respective CAN controller nodeis logically disconnected from the associated CAN bus and does not participate in anymessage transfer. This is indicated by the ACR/BCR control register bit INIT = ‘1’, whichis automatically set in case of a reset or while the CAN node is bus-off. Furthermore, theCAN node will be disconnected by setting bit INIT to ‘1’ via software. While INIT is active,all message transfers between the affected CAN node controller and its associated CANbus are stopped and the bus output pin (TXDC) is held on ‘1’ level (recessive state).

After an external hardware reset, all control and message object registers are reset totheir associated reset values. During the bus-off-state or after a write access to registerACR/BCR with INIT = ‘1’, all respective control and message object registers hold theircurrent values (except the error counters).

Resetting bit INIT to ‘0’ without being in the bus-off-state starts the synchronizationsequence (= connection to the CAN bus), which has to monitor at least one bus-idleevent (11 consecutive ‘recessive’ bits) on the associated CAN bus before the node isallowed to take part in CAN traffic again.

During the bus-off recovery sequence:

• The receive and the transmit error counter within the error handling logic are reset.• 128 bus-idle events (11 consecutive ‘recessive’ bits) have to be detected, before the

synchronization sequence can be initiated. The monitoring of the bus idle events isimmediately started by hardware after entering the bus-off state. The number ofalready detected bus-idle events is counted and indicated by the receive errorcounter.

• The reconnect procedure tests bit INIT by hardware after 128 bus-idle events. If INITis still set, the affected CAN node controller waits until INIT is cleared and at least onebus-idle event is detected on the CAN bus, before the node takes part in CAN trafficagain. If INIT has been already cleared, the message transfer between the affectedCAN node controller and its associated CAN bus is immediately enabled.



TwinCAN Module

21.1.2.2 Interrupt Request Compressor

The CAN module is equipped with 32 × 2 message object specific interrupt requestsources and 2 × 4 node control interrupt request sources. A request compressorcondenses these 72 sources to 8 CAN interrupt nodes reporting the interrupt requestsof the CAN module. Each request source is provided with an interrupt node pointer,selecting the interrupt node to start the associated service routine in order to increaseflexibility in interrupt processing. Each of the 8 CAN interrupt nodes can trigger anindependent interrupt routine with its own interrupt vector and its own priority.

Figure 21-3 Interrupt Node Pointer and Interrupt Request Compressor

Note: All interrupts are event-oriented. The event sets the corresponding indication flagand can generate an interrupt to the system. An interrupt event occurring while itscorresponding indication flag is still set, can generate a new interrupt.

MCA05473

>1_

RequestCompressor

CAN InterruptNode 0

To InterruptController

Interrupt Node Pointerof Request Source k

InterruptRequest Source k

>1_

CAN InterruptNode 7

To InterruptController

Interrupt Node Pointerof Request Source n

InterruptRequest Source n



TwinCAN Module

21.1.2.3 Global Control and Status Logic

The receive interrupt pending register RXIPND contains 32 individual flags indicating apending receive interrupt for the associated message objects. Flag RXIPNDn is set byhardware if the corresponding message object has correctly received a data or remoteframe and the correlated interrupt request generation has been enabled by RXIEn = ‘10’.RXIPNDn can be cleared by software by resetting bit INTPNDn in the correspondingmessage object control register MSGCTRn.

The transmit interrupt pending register TXIPND has a similar functionality as theRXIPND register and provides identical information about pending transmit interrupts.



TwinCAN Module

21.1.3 CAN Node Control Logic

21.1.3.1 Overview

Each node is equipped with an individual node control logic configuring the globalbehavior and providing status information.

The configuration mode is activated when the ACR/BCR register bit CCE is set to ‘1’.This mode allows modifying the CAN bit timing parameters and the error counterregisters.

The CAN analyzer mode is activated when bit CALM in control register ACR/BCR is setto ‘1’. In this operation mode, data and remote frames are monitored without an activeparticipation in any CAN transfer (CAN transmit pin is held on recessive level). Incomingremote frames are stored in a corresponding transmit message object, while arrivingdata frames are saved in a matching receive message object.

In CAN analyzer mode, the entire configuration information of the received frame isstored in the corresponding message object and can be evaluated by the CPUconcerning their identifier, XTD bit information and data length code. If the remotemonitoring mode is active by RMM = ‘1’, this information is also available for receivedremote frames. Incoming frames are not acknowledged and no error frames aregenerated. Neither remote frames are answered by the corresponding data frame nordata frames can be transmitted by setting TXRQ, if CAN analyzer mode is enabled.Receive interrupts are generated (if enabled) for all correctly received frames and therespective remote pending RMTPNDn is set in case of received remote frames.

The node specific interrupt configuration is also defined by the node control logic via theACR/BCR register bits SIE, EIE and LECIE:

• If control bit SIE is set to ‘1’, a status change interrupt occurs when the ASR/BSRregister has been updated (by each successfully completed message transfer).

• If control bit EIE is set to ‘1’, an error interrupt is generated when a bus-off conditionhas been recognized or the error warning level has been exceeded or underrun.

• If control bit LECIE is set to ‘1’, a last error code interrupt is generated when an errorcode is set in bitfield LEC in the status registers ASR or BSR.

The status register (ASR/BSR) provides an overview about the current state of therespective TwinCAN node:

• Flag TXOK is set when a message has been transmitted successfully andacknowledged by at least one other CAN node,

• flag RXOK indicates an error-free reception of a CAN bus message,• bitfield LEC indicates the last error occurred on the CAN bus. Stuff, form, and CRC

errors as well as bus arbitration errors (Bit0, Bit1) are reported,• bit EWRN is set when at least one of the error counters in the error handling logic has

reached the error warning limit (default value 96),



TwinCAN Module

• bit BOFF is set when the transmit error counter exceeded the error limit of 255 andthe respective CAN node controller has been logically disconnected from theassociated CAN bus.

The CAN frame counter can be used to check the transfer sequence of message objectsor to obtain information about the time instant, a frame has been transmitted or receivedfrom the associated CAN bus. CAN frame counting is performed by a 16-bit counter,which is controlled by register AFCR/BFCR. Bitfield CFCMD defines the operation modeand the trigger event incrementing the frame counter:

• After correctly transmitted frames,• after correctly received frames,• after a foreign frame on the CAN bus (not transmitted/received by the CAN node

itself),• at beginning of a new bit time.

The captured frame counter value is copied to the CFCVAL field of the associatedMSGCTRn register at the end of the monitored frame transfer. Flag CFCOV is set on aframe counter overflow condition (FFFFH to 0000H) and an interrupt request is generatedif bit CFCIE is set to ‘1’.



TwinCAN Module

21.1.3.2 Timing Control Unit

According to ISO-DIS 11898 standard, a CAN bit time is subdivided into differentsegments (Figure 21-4). Each segment consists of multiples of a time quantum tq. Themagnitude of tq is adjusted by the bitfield BRP and by bit DIV8X, both controlling thebaud rate prescaler (see bit timing register ABTR/BBTR). The baud rate prescaler isdriven by the CAN module clock fCAN.

Figure 21-4 CAN Bus Bit Timing Standard

The synchronization segment (TSync) allows a phase synchronization betweentransmitter and receiver time base. The synchronization segment length is always 1 tq.The propagation time segment (TProp) takes into account the physical propagation delayin the transmitter output driver, on the CAN bus line and in the transceiver circuit. For aworking collision detect mechanism, TProp has to be two times the sum of all propagationdelay quantities rounded up to a multiple of tq. The phase buffer segments 1 and 2 (Tb1,Tb2) before and after the signal sample point are used to compensate a mismatchbetween transmitter and receiver clock phase detected in the synchronization segment.

The maximum number of time quanta allowed for resynchronization is defined by bitfieldSJW in bit timing register ABTR/BBTR. The propagation time segment and the phasebuffer segment 1 are combined to parameter TSeg1, which is defined by the value TSEG1in the respective bit timing register ABTR/BBTR. A minimum of 3 time quanta isrequested by the ISO standard. Parameter TSeg2, which is defined by the value of TSEG2in the bit timing register ABTR/BBTR, covers the phase buffer segment 2. A minimum of2 time quanta is requested by the ISO standard. According ISO standard, a CAN bit time,calculated as the sum of TSync, TSeg1 and TSeg2, must not fall below 8 time quanta.

Note: The access to bit timing register ABTR/BBTR is only enabled if bit CCE in controlregister ACR/BCR is set to ‘1’.

MCT05474

Sample Point Transmit Point

Sync.Segment

1 Bit Time

1 Time Quantum (tq)

TSync

TProp Tb1 Tb1

TSeg1 TSeg2



TwinCAN Module

Calculation of the Bit Time

tq = (BRP + 1) / fCAN, if DIV8X = ‘0’

= (BRP + 1) / 8 × fCAN, if DIV8X = ‘1’

TSync = 1 tq

TSeg1 = (TSEG1 + 1) × tq (min. 3 tq)

TSeg2 = (TSEG2 + 1) × tq (min. 2 tq)

bit time = TSync + TSeg1 + TSeg2 (min. 8 tq)

To compensate phase shifts between clocks of different CAN controllers, the CANcontroller has to synchronize on any edge from the recessive to the dominant bus level.If the hard synchronization is enabled (at the start of frame), the bit time is restarted atthe synchronization segment. Otherwise, the resynchronization jump width TSJW definesthe maximum number of time quanta a bit time may be shortened or lengthened by oneresynchronization. The value of SJW is programmed in the ABTR/BBTR registers.

TSJW = (SJW + 1) × tq

TSeg1 ≥ TSJW + Tprop

TSeg2 ≥ TSJW

The maximum relative tolerance for fCAN depends on the phase buffer segments and theresynchronization jump width.

dfCAN ≤ min (Tb1, Tb2) / 2 × (13 × bit time - Tb2) AND

dfCAN ≤ TSJW / 20 × bit time

Calculation of the Baudrate

Baudrate = fCAN / ((BRP + 1) × (1 + TSeg1 + TSeg2))



TwinCAN Module

21.1.3.3 Bitstream Processor

Based on the objects in the message buffer, the bitstream processor generates theremote and data frames to be transmitted via the CAN bus. It controls the CRC generatorand adds the checksum information to the new remote or data frame. After including thestart of frame bit SOF and the end of frame field EOF, the bitstream processor starts theCAN bus arbitration procedure and continues with the frame transmission when the buswas found in idle state. While the data transmission is running, the bitstream processormonitors continuously the I/O line. If (outside the CAN bus arbitration phase or theacknowledge slot) a mismatch is detected between the voltage level on the I/O line andthe logic state of the bit currently sent out by the transmit shift register, a last errorinterrupt request is generated and the error code is indicated by bitfield LEC in statusregister ASR/BSR.

An incoming frame is verified by checking the associated CRC field. When an error hasbeen detected, the last error interrupt request is generated and the associated error codeis presented in status register ASR/BSR. Furthermore, an error frame is generated andtransmitted on the CAN bus. After decomposing a faultless frame into identifier and dataportion, the received information is transferred to the message buffer executing remoteand data frame handling, interrupt generation and status processing.

21.1.3.4 Error Handling Logic

The error handling logic is responsible for the fault confinement of the CAN device. Itstwo counters, the receive error counter and the transmit error counter (control registersAECNT, BECNT), are incremented and decremented by commands from the bit streamprocessor. If the bit stream processor itself detects an error while a transmit operation isrunning, the transmit error counter is incremented by 8. An increment of 1 is used, whenthe error condition was reported by an external CAN node via an error frame generation.For error analysis, the transfer direction of the disturbed message and the node,recognizing the transfer error, are indicated in the control registers AECNT, BECNT.According to the values of the error counters, the CAN controller is set into the stateserror-active, error-passive or bus-off.

The CAN controller is in error-active state, if both error counters are below the error-passive limit of 128. It is in error-passive state, if at least one of the error counters equalsor exceeds 128.

The bus-off state is activated if the transmit error counter equals or exceeds the bus-offlimit of 256. This state is reported by flag BOFF in the ASR/BSR status register. Thedevice remains in this state, until the bus-off recovery sequence is finished. Additionally,there is the bit EWRN in the ASR/BSR status register, which is set if at least one of theerror counters equals or exceeds the error warning limit defined by bitfield EWRNLVL inthe control registers AECNT, BECNT. Bit EWRN is reset if both error counters fall belowthe error warning limit again.



TwinCAN Module

21.1.3.5 Node Interrupt Processing

Each CAN node is equipped with 4 interrupt sources supporting the

• global transmit/receive logic,• CAN frame counter,• error reporting system.

Figure 21-5 Node Specific Interrupt Control

If enabled by bit SIE = ‘1’ in the ACR/BCR register, the global transmit/receive logicgenerates an interrupt request, if the node status register (ASR/BSR) is updated afterfinishing a faultless transmission or reception of a message object. The associatedinterrupt node pointer is defined by bitfield TRINP in control register AGINP/BGINP.

An error is reported by a last error code interrupt request, if activated by LECIE = ‘1’ inthe ACR/BCR register. The corresponding interrupt node pointer is defined by bitfieldLECINP in control register AGINP/BGINP.

The CAN frame counter creates an interrupt request upon an overflow, when theAFCR/BFCR control register bit CFCIE is set to ‘1’. Bitfield CFCINP, located also in theAGINP/BGINP control register, selects the corresponding interrupt node pointer.

The error logic monitors the number of CAN bus errors and sets or resets the errorwarning bit EWRN according to the value in the error counters. If bit EIE in control

CANFrame

Counter

GlobalCAN

Transmitand

ReceiveLogic

MCA05475

>1_

LECIESIE

>1_

EIE

CFCIE

TRINP

LECINP

EINP

CFCINP

TXOK

RXOK

LEC

EWRN

BOFF

CFCOV



TwinCAN Module

register ACR/BCR is set to ‘1’, an interrupt request is generated on any modification ofbits EWRN and BOFF. The associated interrupt node pointer is defined by bitfield EINPin control register AGINP/BGINP.

21.1.3.6 Message Interrupt Processing

Each message object is equipped with 2 interrupt request sources indicating thesuccessful end of a message transmission or reception.

Figure 21-6 Message Specific Interrupt Control

The message based transfer interrupt sources are enabled, if bit TXIE or RXIE in theassociated message control register MSGCTRn are set to ‘10’. The associated interruptnode pointers are defined by bitfields RXINP and TXINP in message configurationregister MSGCFGn.

21.1.3.7 Interrupt Indication

The AIR/BIR register provides an INTID bitfield indicating the source of the pendinginterrupt request with the highest internal priority (lowest message object number). Thetype of the monitored interrupt requests, taken into account by bitfield INTID, can beselected by registers AIMR0/AIMR4 and BIMR0/BIMR4 containing a mask bit for eachinterrupt source. If no interrupt request is pending, all bits of AIR/BIR are cleared. Theinterrupt requests INTPNDn have to be cleared by software.

MCA05476

>1_INTPND

RXIPND

TXIPNDTXIE

RXIE

Transmit

Receive

Correct Transfer ofMessage Object n

TXINP

RXINP



TwinCAN Module

Figure 21-7 INTID Mask for Global Interrupt Request Sources

Registers AIMR0/4 and BIMR0/4 contain a mask bit for each interrupt source(AIMR0/BIMR0 for message specific interrupt sources and AIMR4/BIMR4 for the nodespecific interrupt sources). If a mask bit is reset, the corresponding interrupt source is nottaken into account for the generation of the INTID value.

Figure 21-8 INTID Mask for Message Interrupt Request Sources

MCA05477

GlobalCAN

Transmitand

ReceiveLogic >1_

TXOK

RXOK

LEC

EWRN

BOFF

>1_

IMC34 IMC33 IMC32

>1_

INTD = 1

Interrupt Request Source INTID ValueIMR4 Mask Register

MCA05478

INTID = n + 2

AIRInterrupt PendingRegister

INTID = n + 2

IMCn

IMCn

INTPNDn

BIRInterrupt PendingRegister

AIMR0Mask Register

BIMR0Mask Register

Message ControlRegister forObject n



TwinCAN Module

21.1.4 Message Handling Unit

A message object is the basic information unit exchanged between the CPU and theCAN controller. 32 message objects are provided by the internal CAN memory. Each ofthese objects has an identifier, its own set of control and status bits and a separate dataarea. Each message object covers 32 bytes of internal memory subdivided into controlregisters and data storage as illustrated in Figure 21-9.

Figure 21-9 Structure of a Message Object

In normal operation mode, each message object is associated with one CAN node. Onlyin shared gateway mode, a message object can be accessed by both CAN nodes(according to the corresponding bitfield NODE).

In order to be taken into account by the respective CAN node control logic, the messageobject must be declared valid in its associated message control register (bit MSGVAL).

When a message object is initialized by the CPU, bitfield MSGVAL in message controlregister MSGCTRn should be reset, inhibiting a read or write access of the CAN nodecontroller to the associated register and data buffer storage. Afterwards, the messageidentifier and operation mode (transmit, receive) must be defined. If a successfultransmission and/or reception of a message object should be followed by the executionof an interrupt service routine, the respective bitfields TXIE and RXIE have to be set andthe interrupt pending indicator (bitfield INTPND) should be reset.

If the automatic response of an incoming remote frame with matching identifier is notrequested, the respective transmission message object should be configured withCPUUPD = ‘10’.

As soon as bitfield MSGVAL is set to ‘10’, the respective message object is operable andtaken into account by the associated CAN node controller.

MCA05479

+18H

+14H

+10H

+0CH

+08H

+00H

Message Object n

Module Offset + 300H + n*20H

FIFO/Gateway ControlMessage Configuration

Message ControlAcceptance Mask

Arbitration (Identifier)

Data



TwinCAN Module

21.1.4.1 Arbitration and Acceptance Mask Register

The arbitration register MSGARn is used to filter the incoming messages and to providethe outgoing messages with an identifier. The acceptance mask register MSGAMRnmay be used to disable some identifier bits of an incoming message for the acceptancetest.

The identifier of a received message is compared (bitwise XOR) to the identifiers of allmessage objects stored in the internal CAN controller memory. The compare operationstarts at object 0 and takes into account all objects with

• a valid message flag (MSGVAL = ‘10’),• a suitable NODE declaration (register MSGCFGn),• a cleared DIR control bit (receive message object) for data frame reception,• DIR = ‘1’ (transmit message object) for remote frame reception,• a matching identifier length declaration (XTD = ‘1’ marks extended 29-bit identifiers,

XTD = ‘0’ indicates standard 11 bit identifiers).

The result of the compare operation is bit-by-bit ANDED with the contents of theacceptance mask register (Figure 21-10). If concordance is detected, the receivedmessage is stored into the CAN controller’s message object. The compare operation isfinished after analyzing message object 31.

Note: Depending on the allocated identifiers and the corresponding mask registercontents, multiple message objects may fulfill the selection criteria describedabove. In this case, the received frame is stored in the fitting message object withthe lowest message number.

Figure 21-10 Acceptance Filtering for Received Message Identifiers

MCA05480

Acceptance Maskof Message Object n

Result = 0:ID of the received framefits to message object nResult > 0:ID of the received frame doesnot fit to message object n

=1

&

Identifierof Message Object n

Identifierof Received Frame Bitwise

XOR

BitwiseAND

‘0’ = Bit Match‘1’ = No Match



TwinCAN Module

21.1.4.2 Handling of Remote and Data Frames

Message objects can be set up for transmit or receive operation according to theselected value for control bit DIR. The impact of the message object type on theassociated CAN node controller concerning the generation or reception of remote anddata frames is illustrated in Table 21-1.

Table 21-1 Handling of Remote and Data Frames

A transmission request (TXRQ = ‘10’) for this message object generates …

If a data frame with matching identifier is received …

If a remote frame with matching identifier is received …

Receive Object (receives data frames, transmits remote frames, control bit DIR = ‘0’)

… a remote frame.The requested data frame is stored in this message object on reception.

… the data frame is stored in this message object.

… the remote frame is NOT taken into account.

Transmit Object (transmits data frames, receives remote frames, control bit DIR = ‘1’)

… a data frame based upon the information stored in this message object.

… the data frame is NOT stored.

… the remote frame is stored in this message object and RMTPND and TXRQ are set to ‘10’.A data frame, based upon the information stored in this message object, is automatically generated if CPUUPD is set to ‘01’.



TwinCAN Module

21.1.4.3 Handling of Transmit Message Objects

A message object with direction flag DIR = ‘1’ (message configuration registerMSGCFGn) is handled as transmit object.

All message objects with bitfield MSGVAL = ‘10’ are operable and taken into account bythe CAN node controller operation described below.

During the initialization phase, the transmit request bitfield (TXRQ), the new informationbitfield (NEWDAT) should be reset to ‘01’ and the update in progress by CPU bitfield(CPUUPD) in register MSGCTRn should be reset to ‘10’. The message bytes to betransmitted are written into the data partition of the message object (MSGDRn0,MSGDRn4). The number of message bytes to be transmitted has to be written to bitfieldDLC in register MSGCFGn. The selected identifier has to be written to register MSGARn.Then, bitfield NEWDAT in register MSGCTRn should be set to ‘10’ and bitfield CPUUPDshould be reset to ‘01’ by the CPU.

When the remote monitoring mode is enabled (RMM = ‘1’ in MSGCFGn), the identifierand the data length code of a received remote frame will be copied to the correspondingtransmit message object, if a matching identifier was found during the compare andmask operation with all CAN message objects. The copy procedure may change theidentifier in the transmit message object, if some MSGAMRn mask register bits havebeen set to ‘0’.

As long as bitfield MSGVAL in register MSGCTRn is set to ‘10’, the reception of a remoteframe with matching identifier automatically sets bitfield TXRQ to ‘10’. Simultaneously,bitfield RMTPND in register MSGCTRn is set to ‘10’ in order to indicate the reception ofan accepted remote frame. Alternatively, TXRQ may be set by the CPU via a writeaccess to register MSGCTRn. If the transmit request bitfield TXRQ is found at ‘10’ (whileMSGVAL = ‘10’ and CPUUPD = ‘01’) by the appropriate CAN controller node, a dataframe based upon the information stored in the respective transmit message object isgenerated and automatically transferred when the associated CAN bus is idle.

If bitfield CPUUPD in register MSGCTRn is set to ‘10’, the automatic transmission of amessage object is prohibited and flag TXRQ is not evaluated by the respective CANnode controller. The CPU can release the pending transmission by clearing CPUUPD.This allows the user to listen on the bus and to answer remote frames under softwarecontrol.

When the data partition of a transmit message object has to be updated by the CPU,bitfield CPUUPD in message control register MSGCTRn should be set to ‘10’, inhibitinga read or write access of the associated CAN node controller. If a remote frame with anaccepted identifier arrives during the update of a message object’s data storage, bitfieldsTXRQ and RMTPND are automatically set to ‘10’ and the transmission of thecorresponding data frame is pending until CPUUPD is reset again.



TwinCAN Module

If several valid message objects with pending transmission request are noticed by theassociated CAN node controller, the contents of the message object with the lowestmessage number is transmitted first.

Bitfield NEWDAT is internally reset by the respective CAN node controller when thecontents of the selected message object’s data registers is copied to the bitstreamprocessor. Bitfields RMTPND and TXRQ are automatically reset when the messageobject has been successfully transmitted.

The captured value of the frame counter is copied to bitfield CFCVAL in registerMSGCTRn and a transmit interrupt request is generated (INTPNDn and TXIPNDn areset) if enabled by TXIE = ‘10’. Then the Frame Counter is incremented by one if enabledin control register AFCR/BFCR.

When a data frame with matching identifier is received, it is ignored by the respectivetransmit object and not indicated by any interrupt request.



TwinCAN Module

Figure 21-11 Handling of Message Objects with Direction = ‘1’ = Transmit by the CAN Controller Node Hardware

MCA05481

MatchingRemote Frame

Received?

NEWDAT := ‘01’Copy Message to

Bitstream Processor

Send Message

TransmissionSuccessful

?

no

yes

TXRQ = ‘10’CPUUPD = ‘01’

no

Bus Free?

yes no

yes

TXRQ := ‘10’RMTPND := ‘10’

RXIE := ‘10’

yes

INTPND := ‘10’

NEWDAT = ‘10’

yes

no

TXIE = ‘10’

yes

no

TXRQ := ‘01’RMTPND := ‘01’

yes

INTPND := ‘10’

no

no

‘01’ : Reset‘10’ : Set



TwinCAN Module

21.1.4.4 Handling of Receive Message Objects

A message object with direction flag DIR = ‘0’ (message configuration registerMSGCFGn) is handled as receive object.

In the initialization phase, the transmit request bitfield (TXRQ), the message lost bitfield(MSGLST) and the NEWDAT bitfield in register MSGCTR should be reset.

All message objects with bitfield MSGVAL = ‘10’ are operable and taken into account bythe CAN node controller operation described below.

When a data frame has been received, the new information is stored in the data partitionof the message object (MSGDRn0, MSGDRn4) and the bitfield DLC in registerMSGCFG is updated with the number of received bytes. Unused message bytes will beoverwritten by non-specified values. If the NEWDAT bitfield in register MSGCTR is stillset, the CAN controller assumes an overwrite of the previously stored message andsignals a data loss by setting bitfield MSGLST. In any case, bitfield NEWDAT isautomatically set to ‘10’ reporting an update of the data register by the CAN controller.The captured value of the frame counter is copied to bitfield CFCVAL in registerMSGCTRn and a receive interrupt request is generated (INTPNDn and RXIPNDn areset) if enabled by RXIE = ‘10’. Then the frame counter is incremented by one if enabledin control register AFCR/BFCR.

When a receive object is marked to be transmitted (TXRQ = ‘10’), bit MSGLST changesautomatically to CPUUPD. If CPUUPD is reset to ‘01’, the CAN controller generates aremote frame which is emitted to the other communication partners via CAN bus. In caseof CPUUPD = ‘10’, the remote frame transfer is prohibited until the CPU releases thepending transmission by resetting CPUUPD to ‘01’. RMTPND and TXRQ areautomatically reset, when the remote frame has been successfully transmitted. Finally,a transmit interrupt request is generated if enabled by TXIE = ‘10’.

When a remote frame with matching identifier is received, it is not answered and notindicated by an interrupt request.



TwinCAN Module

Figure 21-12 Handling of Message Objects with Direction = ‘0’ = Receive by the CAN Controller Node Hardware

MCA05482

MatchingData FrameReceived

?

Load Identifier andControl Bits into

Bitstream Processor

Send Remote Frame

TransmissionSuccessful

?

no

yes

TXRQ = ‘10’CPUUPD = ‘01’

no

Bus Idle?

yes no

yes

RXIE := ‘10’

yes

INTPND := ‘10’

yes

TXIE = ‘10’no

TXRQ := ‘01’RMTPND := ‘01’

yes

INTPND := ‘10’

no

no

NEWDAT := ‘01’

NEWDAT = ‘10’

no

MSGLST := ‘10’

yes

Store MessageNEWDAT := ‘10’

TXRQ := ‘01’RMTPND := ‘01’

‘01’ : Reset‘10’ : Set



TwinCAN Module

21.1.4.5 Single Data Transfer Mode

The single data transfer mode is a useful feature in order to broadcast data over the CANbus without unintended doubling of information. The single data transfer mode isselected via bit SDT in the FIFO/Gateway control register MSGFGCRn.

Each received data frame with matching identifier is automatically stored in thecorresponding receive message object if MSGVAL is set to ‘10’. When data framesaddressing the same message object are received within a short time interval,information might get lost (indicated by MSGLST = ‘10’), if the CPU has not processedthe former message object contents in time.Each arriving remote frame with matching identifier is answered by a data frame basedon the contents of the corresponding message object. This behavior may lead to multiplegeneration and transmission of identical data frames according to the number ofaccepted remote requests.

If SDT is set to ‘1’, the CAN node controller automatically resets bit MSGVAL in amessage object after receiving a data frame with corresponding identifier. All followingdata frames, addressing the disabled message object, are ignored until MSGVAL is setagain by the CPU.If SDT is set to ‘1’, the CAN node controller automatically resets bit MSGVAL in theaddressed message object, when the transmission of the corresponding data frame hasbeen finished successfully. In consequence, all following remote requests concerningthe disabled message object are ignored until MSGVAL is set again by the CPU. Thisfeature allows for transmitting data in a consecutive manner without unintended doublingof any information.

If SDT is cleared, control bitfield MSGVAL is not reset by the CAN node controller.



TwinCAN Module

21.1.5 CAN Message Object Buffer (FIFO)

In case of a high CPU load, it may be difficult to process an incoming data frame beforethe corresponding message object is overwritten with the next input data streamprovided by the CAN node controller. Depending on the application, it could be alsonecessary to ensure a minimum data frame generation rate to fulfill external real timerequirements.

Therefore, a message buffer facility has been implemented in order to avoid a loss ofincoming messages and to minimize the setup time for outgoing messages. Somemessage objects can be configured as a base object using succeeding slave messageobjects as individual buffer storage (building a circular buffer used as message FIFO).

Figure 21-13 FIFO Buffer Control Structure

The number of base and slave message objects, combined to a buffer, has to be a powerof two (2, 4, 8 etc.) and the buffer base address has to be an integer multiple of the bufferlength (e.g. a buffer containing 8 messages can use object 0, 8, 16 or 24 as base objectas illustrated in Table 21-2).

A base object is defined by setting bitfield MMC to ‘010’ in control register MSGFGCRnand the requested buffer size is determined by selecting an appropriate value for FSIZE.A slave object is defined by setting bitfield MMC to ‘011’. Bitfield FSIZE has to be equalin all FIFO elements in the same FIFO.

MCA05483

FIFO Object n + 7FIFO Object n + 6FIFO Object n + 5FIFO Object n + 4FIFO Object n + 3FIFO Object n + 2FIFO Object n + 1

FIFO Object n (base)

Protocol LayerTo / FromCAN Bus

FIFO Control Unit

MessageTransferred

ControlStatus

SelectObject



TwinCAN Module

The identifiers and corresponding acceptance masks have to be identical in all FIFOelements belonging to the same buffer in case of a receive FIFO (DIR = ‘0’). In case ofa transmit FIFO (DIR = ‘1’) the identifier of the currently addressed message object istaken into account for transmission.

Each member of a buffer configuration keeps its individual MSGVAL, NEWDAT,CPUUPD or MSGLST, TXRQ and RMTPND flag and its separate interrupt controlconfiguration. Inside a FIFO buffer, all elements must be

• assigned to the same CAN node (control bit NODE in register MSGCFGn),• programmed for the same transfer direction (control bit DIR),• set up to the same identifier length (control bit XTD),• programmed to the same FIFO length (bitfield FSIZEn) and• set up with the same value for the FIFO direction (bit FD in register MSGFGCRn).• The slave’s CANPTR has to point to the FIFO base object.

The base object’s CANPTR has to be initialized with the message number of the baseobject, the CANPTR pointers of the slave objects have to be set up with the messagenumber of the base object. The CANPTR of the base object addresses the next FIFOelement to be accessed for information transfer and its value can be calculatedaccording the following rule:

CANPTRn(new) := CANPTRn(old) & ∼FSIZEn | (CANPTRn(old) + 1) & FSIZEn

Control bit FD defines which transfer action (reception or transmission) leads to anupdate of the CANPTR bitfield. Bit FD works independently from the direction bit DIR ofthe FIFO elements. The reception of a data frame (DIR = ‘0’) or the reception of a remoteframe (DIR = ‘1’) are receive actions leading to an update of CANPTR if FD = ‘0’. Thetransmission of a data frame (DIR = ‘1’) or the transmission of a remote frame (DIR = ‘0’)are transmit actions initiating an increment of CANPTR if FD = ‘1’.

Note: The overall message object storage size is not affected by the configuration ofbuffer structures. The available storage size may be used for 32 message objectswithout buffering or for one message object with a buffer depth of 32 elements.Additionally, any combination of buffered and unbuffered message objects

Table 21-2 Message Objects Providing FIFO Base Functionality

Msg. Object n >FIFO Size

0 2 4 6 8 10 12 14 16 18 … 30

2 stage FIFO X X X X X X X X X X X

4 stage FIFO X – X – X – X – X – –

8 stage FIFO X – – – X – – – X – –

16 stage FIFO X – – – – – – – X – –

32 stage FIFO X – – – – – – – – – –



TwinCAN Module

according to the FIFO rules is allowed as long as the limit of 32 message objectsis not exceeded.

21.1.5.1 Buffer Access by the CAN Controller

The data transfer between the message buffer and the CAN bus is managed by theassociated CAN controller. Each buffer is controlled by a FIFO algorithm (First In, FirstOut = First Overwritten) storing messages, delivered by the CAN controller, in a circularorder.

Figure 21-14 Structure of a FIFO Buffer with one Base Object and Seven Slave Objects

If the FIFO buffer was initialized with receive objects, the first accepted message isstored in the base message object (number n), the second message is written to bufferelement (n+1) and so on. The number of the element, used to store the next inputmessage, is indicated by bitfield CANPTR in control register MSGFGCRn of the baseobject. If the reserved buffer space has been used up, the base message object(followed by the consecutive slave objects) is addressed again to store the next incomingmessage. When a message object was not read out on time by the CPU, the previous

MCA05484

Element1

Element2

(slave) (slave)

(slave)(base)(slave)(slave)

(slave) (slave)

Element0

Element3

Element7

Element4

Element6

Element5

CAN Pointer= base + 2










TwinCAN Module

message data is overwritten, which is indicated by flag MSGLST in the correspondingMSGCTR register.

If the FIFO buffer was initialized with transmit message objects, the CAN controller startsthe transfer with the contents of buffer element 0 (FIFO base object) and incrementsbitfield CANPTR in control register MSGFGCRn, pointing to the next element to betransmitted.

If the message object, which is currently addressed by the base object’s CANPTR, is notvalid (MSGVAL = ‘01’), the FIFO is not enabled for data transfer. In this case, theMSGVAL bitfields of the other FIFO elements (including the base element if not currentlyaddressed) are not taken into account.

In the case that the MSGVAL bitfields are set to ‘10’ for the FIFO base object and ‘01’ forthe currently addressed FIFO slave object, the data will not be delivered to the slaveobject, whereas the bitfield CANPTR in the FIFO base object is incremented accordingto FIFO rules.

If the FIFO is set up for the transmission of data frames and a matching remote frame isdetected for one of the elements of the FIFO, the transmit request and remote pendingbits will be set automatically in the corresponding message object. The transmission ofthe requested data frame is handled according to the FIFO rules and the value of theCANPTR bitfield in the FIFO base object.

21.1.5.2 Buffer Access by the CPU

The message transfer between a buffer and the CPU has to be managed by software.All message objects, combined to a buffer, can be accessed directly by the CPU. BitfieldCANPTR in control register MSGFGCRn is not automatically modified by a CPU accessto the message object registers.



TwinCAN Module

21.1.6 Gateway Message Handling

The CAN module supports an automatic information transfer between two independentCAN bus systems without CPU interaction.

Figure 21-15 TwinCAN Gateway Functionality

The gateway functionality is handled via the CAN message object memory shared byboth CAN nodes. Each object stored in the message memory is associated to node A orto node B via bit NODE in the message configuration register MSGCFGn. Theinformation exchange between both CAN nodes can be handled by coupling twomessage objects (normal gateway mode) or by sharing one common message object(shared gateway mode).

In the following paragraphs, the gateway side receiving data frames is named “source”(indicated by <s>) and the side transmitting the data frames, which passed the gateway,is called “destination” (indicated by <d>). In concordance to this notation, remote framespassing the gateway are received on the destination side and transmitted on the sourceside.

The gateway function of a message object and the requested information transfer modeare defined by bitfield MMC in the FIFO/Gateway control register MSGFGCRn.

MCA05485

CAN Message Object Memory

Bus Interface

Gateway

CANNode A

CANNode B

CAN Bus A CAN Bus B

CPU



TwinCAN Module

Figure 21-16 Message Burst in Case of FIFO/Gateway

21.1.6.1 Normal Gateway Mode

The normal gateway mode consumes two message objects to transfer a message fromthe source to the destination node. In this mode, different identifiers can be used for thesame message data. Details of the message transfer through the normal gateway arecontrolled by the respective MSGFGCR<s> and MSGFGCR<d> registers. All 8 data bytesfrom the source object (even if not all bytes are valid) are copied to the destination object.

The object receiving the information from the source node has to be configured asreceive message object (DIR = 0) and must be associated to the source CAN bus via bitNODE. Register MSGFGCR<s> should be initialized according the followingenumeration:

• Bitfield MMC<s> has to be set to ‘100’ indicating a normal mode gateway for incoming(data) frames.

• Bitfield CANPTR<s> must be initialized with the number of the message object usedas destination for the data copy process.

• If no FIFO functionality is required on the destination side, bitfield FSIZE<s> has to befilled with ‘00000’. When FIFO capabilities are needed, bitfield FSIZE<s> must containthe FIFO buffer length, which has to be identical with the content of the FIFO baseobject’s FSIZE bitfield on the destination side.

MCA05486

Message 1 Message 2 Message 3 Message 4

Destination BusSpeed B

To FIFOObject n + 3

To FIFOObject n + 2

To FIFOObject n + 1

To FIFOObject n

Message 1

To FIFOObject n

Message 2

To FIFOObject n + 1

Message 3

To FIFOObject n + 2

Message 4

To FIFOObject n + 3

Source BusSpeed A

TwinCAN

Node A

Node B



TwinCAN Module

• When bit IDC<s> is set, the identifier of the source message object is copied to thedestination message object. Otherwise, the identifier of the destination messageobject is not modified.

• If DLCC<s> is set, the data length code of the source message is copied to thedestination object.

• Bit GDFS<s> decides, whether the transmit request flag on the destination side is set(TXRQ<d> = ‘10’ if GDFS<s> = ‘1’) after finishing the data copy process. An automatictransmission of the copied data frame on the destination side takes place, if controlbit CPUUPD<d> is reset to ‘01’.

The destination message object, addressed by CANPTR<s>, has to be configured fortransmit operation (DIR = 1). Depending on the required functionality, the destinationmessage object can be set up in three different operating modes:

• With MMC<d> = ‘000’, the destination message object is declared as standardmessage object. In this case, data frames, received on the source side, can beautomatically emitted on the destination side if enabled by the respective control bitsCPUUPD<d> and GDFS<s>. Remote frames, received on the destination side, are nottransferred to the source side, but can be directly answered by the destinationmessage object if CPUUPD<d> is reset to ‘01’.

• With MMC<d> = ‘100’, the destination message object is declared as normal modegateway for incoming (remote) frames. Data frames, received on the source side, canbe automatically emitted on the destination side if enabled (CPUUPD<d>, GDFS<s>)and remote frames, received on the destination side, are transmitted on the sourceside if enabled by SRREN<d> = ‘1’.

• With MMC<d> = ‘01x’, the destination message object is set up as an element of aFIFO buffering the data frames transferred from the source side through the gateway.Remote frames, received on the destination side, are not transferred to the sourceside, but can be directly answered by the currently addressed FIFO element ifCPUUPD<d> is reset (bits SRREN<d> have to be cleared).

• Remote frame handling is completely done on the destination side according to FIFOrules.



TwinCAN Module

MMC<d> = ‘000’:

The operation with a standard message object on the destination side is illustrated inFigure 21-17.

Figure 21-17 Data Frame Reception in Normal Gateway Mode with a Standard Destination Message Object (MMC<d> = ‘000’)

A matching data frame, arrived at the source node, is automatically copied to thedestination node’s message object addressed by CANPTR<s>. Bitfield CANPTR<d> isloaded with the destination message object number. Regardless of control bitSRREN<d>, remote frames, received on the destination node, are not transferred to thesource side, but can be directly answered by the destination message object. For thispurpose, control bitfields TXRQ<d> and RMTPND<d> are set to ‘10’, which immediatelyinitiates a data frame transmission on the destination CAN bus if CPUUPD<d> is reset to‘01’.

MCA05487

FSIZE = ‘00000’CANPTR = <d>

MMC = ‘100’Node = <s>

DIR = ‘0’DATA

IDDLC

TXRQ = ‘01’RMTPND = ‘01’NEWDAT = ‘10’

INTPND


MMC = ‘000’Node = <d>

DIR = ‘1’DATA

IDDLC

TXRQRMTPND

NEWDAT = ‘10’INTPND

Pointer to DestinationMessage Object

Data Frame (GDFS<s> = ‘1’)Data Frame Copy Data Frame

GatewayDestination

GatewaySource

Gateway

Destination CAN BusSource CAN Bus

Pointer toDestinationMessageObject

Copy if DLCC<s> = ‘1’

CopyCopy if IDC<s> = ‘1’

ResetResetSetSet if RXIE<s> = ‘1’ Set if RXIE<d> = ‘1’

SetUnchanged

Set if GDFS<s> = ‘1’



TwinCAN Module

MMC<d> = ‘100’:

The operation with a normal mode gateway message object for incoming (remote)frames on the destination side is illustrated in Figure 21-18.

Figure 21-18 Remote Frame Transfer in Normal Gateway Mode, MMC<d> = ‘100’

The gateway object on the destination side, setup as transmit object, can receive remoteframes. If bit SRREN<d> in the associated gateway control register MSGFGCRn iscleared, a remote frame with matching identifier is directly answered by the CANdestination node controller. For this purpose, control bits TXRQ<d> and RMTPND<d> areset to ‘10’, which immediately initiates a data frame transmission on the destination CANbus if CPUUPD<d> is reset. When bit SRREN<d> is set to ‘1’, a remote frame received onthe destination side is transferred via the gateway and transmitted again by the CANsource node controller.

A transmit request for the gateway message object on the source side, initiated by theCPU via setting TXRQ<s>, generates always a remote frame on the source CAN bussystem.

MCA05488


MMC = ‘100’Node = <s>

DIR = ‘0’DATA

IDDLC

TXRQRMTPNDNEWDATINTPND

Copy if IDC<d> = ‘1’Copy if DLCC<d> = ‘1’

Set if SRREN<d> = ‘1’Set if SRREN<d> = ‘1’UnchangedSet if RXIE<s> = ‘1’ Set if RXIE<d> = ‘1’

UnchangedSet if SRREN<d> = ‘0’

Set if SRREN<d> = ‘0’

FSIZE = ‘00000’CANPTR = <s>

MMC = ‘100’Node = <d>

DIR = ‘1’DATA

IDDLC


Updated ifRMM<d> = ‘1’Updated ifRMM<d> = ‘1’

Pointer to SourceMessage Object

Pointer to DestinationMessage Object

Remote Frame

Data Frame (SRREN<d> = ‘0’)

Remote Frame Remote Request(SRREN<d> = ‘1’)

GatewayDestination

GatewaySource

Gateway




TwinCAN Module

21.1.6.2 Normal Gateway with FIFO Buffering

MMC<d> = ‘01x’:

When the gateway destination object is programmed as FIFO buffer, bitfield CANPTR<s>is used as pointer to the FIFO element to be addressed as destination for the next copyprocess. CANPTR<s> has to be initialized with the message object number of the FIFObase element on the destination side. CANPTR<s> is automatically updated according tothe FIFO rules, when a data frame was copied to the indicated FIFO element on thedestination side. Bit GDFS<s> determines if the TXRQ<d> bit in the selected FIFO elementis set after reception of a data frame copied from the source side.

The base message object is indicated by <ba>, the slave message objects by <sl>. Thenumber of base and slave message objects, combined to a buffer on the destinationside, has to be a power of two (2, 4, 8 etc.) and the buffer base address has to be aninteger multiple of the buffer length. Bitfield CANPTR<ba> of the FIFO base element andbitfield CANPTR<s> have to be initialized with the same start value (message objectnumber of the FIFO base element). CANPTR<sl> of all FIFO slave elements must beinitialized with the message object number of the FIFO base element. Bitfield FSIZE<d>of all FIFO elements must contain the FIFO buffer length and has to be identical with thecontent of FSIZE<s>.

Figure 21-19 illustrates the operation of a normal gateway with a FIFO buffer on thedestination side.



TwinCAN Module

Figure 21-19 Data Frame Transfer in Normal Gateway Mode with a 2 Stage FIFO on the Destination Side (MMC<d> = ‘01x’)

Remote frames, received on the destination side by a FIFO element, cannot beautomatically passed to the source side. Therefore, the SRREN<d> control bits,associated to the FIFO elements on the destination side, have to be cleared in order toanswer incoming remote frames with matching identifiers directly with a data frame.

Buffered transfers of remote requests from the destination to the source side can behandled by a software routine operating on the FIFO buffered gateway configuration fordata frame transfers. The elements of the FIFO buffer on the destination side should beconfigured as transmit message objects with CPUUPD<d> = ‘10’. An arriving remote

FIFO

CANPTR<sl>MMC<sl> = ‘011’

Node = <d>

MCA05489


MMC = ‘100’Node = <s>

DIR = ‘0’DATA

IDDLC


INTPND

Copy by SW if RequiredCopy by SW if Required

Set by SWReset by SWReset by SWUnchanged Set if RXIE<d> = ‘1’

UnchangedReset by SWReset by SW

FSIZE = ‘00001’CANPTR<ba>

MMC<ba> = ‘010’

Node = <d>

DIR = ‘1’DATA

IDDLC

TXRQ = ‘01’RMTPND = ‘01’

NEWDATINTPND

Remote Frame

Data Frame (CPUUPD<d> = ‘01’)

Remote Frame Copy Remote Request by SW(CPUUPD<d> = ‘10’)

GatewayDestination

GatewaySource

Gateway


Pointer toBaseObject

Pointer to next addressedDestination Message Object



TwinCAN Module

frame with matching identifier should initiate an interrupt service request for theaddressed FIFO message object. The associated interrupt service routine may copy themessage identifier and the data length code from the received remote frame to a receivemessage object linked with the source side CAN node. In any case, TXRQ of theselected receive message object must be set to ‘10’ initiating the transmission of aremote frame on the source side.

Figure 21-20 Remote Frame Transfer in Normal Gateway Mode with a 2-stage FIFO on the Destination Side

FIFO

CANPTR<sl>MMC<sl> = ‘011’

Node = <d>

MCA05490


MMC = ‘100’Node = <s>

DIR = ‘0’DATA

IDDLC


INTPND

Copy if DLCC<s> = ‘1’ResetResetSetSet if RXIE<s> = ‘1’ Set if RXIE<d> = ‘1’

SetUnchanged

Set if GDFS<s> = ‘0’

FSIZE = ‘00001’CANPTR<ba>

MMC<ba> = ‘010’

Node = <d>

DIR = ‘1’DATA

IDDLC

TXRQRMTPND

NEWDAT = ‘10’INTPND

Data Frame (GDFS<s> = ‘1’)Data Frame Copy Data Frame

GatewayDestination

GatewaySource

Gateway


Pointer toBaseObject

Pointer to next addressedDestination Message Object

CopyCopy if IDC<s> = ‘1’



TwinCAN Module

21.1.6.3 Shared Gateway Mode

In shared gateway mode, only one message object is required to implement a gatewayfunctionality. The shared gateway object can be considered as normal message object,which is toggled between the source and destination CAN node as illustrated inFigure 21-21.

Figure 21-21 Principle of the Shared Gateway Mode

Each message object can be used as shared gateway by setting MMC in thecorresponding MSGFGCRn register to ‘101’. When the message configuration bit NODEis cleared, CAN node A is used as source, transferring data frames to destination nodeB. If NODE is set to ‘1’, CAN node B operates as data source. A bidirectional gateway isachieved by using a second message object, configured to shared gateway mode witha complementary NODE declaration. Bitfield CANPTR has to be initialized with theshared gateway’s message object number, whereas FSIZE, IDC and DLCC have to becleared. Bit GDFS in control register MSGFGCRn determines, whether bit TXRQ will beautomatically set in case of an arriving data frame with matching identifier (GDFS = ‘1’).

MCA05491

FSIZE = ‘00000’CANPTR = ‘n’MMC = ‘101’

Node = <s, d>

DIR = ‘0’, ‘1’DATA

IDDLC


DestinationNode

SourceNode


Pointer toMessageObject

Shared GatewayControl Logic



TwinCAN Module

Bit SRREN determines, whether a remote frame, received on the destination side, istransferred through the gateway to the source node or is directly answered by a dataframe generated on the destination side.

The functionality of the shared gateway mode is optimized to support different scenarios:

• a data source, connected with CAN node A, transmits continuously data frames,which have to be automatically emitted on the destination CAN bus by CAN node B.The corresponding transfer state transitions are 1 - 2 - …

• a data source, connected with CAN node A, transmits continuously data frames,which have to be emitted by CAN node B upon a matching remote frame receivedfrom the destination CAN bus.The corresponding transfer state transitions are 7 - 4 - 2 - …

• a data source, connected with CAN node A, transmits a data frame upon a matchingremote frame, which has been triggered by a matching remote frame received byCAN node B. The respective data frame has to be emitted again on the destinationCAN bus by CAN node B.The corresponding transfer state transitions are 5 - 6 - 1 - 3 - …

Depending on the application, the shared gateway message object can be initialized asreceive object on the source side or transmit object on the destination side via anappropriate configuration of NODE, DIR, GDFS and SRREN. The various transfer statesare illustrated in Figure 21-22.

Figure 21-22 Transfer States in Shared Gateway Mode

MCA05492

Transmit ObjectDestination Side

TXRQ Reset

Receive ObjectSource SideTXRQ Set

5Remote FrameReception,SRREN = ‘1’

Transmit ObjectDestination Side

TXRQ Set

Receive ObjectSource SideTXRQ Reset

2Data FrameTransmission,SRREN = ‘0’

1Data FrameReception,GDFS = ‘1’

4

Remote Frame Reception,SRREN = ‘0’

Data Frame Transmission, SRREN = ‘1’

Remote Frame Transmission

6

Data FrameReception,GDFS = ‘0’

7

3



TwinCAN Module

When a shared gateway message object, set up as receive object on the source side(lower left state bubble in Figure 21-22), receives a data frame while GDFS is set to ‘1’,it commutes to a transmission object on the destination side by toggling control bitsNODE and DIR and sends the corresponding data frame without any CPU interaction(upper left state bubble).Depending on control bit SRREN, the shared gateway message object returns to itsinitial function as receive object assigned to the source side (SRREN = ‘0’: statetransition 2 to the lower left state bubble in Figure 21-22) or remains assigned to thedestination side waiting for a remote frame with matching identifier (SRREN = ‘1’: statetransition 3 to the upper right state bubble).When the shared gateway message object is assigned as transmit object to thedestination side (upper right state bubble), it responds to remote frames received on thedestination side. If bit SRREN is cleared, the remote request is directly answered by adata frame based on the contents of the gateway message object (state transition 4 tothe upper left state bubble).If bit SRREN is set and a remote frame is received on the destination side, the sharedgateway message object commutes to a receive object on the source side by togglingcontrol bits NODE and DIR and prepares the emission of the received remote frame bysetting TXRQ and RMTPND to ‘10’ (state transition 5 to the lower right state bubble).Then the shared gateway message object emits the corresponding remote frame withoutany CPU interaction (state transition 6 to the lower left state bubble).The gateway message object remains assigned to the source side until a data frame withmatching identifier arrives (lower left state bubble). Then the shared gateway messageobject returns to the destination side and, depending on control bit GDFS, transmitsimmediately the corresponding data frame (GDFS = ‘1’, upper left state bubble) or waitsupon an action of the CPU setting TXRQ to ‘10’ (GDFS = ‘0’: state transition 7 to theupper right state bubble). Alternatively, a remote frame with matching identifier, arrivingon the destination side, may set TXRQ to ‘10’ and initiate the data frame transmission.

If a data frame arrives on the source side while the shared gateway object with matchingidentifier is switched to the destination side, the data frame on the source side gets lost.Due to the temporary assignment to the destination node, the shared gateway messageobject does not notice the data frame on the source node and is not able to report thedata loss via control bitfield MSGLST = ‘10’. The probability for a data loss is enlarged,if the automatic data frame transmission on the destination side is disabled byGDFS = ‘0’. A corresponding behavior has to be taken into account for incoming remoteframes on the destination bus.

Note: As long as bitfield MSGLST is activated, an incoming data frame cannot beautomatically transmitted on the destination side. Due to the internal toggling ofcontrol bit DIR, the shared gateway object converts from receive to transmitoperation and bitfield MSGLST is interpreted as CPUUPD = ‘10’ preventing theautomatic transmission of a data frame.



TwinCAN Module

Impact of the transfer state transitions on the bitfields in the message object in sharedgateway mode:

Table 21-3 Shared Gateway State Transitions (Part 1 of 2)

Bitfields Transition 1: Data Frame Received, GDFS = ‘1’

Transition 2: Data Frame Transmitted, SRREN = ‘0’

Transition 3: Data Frame Transmitted, SRREN = ‘1’

Transition 4: Remote Frame Received, SRREN = ‘0’

Node toggled to <d> toggled to <s> unchanged unchanged

DIR set reset unchanged unchanged

DATA received unchanged unchanged unchanged

Identifier received unchanged unchanged received if RMM = ‘1’

DLC received unchanged unchanged received if RMM = ‘1’

TXRQ set reset reset set

RMTPND reset reset reset set

NEWDAT set reset reset reset

INTPND set if RXIE = ‘10’ set if TXIE = ‘10’ set if TXIE = ‘10’ set if RXIE = ‘10’

Table 21-4 Shared Gateway State Transitions (Part 2 of 2)

Bitfields Transition 5:Remote Frame Received,SRREN = ‘1’

Transition 6:Remote Frame Transmitted

Transition 7:Data Frame Received, GDFS = ‘0’

Node toggled to <s> unchanged toggled to <d>

DIR reset unchanged set

DATA unchanged unchanged received

Identifier received if RMM = ‘1’ unchanged received

DLC received if RMM = ‘1’ unchanged received

TXRQ set reset reset

RMTPND reset reset reset

NEWDAT unchanged unchanged set

INTPND set if RXIE = ‘10’ set if TXIE = ‘10’ set if RXIE = ‘10’



TwinCAN Module

21.1.7 Programming the TwinCAN Module

A software initialization should be performed by setting bit INIT in the CAN node specificcontrol register ACR/BCR to ‘1’. While bit INIT is set, all message transfers between theCAN controller and the CAN bus are disabled.

The initialization routine should process the following tasks:

• configuration of the corresponding node,• initialization of each associated message object.

21.1.7.1 Configuration of CAN Node A/B

Each CAN node can be individually configured by programming the associated register.Depending on the content of the ACR/BCR control registers, the normal operation modeor the CAN analyzer mode is activated. Furthermore, various interrupt categories (statuschange, error, last error) can be enabled or disabled.The bit timing is defined by programming the ABTR/BBTR register. The prescaler value,the synchronization jump width and the time segments, arranged before and after thesample point, depend on the characteristic of the CAN bus segment linked to thecorresponding CAN node.The global interrupt node pointer register (AGINP/BGINP) controls multiplexerconnecting an interrupt request source (error, last error, global transmit/receive andframe counter overflow interrupt request) with one of the eight common interrupt nodes.The contents of the INTID mask register (AIMR0/4 and BIMR0/4) decides which interruptsources may be reported by the AIR/BIR interrupt pending register.

21.1.7.2 Initialization of Message Objects

The message memory space, containing 32 message objects, is shared by both CANnodes. Each message object has to be configured concerning its target node andoperation properties. An initialization of the message object properties is always startedwith disabling the message object via MSGVAL = ‘01’.The CAN node, associated with a message, is defined by bit NODE in registerMSGCFGn. The message object can be also defined as gateway, transferringinformation from CAN node A to B or vice versa. In this case, the FIFO/Gateway controlregister MSGFGCRn must be programmed to specify the gateway mode (bitfield MMC),the target interrupt node and further details of the information handover.The identifier, correlated with a message, is set up in register MSGARn. Bit XTD inregister MSGCFGn indicates, whether an extended 29-bit or a standard 11-bit identifieris used and has to be set accordingly. Incoming messages can be filtered by the maskdefined in register MSGAMRn.The message interrupt handling can be individually configured for transmit and receivedirection. The direction specific interrupt is enabled by bits TXIE and RXIE in registerMSGCNTn and the target interrupt node is selected by bitfields TXINP and RXINP in



TwinCAN Module

register MSGCFGn.Message objects can be provided with a FIFO buffer. The buffer size is determined bybitfield FSIZE in the FIFO/Gateway control register MSGFGCRn.For transmit message objects, the object property assignment can be already finishedby setting MSGVAL to ‘10’, before the corresponding data partition has been initialized.If bitfield CPUUPD is set to ‘10’, an incoming remote frame with matching identifier iskept in mind via setting TXRQ internally, but is not immediately answered by acorresponding data frame. The message data, stored in register MSGDRn0/MSGDRn4,can be updated as long as CPUUPD is hold on ‘10’. As soon as CPUUPD is reset to ‘01’,the respective data frame is transmitted by the associated CAN node controller.

21.1.7.3 Controlling a Message Transfer

Figure 21-23 illustrates the handling of a transmit message object. The initialization ofthe message object properties is always started with disabling the message object viaMSGVAL = ‘01’. After resetting some control flags (INTPND, RMTPND, TXRQ andNEWDAT), the transfer direction and the identifier are defined. The message objectinitialization is finished by setting MSGVAL to ‘10’.An update of a transmit message data partition should be prepared by setting CPUUPDto ‘10’ followed by a write access to the MSGDRn0/MSGDRn4 register. The datapartition update must be indicated by the CPU via setting NEWDAT to ‘10’. Afterwards,bit CPUUPD must be reset to ‘01’, if an automatic message handling is requested. In thiscase, the data transmission is started, when flag TXRQ in register MSGCTRn has beenset to ‘10’ by software or by the respective CAN node hardware due to a received remoteframe with matching identifier. If CPUUPD remains set, the CPU must initiate the datatransmission by setting TXRQ to ‘10’ and disabling CPUUPD. If a remote frame with anaccepted identifier arrives during the update of a message object’s data storage, bitTXRQ and RMTPND are automatically set to ‘10’ and the transmission of thecorresponding data frame is automatically started by the CAN controller when CPUUPDis reset again.Figure 21-24 demonstrates the handling of a receive message object. The initializationof the message object properties is embedded between disabling and enabling themessage object via MSGVAL as described above. After setting MSGVAL to ‘10’, thetransmission of a remote frame can be initiated by the CPU via TXRQ = ‘10’. Thereception of a data frame is indicated by the associated CAN node controller viaNEWDAT = ‘10’. The processing of the received data frame, stored in registerMSGDRn0/MSGDRn4, should be started by the CPU with resetting NEWDAT to ‘01’.After scanning flag MSGLST, indicating a loss of the previous message, the receivedinformation should be copied to an application data buffer in order to release themessage object for a new data frame. Finally, NEWDAT should be checked again toensure, that the processing was based on a consistent set of data and not on a part ofan old message and part of the new message.



TwinCAN Module

Figure 21-23 CPU Handling of Message Objects with Direction = Transmit

MCA05493

Want to Send?

yes

Update Message?

yesno

noTXRQ := ‘10’

CPUUPD := ‘01’

MSGVAL = ‘01’INTPND := ‘01’RMTPND := ‘01’TXRQ := ‘01’NEWDAT := ‘01’DIR := ‘1’ (transmit object)Identifier := (application specific)XTD := (application specific)TXIE := (application specific)RXIE := (application specific)CPUUPD := ‘10’MSGVAL := ‘10’

Write / Calculate Message Contents

(all bits written with reset values)Power Up

Message Initialization

Update : Start

Update : End

CPUUPD := ‘10’NEWDAT := ‘10’

Update

‘01’ : Reset‘10’ : Set



TwinCAN Module

Figure 21-24 CPU Handling of Message Objects with Direction = Receive

MCA05494

NEWDAT = ‘10’?

Remote FrameTransmission

?

no

no

TXRQ := ‘10’

MSGVAL = ‘01’INTPND := ‘01’RMTPND := ‘01’TXRQ := ‘01’NEWDAT := ‘01’DIR := 0 (receive object)MSGLST := ‘01’TXIE := (application specific)RXIE := (application specific)Identifier := (application specific)XTD := (application specific)MSGVAL := ‘10’

Process Message Contents

(all bits written with reset values)Power Up

Initialization

Data Frame Processing

NEWDAT := ‘01’

yes

yes

Remote Frame Generation

‘01’ : Reset‘10’ : Set

Restart Process



TwinCAN Module

21.1.8 Loop-Back Mode

The TwinCAN module’s loop-back mode provides the means to internally test theTwinCAN module and CAN driver software. CAN driver software can be developed andtested without being connected to a CAN bus system.

In loop-back mode, the transmit pins deliver recessive signals to the transceiver. Thetransmit signals are combined together and are connected to the internal receive signals,as shown in Figure 21-25. The receive input pins are not taken into account in loop-backmode.

Figure 21-25 Loop-back Mode

Loop-back mode is controlled by bits LBM in the bit timing registers of Node A andNode B according to Table 21-5.

Table 21-5 Loop-Back Mode

ABTR.LBM BBTR.LBM Description

0 0 Loop-back mode is disabled.



1 1 Loop-back mode is enabled.

MCA05495

MUX

10

1TxDCB

MUX

10

1TxDCA

&

TwinCANKernel

MUX0

1

MUX0

1

RxDCA

RxDCB

LBM



TwinCAN Module

21.1.9 Single Transmission Try Functionality

Single transmission try functionality is controlled individually for each message object bybit STT in register MSGFGCRn. If the single transmission try functionality is enabled, thetransmit request flag TXRQ is reset immediately after the transmission of a frame relatedto this message object has started. Thus, a transmit frame is only transferred once onthe CAN bus, even if it has been corrupted by error frames.

Note: A message object must be tagged valid by bitfield MSGVAL in order to enable thetransmission of the respective frame.



TwinCAN Module

21.1.10 Module Clock Requirements

The functionality of the TwinCAN module is programmable in several respects. In orderto operate at a specific baudrate with a given functionality a certain minimum moduleclock frequency is required. Table 21-6 lists some examples for certain configurations.These examples cover the worst case conditions where the CPU executes accesses tothe TwinCAN module consecutively and with maximum speed.

The module clock frequency can be reduced (see last column of Table 21-6) if no frameswithout data (data frames with DLC = 0 or remote frames) are transferred over the CANbus. This is possible, because internal operations can be executed while the data part istransferred.

Note: The given numbers are required for the maximum CAN bus speed of 1 Mbit/s. Forlower bit-rates the minimum module clock frequency can be reduced linearly, i.e.half the frequency is required for a bit-rate of 500 kbit/s.However, if two nodes are operated with different bit-rates, the module clockfrequency must be chosen according to the fastest node.

Table 21-6 Minimum Module Clock Frequencies for 1 Mbit/s

1 Node Active,DLC ≥ 0

2 Nodes Active,DLC ≥ 0

2 Nodes Active,DLC ≥ 1

FIFO/gatewayenabled

21 MHz 36 MHz 32 MHz

No FIFO/gateway

20 MHz 29 MHz 26 MHz



TwinCAN Module

21.2 TwinCAN Register Description

21.2.1 Register Map

Figure 21-26 shows all registers associated with the TwinCAN module kernel.

Figure 21-26 TwinCAN Kernel Registers

MCA05496

ACRASR

CAN Node ARegisters

Node A Control RegisterNode A Status RegisterNode A Interrupt Pending RegisterNode A Bit Timing RegisterNode A Global Int. Node Pointer Reg.Node A Frame Counter RegisterNode A INTID Mask Register 0Node A INTID Mask Register 4Node A Error Counter Register

Msg. Object n Data Register 0Msg. Object n Arbitration RegisterMsg. Object n Control RegisterMsg. Object n FIFO/Gatew. Cont. Reg.

Receive Interrupt Pending Register

ACRASRAIRABTRAGINPAFCRAIMR0AIMR4AECNT

MSGDRn0MSGARnMSGCTRnMSGFGCRn

RXIPND

AIRABTRAGINPAFCRAIMR0AIMR4AECNT

BCRBSR

CAN Node BRegisters

BIRBBTRBGINPBFCRBIMR0BIMR4BECNT

MSGDRn0MSGDRn4

CAN MessageObjectRegisters 1)

MSGARnMSGAMRnMSGCTRnMSGCFGnMSGFGCRn

RXIPNDTXIPND

Global CANControl / StatusRegisters

Node B Control RegisterNode B Status RegisterNode B Interrupt Pending RegisterNode B Bit Timing RegisterNode B Global Int. Node Pointer Reg.Node B Frame Counter RegisterNode B INTID Mask Register 0Node B INTID Mask Register 4Node B Error Counter Register

Msg. Object n Data Register 4Msg. Object n Acceptance Mask Reg.Msg. Object n Configuration Register

Transmit Interrupt Pending Register

BCRBSRBIRBBTRBGINPBFCRBIMR0BIMR4BECNT

MSGDRn4MSGAMRnMSGCFGn

TXIPND

1) The number ‘n’ indicates the message object number, n = 0 … 31.



TwinCAN Module

Figure 21-27 TwinCAN Kernel Address Map

...

...

Reserved

MCA05497

+18HFIFO/Gateway ControlMessage Config. Reg. +14H

Message Control Reg. +10H

Acceptance Mask Reg. +0CH

Arbitration Register +08H

Data Register 4 +04H

Data Register 0 +00H

Transmit Int. Pending +08H

Receive Int. Pending +04H

+20HError Counter Reg.INTID Mask 4 Reg. +1CH

INTID Mask 0 Reg. +18H

Frame Counter Reg. +14H

Global INP Reg. +10H

Bit Timing Reg. +0CH

Interrupt Pending Reg. +08H

Status Reg. +04H

Control Reg. +00H

+20HError Counter Reg.INTID Mask 4 Reg. +1CH

INTID Mask 0 Reg. +18H

Frame Counter Reg. +14H

Global INP Reg. +10H

Bit Timing Reg. +0CH

Interrupt Pending Reg. +08H

Status Reg. +04H

Control Reg. +00H

Message Object 31

Message Object n

Message Object 2

+6E0H

+340H

Message Object 1

+320H

Message Object 0

+300H

+2C0H

Global ControlRegisters

+280H

CAN Node BRegisters

+240H

+200H

Reserved

+000H

ModuleOffset

Node A

Node B

CAN Node ARegisters



TwinCAN Module

21.2.2 CAN Node A/B Registers

The Node Control Register controls the initialization, defines the node specific interrupthandling and selects an operation mode.

ACR Node A Control Register Reset Value: 0001HBCR Node B Control Register Reset Value: 0001H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0CAL

MCCE 0

LECIE

EIE SIE 0 INIT

r rw rw r rw rw rw r rwh


INIT 0 rwh Initialization0 Resetting bit INIT starts the synchronization to

the CAN bus. After a synchronization procedure1), the node takes part in CAN communication.

1 After setting bit INIT, the CAN node stops all CAN bus activities and all registers can be initialized without any impact on the actual CAN bus traffic. Bit INIT is automatically set when the bus-off state is entered.

SIE 2 rw Status Change Interrupt EnableA status change interrupt occurs when a message transfer (indicated by the flags TXOK or RXOK in the status registers ASR or BSR) is successfully completed.0 Status change interrupt is disabled.1 Status change interrupt is enabled.

EIE 3 rw Error Interrupt EnableAn error interrupt is generated on a change of bit BOFF or bit EWRN in the status registers ASR or BSR.0 Error interrupt is disabled.1 Error interrupt is enabled.



TwinCAN Module

LECIE 4 rw Last Error Code Interrupt EnableA last error code interrupt is generated when an error code is set in bitfield LEC in the status registers ASR or BSR.0 Last error code interrupt is disabled.1 Last error code interrupt is enabled.

CCE 6 rw Configuration Change Enable0 Access to bit timing register and modification of

the error counters are disabled.1 Access to bit timing register and modification of

the error counters are enabled.

CALM 7 rw CAN Analyzer ModeBit CALM defines if the message objects of the corresponding node operate in analyzer mode.0 The CAN message objects participate in CAN

protocol.1 CAN Analyzer Mode is selected.

0 1, 5, [15:8]

r Reserved; returns ‘0’ if read; should be written with ‘0’.

1) After resetting bit INIT by software without being in the bus-off state (e.g. after power-on), a sequence of11 consecutive recessive bits (11 × ‘1’) on the bus has to be monitored before the module takes part in theCAN traffic.During a bus-off recovery procedure, 128 sequences of 11 consecutive recessive bits (11 × ‘1’) have to bedetected. The monitoring of the recessive bit sequences is immediately started by hardware after entering thebus-off state. The number of already detected 11 × ‘1’ sequences is indicated by the receive error counter.At the end of the bus-off recovery sequence, bit INIT is tested by hardware. If INIT is still set, the affected CANnode controller waits until INIT is cleared and 11 consecutive recessive bits (11 × ‘1’) are detected on the CANbus, before the node takes part in CAN traffic again. If INIT has been already cleared, the message transferbetween the affected CAN node controller and its associated CAN bus is immediately enabled.




TwinCAN Module

The Node Status Register reports error states and successfully ended datatransmissions. This register has to be read in order to release the status change interruptrequest.

ASR Node A Status Register Reset Value: 0000HBSR Node B Status Register Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0B

OFFE

WRN0

RXOK

TXOK

LEC

r rh rh r rwh rwh rwh


LEC [2:0] rwh Last Error CodeBitfield LEC indicates if the latest CAN message transfer has been correct (No Error) or it indicates the type of error, which has been detected. The error conditions are detailed in Table 21-7.000 No Error001 Stuff Error010 Form Error011 Ack Error100 Bit1 Error101 Bit0 Error110 CRC Error111 reserved

TXOK 3 rwh Message Transmitted Successfully0 No successful transmission since last flag reset.1 A message has been transmitted successfully

(error free and acknowledged by at least one other node).

TXOK must be reset by software.

RXOK 4 rwh Message Received Successfully0 No successful reception since last flag reset.1 A message has been received successfully.RXOK must be reset by software.



TwinCAN Module

EWRN 6 rh Error Warning Status0 No warning limit exceeded.1 One of the error counters in the Error

Management Logic reached the error warning limit of 96.

BOFF 7 rh Bus-Off Status0 CAN controller is not in the bus-off state.1 CAN controller is in the bus-off state.

0 5, [15:8]


Table 21-7 Meaning of the LEC Bitfield

LEC Error Description

No Error The latest transfer on the CAN bus has been completed successfully.

Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

Form Error A fixed format part of a received frame has the wrong format.

Ack Error The transmitted message was not acknowledged by another node.

Bit1 Error During a message transmission, the CAN node tried to send a recessive level (‘1’), but the monitored bus value was dominant (outside the arbitration field and the acknowledge slot).

Bit0 Error Two different conditions are signaled by this code:1. During transmission of a message (or acknowledge bit, active

error flag, overload flag), the CAN node tried to send a dominantlevel (‘0’), but the monitored bus value has been recessive.

2. During bus-off recovery, this code is set each time a sequence of11 recessive bits has been monitored. The CPU may use thiscode as an indication, that the bus is not continuously disturbed.

CRC Error The CRC checksum of the received message was incorrect.




TwinCAN Module

The Interrupt Pending Register contains the identification number of the pendinginterrupt request with the highest priority.

AIR Node A Interrupt Pending Register Reset Value: 0000 0000HBIR Node B Interrupt Pending Register Reset Value: 0000 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 INTID

r rwh


INTID [7:0] rwh Interrupt Identifier00H No interrupt is pending.01H LEC, EI, TXOK or RXOK interrupt is pending.02H RX or TX interrupt of message object 0 is pending.03H RX or TX interrupt of message object 1 is pending.… …21H RX or TX interrupt of message object 31 is

pending.Bitfield INTID can be written by software to start an update after software actions and to check for changes.

0 [15:8] r Reserved; returns ‘0’ if read.



TwinCAN Module

Register AECNT/BECNT contains the values of the receive error counter and thetransmit error counter. Some additional status/control bits allow for easier error analysis.

AECNTH Node A Error Counter Register High Reset Value: 0060HAECNTL Node A Error Counter Register Low Reset Value: 0000HBECNTHNode B Error Counter Register High Reset Value: 0060HBECNTLNode B Error Counter Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0LEINC

LETD

EWRNLVL

r rh rh rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TEC REC

rwh rwh


REC [7:0]Low

rwh Receive Error CounterBitfield REC contains the value of the receive error counter for the corresponding node.

TEC [15:8]Low

rwh Transmit Error CounterBitfield TEC contains the value of the transmit error counter for the corresponding node.

EWRNLVL [7:0]Low

rw Error Warning LevelBitfield EWRNLVL defines the threshold value (warning level, default 60H = 96D) to be reached in order to set the corresponding error warning bit EWRN.



TwinCAN Module

Note: Modifying the contents of register AECNT/BECNT requires bit CCE = ‘1’ in registerACR/BCR.

LETD 8High

rh Last Error Transfer Direction0 The last error occurred while the corresponding

CAN node was receiving a message (REC has been incremented).

1 The last error occurred while the corresponding CAN node was transmitting a message (TEC has been incremented).

An error during message reception is indicated without regarding the result of the acceptance filtering.

LEINC 9High

rh Last Error Increment0 The error counter was incremented by 1 due to

the error reported by LETD.1 The error counter was incremented by 8 due to

the error reported by LETD.

0 [15:10]High





TwinCAN Module

The Bit Timing Register contains all parameters to adjust the data transfer baud rate andthe bit timing.

ABTRH Node A Bit Timing Register High Reset Value: 0000HABTRL Node A Bit Timing Register Low Reset Value: 0000HBBTRHNode B Bit Timing Register High Reset Value: 0000HBBTRLNode B Bit Timing Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 LBM

r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIV8X

TSEG2 TSEG1 SJW BRP

rw rw rw rw rw


BRP [5:0]Low

rw Baudrate PrescalerOne bit time quantum corresponds to the period length of the external oscillator clock multiplied by (BRP+1), depending also on bit DIV8X.

SJW [7:6]Low

rw (Re)Synchronization Jump Width(SJW+1) time quanta are allowed for resynchronization.

TSEG1 [11:8]Low

rw Time Segment Before Sample Point(TSEG1+1) time quanta before the sample point take into account the signal propagation delay and compensate a mismatch between transmitter and receiver clock phase.Valid values for TSEG1 are 2 … 15.



TwinCAN Module

Note: Modifying the contents of register ABTR/BBTR requires bit CCE = ‘1’ in registerACR/BCR.

TSEG2 [14:12]Low

rw Time Segment After Sample Point(TSEG2+1) time quanta after the sample point take into account a user defined delay and compensate a mismatch between transmitter and receiver clock phase.Valid values for TSEG2 are 1 … 7.

DIV8X 15Low

rw Division of Module Clock fCAN by 80 The baudrate prescaler is directly driven by fCAN.1 The baudrate prescaler is driven by fCAN/8.

LBM 0High

rw Loop-Back Mode0 Loop-back mode is disabled.1 Loop-back mode is enabled, if bits LBM are set

in the BTR registers of Node A and Node B.

0 [15:1]High

r Reserved; read as ‘0’; should be written with ‘0’.




TwinCAN Module

The Frame Counter Register controls the frame counter functionality and provides statusinformation.

AFCRH Node A Frame Counter Register High Reset Value: 0000HAFCRL Node A Frame Counter Register Low Reset Value: 0000HBFCRHNode B Frame Counter Register High Reset Value: 0000HBFCRLNode B Frame Counter Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0CFCOV

CFCIE

0 CFCMD

r rwh rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFC

rwh


CFC [15:0]Low

rwh CAN Frame CounterThis bitfield contains the count value of the frame counter.At the end of a correct message transfer, the value of CFC (captured value during SOF bit) is copied to bitfield CFCVAL of the corresponding message object control register MSGCTRn.



TwinCAN Module

CFCMD [3:0]High

rw Frame Count ModeThis bitfield defines the operation mode of the frame counter. This counter can work on frame base (frame count) or on time base (time stamp).0XXXB Frame Count:1)

0XX0B The CFC is not incremented after a foreign frame was transferred on the CAN bus.

0XX1B The CFC is incremented each time a foreign frame was transferred correctly on the CAN bus.

0X0XB The CFC is not incremented after a frame was received by the respective CAN node.

0X1XB The CFC is incremented each time a frame was received correctly by the node.

00XXB The CFC is not incremented after a frame was transmitted by the node.

01XXB The CFC is incremented each time a frame was transmitted correctly by the node.

1XXXB Time Stamp:1000B The CFC is incremented with the beginning

of a new bit time. The value is sampled during the SOF bit.

1001B The CFC is incremented with the beginning of a new bit time. The value is sampled during the last bit of EOF.

others reserved

CFCIE 6High

rw CAN Frame Count Interrupt EnableSetting CFCIE enables the CAN Frame Counter Overflow (CFCO) interrupt request.0 The CFCO interrupt is disabled.1 The CFCO interrupt is enabled.

CFCOV 7High

rwh CAN Frame Count Overflow FlagFlag CFCOV is set on a CFC overflow condition (FFFFH to 0000H). An interrupt request is generated if the corresponding interrupt is enabled (CFCIE = ‘1’).0 An overflow has not yet been detected.1 An overflow has been detected since the bit has

been reset.CFCOV must be reset by software.




TwinCAN Module

0 [5:4], [15:8]High


1) If the frame counter functionality has been selected (CFCMD.3 = ‘0’), bit CFCMD.0 enables or disables thecounting of foreign frames. A foreign frame is a correct frame on the bus, which has not been transmitted/received by the node itself. Bit CFCMD.1 enables or disables the counting of frames, which have beenreceived correctly by the corresponding CAN node. Bit CFCMD.2 enables or disables the counting of frames,which have been transmitted correctly by the corresponding CAN node.




TwinCAN Module

The Global Interrupt Node Pointer Register connects each global interrupt requestsource with one of the 8 available CAN interrupt nodes.

AGINPNode A Global Interrupt Node Pointer Register Reset Value: 0000HBGINPNode B Global Interrupt Node Pointer Register Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 CFCINP 0 TRINP 0 LECINP 0 EINP

r rw r rw r rw r rw


EINP [2:0] rw Error Interrupt Node PointerNumber of interrupt node reporting the “Error Interrupt Request”, if enabled by EIE = ‘1’.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

LECINP [6:4] rw Last Error Code Interrupt Node PointerNumber of interrupt node reporting the last error interrupt request, if enabled by LECIE = ‘1’.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

TRINP [10:8] rw Transmit/Receive OK Interrupt Node PointerNumber of interrupt node reporting the transmit and receive interrupt request, if enabled by SIE = ‘1’.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

CFCINP [14:12] rw Frame Counter Interrupt Node PointerNumber of interrupt node reporting the frame counter overflow interrupt request, if enabled by CFCIE = ‘1’.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

0 3, 7, 11, 15




TwinCAN Module

The Interrupt Identification Mask Registers allow for disabling the identificationnotification of a pending interrupt request in the AIR/BIR register. The Interrupt MaskRegisters AIMR0/BIMR0 are used to enable the message specific interrupt sources(correct transmission/ reception) for the generation of the corresponding INTID value.

AIMRH0 Node A INTID Mask Register 0 High Reset Value: 0000HAIMRL0 Node A INTID Mask Register 0 Low Reset Value: 0000HBIMRH0Node B INTID Mask Register 0 High Reset Value: 0000HBIMRL0Node B INTID Mask Register 0 Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMCn (n = 31-16)

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMCn (n = 15-0)

rw


IMCn(n = 15-0)

IMCn(n = 31-16)

nLow

n-16High

rw Message Object n INTID Mask Control0 Message object n is ignored for the

generation of the INTID value.1 The interrupt pending status of

message object n is taken into accountfor the generation of the INTID value.



TwinCAN Module

The Interrupt Mask Registers AIMR4/BIMR4 are used to enable the node specificinterrupt sources (last error, correct reception, error warning/bussoff) for the generationof the corresponding INTID value.

AIMR4Node A INTID Mask Register 4 Reset Value: 0000HBIMR4Node B INTID Mask Register 4 Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0IMC34

IMC33

IMC32

r rw rw rw


IMC32 0 rw Last Error Interrupt INTID Mask Control0 The last error interrupt source is ignored for

the generation of the INTID value.1 The last error interrupt source is taken into

account for the generation of the INTID value.

IMC33 1 rw TX/RX Interrupt INTID Mask Control0 The TX/RX interrupt source is ignored for the

generation of the INTID value.1 The TX/RX interrupt pending status is taken

into account for the generation of the INTID value.

IMC34 2 rw Error Interrupt INTID Mask Control0 The error interrupt source is ignored for the

generation of the INTID value.1 The error interrupt pending status is taken

into account for the generation of the INTID value.

0 [15:3] r Reserved; read as ‘0’; should be written with ‘0’.



TwinCAN Module

21.2.3 CAN Message Object Registers

Each message object is provided with a set of control and data register. Thecorresponding register names are supplemented with a variable n running from 0 to 31(e.g. MSGDRn0 means that data register MSGDR300 is assigned with message objectnumber 30).The Message Data Register 0 contains the data bytes 0 to 3 of message object n.

MSGDRHn0 (n = 31-0) Message Object n Data Register 0 High Reset Value: 0000HMSGDRLn0 (n = 31-0)Message Object n Data Register 0 Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA3 DATA2

rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA1 DATA0

rwh rwh


DATA0 [7:0]Low

rwh Data Byte 0 Associated to Message Object n

DATA1 [15:8]Low


DATA2 [7:0]High


DATA3 [15:8]High




TwinCAN Module

The Message Data Register 4 contains the data bytes 4 to 7 of message object n.

MSGDRHn4 (n = 31-0) Message Object n Data Register 4 High Reset Value: 0000HMSGDRLn4 (n = 31-0)Message Object n Data Register 4 Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA7 DATA6

rwh rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA5 DATA4

rwh rwh


DATA4 [7:0]Low


DATA5 [15:8]Low


DATA6 [7:0]High


DATA7 [15:8]High




TwinCAN Module

Register MSGARn contains the identifier of message object n.

MSGARHn (n = 31-0) Message Object n Arbitration Register High Reset Value: 0000HMSGARLn (n = 31-0)Message Object n Arbitration Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 ID[28:16]

r rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID[15:0]

rwh


ID[15:0]

ID[28:16]

[15:0]Low[12:0]High

rwh Message IdentifierIdentifier of a standard message (ID[28:18]) or an extended message (ID[28:0]). For standard identifiers bits ID[17:0] are “don’t care”.

0 [15:13]High




TwinCAN Module

Register MSGAMRn contains the mask bits for the acceptance filtering of messageobject n.

MSGAMRHn (n = 31-0) Message Object n Arbitration Mask Register High Reset Value: FFFFHMSGAMRLn (n = 31-0)Message Object n Arbitration Mask Register Low Reset Value: FFFFH

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 AM[28:16]

r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AM[15:0]

rw


AM[15:0]

AM[28:16]

[15:0]Low[12:0]High

rw Message Acceptance MaskMask to filter incoming messages with standard identifiers (AM[28:18]) or extended identifiers (AM[28:0]). For standard identifiers bits AM[17:0] are “don’t care”.0 Identifier bit is ignored for acceptance test.1 Identifier bit is taken into account for the

acceptance filtering.

1 [15:13]High




TwinCAN Module

Register MSGCTRn affects the data transfer between a CAN node controller and thecorresponding message object n and provides a bitfield to store the captured value ofthe frame counter.

MSGCTRHn (n = 31-0) Message Object n Message Control Register High Reset Value: 0000HMSGCTRLn (n = 31-0) Message Object n Message Control Register Low Reset Value: 5555H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFCVAL

rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RMTPND TXRQMSGLSTCPUUPD

NEWDAT MSGVAL TXIE RXIE INTPND

rwh rwh rwh rwh rwh rw rw rwh


INTPND [1:0]Low

rwh Message Object Interrupt PendingINTPND is generated by an “OR” operation between the RXIPNDn and TXIPNDn flags (if enabled by TXIE or RXIE). INTPND must be reset by software. Resetting INTPND also resets the corresponding RXIPND and TXIPND flags.01 No message object interrupt request is

pending.10 The message object has generated an interrupt

request.

RXIE [3:2]Low

rw Message Object Receive Interrupt Enable01 Message object receive interrupt is disabled.10 Message object receive interrupt is enabled.

If RXIE is set, bits INTPND and RXIPND are set after successful reception of a frame.

TXIE [5:4]Low

rw Message Object Transmit Interrupt Enable01 Message object transmit interrupt is disabled.10 Message object transmit interrupt is enabled.

If TXIE is set, bits INTPND and TXIPND are set after successful transmission of a frame.



TwinCAN Module

MSGVAL1) [7:6]Low

rwh Message Object ValidThe CAN controller only operates on valid message objects. Message objects can be tagged invalid while they are changed or if they are not used at all.01 Message object is invalid.10 Message object is valid.

NEWDAT2) [9:8]Low

rwh New Message Object Data Available01 No update of message object data occurred.10 New message object data has been updated.

MSGLST [11:10]Low

rwh Message Lost (for reception only)01 No message object data is lost.10 The CAN controller has stored a new message

into the message object while NEWDAT was still set. The previously stored message is lost.

MSGLST must be reset by software.

CPUUPD3) [11:10]Low

rwh CPU Update (for transmission only)Indicates that the corresponding message object can not be transmitted now. The software sets this bit in order to inhibit the transmission of a message that is currently updated by the CPU or to control the automatic response to remote requests.01 The message object data can be transmitted

automatically by the CAN controller.10 The automatic transmission of the message

data is inhibited.

TXRQ4) [13:12]Low

rwh Message Object Transmit Request Flag01 No message object data transmission is

requested by the CPU or a remote frame.10 The transmission of the message object data,

requested by the CPU or by a remote frame, is pending.

Automatic setting of TXRQ by the CAN node controller can be disabled for Gateway Message Objects via control bit GDFS = ‘0’.TXRQ is automatically reset, when the message object has been successfully transmitted.If there are several valid message objects with pending transmit requests, the message object with the lowest message number will be transmitted first.




TwinCAN Module

Note: For transmitting frames (remote frames or data frames), bitfieldCPUUPD/MSGLST has to be reset.

RMTPND [15:14]Low

rwh Remote Pending Flag (used for transmit-objects)01 No remote node request for a message object

data transmission.10 Transmission of the message object data has

been requested by a remote node but the data has not yet been transmitted. When RMTPND is set, the CAN node controller also sets TXRQ.

RMTPND is automatically reset, when the message object data has been successfully transmitted.

CFCVAL [15:0]High

rwh Message Object Frame Counter ValueCFCVAL contains a copy of the frame counter content valid for the last correct data transmission or reception executed for the corresponding message object.

1) MSGVAL has to be set from ‘01’ to ‘10’ in order to take into account an update of bits XTD, DIR, NODE andCANPTR.

2) Bit NEWDAT indicates that new data has been written into the data registers of this corresponding messageobject. For transmit objects, NEWDAT should be set by software and is reset by the respective CAN nodecontroller when the transmission is started.For receive objects, NEWDAT is set by the respective CAN node controller after receiving a data frame withmatching identifier. It has to be reset by software.When the CAN controller writes new data into the message object, unused message bytes will be overwrittenwith non-specified values. Usually, the CPU will clear this bitfield before working on the data and will verify thatthe bitfield is still cleared once the CPU has finished working to ensure a consistent set of data. For transmitobjects, the CPU should set this bitfield along with clearing bitfield CPUUPD. This will ensure that, if themessage is actually being transmitted during the time the message is updated by the CPU, the CAN controllerwill not reset bitfield TXRQ. In this way, TXRQ is only reset once the actual data has been transferred correctly.

3) While bitfield MSGVAL is set (‘10’) an incoming matching remote frame is taken into account by automaticallysetting bitfields TXRQ and RMTPND to ‘10’ (independent from bitfield CPUUPD/MSGLST). The transmissionof a frame is only possible if CPUUPD is reset (‘01’).

4) If a receive object (DIR = ‘0’) is requested for transmission, a remote frame will be sent in order to request adata frame from another node. If a transmit object (DIR = ‘1’) is requested for transmission, a data frame willbe sent. Bitfield TXRQ will be reset by the CAN controller along with bitfield RMTPND after the correcttransmission of the data frame if bitfield NEWDAT has not been set or after correct transmission of a remoteframe.




TwinCAN Module

The control and status element of the message control registers is implemented with twocomplementary bits (except the frame counter value). This special mechanism allowsthe selective setting or resetting of a specific element (leaving others unchanged) withoutrequiring read-modify-write cycles. Table 21-8 illustrates how to use these 2-bitfields.

Register MSGCFGn defines the configuration of message object n and the associatedinterrupt node pointers. Changes of bits XTD, NODE or DIR by software are only takeninto account after setting bitfield MSGVAL to ‘10’. This avoids unintentional modificationwhile the message object is still active by explicitly defining a timing instant for theupdate. Bits XTD, NODE or DIR can be written while MSGVAL is ‘01’ or ‘10’, the updatealways takes place by setting MSGVAL to ‘10’.

Table 21-8 Setting/Resetting the Control and Status Element of the Message Control Registers

Value ofthe 2-bitfield

Function on Write Meaning on Read

00B reserved reserved

01B Reset element Element is reset

10B Set element Element is set

11B Leave element unchanged reserved

MSGCFGHn (n = 31-0) Message Object n Message Configuration Register High Reset Value: 0000HMSGCFGLn (n = 31-0) Message Object n Message Configuration Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 TXINP 0 RXINP

r rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 DLC DIR XTDNODE

RMM

r rwh rwh rw rwh rw



TwinCAN Module


RMM 0Low

rw Transmit Message Object Remote Monitoring Mode0 Remote Monitoring mode is disabled.1 Remote Monitoring mode is enabled for this

transmit message object. The identifier and DLC code of a remote frame with matching identifier are copied to this transmit message object in order to monitor incoming remote frames.

Bit RMM is only available for transmit objects and has no impact for receive objects.

NODE 1Low

rwh Message Object CAN Node Select0 The message object is assigned to CAN node A.1 The message object is assigned to CAN node B.

XTD 2Low

rw Message Object Extended Identifier0 This message object uses a standard 11-bit

identifier.1 This message object uses an extended 29-bit

identifier.

DIR 3Low

rwh Message Object Direction Control0 The message object is defined as receive

object. If TXRQ = ‘10’, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, the message data is stored in the corresponding MSGDRn0/MSGDRn4 registers.

1 The message object is declared as transmit object. If TXRQ = ‘10’, the respective data frame is transmitted. On reception of a remote frame with matching identifier, RMTPND and TXRQ are set to ‘10’.

DLC1) [7:4]Low

rwh Message Object Data Length Code0000B - 1XXXBDLC contains the number of data bytes associated to the message object.Bitfield DLC may be modified by hardware in Remote Monitoring Mode and in Gateway Mode.



TwinCAN Module

The FIFO/gateway control register MSGFGCRn contains bits to enable and to controlthe FIFO functionality, the gateway functionality and the desired transfer actions.

RXINP [2:0]High

rw Receive Interrupt Node PointerBitfield RXINP determines which interrupt node is triggered by a message object receive event, if bitfield RXIE in register MSGCTRn is set.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

TXINP [6:4]High

rw Transmit Interrupt Node PointerBitfield TXINP determines which interrupt node is triggered by a message object transmit event, if bitfield TXIE in register MSGCTRn is set.000B CAN interrupt node 0 is selected.… …111B CAN interrupt node 7 is selected.

0 [15:8]Low3, [15:7]High


1) The maximum number of data bytes is 8. A value > 8 written by the CPU, is internally corrected to 8 but thecontent of bitfield DLC is not updated.If a received data frame contains a data length code value > 8, only 8 bytes are taken into account. A readaccess to bitfield DLC returns the original value of the DLC field of the received data frame.




TwinCAN Module

MSGFGCRHn (n = 31-0) Message Object n FIFO/Gateway Control Register High Reset Value: 0000HMSGFGCRLn (n = 31-0) Message Object n FIFO/Gateway Control Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 MMC 0 CANPTR

r rw r rwh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STT SDT FD 0DLCC

IDCSRREN

GDFS

0 FSIZE

rw rw rw r rw rw rw rw r rw


FSIZE [4:0]Low

rw FIFO Size ControlBitfield FSIZE determines the number of message objects combined to a FIFO buffer. Even numbered message objects may provide FIFO base or slave functionality, while odd numbered message objects are restricted to slave functionality. In gateway mode, FSIZE determines the length of the FIFO on the destination side.00000B message object n is part of a 1-stage FIFO00001B message object n is part of a 2-stage FIFO00011B message object n is part of a 4-stage FIFO00111B message object n is part of a 8-stage FIFO01111B message object n is part of a 16-stage FIFO11111B message object n is part of a 32-stage FIFOelse reservedFSIZE = ‘00000’ leads to the behavior of a standard message object (the pointer CANPTR used for this action will not be changed). This value has to be written if a gateway transfer to a single message object (no FIFO) as destination is desired.FSIZE is not evaluated for message objects configured in standard mode, shared gateway mode or FIFO slave functionality. In this case, FSIZE should be programmed to ‘00000’.



TwinCAN Module

GDFS 8Low

rw Gateway Data Frame SendSpecifies if a CAN data frame will be automatically generated on the destination side after new data has been transferred via gateway from the source to the destination side.0 No additional action, TXRQ will not be set on the

destination side.1 The corresponding data frame will be sent

automatically (TXRQ of the message object, pointed to by CANPTRn, will be set by hardware).

Bit GDFS is only taken into account, if a data frame has been received (DIR<s> = ‘0’).

SRREN 9Low

rw Source Remote Request EnableSpecifies if the transmit request bit is set in message object n itself (to generate a data frame) or in the message object pointed to by CANPTRn (in order to generate a remote frame on the source bus).0 A remote on the source bus will not be generated,

a data frame with the contents of the destination object will be generated on the destination bus, instead (TXRQn will be set).

1 A data frame with the contents of the destination object will not be sent. Instead, a corresponding remote frame will be generated by the message object pointed to by bitfield CANPTRn (TXRQ[CANPTRn] will be set).

SRREN is restricted to transmit message objects in normal or shared gateway mode (DIR = ‘1’). This bit is only taken into account if a remote frame has been received.Bit SRREN must not be set if message object n is part of a FIFO buffer.In order to generate a remote frame on the source side, CANPTR has to point to the source message object.




TwinCAN Module

IDC 10Low

rw Identifier CopyIDC controls the identifier handling during a frame transfer through a gateway.0 The identifier of the receiving object is not copied

to the transmitting message object.1 The identifier of the receiving object is

automatically copied to the transmitting message object.

Bitfield IDC is restricted to message objects configured in normal gateway mode.

DLCC 11Low

rw Data Length Code CopyDLCC controls the handling of the data length code during a data frame transfer through a gateway.0 The data length code, provided by the source

object, is not copied to the transmitting object.1 The data length code, valid for the receiving

object, is copied automatically to the transmitting object.

Bitfield DLCC is restricted to message objects configured in normal gateway mode.




TwinCAN Module

FD 13Low

rw FIFO DirectionFD is only taken into account for a FIFO base object (the FD bits of all FIFO elements should have an identical value). It defines which transfer action (reception or transmission) leads to an update of the FIFO base object’s CANPTR.0 FIFO Reception: The CANPTR (of the FIFO base

object) is updated after a correct reception of a data frame (DIR = ‘0’) or a remote frame (DIR = ‘1’) by the currently addressed message object. The CANPTR is left unchanged after any transmission.

1 FIFO Transmission: The CANPTR (of the FIFO base object) is updated after a correct transmission of a data frame (DIR = ‘1’) or a remote frame (DIR = ‘0’) from the currently addressed message object. The CANPTR is left unchanged after any reception.

Bitfield FD is not correlated with bit DIR.

SDT 14Low

rw Single Data Transfer ModeThis bit is taken into account in any transfer mode (FIFO mode or as standard object, receive and transmit objects).0 Control bit MSGVAL is not reset when this object

has taken part in a successful data transfer (receive or transmit).

1 Control bit MSGVAL is automatically reset after a successful data transfer (receive or transmit) has taken place.

Bit SDT is not taken into account for remote frames.Bit SDT has to be reset in all message objects belonging to a FIFO buffer.

STT 15Low

rw Single Transmission Try0 Single transmission try is disabled.1 Single transmission try is enabled. The

corresponding TXRQ bit is reset immediately after the transmission has started1).




TwinCAN Module

CANPTR [4:0]High

rwh CAN Pointer for FIFO/Gateway FunctionsMessage object is configured in standard mode(MMC = ‘000’):No impact, CANPTR should be initialized with the respective message object number.Message object is configured as FIFO base object(MMC = ‘010’):CANPTR contains the number of the message object addressed by the associated CAN controller for the next transmit or receive operation.For initialization, CANPTR should be written with the message number of the respective FIFO base object.Message object is configured as FIFO slave object(MMC = ‘011’):CANPTR has to be initialized with the respective message object number of the FIFO base object.Message object is configured for normal gateway mode (MMC = ‘100’):CANPTR contains the number of the message object used as gateway destination object.Message object is configured as gateway destination object without FIFO functionality(MMC = ‘000’):If SRREN is set to ‘1’, CANPTR has to be initialized with the number of the message object used as gateway source. The backward pointer is required to transfer remote frames from the destination to the source side.If SRREN is cleared, CANPTR is not evaluated and must be initialized with the respective message object number.Message object is configured for shared gateway mode (MMC = ‘101’):No impact, CANPTR has to be initialized with the respective message object number.For FIFO functionality (or gateway functionality with a FIFO as destination), CANPTRn should not be written by software while FIFO mode is activated and data transfer is in progress. This bitfield can be used to reset the FIFO by software.




TwinCAN Module

Note: Changes of bitfield CANPTR for transmission objects are only taken into accountafter setting bitfield MSGVAL to ‘10’. This avoids unintentional modification whilethe message object is still active by explicitly defining a timing instant for theupdate. Bitfield CANPTR for transmission objects can be written while MSGVALis ‘01’ or ‘10’, the update always takes place by setting MSGVAL to ‘10’. Changesof bitfield CANPTR for receive objects are immediately taken into account.

MMC [10:8]High

rw Message Object Mode ControlBitfield MMC controls the functionality of messageobject n.000B Standard message object functionality010B FIFO functionality enabled (base object)011B FIFO functionality enabled (slave object)100B Normal gateway functionality for incoming

frames101B Shared gateway functionality for incoming

framesothers reserved

0 [7:5], 12Low[7:5], [15:11]High


1) As a result, a message will not be re-transmitted if it has lost arbitration or has been corrupted by an errorframe.




TwinCAN Module

21.2.4 Global CAN Control/Status Registers

The Receive Interrupt Pending Register indicates the pending receive interrupts formessage object n.

RXIPNDH Receive Interrupt Pending Register High Reset Value: 0000HRXIPNDL Receive Interrupt Pending Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXIPNDn (n = 31-16)

rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXIPNDn (n = 15-0)

rh


RXIPNDn(n = 15-0)

RXIPND(n = 31-16)

nLow

n-16High

rh Message Object n Receive Interrupt PendingBit RXIPNDn is set by hardware if message object n received a frame and bit RXIEn has been set.0 No receive is pending for message object n.1 Receive is pending for message object n.RXIPNDn can be cleared by software via resetting the corresponding bit INTPNDn.



TwinCAN Module

The Transmit Interrupt Pending Register indicates whether a transmit interrupt ispending for message object n.

TXIPNDH Transmit Interrupt Pending Register High Reset Value: 0000HTXIPNDL Transmit Interrupt Pending Register Low Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TXIPNDn (n = 31-16)

rh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TXIPNDn (n = 15-0)

rh


TXIPNDn(n = 15-0)

TXIPND(n = 31-16)

nLow

n-16High

rh Message Object n Transmit Interrupt PendingBit TXIPNDn is set by hardware if message object n transmitted a frame and bit TXIEn has been set.0 No transmit is pending for message object n.1 Transmit is pending for message object n.TXIPNDn can be cleared by software via resetting the corresponding bit INTPNDn.



TwinCAN Module

21.3 XC164 Module Implementation Details

This section describes:

• the TwinCAN module related interfaces such as port connections and interruptcontrol

• all TwinCAN module related registers with its addresses and reset values

21.3.1 Interfaces of the TwinCAN Module

In XC164 the TwinCAN module is connected to IO ports according to Figure 21-28.

Figure 21-28 TwinCAN Module IO Interface

The input receive pins can be selected by bitfield RISA (for node A) and bitfield RISB (fornode B) in the PISEL register. The output transmit pins are defined by the correspondingALTSEL registers of Port 4 or Port 9.

The TwinCAN has eight interrupt request lines.

Port 9Control

MCA05498

InterruptControl

CAN0INT

CAN5INT

CAN1INT

CAN2INT

CAN3INT

CAN4INT

CAN7INT

CAN6INT

AddressDecoder

TwinCANModule(Kernel)

fCAN

P9.2

P9.3

P9.1

P9.0

ALTSEL

P4.6

P4.7

P4.5

P4.4Port 4

Control

ALTSEL

Port 7Control

P7.6

P7.7

P7.5

P7.4

ALTSEL

P9.3_tx

MUX

RxDCA

P9.2_rx

P9.1_tx

P9.0_rx

P7.7_tx

P7.5_tx

P7.6_rx

P7.4_rx

P4.7_rx

P4.7_tx

P4.6_tx

P4.5_rx

P4.4_rx

MUXRxDCB

PISEL

3 3

TxDCB

TxDCA



TwinCAN Module

21.3.2 TwinCAN Module Related External Registers

Figure 21-29 shows the module related external registers which are required forprogramming the TwinCAN module.

Figure 21-29 TwinCAN Implementation Specific Registers

MCA05499_X4

ALTSEL0P4DP4

Port Registers

ALTSEL0P9DP9

CAN_0ICCAN_1IC

Interrupt Registers

CAN_2ICCAN_3ICCAN_4ICCAN_5IC

CAN_PISEL

System Registers

CAN_6ICCAN_7IC



TwinCAN Module

21.3.2.1 System Registers

Register CAN_PISEL allows the user to select the input pins for the two TwinCANreceive signals RXDCA and RXDCB.

CAN_PISELTwinCAN Port Input Select Register Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 RISB RISA

r rw rw


RISA [2:0] rw Receive Input Selection for Node ABitfield RISA defines the input pin for the TwinCAN receive line RXDCA for node A.000 The input pin for RXDCA is P4.5001 The input pin for RXDCA is P4.7010 Reserved.011 The input pin for RXDCA is P9.21XX Reserved.

RISB [5:3] rw Receive Input Selection for Node BBitfield RISB defines the input pin for the TwinCAN receive line RXDCB for node B.000 The input pin for RXDCB is P4.4001 The input pin for RXDCB is P9.0010 Reserved.011 Reserved.1XX Reserved.

0 [15:6] r Reserved; returns ‘0’ if read; should be written with ‘0’.



TwinCAN Module

21.3.2.2 Port Registers

The port registers required to program to TwinCAN operation are listed as follows.

Note: Shaded bits are not related to TwinCAN operation.

ALTSEL0P4P4 Alternate Select Register 0 Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 P7 P6 0

r rw rw r

Field Bit Type Description

ALTSEL0P4.y

7, 6 rw P4 Alternate Select Register 0 bit y0 associated peripheral output is not selected as

alternate function1 associated peripheral output is selected as

alternate function

DP4 P4 Direction Ctrl. Register Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 P7 P6 P5 P4 P3 P2 P1 P0

r rw rw rw rw rw rw rw rw


DP4.y 7 … 4 rw Port Direction Register DP4 Bit y0 Port line P4.y is an input

(high-impedance)1 Port line P4.y is an output



TwinCAN Module



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 P3 0 P1 0

r rw rw rw rw rw rw


ALTSEL0P9.y

3, 1 rw P9 Alternate Select Register 0 Bit y0 associated peripheral output is not selected as


alternate function


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 P3 0 P1 0

r rw rw rw rw rw rw


ALTSEL1P9.y

3, 1 rw P9 Alternate Select Register 1 Bit y0 associated peripheral output is not selected as


alternate function



TwinCAN Module


DP9 P9 Direction Ctrl. Register Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 P5 P4 P3 P2 P1 P0

r rw rw rw rw rw rw


DP9.y 3 … 0 rw Port Direction Register DP9 Bit y0 Port line P9.y is an input (high-impedance)1 Port line P9.y is an output



TwinCAN Module

Table 21-9 shows the required register setting to configure the IO lines of the TwinCANmodule for operation.

Note: The ALTSEL1 register of Port 4 is ‘don’t care’ for selecting the TwinCAN alternateoutput function.

Table 21-9 TwinCAN IO Selection and Setup

Port Lines Alternate Select Register

Port Input Select Register

Direction Control Register

IO

TwinCAN Node A

P4.5 / RxDCA – CAN_PISEL[2:0] =000

DP4.P5 = 0 Input

P4.6 / TxDCA ALTSEL0P4.P6 = 1 – DP4.P6 = 1 Output


DP4.P7 = 0 Input


DP9.P2 = 0 Input

P9.3 / TxDCA ALTSEL0P9.P3 = 1 andALTSEL1P9.P3 =1

– DP9.P3 = 1 Output

TwinCAN Node B

P4.4 / RxDCB – CAN_PISEL[5:3] =000

DP4.P4 = 0 Input

P4.7 / TxDCB ALTSEL0P4.P7 = 1 – DP4.P7 = 1 Output

P9.0 / RxDCB – CAN_PISEL[5:3] =001

DP9.P0 = 0 Input

P9.1 / TxDCB ALTSEL0P9.P1 = 1 andALTSEL1P9.P1 =1

– DP9.P1 = 1 Output



TwinCAN Module

21.3.2.3 Interrupt Registers

The interrupts of the TwinCAN module are controlled by the following interrupt controlregisters:

• CAN_0IC• CAN_1IC• CAN_2IC• CAN_3IC• CAN_4IC• CAN_5IC• CAN_6IC• CAN_7IC

All interrupt control registers have the same structure. Refer to the System Units for itsdescription and also details on interrupt handling and processing.



TwinCAN Module

21.3.3 Register Table

Table 21-10 shows the system registers related to the TwinCAN module. It summarizesthe addresses and reset values. In order to simplify the kernel description, the prefix‘CAN_’ is added only in this register list.

The start address for the TwinCAN module is 20’0000H, the register offsets (relative tothis address) are given in the TwinCAN kernel description. See Figure 21-27. A fullregister listing of all CAN registers is provided in register table section and in the systembook.

Table 21-10 TwinCAN Module Register Summary

Name Description Address1)

1) The 8-bit short addresses are not available for the TwinCAN module kernel registers.

Reset Value16-Bit

TwinCAN Module System Registers

CAN_PISEL TwinCAN Port Input Select Register 20’0004H 0000H

CAN_0IC TwinCAN Interrupt Control Register for the CAN interrupt node 0.

F196H 0000H


F142H 0000H


F144H 0000H


F146H 0000H


F148H 0000H


F14AH 0000H


F14CH 0000H


F14EH 0000H



Register Set

22 Register Set This chapter summarizes all the kernel and module related external registers of theperipherals. The register list is organized into two parts - the first for PD+BUS peripheralsand the second for LXBus peripherals.

22.1 PD+BUS Peripherals

Note: The address space for PD+BUS peripherals is assigned to Segment 0.

Table 22-1 PD+BUS Register Listing

Short Name Address Description Reset ValuePhysical 8-bit Area

Asynchronous/Synchronous Serial Interface 0 (ASC0)

ASC0_CON FFB0H D8H SFR ASC0 Control Register 0000H

ASC0_TBUF FEB0H 58H SFR ASC0 Transmit Buffer Register 0000H

ASC0_RBUF FEB2H 59H SFR ASC0 Receive Buffer Register 0000H

ASC0_ABCON

F1B8H DCH ESFR ASC0 Autobaud Control Register 0000H

ASC0_ABSTAT

F0B8H 5CH ESFR ASC0 Autobaud Status Register 0000H

ASC0_BG FEB4H 5AH SFR ASC0 Baud Rate Generator Reload Register

0000H

ASC0_FDV FEB6H 5BH SFR ASC0 Fractional Divider Register 0000H

ASC0_PMW FEAAH 55H SFR ASC0 IrDA Pulse Mode and Width Reg.

0000H

ASC0_RXFCON

F0C6H 63H ESFR ASC0 Receive FIFO Control Register

0000H

ASC0_TXFCON

F0C4H 62H ESFR ASC0 Transmit FIFO Control Register

0000H

ASC0_FSTAT F0BAH 5DH ESFR ASC0 FIFO Status Register 0000H

Asynchronous/Synchronous Serial Interface 1 (ASC1)

ASC1_CON FFB8H DCH SFR ASC1 Control Register 0000H

ASC1_TBUF FEB8H 5CH SFR ASC1 Transmit Buffer Register 0000H

ASC1_RBUF FEBAH 5DH SFR ASC1 Receive Buffer Register 0000H

ASC1_ABCON

F1BCH DEH ESFR ASC1 Autobaud Control Register 0000H

User’s Manual 22-1 V2.1, 2004-03RegSet_X41, V2.0


Register Set

ASC1_ABSTAT

F0BCH 5EH ESFR ASC1 Autobaud Status Register 0000H

ASC1_BG FEBCH 5EH SFR ASC1 Baud Rate Generator Reload Register

0000H

ASC1_FDV FEBEH 5FH SFR ASC1 Fractional Divider Register 0000H

ASC1_PMW FEACH 56H SFR ASC1 IrDA Pulse Mode and Width Reg.

0000H

ASC1_RXFCON

F0A6H 53H ESFR ASC1 Receive FIFO Control Register

0000H

ASC1_TXFCON

F0A4H 52H ESFR ASC1 Transmit FIFO Control Register

0000H

ASC1_FSTAT F0BEH 5FH ESFR ASC1 FIFO Status Register 0000H

Synchronous Serial Channel 0 (SSC0)

SSC0_CON FFB2H D9H SFR SSC0 Control Register 0000H

SSC0_BR F0B4H 5AH ESFR SSC0 Baudrate Timer Reload Register

0000H

SSC0_TB F0B0H 58H ESFR SSC0 Transmit Buffer Reg. 0000H

SSC0_RB F0B2H 59H ESFR SSC0 Receive Buffer Reg. 0000H

Synchronous Serial Channel 1 (SSC1)

SSC1_CON FF5EH AFH SFR SSC1 Control Register 0000H

SSC1_BR F05EH 2FH ESFR SSC1 Baudrate Timer Reload Register

0000H

SSC1_TB F05AH 2DH ESFR SSC1 Transmit Buffer Reg. 0000H

SSC1_RB F05CH 2EH ESFR SSC1 Receive Buffer Reg. 0000H

General Purpose Timer Unit (GPT12E)

GPT12E_T2CON

FF40H A0H SFR GPT12E Timer 2 Control Register 0000H

GPT12E_T3CON


GPT12E_T4CON


Table 22-1 PD+BUS Register Listing (cont’d)




Register Set

GPT12E_T5CON


GPT12E_T6CON


GPT12E_CAPREL

FE4AH 25H SFR GPT12E Capture/Reload Register 0000H

GPT12E_T2 FE40H 20H SFR GPT12E Timer 2 Register 0000H





Real Time Clock (RTC)

RTC_CON F110H 88H ESFR RTC Control Register, low word 8003H

RTC_T14 F0D2H 69H ESFR Timer 14 Register UUUUH

RTC_T14REL F0D0H 68H ESFR Timer 14 Reload Register UUUUH

RTC_RTCL F0D4H 6AH ESFR RTC Timer Low Register UUUUH

RTC_RTCH F0D6H 6BH ESFR RTC Timer High Register UUUUH

RTC_RELL F0CCH 66H ESFR RTC Reload Low Register 0000H

RTC_RELH F0CEH 67H ESFR RTC Reload High Register 0000H

RTC_ISNC F10CH 86H ESFR RTC Interrupt Subnode Register 0000H


CC1_M0 FF52H A9H SFR CAPCOM1 Mode Control Register 0

0000H

CC1_M1 FF54H AAH SFR CAPCOM1 Mode Control Register 1

0000H

CC1_M2 FF56H ABH SFR CAPCOM1 Mode Control Register 2

0000H

CC1_M3 FF58H ACH SFR CAPCOM1 Mode Control Register 3

0000H

CC1_SEE FE2EH 17H SFR CAPCOM1 Single Event Enable Register

0000H





Register Set

CC1_SEM FE2CH 16H SFR CAPCOM1 Single Event Mode Register

0000H

CC1_DRM FF5AH ADH SFR CAPCOM1 Double Register Mode Register

0000H

CC1_OUT FF5CH AEH SFR CAPCOM1 Output Register 0000H

CC1_T0 FE50H 28H SFR CAPCOM1 Timer 0 Register 0000H

CC1_T0REL FE54H 2AH SFR CAPCOM1 Timer 0 Reload Register

0000H

CC1_T1 FE52H 29H SFR CAPCOM1 Timer 1 Register 0000H

CC1_T1REL FE56H 2BH SFR CAPCOM1 Timer 1 Reload Register

0000H

CC1_T01CON FF50H A8H SFR CAPCOM1 Timer 0 and Timer 1 Control Register

0000H

CC1_IOC F062H 31H ESFR CAPCOM1 I/O Control Register 0000H

CC1_CC0 FE80H 40H SFR CAPCOM1 Register 0 0000H





CC1_CC5 FE8AH 45H SFR CAPCOM1 Register 5 0000H

CC1_CC6 FE8CH 46H SFR CAPCOM1 Register 6 0000H

CC1_CC7 FE8EH 47H SFR CAPCOM1 Register 7 0000H



CC1_CC10 FE94H 4AH SFR CAPCOM1 Register 10 0000H

CC1_CC11 FE96H 4BH SFR CAPCOM1 Register 11 0000H

CC1_CC12 FE98H 4CH SFR CAPCOM1 Register 12 0000H

CC1_CC13 FE9AH 4DH SFR CAPCOM1 Register 13 0000H

CC1_CC14 FE9CH 4EH SFR CAPCOM1 Register 14 0000H

CC1_CC15 FE9EH 4FH SFR CAPCOM1 Register 15 0000H





Register Set

Capture / Compare Unit 2 (CAPCOM2)

CC2_M4 FF22H 91H SFR CAPCOM2 Mode Control Register 4

0000H


0000H


0000H


0000H

CC2_SEE FE2AH 15H SFR CAPCOM2 Single Event Enable Register

0000H

CC2_SEM FE28H 14H SFR CAPCOM2 Single Event Mode Register

0000H

CC2_DRM FF2AH 95H SFR CAPCOM2 Double Register Mode Register

0000H

CC2_OUT FF2CH 96H SFR CAPCOM2 Output Register 0000H

CC2_T7 F050H 28H ESFR CAPCOM2 Timer 7 Register 0000H

CC2_T8 F052H 29H ESFR CAPCOM2 Timer 8 Register 0000H

CC2_T7REL F054H 2AH ESFR CAPCOM2 Timer 7 Reload Register

0000H

CC2_T8REL F056H 2BH ESFR CAPCOM2 Timer 8 Reload Register

0000H

CC2_T78CON FF20H 90H SFR CAPCOM2 Timer 7 and Timer 8 Control Register

0000H

CC2_IOC F066H 33H ESFR CAPCOM2 I/O Control Register 0000H






CC2_CC21 FE6AH 35H SFR CAPCOM2 Register 21 0000H

CC2_CC22 FE6CH 36H SFR CAPCOM2 Register 22 0000H





Register Set

CC2_CC23 FE6EH 37H SFR CAPCOM2 Register 23 0000H



CC2_CC26 FE74H 3AH SFR CAPCOM2 Register 26 0000H

CC2_CC27 FE76H 3BH SFR CAPCOM2 Register 27 0000H

CC2_CC28 FE78H 3CH SFR CAPCOM2 Register 28 0000H

CC2_CC29 FE7AH 3DH SFR CAPCOM2 Register 29 0000H

CC2_CC30 FE7CH 3EH SFR CAPCOM2 Register 30 0000H

CC2_CC31 FE7EH 3FH SFR CAPCOM2 Register 31 0000H

Capture / Compare Unit 6 (CCU6)

CCU6_T12 E890H – IO Timer 12 Counter Register 0000H

CCU6_T12PR E892H – IO Timer 12 Period Register 0000H

CCU6_T12DTC

E894H – IO Dead-Time Control Register for Timer 12

0000H

CCU6_CC60R E898H – IO Capture/Compare Register (Ch. 0) 0000H

CCU6_CC61R E89AH – IO Capture/Compare Register (Ch. 1) 0000H

CCU6_CC62R E89CH – IO Capture/Compare Register (Ch. 2) 0000H

CCU6_CC60SR

E8A0H – IO Capture/Compare Shadow Register (Ch. 0)

0000H

CCU6_CC61SR


0000H

CCU6_CC62SR


0000H

CCU6_T13 E8B0H – IO Timer 13 Counter Register 0000H

CCU6_T13PR E8B2H – IO Timer 13 Period Register 0000H

CCU6_CC63R E8B4H – IO Compare Register for Timer 13 0000H

CCU6_CC63SR

E8B6H – IO Compare Shadow Register for Timer 13

0000H

CCU6_CMPSTAT

E8A8H – IO Compare State Register 0000H





Register Set

CCU6_CMPMODIF

E8AAH – IO Compare State Modification Register

0000H

CCU6_TCTR0 E8ACH – IO Timer Control Register 0 0000H

CCU6_TCTR2 E8AEH – IO Timer Control Register 2 0000H

CCU6_TCTR4 E8A6H – IO Timer Control Register 4 0000H

CCU6_MODCTR

E8C0H – IO Modulation Control Register 0000H

CCU6_TRPCTR

E8C2H – IO Trap Control Register 0000H

CCU6_PSLR E8C4H – IO Passive State Level Register 0000H

CCU6_T12MSEL

E8C6H – IO T12 Capture/Compare Mode Select Register

0000H

CCU6_MCMOUTS

E8CAH – IO Multi-Channel Mode Output Shadow Register

0000H

CCU6_MCMOUT

E8CCH – IO Multi-Channel Mode Output Register

0000H

CCU6_MCMCTR

E8CEH – IO Multi-Channel Mode Control Register

0000H

CCU6_IS E8D0H – IO Capture/Compare Interrupt Status Register

0000H

CCU6_ISS E8D2H – IO Capture/Compare Interrupt Status Set Register

0000H

CCU6_ISR E8D4H – IO Capture/Compare Interrupt Status Reset Register

0000H

CCU6_INP E8D6H – IO Capture/Compare Interrupt Node Pointer Register

3940H

CCU6_IEN E8D8H – IO Capture/Compare Interrupt Node Pointer Register

0000H

A/D Converter (ADC)

ADC_CON FFA0H D0H SFR A/D Converter Control Register 0000H

ADC_CON1 FFA6H D3H SFR A/D Converter Control Register 0000H

ADC_CTR0 FFBEH DFH SFR A/D Converter Control Register 0 1000H





Register Set

ADC_CTR2 F09CH 4EH ESFR A/D Converter Control Register 2 0000H

ADC_CTR2IN F09EH 4FH ESFR A/D Converter Injection Control Register 2

0000H

ADC_DAT FEA0H 50H SFR A/D Converter Result Register 0000H

ADC_DAT2 F0A0H 50H ESFR A/D Converter 2 Result Register 0000H

Interrupt Control

SSC0_TIC FF72H B9H SFR SSC0 Transmit Interrupt Control Register

0000H

SSC0_RIC FF74H BAH SFR SSC0 Receive Interrupt Control Register

0000H

SSC0_EIC FF76H BBH SFR SSC0 Error Interrupt Control Register

0000H

SSC1_TIC F1AAH D5H ESFR SSC1 Transmit Interrupt Control Register

0000H

SSC1_RIC F1ACH D6H SFR SSC1 Receive Interrupt Control Register

0000H

SSC1_EIC F1AEH D7H ESFR SSC1 Error Interrupt Control Register

0000H

ASC0_TIC FF6CH B6H SFR ASC0 Transmit Interrupt Control Register

0000H

ASC0_RIC FF6EH B7H SFR ASC0 Receive Interrupt Control Register

0000H

ASC0_EIC FF70H B8H SFR ASC0 Error Interrupt Control Register

0000H

ASC0_TBIC F19CH CEH ESFR ASC0 Transmit Buffer Interrupt Control Register

0000H

ASC0_ABIC F15CH AEH ESFR ASC0 Autobaud Interrupt Control Register

0000H

ASC1_TIC F182H C1H ESFR ASC1 Transmit Interrupt Control Register

0000H

ASC1_RIC F18AH C5H ESFR ASC1 Receive Interrupt Control Register

0000H





Register Set

ASC1_EIC F192H C9H ESFR ASC1 Error Interrupt Control Register

0000H

ASC1_TBIC F150H A8H ESFR ASC1 Transmit Buffer Interrupt Control Register

0000H

ASC1_ABIC F1BAH DDH ESFR ASC1 Autobaud Interrupt Control Register

0000H

GPT12E_T2IC

FF60H B0H SFR GPT12E Timer 2 Interrupt Control Register

0000H

GPT12E_T3IC


0000H

GPT12E_T4IC


0000H

GPT12E_T5IC


0000H

GPT12E_T6IC


0000H

GPT12E_CRIC

FF6AH B5H SFR GPT12E CAPREL Interrupt Control Register

0000H

CC1_T0IC FF9CH CEH SFR CAPCOM Timer 0 Interrupt Control Register

0000H

CC1_T1IC FF9EH CFH SFR CAPCOM Timer 1 Interrupt Control Register

0000H

CC2_T7IC F17AH BDH ESFR CAPCOM Timer 7 Interrupt Control Register

0000H

CC2_T8IC F17CH BEH ESFR CAPCOM Timer 8 Interrupt Control Register

0000H

CC1_CC0IC FF78H BCH SFR CAPCOM Register 0 Interrupt Control Register

0000H

CC1_CC1IC FF7AH BDH SFR CAPCOM Register 1 Interrupt Control Register

0000H

CC1_CC2IC FF7CH BEH SFR CAPCOM Register 2 Interrupt Control Register

0000H





Register Set

CC1_CC3IC FF7EH BFH SFR CAPCOM Register 3 Interrupt Control Register

0000H

CC1_CC4IC FF80H C0H SFR CAPCOM Register 4 Interrupt Control Register

0000H


0000H


0000H


0000H


0000H

CC1_CC9IC FF8AH C5H SFR CAPCOM Register 9 Interrupt Control Register

0000H

CC1_CC10IC FF8CH C6H SFR CAPCOM Register 10 Interrupt Control Register

0000H

CC1_CC11IC FF8EH C7H SFR CAPCOM Register 11 Interrupt Control Register

0000H


0000H


0000H

CC1_CC14IC FF94H CAH SFR CAPCOM Register 14 Interrupt Control Register

0000H

CC1_CC15IC FF96H CBH SFR CAPCOM Register 15 Interrupt Control Register

0000H

CC2_CC16IC F160H B0H ESFR CAPCOM Register 16 Interrupt Control Register

0000H


0000H


0000H





Register Set


0000H


0000H

CC2_CC21IC F16AH B5H ESFR CAPCOM Register 21 Interrupt Control Register

0000H

CC2_CC22IC F16CH B6H ESFR CAPCOM Register 22 Interrupt Control Register

0000H

CC2_CC23IC F16EH B7H ESFR CAPCOM Register 23 Interrupt Control Register

0000H


0000H


0000H

CC2_CC26IC F174H BAH ESFR CAPCOM Register 26 Interrupt Control Register

0000H

CC2_CC27IC F176H BBH ESFR CAPCOM Register 27 Interrupt Control Register

0000H

CC2_CC28IC F178H BCH ESFR CAPCOM Register 28 Interrupt Control Register

0000H

CC2_CC29IC F184H C2H ESFR CAPCOM Register 29 Interrupt Control Register

0000H

CC2_CC30IC F18CH C6H ESFR CAPCOM Register 30 Interrupt Control Register

0000H

CC2_CC31IC F194H CAH ESFR CAPCOM Register 31 Interrupt Control Register

0000H

CCU6_IC F140H A0H ESFR Interrupt Control Register for other Interrupts (module intr. node I3)

0000H

CCU6_EIC F188H C4H ESFR Interrupt Control Register for Emergency Interrupts(module intr. node I2)

0000H

CCU6_T12IC F190H C8H ESFR Interrupt Control Register for T12 Interrupts (module intr. node I0)

0000H





Register Set

CCU6_T13IC F198H CCH ESFR Interrupt Control Register for T13 Interrupts (module intr. node I1)

0000H

ADC_CIC FF98H CCH SFR A/D Converter End of Conversion Interrupt Control Register

0000H

ADC_EIC FF9AH CDH SFR A/D Converter Overrun Error Interrupt Control Register

0000H

CAN_0IC F196H CBH ESFR TwinCAN Interrupt Control Register 0

0000H

CAN_1IC F142H A1H ESFR TwinCAN Interrupt Control Register 1

0000H


0000H


0000H


0000H

CAN_5IC F14AH A5H ESFR TwinCAN Interrupt Control Register 5

0000H

CAN_6IC F14CH A6H ESFR TwinCAN Interrupt Control Register 6

0000H

CAN_7IC F14EH A7H ESFR TwinCAN Interrupt Control Register 7

0000H

EOPIC F180H C0H ESFR End of PEC Subchannel Interrupt Control Register

0000H

PLL_IC F19EH CFH ESFR PLL Interrupt Control Register 0000H

RTC_IC F1A0H D0H ESFR RTC Interrupt Control Register 0000H

Ports

PICON F1C4H E2H ESFR Port Input Threshold Control Register

0000H

POCON0L F080H 40H ESFR P0L Output Control Register 0000H

POCON0H F082H 41H ESFR P0H Output Control Register 0000H

POCON1L F084H 42H ESFR P1L Output Control Register 0000H

POCON1H F086H 43H ESFR P1H Output Control Register 0000H





Register Set

POCON2 F088H 44H ESFR P2 Output Control Register 0000H

POCON3 F08AH 45H ESFR P3 Output Control Register 0000H

POCON4 F08CH 46H ESFR P4 Output Control Register 0000H

POCON6 F08EH 47H ESFR P6 Output Control Register 0000H

POCON9 F094H 4AH ESFR P9 Output Control Register 0000H

POCON20 F0AAH 55H ESFR P20 Output Control Register 0000H

P0L FF00H 80H SFR PORT0 Low Register 0000H

P0H FF02H 81H SFR PORT0 High Register 0000H

DP0L F100H 80H ESFR P0L Direction Control Register 0000H

DP0H F102H 81H ESFR P0H Direction Control Register 0000H

P1L FF04H 82H SFR PORT1 Low Register 0000H

P1H FF06H 83H SFR PORT1 High Register 0000H

DP1L F104H 82H ESFR P1L Direction Control Register 0000H

DP1H F106H 83H ESFR P1H Direction Control Register 0000H

ALTSEL0P1L F130H 98H ESFR P1L Alternate Select Register 0 0000H

ALTSEL0P1H F120H 90H ESFR P1H Alternate Select Register 0 0000H

P2 FFC0H E0H SFR Port 2 Data Register 0000H

DP2 FFC2H E1H SFR P2 Direction Control Register 0000H

ODP2 F1C2H E1H ESFR P2 Open Drain Control Register 0000H

ALTSEL0P2 F122H 91H ESFR P2 Alternate Select Register 0 0000H


DP3 FFC6H E3H SFR P3 Direction Control Register 0000H

ODP3 F1C6H E3H ESFR P3 Open Drain Control Register 0000H




DP4 FFCAH E5H SFR P4 Direction Control Register 0000H

ODP4 F1CAH E5H ESFR P4 Open Drain Control Register 0000H

ALTSEL0P4 F12AH 95H ESFR P4 Alternate Select Register 0 0000H





Register Set

ALTSEL1P4 F136H 9BH ESFR P4 Alternate Select Register 1 0000H

P5 FFA2H D1H SFR Port 5 Data Register 0000H

P5DIDIS FFA4H D2H SFR Port 5 Digital Input Disable Register

0000H

P9 FF16H 8BH SFR Port 9 Data Register 0000H

DP9 FF18H 8CH SFR P9 Direction Control Register 0000H

ODP9 FF1AH 8DH SFR P9 Open Drain Control Register 0000H

ALTSEL0P9 F138H 9CH ESFR P9 Alternate Select Register 0 0000H

ALTSEL1P9 F13AH 9DH ESFR P9 Alternate Select Register 1 0000H

P20 FFB4H DAH SFR Port 20 Data Register 0000H

DP20 FFB6H DBH SFR P20 Direction Control Register 0000H





Register Set

22.2 LXBUS Peripherals

Note: The address space for LXBUS peripherals is assigned to Segment 32; it may bechanged by user SW.

Table 22-2 LXBUS Register Listing

Short Name Physical Address

Description Reset Value

TwinCAN

CAN_PISEL 20’0004H TwinCAN Port Input Select Register 0000H

CAN_ACR 20’0200H Node A Control Register 0001H

CAN_ASR 20’0204H Node A Status Register 0000H

CAN_AIR 20’0208H Node A Interrupt Pending Register 0000H

CAN_ABTRL 20’020CH Node A Bit Timing Register Low 0000H

CAN_ABTRH 20’020EH Node A Bit Timing Register High 0000H

CAN_AGINP 20’0210H Node A Global Int. Node Pointer Register 0000H

CAN_AFCRL 20’0214H Node A Frame Counter Register Low 0000H

CAN_AFCRH 20’0216H Node A Frame Counter Register High 0000H

CAN_AIMRL0 20’0218H Node A INTID Mask Register 0 Low 0000H

CAN_AIMRH0 20’021AH Node A INTID Mask Register 0 High 0000H

CAN_AIMR4 20’021CH Node A INTID Mask Register 4 0000H

CAN_AECNTL 20’0220H Node A Error Counter Register Low 0000H

CAN_AECNTH 20’0222H Node A Error Counter Register High 0060H

CAN_BCR 20’0240H Node B Control Register 0001H

CAN_BSR 20’0244H Node B Status Register 0000H

CAN_BIR 20’0248H Node B Interrupt Pending Register 0000H

CAN_BBTRL 20’024CH Node B Bit Timing Register Low 0000H

CAN_BBTRH 20’024EH Node B Bit Timing Register High 0000H

CAN_BGINP 20’0250H Node B Global Int. Node Pointer Register 0000H

CAN_BFCRL 20’0254H Node B Frame Counter Register Low 0000H

CAN_BFCRH 20’0256H Node B Frame Counter Register High 0000H

CAN_BIMRL0 20’0258H Node B INTID Mask Register 0 Low 0000H

CAN_BIMRH0 20’025AH Node B INTID Mask Register 0 High 0000H

CAN_BIMR4 20’025CH Node B INTID Mask Register 4 0000H



Register Set

The base address of each Message Object n, where n = 0-31, is listed in Table 22-3.The offset address of each register in Message Object n is given in Table 22-4.

CAN_BECNTL 20’0260H Node B Error Counter Register Low 0000H

CAN_BECNTH 20’0262H Node B Error Counter Register High 0060H

CAN_RXIPNDL 20’0284H Receive Interrupt Pending Register Low 0000H

CAN_RXIPNDH 20’0286H Receive Interrupt Pending Register High 0000H

CAN_TXIPNDL 20’0288H Transmit Interrupt Pending Register Low 0000H

CAN_TXIPNDH 20’028AH Transmit Interrupt Pending Register High 0000H

Interrupt Control

CAN_0IC 00’F196H1) TwinCAN Interrupt Control Register 0 0000H





CAN_5IC 00’F14AH1) TwinCAN Interrupt Control Register 5 0000H

CAN_6IC 00’F14CH1) TwinCAN Interrupt Control Register 6 0000H

CAN_7IC 00’F14EH1) TwinCAN Interrupt Control Register 7 0000H

1) This register is located in the ESFR area.

Table 22-3 Base Address of Message Objects

Message Object Number Base Address

Message Object 0 20’0300H





Message Object 5 20’03A0H

Message Object 6 20’03C0H

Message Object 7 20’03E0H


Table 22-2 LXBUS Register Listing (cont’d)

Short Name Physical Address




Register Set
























Table 22-3 Base Address of Message Objects (cont’d)

Message Object Number Base Address



Register Set

Note: n = 0 to 31

Table 22-4 Offset Address of Message Object Registers

Short Name Offset Address


CAN_MSGDRLn0

00H Message Object n Data Register 0 Low 0000H

CAN_MSGDRHn0

02H Message Object n Data Register 0 High 0000H

CAN_MSGDRLn4

04H Message Object n Data Register 4 Low 0000H

CAN_MSGDRHn4

06H Message Object n Data Register 4 High 0000H

CAN_MSGARLn

08H Message Object n Arbitration Register Low

0000H

CAN_MSGARHn

0AH Message Object n Arbitration Register High

0000H

CAN_MSGAMRLn

0CH Message Object n Acceptance Mask Register Low

0000H

CAN_MSGAMRHn

0EH Message Object n Acceptance Mask Register High

0000H

CAN_MSGCTRLn

10H Message Object n Control Register Low 0000H

CAN_MSGCTRHn

12H Message Object n Control Register High 0000H

CAN_MSGCFGLn

14H Message Object n Configuration Register Low

0000H

CAN_MSGCFGHn

16H Message Object n Configuration Register High

0000H

CAN_MSGFGCRLn

18H Message Object n FIFO/Gateway Control Register Low

0000H

CAN_MSGFGCRHn

1AH Message Object n FIFO/Gateway Control Register High

0000H



Keyword Index

Keyword IndexThis section lists a number of keywords which refer to specific details of the XC164 interms of its architecture, its functional units or functions. This helps to quickly find theanswer to specific questions about the XC164.

This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. Foryour convenience this keyword index (and also the table of contents) refers to bothvolumes, so you can immediately find the reference to the desired section in thecorresponding document ([1] or [2]).

BG 19-22 [2]
AAcronyms 1-9 [1]Adapt Mode 6-21 [1]ADC 2-22 [1], 16-1 [2]ADC_CIC, ADC_EIC 16-21 [2]ADC_CON 16-3 [2]ADC_CON1 16-4 [2]ADC_CTR0 16-5 [2]ADC_CTR2 16-7 [2]ADC_CTR2IN 16-7 [2]Address
Boundaries 3-15 [1]Mapping 3-3 [1]Segment 6-19 [1]

Addressing ModesCoREG Addressing Mode 4-51 [1]DSP Addressing Modes 4-47 [1]Indirect Addressing Modes 4-45 [1]Long Addressing Modes 4-41 [1]Short Addressing Modes 4-39 [1]

Alternate Port Functions 7-8 [1]ALU 4-58 [1]Analog/Digital Converter 16-1 [2]Arbitration of conversions 16-16 [2]ASC 19-1 [2]

ASCx_EIC, ASCx_RIC 19-35 [2]ASCx_TIC, ASCx_TBIC 19-35 [2]Autobaud Detection 19-27 [2]Error Detection 19-34 [2]Features and Functions 19-1 [2]IrDA Frames 19-8 [2]Register

RBUF 19-12 [2], 19-20 [2]TBUF 19-9 [2], 19-20 [2]

Transmit FIFO 19-9 [2]ASCx_BG 19-42 [2]ASCx_CON 19-40 [2]ASCx_FDV 19-43 [2]Auto Scan conversion 16-12 [2]Autobaud Detection 19-27 [2]

BBANKSELx 5-33 [1]Baudrate

ASC0 19-22 [2]Bootstrap Loader 10-5 [1]CAN 21-56 [2]

BitHandling 4-61 [1]Manipulation Instructions 12-2 [1]protected 2-32 [1], 4-62 [1]reserved 2-16 [1]

Block Diagram ITC / PEC 5-3 [1]Bootstrap Loader 6-21 [1], 10-1 [1]Boundaries 3-15 [1]Bus

ASC 19-1 [2]CAN 2-25 [1]Mode Configuration 6-20 [1]SSC 20-1 [2]

CCalibration 16-17 [2]

User’s Manual i-1 V2.1, 2004-03


Keyword Index

CANacceptance filtering 21-16 [2]analysing mode 21-7 [2]arbitration 21-16 [2]baudrate 21-56 [2]bit timing 21-9 [2], 21-56 [2]bus off

recovery sequence 21-4 [2]status bit 21-51 [2]

CAN siehe TwinCAN 21-1 [2]error counters 21-55 [2]error handling 21-11 [2]error warning level 21-55 [2]frame counter/time stamp 21-55 [2],21-58 [2]Interface 2-25 [1]single data transfer 21-23 [2]

CAPCOM 2-18 [1]CAPCOM12 2-16 [1]

Capture Mode 17-13 [2]Counter Mode 17-8 [2]

CAPREL 14-54 [2]Capture Mode

GPT1 14-26 [2]GPT2 (CAPREL) 14-46 [2]

Capture/Compare Registers 17-10 [2]CC1_DRM, CC2_DRM 17-23 [2]CC1_IOC, CC2_IOC 17-29 [2]CC1_M0-3 17-10 [2]CC1_OUT, CC2_OUT 17-25 [2]CC1_SEE, CC2_SEE 17-28 [2]CC1_SEM, CC2_SEM 17-27 [2]CC1_T01CON 17-5 [2]CC1_T0IC 17-9 [2]CC1_T1IC 17-9 [2]CC2_M4-7 17-11 [2]CC2_T78CON 17-5 [2]CC2_T7IC 17-9 [2]CC2_T8IC 17-9 [2]CC63R 18-40 [2]CC63SR 18-40 [2]CC6xR 18-18 [2]CC6XSR 18-19 [2]

CCU6xIC 18-79 [2]CCxIC 17-34 [2]Chip Select

Configuration 6-19 [1]Clock

generation 2-29 [1]generator modes 6-18 [1]output signal 6-38 [1]

CMPMODIF 18-46 [2]CMPSTAT 18-45 [2]Command sequences

(Flash) 3-19 [1](ROM) 3-39 [1]

Concatenation of Timers 14-22 [2],14-45 [2]

ConfigurationAddress 6-19 [1]Bus Mode 6-20 [1]Chip Select 6-19 [1]default 6-23 [1]PLL 6-18 [1]Reset 6-14 [1]Reset Output 6-22 [1]special modes 6-21 [1]Write Control 6-20 [1]

ContextPointer Updating 4-34 [1]Switch 4-33 [1]Switching 5-32 [1]

Conversionanalog/digital 16-1 [2]Arbitration 16-16 [2]Auto Scan 16-12 [2]timing control 16-18 [2]

Count direction 14-6 [2], 14-35 [2]Counter 14-20 [2], 14-43 [2]Counter Mode (GPT1) 14-10 [2], 14-39 [2]CP 4-36 [1]CPU 2-2 [1], 4-1 [1]CPUCON1 4-26 [1]CPUCON2 4-27 [1]CRIC 14-55 [2]CSP 4-38 [1]



Keyword Index

DData Management Unit (Introduction)

2-9 [1]Data Page 4-42 [1]

boundaries 3-15 [1]Data SRAM 3-9 [1]Default startup configuration 6-23 [1]Development Support 1-8 [1]Direction

count 14-6 [2], 14-35 [2]Disable

Interrupt 5-29 [1]Division 4-63 [1]Double-Register Compare 17-22 [2]DP0L, DP0H 7-10 [1]DP1L, DP1H 7-14 [1]DP20 7-60 [1]DP3 7-25 [1]DP4 7-38 [1], 21-85 [2]DP9 7-51 [1], 21-87 [2]DPP 4-42 [1]Driver characteristic (ports) 7-4 [1]DSTPx 5-23 [1]Dual-Port RAM 3-9 [1]

EEBC

Bus Signals 9-3 [1]Memory Table 9-23 [1]

EBCMOD0 9-12 [1]Edge characteristic (ports) 7-5 [1]EMUCON 6-47 [1]Enable

Interrupt 5-29 [1]End of PEC Interrupt Sub Node 5-28 [1]EOPIC 5-27 [1]Erase command (Flash) 3-21 [1]Error correction 3-25 [1]Error Detection

ASC 19-34 [2]SSC 20-14 [2]

EXICON 5-37 [1]

EXISEL0 5-38 [1]EXISEL1 5-38 [1]External

Bus 2-13 [1]Fast interrupts 5-37 [1]Interrupt pulses 5-40 [1]Interrupt source control 5-37 [1]Interrupts 5-35 [1]Interrupts during sleep mode 5-39 [1]

FFast external interrupts 5-37 [1]FINT0ADDR 5-16 [1]FINT0CSP 5-17 [1]FINT1ADDR 5-16 [1]FINT1CSP 5-17 [1]Flags 4-57 [1]–4-60 [1]Flash

command sequences 3-19 [1]memory 3-11 [1]memory mapping 3-16 [1]waitstates 3-43 [1]

FOCON 6-39 [1]Frequency

output signal 6-38 [1]FSR 3-32 [1]

GGated timer mode (GPT1) 14-9 [2]Gated timer mode (GPT2) 14-38 [2]GPR 3-6 [1]GPT 2-19 [1]GPT1 14-2 [2]GPT12E_CAPREL 14-54 [2]GPT12E_T2,-T3,-T4 14-29 [2]GPT12E_T2CON 14-15 [2]GPT12E_T2IC,-T3IC,-T4IC 14-30 [2]GPT12E_T3CON 14-4 [2]GPT12E_T4CON 14-15 [2]GPT12E_T5,-T6 14-54 [2]GPT12E_T5CON 14-40 [2]GPT12E_T5IC,-T6IC,-CRIC 14-55 [2]GPT12E_T6CON 14-33 [2]



Keyword Index

GPT2 14-31 [2]

HHardware

Traps 5-43 [1]

IIDCHIP 6-63 [1]Idle Mode 6-53 [1]IDMANUF 6-63 [1]IDMEM 6-64 [1]IDPROG 6-64 [1]IDX0, IDX1 4-47 [1]IEN 18-77 [2]IMB

block diagram 3-40 [1]control functions 3-45 [1]memories

address map 3-41 [1]wait states 3-45 [1]

IMBCTR 3-45 [1]Incremental Interface Mode (GPT1)

14-11 [2]Indication of reset source 6-45 [1]INP 18-78 [2]Instruction 12-1 [1]

Bit Manipulation 12-2 [1]Pipeline 4-11 [1]protected 12-6 [1]

InterfaceASC 19-1 [2]CAN 2-25 [1]External Bus 9-1 [1]SSC 20-1 [2]

InterruptArbitration 5-4 [1]during sleep mode 5-39 [1]Enable/Disable 5-29 [1]External 5-35 [1]Fast external 5-37 [1]input timing 5-40 [1]Jump Table Cache 5-16 [1]Latency 5-41 [1]

Node Sharing 5-34 [1]Priority 5-7 [1]Processing 5-1 [1]RTC 15-12 [2]source control 5-37 [1]Sources 5-12 [1]System 2-8 [1], 5-2 [1]Vectors 5-12 [1]

Interrupt HandlingCAN transfer 21-6 [2]

IP 4-38 [1]IrDA Frames ASC 19-8 [2]IS 18-72 [2]ISR 18-76 [2]ISS 18-75 [2]

LLatency

Interrupt, PEC 5-41 [1]LXBus 2-13 [1]

MMAH, MAL 4-69 [1]MAR 3-26 [1]Margin check 3-25 [1]MCMCTR 18-60 [2]MCMOUT 18-58 [2]MCMOUTS 18-57 [2]MCW 4-66 [1]MDC 4-64 [1]MDH 4-63 [1]MDL 4-64 [1]Memory 2-10 [1]

Areas (Data) 3-8 [1]Areas (Program) 3-10 [1]DPRAM 3-9 [1]DSRAM 3-9 [1]External 3-14 [1]Flash 3-11 [1]Program Flash 3-16 [1]Program ROM 3-37 [1]PSRAM 3-11 [1]

MODCTR 18-49 [2]



Keyword Index

MRW 4-72 [1]MSW 4-70 [1]Multiplication 4-63 [1]

NNMI 5-1 [1], 5-48 [1]Noise filter (Ext. Interrupts) 5-39 [1]

OOCDS

Requests 5-40 [1]ODP3 7-26 [1]ODP4 7-39 [1]ODP9 7-52 [1]ONES 4-74 [1]Open Drain Mode 7-3 [1]OPSEN 6-48 [1]Oscillator

circuitry 6-27 [1]measurement 6-27 [1]Watchdog 6-22 [1], 6-37 [1]

PP0L, P0H 7-9 [1]P1L, P1H 7-13 [1]P3 7-25 [1]P4 7-38 [1]P5 7-47 [1], 7-48 [1]P8 7-51 [1], 7-60 [1]PEC 2-10 [1], 5-18 [1]

Latency 5-41 [1]Transfer Count 5-19 [1]

PEC pointers 3-7 [1]PECCx 5-19 [1]PECISNC 5-27 [1]PECSEGx 5-23 [1]Peripheral

Event Controller --> PEC 5-18 [1]Register Set 22-1 [2]Summary 2-14 [1]

Phase Locked Loop (->PLL) 6-26 [1]PICON 7-2 [1]Pins 8-1 [1]

Pipeline 4-11 [1]PLL 6-18 [1], 6-26 [1]PLL_IC 6-37 [1]PLLCON 6-31 [1]POCON* 7-6 [1]Port 2-27 [1]Ports

Alternate Port Functions 7-8 [1]Driver characteristic 7-4 [1]Edge characteristic 7-5 [1]

Power Management 2-29 [1], 6-53 [1]PROCON 3-28 [1]Program Management Unit (Introduction)

2-9 [1]Programming command (Flash) 3-21 [1]Protected

Bits 2-32 [1], 4-62 [1]instruction 12-6 [1]

Protectioncommands (Flash) 3-23 [1]features (Flash) 3-27 [1]features (ROM) 3-37 [1]

PSLR 18-68 [2]PSW 4-57 [1]

QQR0 4-46 [1]QR1 4-46 [1]QX0, QX1 4-48 [1]

RRAM

data SRAM 3-9 [1]dual ported 3-9 [1]program/data 3-11 [1]status after reset 6-7 [1]

Real Time Clock (->RTC) 2-21 [1], 15-1 [2]Register Areas 3-4 [1]Register map

TwinCAN module 21-47 [2]Register Table

LXBUS Peripherals 22-15 [2]PD+BUS Peripherals 22-1 [2]



Keyword Index

RELH, RELL 15-9 [2]Reserved bits 2-16 [1]Reset 6-2 [1]

Configuration 6-14 [1]Output 6-9 [1]Source indication 6-45 [1]Values 6-6 [1]

ROM 3-37 [1]command sequences 3-39 [1]

RSTCFG 6-16 [1]RSTCON 6-24 [1]RTC 2-21 [1], 15-1 [2]RTC_CON 15-5 [2]RTC_IC 15-13 [2]RTC_ISNC 15-13 [2]RTCH, RTCL 15-8 [2]

SSCUSLC 6-51 [1]SCUSLS 6-50 [1]Security

features (Flash) 3-27 [1]features (ROM) 3-37 [1]

SegmentAddress 6-19 [1]boundaries 3-15 [1]

Segmentation 4-37 [1]Self-calibration 16-17 [2]Serial Interface 2-23 [1], 2-24 [1]

ASC 19-1 [2]Asynchronous 19-5 [2]CAN 2-25 [1]SSC 20-1 [2]Synchronous 19-19 [2]

SFR 3-5 [1]Sharing

Interrupt Nodes 5-34 [1]Sleep mode 6-55 [1]Software

Traps 5-43 [1]Source

Interrupt 5-12 [1]Reset 6-45 [1]

SP 4-54 [1]Special operation modes (config.) 6-21 [1]SPSEG 4-54 [1]SRAM

Data 3-9 [1]SRCPx 5-23 [1]SSC 20-1 [2]

Baudrate generation 20-12 [2]Block diagram 20-3 [2]Continous transfer operation 20-12 [2]Error detection 20-14 [2]Full duplex operation 20-8 [2]General Operation 20-1 [2]Half duplex operation 20-11 [2]Interrupts 20-14 [2]

SSCx_CON 20-4 [2], 20-5 [2]Stack 3-12 [1], 4-53 [1]Startup Configuration 6-14 [1]STKOV 4-56 [1]STKUN 4-56 [1]SYSCON0 6-42 [1]SYSCON1 6-43 [1]SYSCON3 6-57 [1]SYSSTAT 6-44 [1]

TT0IC 17-9 [2]T12 18-6 [2]T12DTC 18-23 [2]T12MSEL 18-20 [2]T12PR 18-6 [2]T13 18-31 [2]T13PR 18-31 [2]T1IC 17-9 [2]T2, T3, T4 14-29 [2]T2CON 14-15 [2]T2IC, T3IC, T4IC 14-30 [2]T3CON 14-4 [2]T4CON 14-15 [2]T5, T6 14-54 [2]T5CON 14-40 [2]T5IC, T6IC 14-55 [2]T6CON 14-33 [2]



Keyword Index

T7IC 17-9 [2]T8IC 17-9 [2]TCTR0 18-41 [2]TCTR2 18-43 [2]TCTR4 18-44 [2]TFR 5-45 [1]Timer 14-2 [2], 14-31 [2]

Auxiliary Timer 14-15 [2], 14-40 [2]Concatenation 14-22 [2], 14-45 [2]Core Timer 14-4 [2], 14-33 [2]Counter Mode (GPT1) 14-10 [2],14-39 [2]Gated Mode (GPT1) 14-9 [2]Gated Mode (GPT2) 14-38 [2]Incremental Interface Mode (GPT1)14-11 [2]Mode (GPT1) 14-8 [2]Mode (GPT2) 14-37 [2]

Tools 1-8 [1]Transmit FIFO ASC 19-9 [2]Traps 5-43 [1]TRPCTR 18-63 [2]TwinCAN

FIFObase object 21-24 [2]circular buffer 21-26 [2]configuration 21-73 [2]for CAN messages 21-24 [2]gateway control 21-73 [2]slave objects 21-26 [2]

framescounter 21-8 [2]handling 21-17 [2]

gatewayconfiguration 21-73 [2]normal mode 21-29 [2]shared mode 21-36 [2]with FIFO 21-33 [2]

initialization 21-40 [2]interrupts

indication/INTID 21-13 [2],21-53 [2]node pointer/request compressor

21-5 [2]loop-back mode 21-44 [2]message handling 21-15 [2]

FIFO 21-24 [2]gateway overview 21-28 [2]gateway+FIFO 21-33 [2]normal gateway 21-29 [2]shared gateway 21-36 [2]transfer control 21-41 [2]

message interrupts 21-13 [2]message object

configuration 21-71 [2]control bits 21-68 [2]interrupt indication 21-13 [2]interrupts 21-13 [2]register description 21-64 [2]transfer handling 21-17 [2]

node control 21-7 [2]node interrupts 21-11 [2], 21-12 [2]node selection 21-71 [2]overview 21-1 [2]register map 21-47 [2]registers (global)

receive interrupt pending 21-80 [2]transmit interrupt pending 21-81 [2]

registers (message specific)acceptance mask 21-67 [2]arbitration (identifier) 21-66 [2]configuration 21-71 [2]control 21-68 [2]data 21-64 [2]

registers (node specific)bit timing 21-56 [2]control 21-49 [2]error counter 21-55 [2]frame counter 21-58 [2]global interrupt node pointer21-61 [2]interrupt pending 21-53 [2]INTID mask 21-62 [2]status 21-51 [2]

single transmission 21-45 [2]single-shot mode 21-23 [2]



Keyword Index

transfer interrupts 21-6 [2]TwinCAN Registers (short names)

ABTRH 21-56 [2]ABTRL 21-56 [2]ACR 21-49 [2]AECNTH 21-54 [2]AECNTL 21-54 [2]AFCRH 21-58 [2]AFCRL 21-58 [2]AGINP 21-61 [2]AIMR0H 21-62 [2]AIMR0L 21-62 [2]AIMR4 21-63 [2]AIR 21-53 [2]ASR 21-51 [2]BBTRH 21-56 [2]BBTRL 21-56 [2]BCR 21-49 [2]BECNTH 21-54 [2]BECNTL 21-54 [2]BFCRH 21-58 [2]BFCRL 21-58 [2]BGINP 21-61 [2]BIMR0H 21-62 [2]BIMR0L 21-62 [2]BIMR4 21-63 [2]BIR 21-53 [2]BSR 21-51 [2]MSGAMRHn 21-67 [2]MSGAMRLn 21-67 [2]MSGARHn 21-66 [2]MSGARLn 21-66 [2]MSGCFGHn 21-71 [2]MSGCFGLn 21-71 [2]MSGCTRHn 21-68 [2]MSGCTRLn 21-68 [2]MSGDRH0 21-64 [2]MSGDRH4 21-65 [2]MSGDRL0 21-64 [2]MSGDRL4 21-65 [2]MSGFGCRHn 21-74 [2]MSGFGCRLn 21-74 [2]RXIPNDH 21-80 [2]

RXIPNDL 21-80 [2]TXIPNDH 21-81 [2]TXIPNDL 21-81 [2]

VVECSEG 5-11 [1]

WWaitstates

Flash 3-43 [1]Watchdog 2-26 [1], 6-58 [1]

after reset 6-7 [1]Oscillator 6-22 [1], 6-37 [1]

WDT 6-59 [1]WDTCON 6-61 [1]

ZZEROS 4-74 [1]


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Documents

Infineon XC164-16 User's Manual (Peripheral Units) · User’s Manual, V2.1, March 2004 Microcontrollers Never stop thinking. XC164-16 16-Bit Single-Chip Microcontroller with C166SV2