Aim : To study diode charachteristic

Circuit Diagram:

Code:

* Diode Charachteristic

V1 1 0 DC 0VD1 1 0 D1N4148.MODEL D1N4148 D (VJ=0.2V BV=3V).DC V1 -4 1.5 0.01.PROBE I(D1).END

Aim : To study the variation of diode charachteristic with

temperature.

Circuit Diagram:

Code:

* Diode Charachteristic WITH TEMPERATURE

V1 1 0 DC 0VD1 1 0 D1N4148.MODEL D1N4148 D (VJ=0.2V BV=3V).DC V1 -4 1.5 0.01.TEMP 10 30 60.PROBE I(D1).END

Aim : To find the Q Point of a diode

Circuit Diagram:

Code:

* LOAD LINE ANALYSIS OF A DIODE

V1 1 0 DC 0VR1 1 2 100D1 2 0 D1N4148.MODEL D1N4148 D.DC V1 0 2 0.001.PROBE.END

Aim : To study Half Wave Rectifier.

Circuit Diagram:

Code:

*Half Wave Rectifier

V1 1 0 SIN(0 10 50Hz)R1 1 2 10D1 2 0 D1N4148.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE.END

Aim : To study Bridge Rectifier.

Circuit Diagram:

Code:

* Full Wave Rectifier

V1 1 0 SIN(0 10V 50Hz)D1 2 1 D1N4148D2 1 3 D1N4148D3 2 0 D1N4148D4 0 3 D1N4148R1 3 2 1k.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE.END

Aim : To study Center tap full wave rectifier.

Circuit Diagram:

Code:

*Center tap RectifierV1 1 0 SIN(0 10V 50Hz)R2 1 2 0.1L3 2 0 2MHL1 3 0 1MHL2 0 5 1MHK L3 L1 L2 1D1 3 4 D1N4148R1 4 0 10D2 5 4 D1N4148.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(4).END

Aim : To study a simple clipper circuit.

Circuit Diagram:

Code:

* Simple clipperV1 1 0 SIN(0 50V 50Hz)D1 2 1 D1N4148R1 2 0 10.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study a biased Clipper I

Circuit Diagram:

Code:

*Biased Clipper 1V1 1 0 SIN(0 50V 50Hz)V2 1 2 DC 10D1 3 2 D1N4148R1 3 0 100.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(3).END

Aim : To study a biased Clipper Circuit II

Circuit Diagram:

Code:

*Biased Clipper 2V1 1 0 SIN(0 50V 50Hz)V2 1 2 DC -10D1 3 2 D1N4148R1 3 0 100.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(3).END

Aim : To study a simple parallel clipper.

Circuit Diagram:

Code:

*Simple parallel clipper 1V1 1 0 SIN(0 50V 50Hz)R1 1 2 10D1 2 0 D1N4148.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study a biaed parallel clipper I

Circuit Diagram:

Code:

*Biased Parallel clipper 1V1 1 0 SIN(0 50V 50Hz)R1 1 2 10D1 2 3 D1N4148.MODEL D1N4148 DV2 3 0 DC 10.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study a biaed parallel clipper II

Circuit Diagram:

Code:

*Biased Parallel clipper 2V1 1 0 SIN(0 50V 50Hz)R1 1 2 10D1 2 3 D1N4148.MODEL D1N4148 DV2 3 0 DC -10.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : Best Parallel biaed circuit

Circuit Diagram:

Code:

*Biased parallel bestV1 1 0 SIN(0 50V 50Hz)R1 1 2 10D1 2 4 D1N4148V2 4 0 DC 10VD2 5 2 D1N4148V3 0 5 DC 5V.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study a simple clamper.

Circuit Diagram:

Code:

*Simple ClamperV1 1 0 PULSE(-20V 20V 0 0 0 0.5s 1s)C1 1 2 10uFD1 2 0 D1N4148R1 2 0 10MEG.MODEL D1N4148 D.TRAN 0.001 3 0 0.001.PROBE V(1) V(2).END

Aim : To study a simple clamper with a sin source.

Circuit Diagram:

Code:

*Simple Clamper with sin sourceV1 1 0 SIN(0 20V 50Hz)C1 1 2 10uFD1 2 0 D1N4148R1 2 0 10MEG.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study a biased clamper circuit.

Circuit Diagram:

Code:

*Biased ClamperV1 1 0 PULSE(-20V 20V 0 0 0 0.5s 1s)C1 1 2 10uFD1 2 3 D1N4148V2 3 0 DC 5VR1 2 0 10MEG.MODEL D1N4148 D.TRAN 0.001 3 0 0.001.PROBE V(1) V(2).END

Aim : To study a biaed clamper circuit II

Circuit Diagram:

Code:

*Biased Clamper IIV1 1 0 PULSE(-20V 20V 0 0 0 0.5s 1s)C1 1 2 10uFD1 2 3 D1N4148V2 3 0 DC -5VR1 2 0 10MEG.MODEL D1N4148 D.TRAN 0.001 3 0 0.001.PROBE V(1) V(2).END

Aim : To study a biaed clamper with sin source

Circuit Diagram:

Code:

*Biased Clipper with sin sourceV1 1 0 SIN(0 20V 50Hz)C1 1 2 10uFD1 2 3 D1N4148V2 3 0 DC 5VR1 2 0 10MEG.MODEL D1N4148 D.TRAN 0.001 0.1 0 0.001.PROBE V(1) V(2).END

Aim : To study the circuit of voltage doubler.

Circuit Diagram:

Code:

*Voltage DoublerV1 1 0 SIN(0 5V 10Hz)C1 1 2 1uFD1 2 0 D1N4148D2 3 2 D1N4148.MODEL D1N4148 DC2 3 0 1uF.TRAN 0.001 1 0 0.001.PROBE V(1) V(3,0).END

Aim : To study the circuit of Voltage Doubler, Tripler and

Quadrupler.

Circuit Diagram:

Code:

* Voltage Doubler, Tripler and QuadruplerV1 1 0 SIN(0 10V 10Hz)C1 1 2 1uFD3 2 0 D1N4148D4 5 2 D1N4148D5 4 5 D1N4148D6 6 4 D1N4148.MODEL D1N4148 DC2 0 5 1uFC3 2 4 1uFC4 5 6 1uF.TRAN 0.001 3 0 0.001.PROBE V(1) V(5) V(4,1) V(6).END

Aim : To study zener diode as voltage regulator when voltage

across the diode is less than the Break Down Voltage.

Circuit Diagram:

Code:

*Zener as voltage regulator(Failed)V1 1 0 DC 50VR1 1 2 1KV2 2 3 DC 0VR2 3 5 10KD1 4 3 D1N4148V3 4 0 DC 0VV4 5 0 DC 0V.MODEL D1N4148 D(BV=50V).OP.END

Output:

Here is a section of the ouput file.

Aim : To study zener diode as voltage regulator when voltage

across the diode is more than the Break Down Voltage I

Circuit Diagram:

Code:

*Zener as voltage regulator(Succes)V1 1 0 DC 150VR1 1 2 1KV2 2 3 DC 0VR2 3 5 10KD1 4 3 D1N4148V3 4 0 DC 0VV4 5 0 DC 0V.MODEL D1N4148 D(BV=50V).OP.END

Output:

Here is a section of the ouput file.

Aim : To study zener diode as voltage regulator when voltage

across the diode is more than the Break Down Voltage II

Circuit Diagram:

Code:

*Zener as voltage regulator(Success II)V1 1 0 DC 250VR1 1 2 1KV2 2 3 DC 0VR2 3 5 10KD1 4 3 D1N4148V3 4 0 DC 0VV4 5 0 DC 0V.MODEL D1N4148 D(BV=50V).OP.END

Output:

Here is a section of the ouput file.