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Integrated Circuit Design ELCT 701 (Winter 2019)
Notes on Dynamic Behavior of
InvertersDr. Eman Azab
Assistant Professor
Office: C3.315
E-mail: [email protected]
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
1
Notes on CMOS InverterDynamic Behavior
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
2
Calculation of Propagation
delays
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
3
Notes:
In the previous lecture, weassumed that the input voltageis an ideal step with zero riseand fall time
In practice, the input signal hasnon-zero rise and fall time
“𝝉𝒓 & 𝝉𝒇”
We can use the calculatedpropagation delays at idealinput voltage to obtain theactual delays
These equations are empiricalones, yet they provide goodestimation of the actual delays
Calculation of rise and fall time
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
4
Example:
A CMOS inverter with the following parameters: VDD=5V,
µnCox= 20µA/V2, W/Ln=10, VT,n=1V, Cload=1pF, Calculate
‘tfall’?
tfall is the time that the load capacitor discharge from 90% to 10% ofVOH
Output voltage will drop from 4.5V to 0.5V
Using the average current method:
Assignment, Calculate the fall time using differential equations!
𝐼𝑎𝑣𝑔 =1
2𝐼𝐷,𝑛(𝑉𝑖𝑛 = 5𝑉, 𝑉𝑜𝑢𝑡 = 4.5𝑉) + 𝐼𝐷,𝑛(𝑉𝑖𝑛 = 5𝑉, 𝑉𝑜𝑢𝑡 = 0.5𝑉)
𝐼𝑎𝑣𝑔 =1
2
𝑘𝑛2
(𝑉𝑖𝑛 − 𝑉𝑇,𝑛)2 +
𝑘𝑛2(2 𝑉𝑖𝑛 − 𝑉𝑇,𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑜𝑢𝑡
2 = 0.9875𝑚𝐴
𝜏𝑓𝑎𝑙𝑙 =𝐶𝑙𝑜𝑎𝑑∆𝑉𝑜𝑢𝑡
𝐼𝑎𝑣𝑔=𝐶𝑙𝑜𝑎𝑑 4.5 − 0.5
𝐼𝑎𝑣𝑔= 4.05 𝑛𝑠
Inverter Design with Delay
Constraints
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
5
How to select the transistor’s aspect ratio to satisfy delay
constraints?
For simplicity, if we considered Cload as a constant cap. (interconnect only)independent on transistor’s sizing, it’s a straight forward problem, ex.:
We have to balance between delays constraints and the rest of the inverter’sparameters
Note: If we took the parasitic caps of the transistors into consideration, wehave to calculate the capacitance per unit length first
Delay Calculations using
first-order RC approximationDynamic Behavior
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
6
© Digital Integrated Circuits2nd Inverter
CMOS Inverter: Transient Response
tpHL = f(Ron.CL)
= 0.69 RonCL
V outVout
R n
R p
VDDV DD
V in 5 VDDV in 5 0
(a) Low-to-high (b) High-to-low
CLCL
© Digital Integrated Circuits2nd Inverter
CMOS Inverter Propagation Delay
RC Network Approach
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
© Digital Integrated Circuits2nd Inverter
0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vout(V
)
tp = 0.69 CL (Reqn+Reqp)/2
tpLHtpHL
CMOS Inverter Propagation Delay
RC Network Approach
© Digital Integrated Circuits2nd Inverter
What is a Transistor?
VGS VT
Ron
S D
A Switch!
|VGS|
An MOS Transistor
© Digital Integrated Circuits2nd Inverter
The MOS Transistor
Polysilicon Aluminum
© Digital Integrated Circuits2nd Inverter
MOS Transistors -
Types and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
© Digital Integrated Circuits2nd Inverter
Threshold Voltage: Concept
n+n+
p-substrate
DSG
B
VGS
+
-
Depletion
Region
n-channel
© Digital Integrated Circuits2nd Inverter
The Threshold Voltage
© Digital Integrated Circuits2nd Inverter
The Body Effect
-2.5 -2 -1.5 -1 -0.5 00.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
VBS
(V)
VT (
V)
© Digital Integrated Circuits2nd Inverter
Current-Voltage Relations
A good ol’ transistor
QuadraticRelationship
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS
(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
© Digital Integrated Circuits2nd Inverter
Transistor in Linear
n+n+
p-substrate
D
S
G
B
VGS
xL
V(x)+–
VDS
ID
MOS transistor and its bias conditions
© Digital Integrated Circuits2nd Inverter
Transistor in Saturation
n+n+
S
G
VGS
D
VDS > VGS - VT
VGS - VT+-
Pinch-off
© Digital Integrated Circuits2nd Inverter
Current-Voltage Relations
Long-Channel Device
© Digital Integrated Circuits2nd Inverter
A model for manual analysis
© Digital Integrated Circuits2nd Inverter
Current-Voltage Relations
The Deep-Submicron Era
LinearRelationship
-4
VDS
(V)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
© Digital Integrated Circuits2nd Inverter
Velocity Saturation
x (V/µm)xc = 1.5
un
(m/s
)
usat = 105
Constant mobility (slope = µ)
Constant velocity
© Digital Integrated Circuits2nd Inverter
Perspective
IDLong-channel device
Short-channel device
VDSVDSAT VGS - VT
VGS = VDD
© Digital Integrated Circuits2nd Inverter
ID versus VGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VGS
(V)
I D(A
)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VGS
(V)
I D(A
)
quadratic
quadratic
linear
Long Channel Short Channel
© Digital Integrated Circuits2nd Inverter
ID versus VDS
-4
VDS(V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
Long Channel Short Channel
© Digital Integrated Circuits2nd Inverter
A unified model
for manual analysis
S D
G
B
© Digital Integrated Circuits2nd Inverter
Simple Model versus SPICE
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VDS
(V)
I D(A
)
VelocitySaturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
© Digital Integrated Circuits2nd Inverter
A PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D(A
)
Assume all variablesnegative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
© Digital Integrated Circuits2nd Inverter
Transistor Model
for Manual Analysis
© Digital Integrated Circuits2nd Inverter
The Transistor as a Switch
VGS VT
Ron
S D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
Dynamic Power
Calculations
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
31
Dynamic Power Dissipation
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
32
Switching Power Dissipation:
Changing the input voltage from high to low (or low to high) causescharging and discharging of the load capacitance
This process leads to power dissipation in the form of heat at theseswitching instants
F is the switching frequency
Dynamic Power Dissipation
Dr. Eman Azab
Electronics Dept., Faculty of IET
The German University in Cairo
33
Notes on: Switching Power
Dissipation
Power dissipation is directlyproportional to the circuitswitching speed
Higher speed more power
dissipation
Power dissipation isindependent of transistor sizing
Power-delay product:
A performance parameter to
evaluate the inverter design