Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003

Integrated Circuits Laboratory

Faculty of Engineering

Digital Design Flow Digital Design Flow Using Mentor Graphics ToolsUsing Mentor Graphics Tools

Presented by: Sameh Assem Ibrahim 16-October-2003

2/36 Integrated Circuits Laboratory


ObjectivesObjectives

Learn the digital design flow starting from VHDL down to physical device verification.

Be familiar with the basics of downloading a design into an FPGA and testing it.

Learn Mentor Graphics Tools:

- FPGA Advantage 5.x : - HDL Designer Series (Design Entry)

- ModelSim (Simulation)

- Leonardo Spectrum (Synthesis)

Learn Xilinx Tools:

- ISE Alliance (Placement and Routing)

- iMPACT (Design Downloading into FPGA)



Digital Design FlowDigital Design Flow

HDL Designer Series

(Design Entry)

Download design to FPGA chip Design Architect

(Schematic editing)

ENIREAD & SG(Format conversion)

(Schematic generation)

Xilinx Alliance(FPGA Implementation)

ModelSim

(VHDL Simulation)

FPGA ASIC

Leonardo Spectrum(FPGA or ASIC synthesis)

VHDL netlist and SDF file for timing simulation

VHDL netlist & VITAL Post synthesis verification

Testing

fail

fail



Digital Design FlowDigital Design Flow

ASIC

GDSII format to foundry

Mach TA/PA(Timing and Power

analysis)

QuickSim(Digital simulation

with delays)

SPICE netlist

IC station(Autoplace, Autoroute, DRC, LVS, netlist and parasitics extraction)

DVE(Viewpoints generation)

fail



Design EntryDesign Entry

Using HDL Designer Series.

First step is to create a design library.

Design entry can either be Top-Down or Bottom-Up.

Five different design entry methods are available:

- VHDL / Verilog

- Truth Table

- Flow Charts

- State Machines

- Block Diagrams



Creating the Design Library (1)Creating the Design Library (1)

Design Entry

1. Run HDL Designer Series:

> Start > All Programs > FPGA Advantage 5.x > Design > HDL Designer



Creating the Design Library (2)Creating the Design Library (2)

Design Entry

Library Folder

Library Name

Press OK and Open Library to create designs



Creating the DesignCreating the Design

Design Entry



VHDL Entry (1)VHDL Entry (1)

Design Entry




Design Entry

Entity Name

Library Name

Architecture Name




Entity is written here

Architecture is written here

Design Entry

Save



Truth Table Entry (1)Truth Table Entry (1)

Blue = Input

Yellow = OutputRight click to add or remove columns

Design Entry




Design EntryEnter required inputs and outputs

Save




Design Entry

Library NameEntity Name

Architecture Name

Yet an entity is still required




Design Entry




Design Entry

Library Name

Truth Table Entity Name




Design Entry




Generate HDL

Design Entry



Flow Chart EntryFlow Chart Entry

Design Entry

Save

Generate HDL

Flow

End Point

Action

Stat Point

An Entity is required



State Diagram EntryState Diagram Entry

Mainly Used for Controllers (Finite State Machines “FSM”)

Design Entry

Add state Start state

1st one added

Double click to add action

Double click to add transition condition

Add transition

Generate HDL



Block Diagram Entry (1)Block Diagram Entry (1)

Design Entry

Block Diagram Editor

Adding a block (for Top-Down designs)

Adding a component (for Bottom-Up designs)

Adding a moduleware (a library of VHDL blocks)

ConnectorsI/O ports




Adding a component

Design Entry

Browse for your libraries here

Browse for your components here

Then drag to your Block diagram




Adding a modulware

Design Entry




Design EntryExample of a Block Diagram



Test BenchesTest Benches

Test benches are generated automatically as a block diagram with a tester and a block under test.

The tester is a VHDL file with the entity already specified, only the test waveforms are required.

Design Entry



SimulationSimulation

Using ModelSim.

The created testbench can be used.

Test Waveforms can be created within the program.

Outputs can be checked either as waveforms or as a list of numbers.



Starting ModelSimStarting ModelSim

Select the design to be simulated and then press

Compilation is done and then ModelSim starts.

Simulation



ModelSim WindowsModelSim Windows

Simulation



Using ModelSim (1)Using ModelSim (1)

Simulation




Simulation




Simulation

Select a signal and either use Force for a specific input or Clock for a periodic signal




Simulation

Time of simulation in ns

Run simulation



SynthesisSynthesis

Using Leonardo Spectrum.

A technology dependent step.

Either ASICs or FPGAs can be targeted.

Various output formats can be obtained (VHDL/SDF/EDIF)



Running Leonardo SpectrumRunning Leonardo Spectrum

Synthesis

Click on the synthesizer button

Select your designunit



Adjusting Synthesis FlowAdjusting Synthesis Flow

Synthesis

Choose yourdevice family

Choose yourdevice

Choose yourspeed grade

Choose yourwiring table

Choose what tooptimize for andwhether topreservehierarchy or not

Check insert I/0 pads



Generating the EDIF FileGenerating the EDIF File

SynthesisPress Run Flow

The EDIF file is created in this path



Other Outputs (1)Other Outputs (1)

SynthesisRTL Schematic Technology Schematic



Other Outputs (2)Other Outputs (2)

Synthesis

VHDL & SDF Area Report



Xilinx ISE4.2i FlowXilinx ISE4.2i Flow

The input to the flow is the EDIF file from Leonardo Spectrum.

The output is a bit file to be downloaded into the FPGA.

Steps are:

- Mapping the design blocks into the FPGA design units.

- Placement and Rouing of these units.

- Genration of the bit file and downloading it to the FPGA.

An FPGA programmer kit must be present, connected to the PC and with a manual at hand to know pins configuration.



Creating a New Project (1)Creating a New Project (1)

Design Implementation





Insert the nameof the project

Insert the path you want to createthe project in

Add data related to device family,the device itself, and the design flowused





Choose whether to add the EDIFnetlist or to add a copy from it



Implementing the DesignImplementing the Design


There are 3 steps for implementing the design:

1. Translating the EDIF netlist into primitives.

2. Mapping these primitives into their technology dependent counterpart.

3. Placing and routing these technology primitives.



Translating the Design (1)Translating the Design (1)


Translates the EDIF and gives a report declaring success of translationor gives warnings and errors.

Generates a post translation modelthat can be in VHDL format fora first step back annotation



Right click on this tab

Choose properties

Translating the Design (2)Translating the Design (2)


Choose VHDL Format

VHDL File Name



Mapping the DesignMapping the Design


Maps the primitives into technology primitives and generates a report.

Generates a VHDL as before.



Placement and Routing of the Placement and Routing of the DesignDesign




Programming the FPGAProgramming the FPGA


Generates the programming bit file for the FPGA

Generates a file to be loaded into the PROM (if present in the kit)

Downloads the design into the FPGA(iMPACT software)



ThanksThanks

Special thanks go to1. Eng. Sameh Talal (Aiat Co.)2. Eng. Ahmed Mohsen

For their help in preparing the material for this presentation.

Documents

Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003