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Integrating Time
Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic
Frequency Generators
Michael S. McCorquodale, Ph.D.Founder and CTO, Mobius Microsystems, Inc.
2008 IEEE International Frequency Control Symposium Honolulu, HI
Session B3L-A: Novel Oscillators and ModelingTuesday, May 20, 2008
Slide 2 of 41
Outline• A brief history of frequency synthesis• Emerging integration technologies• Self-referenced, trimmed and compensated RF
CMOS harmonic (LC) oscillators (CHOs)– Motivation and concepts– Simplified architecture– Published implementations
• Performance benchmarking– Total frequency error– Single sideband phase noise power spectral density– Period and cycle-to-cycle timing jitter
• ConclusionsHistory Emerging CHOs Benchmarking Conclusions
Slide 3 of 41
A brief history of frequency synthesis
History Emerging CHOs Benchmarking Conclusions
Slide 4 of 41
A brief history of frequency synthesis
• Crystal oscillators (past – present)– 1880: piezoelectricity discovered by the Curies– 1917: XTAL resonance explored by Langevin for SONAR– 1919: frequency control using XTALs by Nicholson and Cady– 1919 – present: XOs proliferate
• Phase-locked frequency synthesizers (present)– 1980s – present: PLLs developed to allow for multiple and
rational frequencies to be synthesized from one XTAL reference – Degraded phase noise and jitter relative to fundamental mode
XOs, but silicon integration becomes paramount• Integrated frequency references (future?)
– Significant work toward realizing integrated frequency references begins a “race” to replace quartz
– 1990’s – present: MEMS microresonators– 2000’s – present: CMOS harmonic oscillators (this work)
History Emerging CHOs Benchmarking Conclusions
Slide 5 of 41
Emerging integration technologies
History Emerging CHOs Benchmarking Conclusions
Slide 6 of 41
[SiTime]
Emerging integration technologies
• Surface and bulk MEMS microresonators have emerged as possible replacement for quartz technology as a frequency reference– Objective is integration: smaller form-factor, lower cost, etc.– Integration may enable advanced timing or carrier
synthesis architectures as references become “free”
[Discera]
History Emerging CHOs Benchmarking Conclusions
Slide 7 of 41
Emerging integration technologies
• Fundamental challenges– New process technology– Hermetic packaging– Relatively high freq. temperature coefficient (fTC)– Scaling resonator frequency– Power handling– High motional resistance complicates circuit design– Nonlinear transduction incurs noise penalty
• Current MEMS-referenced implementations– Low frequency MEMS resonator with fractional-N PLL
where divider is dithered based on input of a temperature sensor for compensation of fTC
– Synthesizes frequencies in the 10’s of MHz bandHistory Emerging CHOs Benchmarking Conclusions
Slide 8 of 41
Self-referenced, trimmed and compensated RF CMOS harmonic (LC) oscillators (CHOs)
History Emerging CHOs Benchmarking Conclusions
Slide 9 of 41
CHOs: Motivation and concepts
• Achieve integration with a solid-state technology to realize monolithic timing references– Leverage advances in RF CMOS– Explore performance limits of CMOS oscillators
• Conceive an architecture to achieve:– Low frequency error, low phase noise and low timing jitter
• Develop with an eye toward consumer timing– Clock references for serial wire interfaces such as USB
(±500ppm), S-ATA (±350ppm) and PCI (±300ppm)– Here bit error rate (BER) is paramount and dominated by
eye closure due to total frequency error and timing jitter History Emerging CHOs Benchmarking Conclusions
Slide 10 of 41
CHOs: Motivation and concepts
History Emerging CHOs Benchmarking Conclusions
Commercial serial-wire interfaces have eye-opening
specifications (USB test shown here)
Specificationtemplate
Measured eye-opening
Period jitter determines the eye-opening and eye-opening determines the BER
Slide 11 of 41
CHOs: Motivation and concepts
• Key concepts– Far-from-carrier phase noise is the most
significant contributor to timing jitter – Linear frequency multiplication/division
increases/decreases phase noise power quadratically
– Total timing error is dominated by jitter, not frequency error
• With these concepts is it possible to develop a monolithic low-Q RF LCoscillator and achieve low timing jitter as well as low frequency error?
History Emerging CHOs Benchmarking Conclusions
Slide 12 of 41
CHOs: Motivation and concepts
Offset from fundamental (Hz)
SSBphase noise PSD(dBc/Hz)
sinesquare
σp = RMS period jitterωo = fundamental radian frequency
To = fundamental periodfm = offset frequency from fundamental
(No/Po)fm= phase noise at offset fm from fundamental
History Emerging CHOs Benchmarking Conclusions
∫∞
π⎟⎟⎠
⎞⎜⎜⎝
⎛ω
=σ0
22 sin8
momfo
o
op dfTf
PN
m
How does phase noise manifest into period jitter?
Slide 13 of 41
CHOs: Motivation and concepts
100
102
104
106
108
10-15
10-10
10-5
100
Per
iod
Jitte
r sin
2 (π f
To)
Inte
grat
ion
Mas
k
Offset Frequency (Hz)0 1 2 3 4 5 6 7 8 9 10
x 106
0
0.2
0.4
0.6
0.8
1
Per
iod
Jitte
r sin
2 (π f
To)
Inte
grat
ion
Mas
k
Offset Frequency (Hz)
-50dBat 10kHz
Peak at fm = ½ fo
Null at fo(fm = 0)
Null at 2fo(fm = fo)
Close-to-carrier phase noise (<10kHz) is significantly attenuated
when converting to period jitter
Consider 10MHz reference
History Emerging CHOs Benchmarking Conclusions
Linear to log
Slide 14 of 41
CHOs: Motivation and concepts
Visualizing frequency multiplication and division effects and the typical net performance degradation in a phase-locked loop relative to the reference
History Emerging CHOs Benchmarking Conclusions
fm (Hz)
Pha
se n
oise
PS
D (d
Bc/
Hz)
+20log10(N)
×NReferencePLL VCO (unlocked)÷N
-20log10(N)
XO/MEMSreference
+10log10(N 2)
PLLloop BW
PLLoutputpath
Pha
se n
oise
PS
D (d
Bc/
Hz)
fm (Hz)
Period jitter integration masksin2(πfmTo)
Close-to-carrier phase noise is attenuated and far-from carrier phase noise is
amplified
Slide 15 of 41
CHOs: Simplified architecture
• Free-run a CMOS RF LC oscillator near 1GHz
• Frequency divide by a large ratio
• Implement high-resolution process trimming
• Implement open-loop temperature compensation
• Implement closed-loop long-term drift stabilization
• Actively regulate the power supply
History Emerging CHOs Benchmarking Conclusions
Slide 16 of 41
CHOs: Simplified architecture
History Emerging CHOs Benchmarking Conclusions
TR[12:0]
Cf [12:0]
MR[12:0] TR[12:0]
Cf [12:0]
MR[12:0]
vcmc
+_
TC[5:0]TC[5:0]
vctrl(T) 2.5
Cv [5:0]
TC[5:0]
vctrl(T)2.5
Cv [5:0]
TC[5:0]
Amplitude detector
Commonmode
detector
2.5
vbias
2.5 vac2.5
+_
Fixed thin film caps trim nominal
frequencyCv(vctrl(T))compensates LCO over T
Control loops
mitigate drift
High-swing pMOScascode bias
Slide 17 of 41
CHOs: Simplified architecture
CHO
vctrl(T)ICTAT
IPTAT
+_
I2C FLL
SSCGNVM Control
96-bitMTPNVM
SDL
SDA
To trimming switches and
programmablelogic
vBG
3.3
2.5
vBG
+
_
3.3
History Emerging CHOs Benchmarking Conclusions
D2S CLK
3.3
Regulated supply via bandgap-referenced
LDO
Programmable T-dependent compensating analog voltage
Differential to single-ended converter, programmable divider
and configurable output
Logic for I2C interface, trimming, spread-spectrum clock generation and NVM
Slide 18 of 41
Recently published implementations1500µm
LDO
2.5-to-3.3VLevel Shift
96-bit MTP NVM
I2C, FLL, SSCG,NVM Control
Band-Gap Reference
–gm Amplifier, Amplitude andCommon ModeControl Loops
Process Control Structures
POR
Config.Dividers
Bias Generation& Distribution
TestStructures 2 x Cv [5:0] and TC[5:0]
vctrl(T)Generator
D2S
Cf[
12:0
] and
M[1
2:0]
I/O+
ESDI/O+
ESD
Cf[
12:0
] and
M[1
2:0]
LDO
2.5-to-3.3VLevel Shift
96-bit MTP NVM
I2C, FLL, SSCG,NVM Control
Band-Gap Reference
–gm Amplifier, Amplitude andCommon ModeControl Loops
Process Control Structures
POR
Config.Dividers
Bias Generation& Distribution
TestStructures 2 x Cv [5:0] and TC[5:0]
vctrl(T)Generator
D2S
Cf[
12:0
] and
M[1
2:0]
I/O+
ESDI/O+
ESD
Cf[
12:0
] and
M[1
2:0]
Bias –gmamplifier
Frequency dividers
½f o
disc
rete
ca
libra
tion
arra
y
CB<7:0>
fTC cal. bus
Bias
f TC
open
-loop
tem
p. c
omp.
A
-MO
S va
ract
ors
f TC
open
-loop
tem
p. c
omp.
A
-MO
S va
ract
ors
½f o
disc
rete
ca
libra
tion
arra
y
400µm
1500
µm
550µ
m
Michael S. McCorquodale, et al., “A 0.5–480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread Spectrum Capability,”
IEEE Int. Solid State Circuits Conf. Dig. of Tech. Papers, San Francisco, CA 2008.
Michael S. McCorquodale, et al., “A Monolithic and Self-Referenced RF LC Clock Generator Compliant with USB 2.0,” IEEE J. of Solid
State Circuits, vol. 42, no. 2, Feb. 2007, pp. 385-399.
History Emerging CHOs Benchmarking Conclusions
Slide 19 of 41
Performance benchmarking
History Emerging CHOs Benchmarking Conclusions
Slide 20 of 41
Performance benchmarking• Existing (XO/XO-PLL)
– 24MHz 4-pin can crystal oscillator (XO)– 24MHz 2-pin passive crystal-referenced phase-locked loop (XO-PLL)– 12MHz 2-pin passive ceramic resonator + sustaining circuit
• Emerging (MEMS-PLL)– 20MHz MEMS-referenced PLL (vendor #1)– 12MHz MEMS-referenced PLL (vendor #2)
• This work (CHO)– 12MHz, 1.536GHz LC-referenced CHO– 12MHz, 960MHz LC-referenced CHO
• Benchmarks– Total frequency inaccuracy (due to trimming, power supply and temp.)– SSB phase noise PSD– Period and cycle-to-cycle jitter– Total timing error
History Emerging CHOs Benchmarking Conclusions
Slide 21 of 41
-50.0
-25.0
0.0
25.0
50.0
-20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
Nor
mal
ized
freq
uenc
y in
nacu
racy
, δf
/fo (
ppm
)
-3500
-1750
0
1750
3500
Nor
mal
ized
freq
uenc
y in
nacu
racy
, δf
/fo
(ppm
)
24MHz XO20MHz MEMS-PLL12MHz MEMS-PLL12MHz CHO VDD + 10%12MHz CHO nominal VDD12MHz CHO VDD -10%12MHz Ceramic
Total frequency inaccuracy
History Emerging CHOs Benchmarking Conclusions
CHO trim occurs at
35°C
Best CHO performance in Si to
date shown Typical production yield is ±150ppm
Slide 22 of 41
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO
Slide 23 of 41
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
Ceramic resonator is lower Q than XO so
close-to-carrier phase noise is higher
Slide 24 of 41
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
Outside PLL loop BW, phase noise tracks VCO (note PLL loop mult. is 1)
Slide 25 of 41
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL
Slide 26 of 41
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
MEMS-PLL frequency multiplication
increases phase noise inside PLL loop BW
Outside PLL loop BW, phase noise tracks VCO
Slide 27 of 41
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO
Slide 28 of 41
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO12MHz CHO
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
CHOs have much lower far-from-carrier phase
noise than PLLs
Close-to-carrier phase noise is
higher in CHO but comparable to
MEMS-PLL
Slide 29 of 41
101 102 103 104 105 106
-160
-140
-120
-100
-80
-60
-40
-20
0
SS
B p
hase
noi
se P
SD
, (N
o/Po) f m
(dB
c/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO12MHz CHO
101 102 103 104 105 106
-220
-200
-180
-160
-140
-120
-100
SS
B p
hase
noi
se P
SD
× si
n2 (π f
m T
o) (d
Bc/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO12MHz CHO
Single sideband phase noise PSD
History Emerging CHOs Benchmarking Conclusions
From ~30kHz all PLL implementations are noisier than CHOs
Project onto sin2(πfmTo)
Slide 30 of 41
0 1 2 3 4 5-200
-190
-180
-170
-160
-150
-140
-130
-120
SS
B p
hase
noi
se P
SD
× si
n2 (π f
m T
o) (d
Bc/H
z)
Offset frequency (MHz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO12MHz CHO
101 102 103 104 105 106
-220
-200
-180
-160
-140
-120
-100
SS
B p
hase
noi
se P
SD
× si
n2 (π f
m T
o) (d
Bc/H
z)
Offset frequency (Hz), fm (Hz)
24MHz XO12MHz Ceramic Oscillator24MHz XO-PLL12MHz MEMS-PLL20MHz MEMS-PLL12MHz CHO12MHz CHO
Single sideband phase noise PSDCHO, XO and Ceramic
Oscillator all exhibit similar far-from-carrier noise
>15dB
History Emerging CHOs Benchmarking Conclusions
Visualize on linear scale
Projected CHO noise approaches XO noise but XO is at twice the frequency
Slide 31 of 41
Period and cycle-to-cycle jitter• Phase noise measurements show that
far-from-carrier phase noise is very similar for XO, ceramic oscillator and CHO
• Far-from-carrier phase noise for CHO appears lower than all implementations, except XO, due to higher power in LCO (but XO at double freq.)
• Theory predicts that these three implementations should exhibit similar period jitter and CHO should exhibit the lowest jitter
• Theory also predicts that the PLL implementations should exhibit comparatively higher period jitter
History Emerging CHOs Benchmarking Conclusions
Slide 32 of 41
Period and cycle-to-cycle jitter24MHz XO
σp = 6.52psrmsσcc = 11.48psrms
24MHz XO-PLLσp = 10.38psrmsσcc = 18.89psrms
12MHz Ceramicσp = 6.52psrms
σcc = 11.01psrms
History Emerging CHOs Benchmarking Conclusions
Ceramic oscillator and XO have similar jitter;1x multiplier in PLL degraded jitter in XO-PLL
Slide 33 of 41
Period and cycle-to-cycle jitter
20MHz MEMS-PLLσp = 12.16psrmsσcc = 17.60psrms
12MHz MEMS-PLLσp = 36.40psrmsσcc = 46.99psrms
History Emerging CHOs Benchmarking Conclusions
Jitter for both implementations is much
higher than XO and XO-PLL as expected
Slide 34 of 41
Period and cycle-to-cycle jitter
12MHz CHOσp = 6.41psrms
σcc = 11.25psrms
12MHz CHOσp = 5.73psrmsσcc = 9.32psrms
History Emerging CHOs Benchmarking Conclusions
CHO has lowest jitter and is directly comparable to high-Q
XO because CHO has low far-from-carrier phase noise
Slide 35 of 41
Period and cycle-to-cycle jitter
CHO has the lowest jitter
MEMS-PLL is >6x higher
History Emerging CHOs Benchmarking Conclusions
Slide 36 of 41
t
v
Fractional total timing errorIntroduce the concept of the fractional total timing error, or the maximum error in any period due to frequency inaccuracy and jitter
( )( ) opooo
TffTTT ασ+δ×=⎟⎟⎠
⎞⎜⎜⎝
⎛ δ maxmax
History Emerging CHOs Benchmarking Conclusions
Idealperiod
Maximum jitter for a bounding cycle count
Maximum period error
To
⎟⎟⎠
⎞⎜⎜⎝
⎛ δ
oTTmax
Basically, consider the sum of the total
frequency error AND the maximum
period jitter as a metric which is relevant to eye
closure
Slide 37 of 41
Total timing error
82.20
90.38
513.52
171.46
120.00
92.07
ασp
α = 14.1(ps)
1012
1485
6171
3466
2888
2218
max(δT/To)(ppm)
97.45.832.172612CHO
73.16.4133.3340012CHO
99.936.420.75912MEMS + PLL
98.912.161.853720MEMS + PLL
99.78.510.33824XO + PLL
99.66.530.33824XO
ασp /max(δT/To)(%)
σp
(ps)max(|f-1|)
(ps)max(δf/fo)
(ppm)fo
(MHz)
History Emerging CHOs Benchmarking Conclusions
This is the worst-case fractional period error
and determines eye opening and BER
α = 14.1 is for 1012 cycles (a common specification)
Slide 38 of 41
Period jitter summary• A low-Q LCO can achieve period jitter much lower than
high-Q implementations (including XOs and MEMS) by:
– Exploiting frequency division
– Exhibiting low far-from-carrier phase noise
• High-Q MEMS oscillators do not achieve low jitter and phase noise due to loop multiplication and PLL VCO
• A low-Q LCO can be implemented in a standard solid state process technology and achieve period jitter performance directly comparable high-Q oscillators
• Power dissipation in the CHO is comparable to the XO-PLL and MEMS-PLL implementations
History Emerging CHOs Benchmarking Conclusions
Slide 39 of 41
Conclusions
History Emerging CHOs Benchmarking Conclusions
Slide 40 of 41
Conclusions
• Self-referenced, trimmed and compensated RF CMOS harmonic oscillators (CHOs) were introduced as monolithic frequency generators realized entirely in a solid-state process technology
• CHO implementations were benchmarked against incumbent XOs/XO-PLLs and emerging MEMS-PLLs where it was shown that frequency error was comparable and period jitter was superior for the CHO
• CHOs are now entering the production phase History Emerging CHOs Benchmarking Conclusions
Slide 41 of 41
Questions are welcome
History Emerging CHOs Benchmarking Conclusions