Intel Atom Processor Z670 with Intel SM35 Express Chipset Development Kit User … · Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit User Guide July

Document Number: 325470-002

Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit User Guide July 2011

Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit User Guide July 2011 2 Document Number: 325470-002

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Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit July 2011 User Guide Document Number: 325470-002 3

Contents 1 Introduction ................................................................................................................ 7

1.1 Ordering Information ........................................................................................... 8 1.2 Development Kit Items ......................................................................................... 9 1.3 Reference Documents ......................................................................................... 11

2 Customer Reference Board Features ......................................................................... 13 2.1 Processor Support .............................................................................................. 18

2.1.1 VIDs - CPU VIDs and Manual VIDs ............................................................. 19 2.1.2 Power Management and Key Signals .......................................................... 20 2.1.3 Memory Support ..................................................................................... 21 2.1.4 Display .................................................................................................. 21 2.1.5 Touch Panel ........................................................................................... 22 2.1.6 cDMI Interface ....................................................................................... 22 2.1.7 cDVO Interface ....................................................................................... 23 2.1.8 Processor Legacy Signals/Thermals ........................................................... 23 2.1.9 Processor Cooling ................................................................................... 23

2.2 Introduction to the PCH – Intel® SM35 Express Chipset ........................................... 23 2.2.1 SDIO Interface ....................................................................................... 24 2.2.2 HD Audio ............................................................................................... 26 2.2.3 Mott Canyon Usage ................................................................................. 28 2.2.4 SATA Storage ......................................................................................... 28 2.2.5 Displays from Intel® SM35 Express Chipset / PCH ........................................ 29 2.2.6 USB ...................................................................................................... 29 2.2.7 Mini-Cards ............................................................................................. 32 2.2.8 SPI ....................................................................................................... 33 2.2.9 Legacy I/Os ........................................................................................... 33

2.3 Clocks .............................................................................................................. 34 2.3.1 Real-Time Clock ..................................................................................... 35

2.4 Power Management Integrated Circuit (PMIC) ........................................................ 36 2.5 Embedded Controller (EC) ................................................................................... 37 2.6 Debug Interfaces ............................................................................................... 38 2.7 Chassis ............................................................................................................ 38

2.7.1 Opening the Chassis (IMPORTANT) ............................................................ 39 2.8 Power Supply Solutions, Usage and Recommendation ............................................. 40

2.8.1 Power Supply Solutions ........................................................................... 40 2.8.2 Removing/Replacing the Power Management IC (PMIC) ................................ 41 2.8.3 Power Supply Usage and Recommendations ................................................ 42

2.9 Power Management ............................................................................................ 43 2.9.1 Power Management States ....................................................................... 43

2.10 Power Measurement Support ............................................................................... 44

3 Reference Board Summary ........................................................................................ 47 3.1 Features ........................................................................................................... 47 3.2 Back Panel Connectors ....................................................................................... 49 3.3 Configuration Settings ........................................................................................ 50


3.3.1 Configuration Jumpers/Switches ............................................................... 50 3.3.2 Power On and Reset Button ...................................................................... 53

3.4 LEDs ................................................................................................................ 53

4 Quick Start ................................................................................................................ 56 4.1 Required Peripherals .......................................................................................... 56 4.2 Instructions to Program SPI Flash (BIOS) .............................................................. 56

4.2.1 EC Programming ..................................................................................... 57 4.3 Key Jumpers ..................................................................................................... 58 4.4 Power Up .......................................................................................................... 58

A Add-In Cards ............................................................................................................. 64 A.1 Mott Canyon 4 Interposer ................................................................................... 64

A.1.1 Mott Canyon 4 Jumper Settings ................................................................ 65 A.2 Port 80-83 Add-in Card ....................................................................................... 66 A.3 Upham IV Board (PCI Express Interposer Card) ...................................................... 67

B Important Recommendations to Utilize the Intel® SM35 Express Chipset Stepping A2 on Customer Platform ............................................................................................... 70

C Terms and Abbreviations .......................................................................................... 71

Figures

Figure 1. Platform Block Diagram ........................................................................ 9 Figure 2. Alpine Bay Customer Reference Board Block Diagram ............................. 13 Figure 3. Top View of the Alpine Bay CRB ........................................................... 17 Figure 4. Bottom View of the Alpine Bay CRB ...................................................... 18 Figure 5. Manual VID Implementation for Vcc in Alpine Bay ................................... 20 Figure 6. SDIO Block Diagram .......................................................................... 25 Figure 7. USB Implementation on Alpine Bay ...................................................... 30 Figure 8. USB 3-Stack Connector on Alpine Bay ................................................... 31 Figure 9. SPI Block Diagram ............................................................................. 33 Figure 10. Clock (integrated mode) Block Diagram .............................................. 35 Figure 11. Intel® SM35 Express Chipset-EC-PMIC Block Diagram ........................... 37 Figure 12. ACPI States ..................................................................................... 44 Figure 13. Alpine Bay Components – Top View .................................................... 47 Figure 14. Alpine Bay Components –Bottom View ................................................ 49 Figure 15. Back Panel Connectors ...................................................................... 50 Figure 16. SPI Programming Jumpers ................................................................ 57 Figure 17. Embedded Controller Programming Jumpers ........................................ 58 Figure 18. Mott Canyon 4 Interposer Card .......................................................... 64 Figure 19. a) TPM header b) Port 80 c) Port 80 on TPM header in CRB .................... 66 Figure 20. Port 80-83 Add-In Card..................................................................... 67 Figure 21. Upham IV Add-In Card ..................................................................... 68

Tables

Table 1. Alpine Bay CRB Feature Set Summary ................................................... 13 Table 2. Memory Configurations Supported on CRB .............................................. 21 Table 3. LVDS Rework Options .......................................................................... 22 Table 4. SDIO [0, 1, 2] Rework Options ............................................................. 25


Table 5. Selection of I/O Voltage for the High Definition Audio ............................... 27 Table 6. SATA Rework Options .......................................................................... 28 Table 7. USB Port Mapping ............................................................................... 30 Table 8. USB Rework Options ........................................................................... 32 Table 9. Power Management States ................................................................... 43 Table 10. Digital Multi-Meter ............................................................................. 45 Table 11. Power Measurement Resistors on Alpine Bay ......................................... 45 Table 12. CRB Components List - Top View ......................................................... 47 Table 13. CRB Components List - Bottom View .................................................... 49 Table 14. Back Panel Connectors ....................................................................... 50 Table 15. Configuration Jumper ........................................................................ 50 Table 16. Power On and Reset Button ................................................................ 53 Table 17. Other CRB Switches ........................................................................... 53 Table 18. CRB LEDs ......................................................................................... 54 Table 19. Mott Canyon 4 Configuration Jumper/Switches Settings .......................... 65 Table 20. Upham IV Default Jumper/Switches Settings ......................................... 68


Revision History

Document Number

Revision Number Description Revision Date

325470 002

Refined Figure 3 and Figure 4 and documented that every Development Kit no longer contains all three vendor PMICs. Added new sections: Chassis and Power Supply Solutions, Usage and Recommendation.

July 2011

001 Initial release April 2011

Introduction


1 Introduction This document describes the typical hardware set-up procedures, features, and use of Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit (code name ‘Oak Trail’), which includes a Customer Reference Board (CRB) / Reference Validation Platform (RVP) named ‘Alpine Bay’ along with other hardware and software components.

Note: While this document includes a Quick Start section, the entire user guide should be read prior to powering on the CRB.

This document is relevant to the Alpine Bay CRB/RVP (PBA# E91153-101, a CRB with 2GB of DDR2-800 memory). The references in this document correlate to reference designators and board properties of the Alpine Bay CRB. Socket and connector locations are labeled with a letter-number combination. For socket locations, please refer to the silkscreen labeling on the CRB.

The CRB supports various additional interfaces through add-in cards. See Appendix 0 for add-in card details.

It is recommended to have both the Alpine Bay schematics (obtained from the Embedded Design Center’s Technical Documents page http://edc.intel.com/Platforms/Atom-Z6xx/#hardware) and CRB present as you use this guide.

The CRB is a sleek, single-channel, DDR2-800 low-power embedded tablet platform. It primarily consists of three major chips:

1. Intel Atom Processor Z6xx Series (code name ‘Lincroft’) with integrated memory and 2D/3D graphics controller. Two different Z6xx series SKUs are supported by the Development Kit: the (Intel Atom processor Z670 @ 1.5 GHz, and the Intel Atom processor Z650 @ 1.2 GHz.

Note: By default, the faster Z670 processor along with 2GB of DDR2-800 memory will be mounted on the CRB. The processor integrates a power-optimized 2D/3D graphics engine, Hardware Video Decode Accelerator, and an 18-bit LVDS display output (24-bit support validated on a limited number of panels).

For ordering purposes, the Product Code (MM) for the 1.5-GHz Intel Atom Processor Z670 (code name ‘Lincroft’) is the 910071. The Product Code (MM) for the 1.2-GHz Intel Atom Processor Z650 (code name ‘Lincroft’) is 910072.

2. Intel® SM35 Express Chipset (Platform Controller Hub (PCH); code name ‘Whitney Point’). This chipset incorporates HDMI 1.3a display output with HDCP copy protection, Intel® High Definition Audio, four USB 2.0 ports, three SDIO ports, two SPI ports, and one SATA Gen2 port for storage along with other I/O functions. For ordering purposes, the Product Code (MM) for the Intel SM35 Express Chipset is 913605.

3. Power management integrated circuit (PMIC) module. The PMICs qualified by Intel for this design include those offered by Renesas (μPD9975/μPD9977),

http://edc.intel.com/Platforms/Atom-Z6xx/#hardware

Introduction


Freescale (SC900844JVK), and Maxim (MAX8958). Contact the vendors for their product information.

1.1 Ordering Information

The name of the platform kit, which contains the Alpine Bay CRB along with all hardware adapter boards and other contents, is the Intel Atom Processor Z670 with Intel SM35 Express Chipset Development Kit. This document is the user guide for the Kit. For ordering purposes, the part number of the Kit is EMBLNCWPTABDVK, and the kit’s product code is MM# 915496.

The product brief for the kit can be downloaded at:


The kit platform comprises a processor, graphics, and I/O core solution for the growing tablet and digital signage markets. It includes two chips: the Intel Atom Z670 (or Z650) processor and Intel SM35 Express Chipset. The processor has two speed SKUs 1.5 GHz (Intel Atom processor Z670) or 1.2 GHz (Intel Atom processor Z650) both at 3W thermal design power (TDP). The Intel Atom processor Z670 / Z650 also includes an integrated power-optimized 2D/3D graphics engine, Hardware Video Decode Acceleration, and an 18-bit LVDS display output, all in an ultra-small 13.8mm x 13.8mm x 1.1mm package. The processor and GPU combined device is paired with the Intel SM35 Express Chipset, which delivers USB 2.0, SDIO, SATA Gen2, High Definition Audio, and an HDMI display output, all at 0.75W TDP. These features enable the platform to be used in a range of innovative, battery-capable, small-form-factor embedded designs with rich multimedia capabilities.

Figure 1 shows block diagram of the platform implemented with the Alpine Bay CRB.


Introduction


Figure 1. Platform Block Diagram

Development kit/board: Development kit name: Intel Atom Processor Z670 with Intel SM35 Express Chipset Development Kit Supported processor: Intel Atom Processor Z670 Chipset: Intel SM35 Express Chipset

Product code: EMBLNCWPTABDVK MM#:915496

1.2 Development Kit Items

This development kit includes the following items:

• Alpine Bay CRB

o Alpine Bay CRB is an ATX-size main board created by Intel that contains the Intel® Atom™ Processor Z670 and Intel SM35 Express Chipset along

Introduction


with other devices required for this completed Oak Trail reference platform.

o The Intel Atom Processor Z670 is housed in an MPI socket. The processor can be removed and replaced with another Z670 or Z650 as needed. For instructions on how to do this, refer to the presentation titled Training: MPI Socket for the Intel® Atom™ Processor Z670 / Z650 & Intel® SM35 Express Chipset posted on http://www.intel.com/p/en_US/embedded/hwsw/hardware/atom-z6xx/hardware

o The Intel SM35 Express Chipset is housed in an MPI socket and can be removed if necessary. For instructions on how to do this, refer to the presentation titled Training: MPI Socket for the Intel® Atom™ Processor Z670 / Z650 & Intel® SM35 Express Chipset posted on http://www.intel.com/p/en_US/embedded/hwsw/hardware/atom-z6xx/hardware

• LVDS 10.1” panel

o Model # = Chunghwa Telecom* CLAA101NT02A

o Has multi-touch capability

o Included in Development Kit by being mounted into the Antec* Two Hundred (v2) PC chassis

• PMIC module(s):

o One PMIC will be pre-installed in the “PMIC Connector” socket (see Figure 3) on the Alpine Bay main board. This is removable and can be replaced with those (in Kit) from the other two vendors

o Each development kit contains one to three of the following PMICs: Renesas (μPD9975/μPD9977) http://america2.renesas.com/pmd/pmics.html Freescale (SC900844JVK) http://www.freescale.com/webapp/sps/site/overview.jsp?code=PMICINTEL Maxim (MAX8958) http://www.maxim-ic.com/datasheet/index.mvp/id/7013

o AS OF JULY 2011 - EACH KIT WILL COME WITH AT LEAST ONE AND UP TO THREE PMICS AS AVAILABILITY PERMITS AMONG THE THREE VENDORS (RENESAS, MAXIM, AND FREESCALE)

Note: Intel doesn’t recommend a specific PMIC device. All PMIC devices listed have passed Intel’s design specifications related to power delivery in Oak Trail based platforms.

• Antec Two Hundred (v2) PC chassis

o This contains the Alpine Bay CRB, LVDS panel, PMIC, power supply, and other necessary hardware.

o Refer to http://store.antec.com/Product/enclosure-gear_for_gamers/two-hundred-v2/0-761345-15253-2.aspx for more information.

• Intel® Atom™ Processor Z670 with Intel SM35 Express Chipset Development Kit User Guide (this document)

• Mini cards included with Development Kit:

http://www.intel.com/p/en_US/embedded/hwsw/hardware/atom-z6xx/hardware




http://america2.renesas.com/pmd/pmics.html

http://www.freescale.com/webapp/sps/site/overview.jsp?code=PMICINTEL

http://www.maxim-ic.com/datasheet/index.mvp/id/7013

http://store.antec.com/Product/enclosure-gear_for_gamers/two-hundred-v2/0-761345-15253-2.aspx

http://store.antec.com/Product/enclosure-gear_for_gamers/two-hundred-v2/0-761345-15253-2.aspx

Introduction


WiFi half-mini card (Lite-On WN6607LH) USB LAN adapter (Belkin FD5055)

• Other add-in cards (not included in Development Kit; contact your Intel representative): Wireless LAN – Intel WiMAX 6150 (Kelsey Peak) Upham 4 Fab 1 (D86916-101)

o Upham is a Mini PCIe* interposer board for wireless communication that supports a Bluetooth* module and allows the concurrent usage of Bluetooth and PCIe mini cards

Mott Canyon 4 Fab 1 (D34533-101 ) o Mott Canyon provides Intel High Definition Audio, audio output/mic in, and

modem functions Port 80 (IPN: D32188-301 ) – if needed

o Aids in debugging BIOS code

1.3 Reference Documents

Document Document No./Location

Oak Trail Platform, Alpine Bay – Customer Reference Board (CRB) Schematic 448204 / EDC

Oak Trail Platform, Alpine Bay – Customer Reference Board (CRB) File 448206 / EDC

Oak Trail Platform, Alpine Bay Customer Reference Board (CRB) – Cadence* / OrCAD* Symbol Files 448207 / EDC

Oak Trail Platform, Alpine Bay – Customer Reference Board (CRB) BOM E91153-10 / EDC

Oak Trail Platform – Intel® Atom™ Processor Z6xx Series Processor I/O Buffer Information Specification (IBIS) Model 448226 / EDC

Intel® SM35 Express Chipset PCH, Oak Trail Platform – I/O Buffer Information Specification (IBIS) Model 454168 / EDC

Oak Trail Platform Design Guide 448203/Intel Business Portal

Oak Trail Platform Trace Length Calculator 451595/ Intel Business Portal

PBA-board file number that matches the CRB with 2 GB of DDR2 memory.

• The E91153-102 number is based on the amount of DDR2 memory mounted on the CRB.

E91153-102: for the Alpine Bay CRB with 2GB of DDR2-800 memory down on the board

Introduction


Document Document No./Location

PBA-board file number that matches the CRB with 1 GB of DDR2 memory.

• The E95620-101 number is based on the amount of DDR2 memory mounted on the CRB.

E95620-101: for the Alpine Bay CRB with 1GB of DDR2-800 memory down on the board

Note: Refer to the Embedded Design Center (EDC) Technical Documents page for the most recent schematics and board files cited in the table above:


Consult the Intel Embedded Design Center (EDC) Technical Documents page for additional Alpine Bay documents, here:

http://edc.intel.com/Platforms/Atom-Z6xx/#overview


http://edc.intel.com/Platforms/Atom-Z6xx/#overview

Customer Reference Board Features


2 Customer Reference Board Features

Figure 2. Alpine Bay Customer Reference Board Block Diagram

Table 1. Alpine Bay CRB Feature Set Summary

Component CRB Implementation Comments

Processor

Intel Atom Processor Z670 / Z650 supported in a 13.8-mm x 13.8-mm x 1.10-mm FCBGA package - 0.5-mm pitch

• Intel Atom processor Z670 = 1.5 GHz (default processor on CRB)

• Intel Atom processor Z650 = 1.2 GHz (optional)

• MPI socket




PCH Intel SM35 Express Chipset -14mmx14mmx1.3mm PBGA halogen-free package - 0.5mm pitch

• Intel SM35 Express Chipset

• MPI socket

Power Management IC PMIC module (socketed)

• Renesas = μPD9975 / μPD9977 (cost-reduced) PMIC

• Freescale = SC900844JVK PMIC

• Maxim = MAX8958 PMIC

• All have 500-pin socket connector

Memory

Single-channel, dual-rank DDR2-800 with a 32-bit data bus

Eight on-board SDRAMs (2Rx8) of total memory size 2GB

• 1GB is also supported in two ways: using 1Gb devices unstuffing four 2Gb parts on board

Display

Single-channel LVDS interface; pixel clock up to 80 MHz

• 50 pin connector (J3F1) on board

• 18-bit (24-bit support validated on a limited number of panels)

• Maximum resolution for LVDS port on Intel Z6xx series processors is 1366x768 @60 Hz

• Maximum resolution supported with LVDS panel included with CRB is 1024x600

• Panel part number included with the Development Kit: Chunghwa Telecom CLAA101NT02A

• Cable part number: LA10LM004-1N

HDMI connector J4A1

• HDMI 1.3a (720 p @ 60Hz, 1080p @ 30 Hz, 1080i @ 60 Hz all supported)

• Maximum clock rate for HDMI = 108 MHz

• HDMI data rate: 1.65 Gbps

SPI devices SPI flash devices; 2 MB devices one each for the Embedded Controller (EC) and firmware

• Dediprog support is provided to program the on-board flashes

• No socket is provided




EC Embedded Controller (NPCE791EA0DX)

• Nuvoton NPCE791EA0DX* Embedded Controller

• This CRB uses the NPCE791x series embedded controller for the following purposes: Interfaces to the chipset through the LPC bus Controls 16x8 scan matrix keyboard and PS/2

keyboard, mouse Controls one serial port, Port 80, and battery

charger Provides LVDS backlight control and ambient

light sensor

• Request datasheet from Nuvoton

• Contact Nuvoton technical support for datasheets and product inquiries:

[email protected]

Soft Audio/Soft Modem Audio codec is used on board

• Mott Canyon 4 daughter card is supported (but not included in Development Kit; contact your Intel representative for samples)

SATA 1x SATA Gen 2 Port – 1 direct connect connector is supported

• 1 ports capable of 3GT/s

• Rework option is provided to connect to cable connect

USB 2.0

Four USB 2.0 ports.

No 1.1 USB support through Intel SM35 Express Chipset

USB hub is used on port 0 for additional ports

Total: Seven USB ports

See Section 2.2.6

LPC No LPC slot, CRB just has a TPM header

Clocks

The platform requires support of 14.318-MHz oscillator and 25-MHz crystal input to the Intel SM35 Express Chipset.

Other clocks required are 32.768 KHz to the PMIC for RTC, 32.768 KHz to EC, and 24-MHz crystal for USB hub as per hub requirement.

RTC

PMIC RTC is powered by coin-cell. Maintains time function.

Intel SM35 Express Chipset RTC functional during S0 only.

SDIO

Three SDIO ports; two ports are 8-bit compatible for SD/MMC/MMC Plus.

SDIO2 is a 4-bit port that can be used for communication modules.

mailto:[email protected]




Processor Voltage

Regulator PMIC

Uses Parallel VID interface

Power Supply Desktop Mode/Mobile mode

Desktop mode - ATX power supply support

Mobile mode:

• Battery pack (smart battery support)

• Mobile AC brick

Debug Interfaces

CPU XDP

Port 80 display

JTAG connectors

DAFCA port

Provision for accessing chipset JTAG through XDP port.

Form Factor ATX form factor Eight-layer HDI 1-x-1+ board – 12” x 9.6”

The following figures indicate the location of different major components on the Alpine Bay CRB.



Figure 3. Top View of the Alpine Bay CRB

Notes:

• Mini PCIe connectors are only physical adapters to the USB interface. Devices connected to these interfaces are recognized as USB devices.

• There is no SPI0 on the Intel SM35 Express Chipset.



Figure 4. Bottom View of the Alpine Bay CRB

2.1 Processor Support

The Alpine Bay CRB supports the Intel Atom processor Z670 / Z650 in a FCBGA package (U4G1). The processor is a monolithic die with an integrated memory controller and integrated graphics controller. The Alpine Bay CRB supports the processor via an MPI-type socket on the board. The following are the high-level features of the processor:

• Same CPU core as Intel® Atom™ processor D400/500 and N400/500 series

• 1.2 GHz (Z650) and 1.5 GHz (Z670) speed SKUs

• 45-nm High-K process

• 24K data cache, 32K instruction cache

• Enhanced Intel SpeedStep® Technology



• Deep Power Down Technology States

Note: By default, this CRB includes the Intel Atom Processor Z670 @ 1.5 GHz; however, the kit can be used to evaluate the pin-compatible Intel Atom Processor Z650 @ 1.2 GHz. To evaluate the Intel Atom Processor Z650, perform the following: With the Intel Atom Processor Z650, version C0, device in hand, lift the processor socket lid and carefully replace (using appropriate lab and anti-static measures) the Z670 with the Z650. Pin 1 will have a unique marking. Close the lid when finished.

2.1.1 VIDs - CPU VIDs and Manual VIDs

The VID signals VID[6:0] connect to the PMIC. The CPU and graphics core powers (Vcc and Vnn) are controlled by common parallel VID signals.

They indicate a desired voltage for either VCC or VNN depending on the VIDEN[1:0] pins. The VID Enable signals indicate which voltage is being specified on the VID pins as shown below:

00 = VID is invalid

01 = VID = VCC

10 = VID = VNN

11 = RSVD

Manual VIDs:

Alpine Bay supports manual VID operation for Vcc and Vnn from the processor. Jumper J7C6 pins 15-16 is shorted to enable manual VID operation for Vcc VIDs as shown in Figure 5. The intent of manual VIDs is for ease of test and debug.

Similarly, Jumper J7C7 pins 15-16 are shorted to enable manual VID operation for Vnn VIDs.

The VIDs are driven to the PMIC. LEDs are provided for both Vnn and Vcc VIDs, which are listed in Section 3.4.



Figure 5. Manual VID Implementation for Vcc in Alpine Bay

2.1.2 Power Management and Key Signals

The processor supports C0, C1, C1E, C2, C2E, C4, C4E and C6 states. None of the ‘Power State’ status signals can be observed on the board directly.

PowerMode signals: The chipset sequences the Intel Atom processor Z670 / Z650 through various states using the POWERMODE[] pins to facilitate cold reset, warm reset, and S0i3 entry and exit.



2.1.3 Memory Support

The Alpine Bay CRB supports a single-channel DDR2 800 memory interface with on-board DDR2 SDRAM devices configured as two ranks.

The data-width of the memory bus is 32-bits.

Memory size:

The Alpine Bay CRB supports eight on-board (soldered down) DDR2 SDRAM devices (x8 data width, 2 Gbit density for each), with four each on top and bottom. The maximum total memory density size is 2 GB.

The maximum data rate supported by SDRAM devices used on board is 800MT/s.

SPD is not supported in Alpine Bay.

Table 2 shows the memory configuration supported on the CRB.

Table 2. Memory Configurations Supported on CRB

Memory Configuration, DDR2-800, 32 bit, 2 Ranks

Total System Memory

Density/ DRAM Chip

Chip Data Width

DRAM Chips / Rank

Ranks Total Devices

Motherboard Configuration

2 GB 2 Gb x8 4 2 8 4 Top +4 Bottom

1 GB 2 Gb x8 4 1 4 4 Top; 4 Bottom

1 Gb x8 4 2 8 4 Top +4 Bottom

2.1.4 Display

LVDS is the only display directly integrated into the Intel Atom processor Z670 / Z650. Details are as follows:

• Single channel LVDS Interface 18bpp

• Single channel LVDS Interface 18bpp (loosely packed pixel formats)

• Single channel LVDS Interface 24 bpp (with a limited number of validated panels)

• Maximum resolution up to 1366x768 @ 60 Hz

• Maximum pixel clock up to 80 MHz

• 50 pin connector (J3F1) on board

• Backlight control and ambient light sensor are supported from Embedded Controller

• EDID read is supported through the Intel SM35 Express Chipset I2C



Caution: Do not use a dual-channel LVDS panel on the platform.

The rework options for LVDS are shown in Table 3.

Table 3. LVDS Rework Options

Description Options STUFF NO_STUFF

LVDS VDD options for panels

3.3V panel - default R3V9 R3V7

5V panel R3V7 R3V9

LVDS VDD Backlight options

Connect to 5V backlight panel- default

R3F10 R3F11

Connect to 12V backlight panel R3F11 R3F10

Pin 37 on the LVDS connector connects to Pin 20 on the panel which is LVDS_EN.

This signal needs to be pulled up to LVDS_EN for the panel (supported in the Kit list) to work.

R2F4

While using panels for the Intel® Atom™ Processors 400 and 500 Series with Intel® 82801 HM I/O Controller CRB, NO STUFF R2F4

Backlight control – PWM or I2C control

Jumper- J2F1

1-x - PWM brightness control - Default

1-2 - I2C control

LVDS PWM selection

Jumper J2D3

1-x: Normal PWM - Default

1-2: Inverted PWM

2.1.5 Touch Panel

The CRB provides support for USB-based Multi-touch interface. Multi-touch panel (CLAA101NT02A) has a USB-based Multi-touch interface assembled with the LVDS panel.

2.1.6 cDMI Interface

• The CRB supports 8-bit cDMI Transmit and receive lanes between the processor and chipset. cDMI is a single-ended bus in the Intel Atom processor Z6xx series.



• cDMI is the key interface between the processor and the Intel SM35 Express Chipset. Peak raw bandwidth of cDMI link per direction is 400 MT/s using a quad-pumped 8-bit transmit and an 8-bit receive data bus.

• Supports CMOS interface. The CRB is configured by default to CMOS by setting the cDMI_GVREF and cDMI_CVREF signals to ½ Vccp. J5E1 and J6E1 are the corresponding jumpers.

2.1.7 cDVO Interface

The cDVO is a dedicated link to transmit the display related pixel information over unidirectional 6-bit lanes from processor to chipset. The maximum speed for this interface is 800 MT/s.

2.1.8 Processor Legacy Signals/Thermals

The thermal diode that monitors the CPU die temperature is connected to a thermal sensor. The thermal diode, that monitors the CPU die temperature, is also available to be probed through a Tj Pro* connector.

The following are important signals:

• IERR#: Asserted when the processor has had an internal error and may have unexpectedly stopped executing. It is indicated by a green LED (CR9H1) on the board.

• PROCHOT#: PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. It is indicated by a red LED (CR9G5) on the board.

• THERMTRIP#: Assertion indicates that the processor junction temperature has reached a level beyond which permanent silicon damage may occur. It is indicated by a red LED (CR9G4) on the board.

2.1.9 Processor Cooling

This embedded platform is passively cooled; however, a 12V fan connector and provided at J6J7 on the CRB.

2.2 Introduction to the PCH – Intel® SM35 Express Chipset

The Alpine Bay CRB supports the Intel SM35 Express chipset (code name ‘Whitney Point’) MPI-socketed on the board. A few high-level features are as follows:

• 65-nm low-power process technology

• Integrated ultra-low-power clock generator

• Fused HDCP 1.3 keys and SCU secured boot



The Intel SM35 Express chipset is the next-generation PCH. Some major feature additions of this chipset over the previous version include:

• HDAudio 1.0 interface with two SDIs

• Single-ported AHCI 1.3 compliant SATA host controller with support for up to 3 Gbps (Gen2) transfer rates

2.2.1 SDIO Interface

The Alpine Bay CRB supports three SDIO ports; SDIO0 and SDIO1 are 8-bit interfaces whereas SDIO2 is a 4-bit interface.

SDIO0 connects to SD/MMC connector J5B1 and can be connected to the eMMC via the stuffing options shown in Table 4.

SDIO1 and 2 connect to another SD/MMC connector J5N1 through a resistor stuffing option. By default, SDIO1 connects to the SD/MMC connector

SDIO2 by default connects to test pads. This option is provided so as to connect to the Comms module.

The three SDIO ports are mapped as shown in Figure 9.



Figure 6. SDIO Block Diagram

Note: WPT signifies code name ‘Whitney Point’, i.e., the Intel SM35 Express Chipset.

The rework options required for SDIO interface are described in Table 4.

Table 4. SDIO [0, 1, 2] Rework Options


SDIO 0

Connect to SD/MMC connector-J5B1

Default

R5P8, R5P5, R5N16, R5P4, R5N13, R5P2, R5N10, R5N17


Connect to eMMC






SD/MMC connector J5N1 (SDIO1/2)

Connect SDIO1 to SD/MMC connector J5N1 (to which SDIO2 is also connected)

Default

R6P12, R6P7, R6P3, R6N13, R6N8, R6N7, R6N6, R6N5

Connect SDIO2 to SD/MMC connector J5N1- in which case SDIO1 will not be available

R6P11, R6P6, R6P2, R6N12, R6P15, R6P19

R5D9, R5D13, R5D14, R5D12, R5D15, R5D10

R6P12, R6P7, R6P3, R6N13, R6N8, R6N7, R6N6, R6N5

R6P20, R6P16

SDIO 2 Connect SDIO2 to test pads

R6P18, P6P14, P6P13,R6P5, R6P1, R6N11

R5D9, R5D13, R5D14, R5D12, R5D15, R5D10

TP6B1, TP6B2, TP5C2, TP5C1, TP5B3, TP5B2

R6P11, R6P6, R6P2, R6N12, R6P15, R6P19

SDIO1 voltage selection for 1.8/3.3V MMC cards on SD/MMC connector

J5N1

3.3V – default

Jumper J6C3- 2-3

1.8V

Jumper J6C3- 1-2

Customers are also advised to implement the board-level changes for SDIO-related items as cited in the Whitney Point PCH Sighting Update (Document Number 458825). Obtain this from your local Intel Field Applications Engineer and/or the Embedded Design Center Technical Documents page:


2.2.2 HD Audio

Intel® High Definition Audio functionality is enabled through the Realtek codec ALC268 (device down). By default, the PCH connects to this codec. The codec is routed to front panel header and back panel header. It provides both 3.3V operation and 1.5V operation (default). The CRB supports low voltage (LV), high-definition codecs I/O. The R6C4 and R6C5 resistors are used to select between 3.3V I/O and 1.5V I/O.




Table 5. Selection of I/O Voltage for the High Definition Audio

I/O Voltage for the High Definition Audio

STUFF NO STUFF

3.3V R6C5 R6C4

1.5V (Default) R6C4 R6C5

2.2.2.1 Audio Back Panel and Front Panel Connector

The HDA codec ALC 268 supports a back-panel three-stack audio jack and a front-panel header. The audio jack and header are supported by a RNM (resistor network method) jack sense line monitoring the plug-in and plug-out status of each jack. This RNM sense line incorporates a resistor-divider network that supports the audio jack and front panel header simultaneously.

The codec ALC268 supports ports A, B, C, D, and F as per the HDA specification. The ports A, C, and F are routed to back panel audio jack and the ports B, D are routed to the back panel header. The assigned functionality for the ports is given in the table below. Also see the pinout table below.

Audio Ports Functions

Pin Number Signal

1 Left channel - Microphone

2 GND

3 Right channel - Microphone

4 PRESENCE#

5 Right channel - Headphone

6 Jack detection return

7 Jack detection sense

8 Key

9 Left channel - Headphone

10 Jack detection return

Front-Panel Audio Header Pinout

Port Name Function

Port A Line Out

Port B Mic

Port C Line In

Port D Head Phone

Port F Mic



Three-Jack Audio Stack

2.2.3 Mott Canyon Usage

The Mott Canyon 4 (MC4) Interposer Card (not included in the Development Kit, but can be obtained from your Intel representative) is provided to enable Intel® High Definition Audio (HDA) and modem functionality on the CRB. Mott Canyon 4 provides two 30-pin MDC1.0 connectors and one 12-pin MDC1.5 connector, supporting up to two HDA codecs simultaneously.

Through reworks, the Mott Canyon 4 card could be used to enable the Intel High Definition Audio functionality. See Appendix A.1 for more information on the Mott Canyon 4 card (J6D2). The SDI signal is routed to Mott Canyon by the following rework:

Description STUFF NO STUFF

SDI routed to MOTT CANYON R5P20 R5P19

2.2.4 SATA Storage

The Intel SM35 Express Chipset has one SATA port, which supports speeds up to 3-Gbps (Gen2) transfer rate.

SATA port is connected to J1C1 (Direct Connect). An option is provided to support a Cable connection through the reworks mentioned in Table 6.

Note: The CRB does not support a power connector for SATA. The ATX power supply included in the Development Kit must be used to power the SATA port via cable connection.

A green LED at CR9G1 indicates activity on SATA channel.

Table 6. SATA Rework Options


SATA Direct connect- default

C1C1, C1C4, C1C6 and C1C8.





Cable connect C1C2, C1C3, C1C5 and C1C7.


2.2.5 Displays from Intel® SM35 Express Chipset / PCH

The CRB supports only HDMI as a Display from the PCH- which is- HDMI 1.3a compliant. The HDMI output supports common consumer-electronic resolutions such as 720 p @ 60Hz, 1080p @ 30 Hz, and 1080i @ 60 Hz. However, any active resolution is possible via the HDMI port so long as the resolution’s pixel clock does not exceed of 108 MHz.

The HDMI connector is located at J4A1. An ESD option is provided on the board which is NO_STUFF by default.

2.2.6 USB

The PCH provides four USB 2.0 ports. It does not support USB 1.1.

In-order to support USB 1.1 and to support more USB ports, an on-board USB RMH (rate matching hub) (EU4B1) is provided which connects to USB port0 of the Intel SM35 Express Chipset.

Overcurrent protection has not been provided.

The Oak Trail Platform Balanced USB Configuration Guide for Windows*7 Technical Advisory (Document Number 473481) includes design recommendations system designers should implement to achieve a balanced USB configuration and optimal performance. The USB implementation is shown in Figure 7.



Figure 7. USB Implementation on Alpine Bay

The USB port mapping is shown in Table 7.

Table 7. USB Port Mapping

USB Port Mapping RefDes

Port 0

Port 0 connects to USB hub – by default. It can connect to back panel connector through reworks.

Port1 and 2 from hub connect to FPIO

Port 3 and 4 from hub connect to- back panel 3-stacked connector

EU4B1- Hub

FPIOs- J5B2

Back panel connector- J4A2



USB Port Mapping RefDes

Port 1

Port 1 connects to Mini-PCIe connector B - use for WiFi

Can be connected to FPIO through reworks

Mini PCIe

PCIe connector J6C1

FPIO - J7C4

Port 2

Port 2 connects to Mini-PCIe connector A - Use for 3G Always On only

Can be connected to FPIO through reworks

Mini PCIe

PCIe connector J8C1

FPIO- J7C4

Port 3- OTG USB On-The-Go (OTG) port connects to back-panel I/O connector

J4A2 (3-stack USB connector)

NOTE: 1. The OTG port which connects to the top port of the triple USB connector (shown in

Figure 8) does not support USB 1.1 devices. 2. OTG USB Client mode requires usage of an external Maxim 3353 USB OTG Charge

Pump IC and supporting circuit along with a special driver from Intel. Intel plans to implement USB OTG Client Mode first and USB OTG Host mode second in priority. Make a request for the USB OTG Technical Advisory and reference circuit from your Intel Field Applications Engineer.

Figure 8. USB 3-Stack Connector on Alpine Bay

USB Hub

A USB 2.0 high-speed hub controller (SMSC USB 2064) is used for extending the number of ports supported on Alpine Bay from four to seven. It has an on-chip driver for a 24-MHz crystal resonator or external 24/48-MHz clock input. It has fully integrated USB termination- pull-up and pull-down resistors.

CRB uses USB2064 36QFN 6x6x0.5mm package at EU4B1.

The different rework options for USB are shown in Table 8.



Table 8. USB Rework Options


USB Port 0

Connect USB Port 0 to USB Hub- default

R4B11, R4B10, R4B36, R4B35

R4B9, R4B8, R4B38, R4B37

Connect Port 0 to back panel connector directly

R4B9, R4B8, R4B38, R4B37

R4B11, R4B10, R4B36, R4B35

USB Port 1

Connect USB Port 1 to mini PCIe connector B – J6C1 (default)

R6D6, R6D4 R6D7, R6D5

Connect USB Port 1 to Front panel header J7C4

R6D7, R6D5 R6D6, R6D4

USB Port 2

Connect USB Port 2 to mini PCIe connector A – J8C1- for “3G Always ON” (default)

R6D2, R7D1 R6D3, R6D1

Connect USB Port 2 to Front panel header J7C4

R6D3, R6D1 R6D2, R7D1

2.2.7 Mini-Cards

The CRB supports the following mini-cards for communications modules:

• 3G: The Ericsson Mobile Broadband Module F3607GW is the 3G card, which is a

USB-based full mini-card. J8C1 - Mini PCIe connector A is implemented with AOAC support. This

connector also has SIM support. The 3G mini-card should be plugged into the mini PCIe connector A only.

AOAC is a feature in which device is powered on even in S3 state. The AOAC feature is enabled using a signal AON_EN from EC. This signal is connected to a FET circuitry, which acts as the switch for Always On voltage rail.

• WiFi: WiFi Card – Lite-On WN6607LH is a USB-based half mini-card (included in

Development Kit).

• WiMAX: WiMAX is supported through the Intel-based half mini-card ‘Kilmer Peak’

(contact Intel to obtain samples). Kilmer Peak is a combo card with both WiFi and WiMAX support. The Alpine

Bay CRB implementation uses only the WiMAX feature that uses the USB interface.

• Bluetooth: Bluetooth is supported through the Intel-based half mini-card ‘Rainbow Peak’. Rainbow Peak is a combo card with both WiFi and Bluetooth support (contact

Intel to obtain samples). The Alpine Bay CRB implementation uses only the Bluetooth feature that uses the USB interface.



All the cards (WiFi, WiMAX, Bluetooth) could be connected to mini-PCIe connector A or B as they don’t support the AOAC feature. But, if the 3G card is used together with any of these cards, the 3G card should always be connected to mini PCIe connector A (J8C1), and the other card to mini PCIe connector B (J6C1).

Upham IV provides the flexibility of using more than two USB-based cards simultaneously.

2.2.8 SPI

Figure 9. SPI Block Diagram

The CRB supports two SPI device down configurations.

• Each SPI device of 2 MB; up to 25-MHz speed

• No socket support for SPI devices

• External programmer is needed to program the SPI devices

SPI #1 – Managed by SCU: 2-Mbyte SPI flash device down (BIOS and SCU Firmware (2 Mbyte)). The SPI device will be on SPI1 CS2#.

SPI #2 - Managed by SCU; used for PMIC.

There is support for on-board Dediprog* programming. Please refer to Section 4.2 for details on SPI programming.

Note: Please ensure that the downloaded SPI image is “verified” before booting.

2.2.9 Legacy I/Os

LPC and I2C are the legacy I/Os supported through the Intel SM35 Express Chipset.

An LPC slot is not provided, but a TPM header is provided via J3E1.

I2C implementation is as shown in the following diagram.



The EC SMBus implementation is as follows:

2.3 Clocks • Integrated clocking is present in the Intel SM35 Express Chipset

Eliminates the need for external clock synthesizer Helps save power by eliminating the need of external clock chips

• Both a 25-MHz crystal and a 14.318-MHz oscillator are required for the Intel SM35 Express Chipset

• The Intel Atom processor Z650 / Z670 requires a 100-MHz BCLK

The block diagram of the platform clocks is shown in Figure 10.



Figure 10. Clock (integrated mode) Block Diagram

2.3.1 Real-Time Clock

The real-time clock (RTC) is implemented in the PMIC and backed up by a coin cell battery. The Intel SM35 Express Chipset doesn’t support the actual RTC and only has virtual RTC support.

This RTC block is clocked from the 32.768-KHz clock from the PMIC. The wake-from-RTC alarm is supported in all Sx states. CMOS RAM is also implemented, but is backed up in SPI NOR flash as there is no RTC-well available in the Intel SM35 Express Chipset.



2.4 Power Management Integrated Circuit (PMIC)

PMIC solutions are available for this platform from Renesas, Maxim, and Freescale Semiconductor.

• Part numbers for each single-chip PMIC are as follows: Renesas = μPD9977 / μPD9975 PMIC Freescale = SC900844JVK PMIC Maxim = MAX8958 PMIC

• System Controller Unit manages the power delivery by requesting PMIC via the SPI bus to deliver appropriate power to the devices

• PMIC interacts with the SCU in the Intel SM35 Express Chipset through SPI2 bus

• There is no standard footprint or solution but all of them follow the voltage rail and sequence requirements

• For more product information and pricing on these PMICs, please visit each vendor’s product page at the following URLs: Renesas (μPD9975/μPD9977)

http://america2.renesas.com/pmd/pmics.html Freescale (SC900844JVK)

http://www.freescale.com/webapp/sps/site/overview.jsp?code=PMICINTEL Maxim (MAX8958)


Note: Intel doesn’t recommend a specific PMIC device. All have passed Intel’s design specifications related to power delivery in Oak Trail based platforms.

http://america2.renesas.com/pmd/pmics.html

http://www.freescale.com/webapp/sps/site/overview.jsp?code=PMICINTEL




2.5 Embedded Controller (EC)

Figure 11. Intel® SM35 Express Chipset-EC-PMIC Block Diagram

The Nuvoton NPCE791E (U2D1A) series embedded controller serves as both SMC and Keyboard controller for the platform. This embedded controller on the platform will be connected to the Intel SM35 Express Chipset through LPC bus. The PMIC and EC devices are connected through GPIOs. 2 MB of flash memory is connected to the EC.

• SCU in the Intel SM35 Express Chipset can communicate with EC over the LPC bus

• Battery Charger is managed by Embedded Controller

• Platform power sequencing is implemented by a combination of the PMIC, EC, and the Intel SM35 Express Chipset

Main functions supported by the EC include:

• Controls 16x8 scan matrix keyboard (J1E2), and PS/2-legacy keyboard and mouse (J1A1)

• Controls one serial port, Port 80, and battery charger

• Provides LVDS backlight control and ambient light sensor

• Serial port – RS232 (J2A1)

• On board Port 80



• Battery monitoring

• Wake/runtime SCI events

• Thermal management

For more information on this EC, visit Nuvoton at:

http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=4fd8a6e3-7caf-4c37-8647-577fb1a0ada9

2.6 Debug Interfaces

The following debug support is provided on the CRB.

• XDP (Extended Debug Port) connector is provided at J6W1 for processor run control debug support. PCH JTAG signals are also connected to the XDP connector.

• On board Port 80 display support. The port 80-83 add-in card could be used on the TPM header located at J3E1.

• DDR2 termination resistors could be used as probing points

• SMA connectors for various debug signals from the Intel Atom Processor Z670 / Z650

• Manual VIDs for Vcc and Vnn from the processor

• Signal injection for 25-MHz clock by using SMA

• Thermal diodes and thermal sensors are supported

• 3.3V compatible JTAG from the Intel SM35 Express Chipset is supported through J6F4 and J6F2

• Power measurement resistor for most platform rails. Power measurement could be done using NetDAQ* jumpers.

• KBC disable option for external KBC tests

• Optional Termination resistors for LVDS

• Battery mode emulation supported

• LID switch present

2.7 Chassis

The Alpine Bay reference board comprises an 8-layer HDI 1-x-1+ board, and measures 12” x 9.6”, and can be mounted in many ATX enclosures.

This CRB as part of this development kit is mounted inside the Antec Two Hundred (v2) standard off-the-shelf PC chassis shown below.





2.7.1 Opening the Chassis (IMPORTANT)

The Development Kit is self-contained in the chassis and designed to allow full access to all of the major interfaces on the CRB. Opening of the chassis and disassembly of any part of the kit is not recommended, but there may be situations (such as removing and replacing the PMIC module) that require you to open the chassis.

The LVDS display cable is connected to the CRB inside the chassis. Care must be taken when removing the chassis side panel so the display cable and the CRB are not damaged. To open the chassis please follow these steps: 1. Unplug the USB connector for USB touch panel functionality, which is plugged into

the topmost port of the USB 3-Stack located on the rear of the case. See the image below for a photo of the USB 3-Stack.

2. Remove the thumbscrews on the rear of the case that allow the removal of the

side panel. 3. Carefully slide the side panel out, taking care not to stretch the display cable. The

cable should allow enough slack for the side panel to be moved far enough to reach into the enclosure.



4. Reach into the enclosure and disconnect the display cable connector using the attached pull tab. Pull directly upward on the tab and never pull on the display cable itself. See the image below - the pull tab is highlighted in a red box.

2.8 Power Supply Solutions, Usage and Recommendation

2.8.1 Power Supply Solutions

The CRB has the option to be powered from three different power sources:

• an ATX power supply

• an AC/DC switching power supply or ‘Mobile Brick’

• one or more external batteries

The Development Kit includes up to three different PMICs (one each for Renesas, Freescale and Maxim subject to availability), and some voltage regulators are necessary to power up the system. There are two main supported power supply configurations Desktop and Mobile. The Desktop solution consists of only using the ATX power supply. The Mobile solution consists of using the Mobile AC brick in conjunction with the batteries. When the Mobile solution is being used, either AC brick or batteries can be plugged in. When both AC brick and the batteries are connected at the same time, the batteries are monitored and charged if necessary.

Notes: 1. Desktop hard drives and cards can only be used with ATX. ATX and AC brick should not

be used simultaneously. 2. Please use an “ATX12V” 1.1 Specification-compliant power supply regardless of vendor

or wattage level (an "ATX12V" rating means V5 min current =0.1 A, "ATX" V5 min



current = 1.0 A, among other differences). For example, the Sparkle Model No. FSP300-60BTVS meets this requirement and is an ATX12V 1.1 Specification-compliant power supply.

3. If the power button on the ATX power supply is used to shut down the system, please wait at least 5 seconds before turning the system on again. Shutting down the system this way is not recommended.

2.8.2 Removing/Replacing the Power Management IC (PMIC)

As stated above, three Power Management IC (PMIC) modules are included. To evaluate each of the different PMIC modules you have received, you will need to open the devkit chassis and replace the existing PMIC module with another of the modules supplied in the kit. Follow the steps below: 1. Open the devkit chassis by following the steps detailed in Section 2.7. 2. Once the chassis side panel has been removed and the display cable disconnected,

locate the PMIC module and unscrew the two fastening screws. The module and screws are pictured below. The screws are highlighted by red boxes in the photo.

3. Remove the PMIC module card by lifting it gently out of the socket. Pull upward from the edge closest to the screws that were removed in the last step and then gently pull up on the opposite end of the card if the card does not pull free of the socket. The photo below illustrates how to do this.



4. Replace the PMIC module with another desired PMIC by inserting the connector on the new PMIC card into the socket on the board. Be sure to orient the PMIC module such that the holes on the module line up with the standoffs for the fastening screws. Press down firmly to ensure the PMIC card lies parallel to the CRB and is securely inserted in the socket.

5. Re-insert and tighten the fastening screws to secure the PMIC module. 6. Plug in the LVDS display cable and replace the chassis side panel. See Section 2.7

to review the steps taken to open the chassis if necessary.

2.8.3 Power Supply Usage and Recommendations

Intel recommends using only Sparkle ATX power supplies for the desktop power supply solution. As the Desktop ATX supplies evolve to meet the increased power for those motherboards, their minimum loading requirements also increase. When you try to run a mobile platform on it, it may not load the 5.0V rail enough to meet the minimum loading requirements for it to maintain regulation.

Intel recommends powering with a 24-pin ATX power supply. A 20-pin ATX power supply can also be used. The following PSU has performed well with Alpine Bay CRBs:

• Sparkle Model No. FSP300-60BTVS meets this requirement and is ATX12V 1.1 Specification-compliant (note that this part may be End Of Life)

These 20-pin ATX power supplies may also work if you can't find the above model number (lower-wattage power supplies are probably better):

• Sparkle (SPI) FSP250-60BT, FSB300-60BT, FSB300-60BTV, FSP350, FSP400-60GN (these supplies have been used to power the CRB, although are not checked against the specification)



2.9 Power Management

2.9.1 Power Management States

Table 9 describes the states of different components during the different power management states:

Table 9. Power Management States

Timer Off Timer On

Component S0 S0 - Idle S3 S4 S5 S4 S5

Intel Atom Processor Z670 / Z650

On, C0-C6

On, C6, power gated Off, DDR SR on Off Off

SM35 chipset On On, power gated On, power gated Off On, power gated

PMIC On On, low leakage On, low leakage Off On, low leakage

SPI Flash On On On Off On

EC On On, low power mode

On, low power mode

AC: On- if battery charging, Off- if battery full Battery: Off

AC: On- if battery charging, Off- if battery full Battery: Off

SATA HDD On On, DPM Off Off Off

HD Audio On On, Suspend Off Off Off

WWAN On On, Suspend Off (on in AON) Off Off

Wake Events All All Hot Keys, WWAN, Power Button, LID, Touch, Timer

Power Button Power Button, Timer

Figure 12 lists the power management states that have been defined for the CRB.



Figure 12. ACPI States

2.10 Power Measurement Support

Power measurement resistors are provided on the platform to measure the power of most subsystems. In Alpine Bay, in-pad power measurement resistors are installed by default. They have the same Intel Part Number (IPN) as the normal resistors. But, from schematics, these can be distinguished from the normal power measurement resistors through resistor symbols that have the word ‘SIP’, as part of the symbol.

All power measurement resistors have a tolerance of 1%. The value of these power measurement resistors are 2 milliohm, 22 milliohm, and 10 milliohm, according to the current rating of each rail. Power on a particular subsystem is calculated using the following formula:

R

VP

2

=

R = value of the sense resistor (e.g., 0.002Ω)



V = the voltage difference measured across the sense resistor.

It is recommended that the user use a high precision digital multi-meter tool such as the Agilent 34401A digital multi-meter to measure the voltage difference. Refer to Table 10 for a comparison of a high precision digital multi-meter (Agilent 34401A) versus a standard precision digital multi-meter (Fluke 79).

Table 10. Digital Multi-Meter

Example System

Sense Resistor Value: 0.002Ω

Voltage Difference Across Resistor: 1.492mV (746mA)

Calculated Power: 1.113mW

Agilent 34401A (6 ½ digit display) Fluke 79 (3 digit display)

Specification: (±0.0030% of reading)

+ (±0.0030% of range)

Specification: ±0.09% ±2 digits

Min Voltage Displayed:

Calculated Power:

1.49193mV

1.1129Mw

Min Voltage Displayed:

Calculated Power:

1.47mV

1.08mW

Max Voltage Displayed:

Calculated Power:

1.49206mV

1.1131mW

Max Voltage Displayed:

Calculated Power:

1.51mV

1.14mW

Error in Power: ±0.009% Error in Power: ±0.3%

As the above table shows, the precision achieved by using a high precision digital multi-meter versus a standard digital multi-meter is ~33 times more accurate.

The Power Measurement resistors provided for the various rails of CPU and PCH are listed in Table 11. The rest of the power measurement resistors will be updated in future revisions of this document.

Table 11. Power Measurement Resistors on Alpine Bay

Signal Group Power Measurement Resistor NetDAQ Support

Intel Atom Processor Z670 / Z650:

VCORE_VCC_LNC_DC R4H1 J3G1

V1p05_VCCPDDR_LNC_DC R5V2 J6G4

V1p8_VCC180_DC R5V1 J5G3

V1p8_VDDQ_DC R5G10 J6G3

V1p8_PANEL_DC R5F23 J6F7

V1p2_VMM_LNC_DC R6G1 J6G1



Signal Group Power Measurement Resistor NetDAQ Support

VGFX_VNN_LNC_DC R5G2 J5G1

V1p05_VCCP_DC R6F1 J6F6

V1p05_VCCPAOAC_DC R5G8 J5G2

V1p5_VCCA_LNC_DC R6H1 J6H1

V1p05_VCCP_DC R5U1 J5F2

Intel SM35 Express Chipset:

VCCAUSB25ABC_LNW_DC R6C6 J5C5

PWRP_LNW_DC R5D21 J5D3

V3p3_FLASH1 R5D16 J5D2

VCC123_LNW_DC R5C5 J5B4

V3p3_VCCADIS_LNW R6C9 J5C6

V2.5_SATA_FB R5C7 J5C3

V1.2_SATA_FB R5B6 J5B3

V_PWR_CSB R3C21 J3C3

VPWRI2S R5C6 J5C1

PWRPPMIC_LNW R6C10 J6C4

VCCHPM_LNW_DC R3D12 J4D2

PWRPBT_LNW_DC R6C2 J5C4

VCC25_LNW_DC R6C1 J5C2

PWRADMINDVO_LNW_DC R3C1 J3C1

PWRPDMIDVO_LNW_DC R6D19 J6D3

VCC_STIO_0_LNW_DC R6D18 J6D1

VCC_STIO_2_LNW_DC R5C8 J5C7

VCCHCLK08_LNW_DC R3D7 J4D1

VCCHCLK33_LNW_DC R5D18 J5D4

VCCHDMI_FILT R4C1 J4B2

VCCHDMIBG_FILT R5B7 J4B1

VCCHDMI18_LNW_DC R4B34 J4B3

Embedded Controller:

V3.3A_KBC R2D4

V3.3S_KBC R2E11

Reference Board Summary


3 Reference Board Summary

3.1 Features

The following figures show the location of the major components on the CRB and the table mentions the RefDes for each component.

Figure 13. Alpine Bay Components – Top View

Table 12. CRB Components List - Top View

Item# Description RefDes

1a 2x10 header SPI1 J9A2

1b 2x10 header SPI0 J9C1




1c Front panel header J9E1

2 PCIe x1 connector J9B3

3 PCIe x1 connector J9D1

4 VID LEDs

5 PCIe mini connector A J8C1

6 PCIe mini connector B J6C1

7 PMIC connector (install PMIC here) J6E8

8 3 stack USB connector J4A2

9 HDMI connector J4A1

10 3 jack Audio connector J3A1

11 Serial port J2A1

12 Audio codec U3B1

13 PS2 J1A1

14 SM35 Express chipset (PCH) U4D1

15 Nuvoton Embedded controller - NPCE791E U2D1

16 SATA receptacle J1C1

17 TPM Header J3E1

18 Intel Atom Processor Z670 / Z650 (CPU) U4G1

19 LVDS connector J3F1

20 Keyboard connector J1E1

21 Power 24-pin J1J1

22 Memory down DDR2- top rank U5H1, U5H2, U4H1, U4H2

23a Reset button SW3J1

23b Power button SW3J2



Figure 14. Alpine Bay Components –Bottom View

Table 13. CRB Components List - Bottom View

Item Description RefDes

1 XDP connector J6W1

2 Memory down DDR2 - bottom rank U5W2, U5W1, U4W2, U4W1

3 cDVO test point -

4 cDMI Tx test point -

5 cDMI Rx test point -

3.2 Back Panel Connectors

Figure 15 shows the back-panel connectors on the Alpine Bay CRB, and Table 14 lists the reference designator for each connector.



Figure 15. Back Panel Connectors

Table 14. Back Panel Connectors

Description RefDes

PS/2 J1A1

Serial port J2A1

3 stack Audio connector J3A1

HDMI connector J4A1

Triple USB 2.0 connector J4A2

SD/MMC connector (SDIO0) J5B1

3.3 Configuration Settings

3.3.1 Configuration Jumpers/Switches

Caution: Do not move jumpers with the power on. Always turn off the power and unplug the power cord from the computer before changing jumper settings; not doing so may damage the board. Table 15 lists the jumpers on Alpine Bay.

Table 15. Configuration Jumper

Ref Default Functionality

J1D1 1-X Virtual Battery

J1F1 1-X Force SMC shutdown

J2B2 1-X Programming EC SPI Flash

J2D1 1-X 1-2: Disable EC

J2D2 1-X 1-2: EC JTAG enable




J2D3 1-X

LVDS PWM selection

1-X: Normal PWM

1-2: Inverted PWM

J2D4 1-X SMC LID switch

J7A1 1-x 1-2: Programming Intel SM35 Express Chipset SPI Flash

J3D1 1-X 1-2: Enable SV setup

J3D2 1-X 1-2: Reserved - CMOS default

J3D4 1-X EC Reserved 1. 1-2: EC_TEST

J5E1 1-X 1-X: CDMI CLK CMOS mode

1-2: Reserved

J6D9 1-X Reserved - PMIC GPIO

J6D10 1-X Reserved - PMIC GPIO Reset

J6E1 1-X 1-X: CDMI Data CMOS mode

1-2: Reserved

J6E2 1-2 1-X: Reserved

1-2: CDVO Data- GTL mode

J6E3 1-2 1-X: Reserved

1-2: CDVO Clk- GTL mode

J6E4 1-X Reserved - ATOM Z670 / Z650 presence detect

1-2: If ATOM Z670 / Z650 is not installed

J6F1 1-X Reserved - SM35 CHIPSET presence detect

1-2: If SM35 CHIPSET is not installed

J6F5 1-X Reserved - PMIC GPIO M5 Stall

J6G2 1-X SM35 CHIPSET JTAG select

J7C3 1-X 1-2: DDR Ratio select

J7D2 1-X Reserved - PMIC GPIO SV Setup

J9F1 1-X 1-2: Force VID Enable

J9F2 1-X 1-2: Force VID Enable

J2F1 1-X

LVDS Backlight select - I2C based or PWM based-

1-X: PWM

1-2: I2C

J6J4 Reserved

J6J5 Reserved

J3B1 Reserved - USB OTG (On The Go) ID




J3C2 Reserved

J2A2 2-3 EC debug on RS232- Rx

J2B1 2-3 EC debug on RS232-Tx

J6C2 2-3

1.8V or 3.3V selection for SDIO1

1-2: 1.8V

2-3: 3.3V

J6C3 2-3

1.8V or 3.3V selection for SDIO1

1-2: 1.8V

2-3: 3.3V

J6F3 1-2

BSEL override

x BSEL1 = 0 100 MHz

2-3 Reserved

1-2 BSEL_LNC (CPU drives) DEFAULT

J6J3 1-2 Reserved - Voltage selection for fusing

J7C1 1-X

GPIO expander

1-2: Pull up OS_LOC0 to 3.3V

1-3: Pull down

J7C2 1-X

GPIO expander

1-2: Pull up OS_LOC1 to 3.3V

1-3: Pull down

J7C5 2-3

PMIC GPIO voltage selection

1-2: Vcc_GPIO on PMIC connects to 1.8V

2-3: Connects to 3.3V

J8A1 1-X Manufacturing mode

J9A1 1-X

GPIO Expander

1-2: FW_RECOV to 3.3V

2-3: Connect to gnd

J9B1 1-X

GPIO Expander

1-2: AC_PRESENT to 3.3V

2-3: Connect to gnd

J9B2 1-X

GPIO Expander

1-2: OS_RECOV to 3.3V

2-3: Connect to gnd




J9B4 2-3

PCIe slot1 power control –

1-2: 3.3U

2-3: 3.3S

J9D2 2-3

PCIe slot2 power control --

1-2: 3.3U

2-3: 3.3S J6J2 1-2, 3-4 2x2 header- THERMAC and THERMDC

Note: A jumper consists of two or more pins mounted on the motherboard. When a jumper cap is placed over two pins, it is designated as 1-2. When there are more than two pins on the jumper, the pins to be shorted are indicated as 1-2 (to short pin 1 to pin 2), or 2-3 (to short pin 2 to pin 3). When no jumper cap is to be placed on the jumper, it is designated as 1-X.

3.3.2 Power On and Reset Button

The CRB has two push-buttons, POWER and RESET. The POWER button releases power to the entire board causing the board to boot. The RESET button forces all systems to warm reset. The two buttons are located as indicated in the following tables.

Table 16. Power On and Reset Button


1 Power Button SW3J2

2 Reset Button SW3J1

Table 17. Other CRB Switches

Item# Description RefDes Default Switch Settings

1 SMC LID switch SW1D1 (1-2)

3 Virtual battery SW2D1 (1-2)

3.4 LEDs

The following LEDs provide status of various functions:

Page numbers in Table 18 are from the Intel document, Schematic: Oak Trail Platform, Alpine Bay—Customer Reference Board (CRB); Document Number 448204.



Table 18. CRB LEDs

Function RefDes LED Color Page# on the

Schematics for reference

Indicates IERR CR9H1 Green 41

PROCHOT CR9G5 Red 41

THERMTRIP CR9G4 Red 41

PMIC PWRGOOD CR9G2 Green 41

SYSTEM POWER GOOD CR2F7 Green 41

RESET OUT CR9G3 Green 41

POWERMODE0 CR6H2 Green 41



BSEL CR6H3 Green 41

VNN_VID0 CR9F7 Green 57







VCC_VID_LED0 CR9F14 Green 57

VCC_VID_LED1 CR9F13 Green 57

VCC_VID2 CR9F12 Green 57





System in S5 CR1F4 Green 41




NUM_LOCK CR2F4 Green 41

CAPS_LOCK CR2F5 Green 41

SCROLL_LOCK CR2F6 Green 41

WPAN_A CR8C2 Green 33



Function RefDes LED Color Page# on the

Schematics for reference

WLAN_A CR8C1 Green 33

WWAN_A CR8C3 Green 33

WPAN_B CR7B1 Green 34

WLAN_B CR7B3 Green 34

WWAN_B CR7B2 Green 34

SATA_LED CR9G1 Green 28

Quick Start


4 Quick Start The following sections summarize the necessary hardware and power-on instructions for the customer reference board (CRB).

4.1 Required Peripherals • ATX power supply or mobile AC brick

• Keyboard, mouse (USB or PS/2)

• Hard drive (SATA required – Intel X25-V (40 GB) or X25-M (80GB or 160 GB) SATA Solid State Drive recommended)

• LVDS panel (Chunghwa Telecom CLAA101NT02A)

• PMIC module (Renesas, Maxim, and Freescale PMIC modules each included in Development Kit)

4.2 Instructions to Program SPI Flash (BIOS)

The Alpine Bay CRB requires one SPI image for BIOS and one SPI for the Embedded Controller (EC) firmware. The Development Kit’s CRB is pre-loaded with the latest EFI BIOS and firmware for both the Embedded Controller (EC) and Intel SM35 Express Chipset. Though not recommended, you can reprogram the BIOS as follows. Obtain the .bin file containing the latest BIOS for Alpine Bay CRB from http://edc.intel.com/Platforms/Atom-Z6xx/default.aspx#software. 1. Remove all the power supplies to the board. 2. Connect the DediProg SF100 at J7B1. 3. Set jumpers J7A1 to 1-2. 4. Flash the .bin image corresponding to SPI. 5. Once the programming is successful on the SPI, set J7A1 to 1-X. 6. Remove the DediProg connector.

http://edc.intel.com/Platforms/Atom-Z6xx/default.aspx#software

Quick Start


Figure 16. SPI Programming Jumpers

4.2.1 EC Programming

The Alpine Bay CRB contains the Nuvoton Embedded Controller (U2D1) on the top side of the board. Though not recommended, you can reprogram the EC’s firmware as follows. 1. Obtain the .bin file containing the latest firmware for the Nuvoton NPCE791EA0DX

Embedded Controller (EC) included in latest firmware package from http://edc.intel.com/Platforms/Atom-Z6xx/default.aspx#software.

2. Remove all the power supplies to the board. 3. Connect the DediProg SF100 at J2B3. 4. Set jumpers J2B2 to 1-2. 5. Flash the .bin image corresponding to SPI. 6. Once the programming is successful on the SPI, set J2B2 to 1-X. 7. Remove the DediProg connector.

http://edc.intel.com/Platforms/Atom-Z6xx/default.aspx#software

Quick Start


Figure 17. Embedded Controller Programming Jumpers

4.3 Key Jumpers

Jumper Position

J2D1 1-X

J2D3 1-X

J6E2 1-2

J6E3 1-2

J2F1 1-X

J6C3 2-3

J9B4 2-3

J9D2 2-3

J6J2 1-2, 3-4

4.4 Power Up

Complete the following steps to operate the reference board.

Note: These steps may already have been completed with the Alpine Bay CRB that you received in the Development Kit.

1. Place the processor in socket U4G1 and lock in place (make sure to align the chip to the pin 1 marking)

Quick Start


2. Place the chipset at U4D1 3. Install the configuration jumpers as shown in the previous section. 4. Verify presence of RTC battery in Battery Holder at XBT8D1.

The following steps need to be completed by the user: 1. For desktop power configuration, plug in an ATX power supply into J1J1. 2. Optionally plug in a battery pack into J2J1. Do not connect an ATX power supply

and AC brick simultaneously. 3. Make sure your chosen PMIC module is connected at J6E8. 4. Attach a SATA based hard drive in J1C1. 5. Connect the LVDS panel (as indicated in the Kit items list) at J3F1 and set the

jumpers as mentioned in the Key jumpers section for this panel. 6. Connect a PS/2 keyboard in J1A1 (bottom) or a USB keyboard in one of the USB

connectors. 7. Connect a PS/2 mouse in J1A1 (top) or a USB mouse in one of the USB

connectors.

Procedure for Connecting LVDS Display 8. Place the flat connector of the LVDS cable as shown below near the port at the

bottom of the display panel.

Insert connector as shown; it should click into place.

Quick Start


Take the opposite end of the LVDS cable and orient it on the board as shown in the photo below.

Press the connector into the slot until it snaps into place as shown below.

Quick Start


Procedure for Connecting USB Touch to the LVDS Panel Take the 6-pin adapter board and match up pin 1 on the board to pin 1 on the ribbon cable on the bottom front of the display.

Clip the ribbon into the board as shown.

Quick Start


Plug the USB to 6-pin adapter cable into the adapter board as shown in the photo, then plug the USB cable into a USB slot on the reference board. The second or third slot should be used, since the top USB slot is for high-speed USB (2.0) devices only.


Powering up the board 1. Press the power button located at SW3J2. 2. As the system boots, press F2 to enter the BIOS setup screen. 3. Check time, date, and configuration settings. The default settings should be

sufficient for most users. 4. Save and exit the BIOS setup. 5. The system boots and is ready for use.

Powering down the board

There are two options for powering-down the Customer Reference Platform (CRB) 1. Use O/S-controlled shutdown through the Windows 7 / Windows Embedded 7

Start menu (or equivalent) 2. Press the power button on the motherboard at SW3J2 to begin power-down. If the

system is hung, it is possible to asynchronously shut the system down by holding the power button down continuously for 4 seconds.

Note: Intel does not recommend powering-down the board by simply shutting off power at the ATX power supply.


A Add-In Cards

A.1 Mott Canyon 4 Interposer

The Mott Canyon 4 (MC4) Interposer Card is not included with this Development Kit, but can be obtained and used to enable Intel® High Definition Audio (HDA) and modem functionality on the Customer Reference Platform (CRB). MC4 provides two 30-pin MDC1.0 connectors and one 12-pin MDC1.5 connector, supporting up to two HDA codecs simultaneously. The Interposer plugs into any PCI Express* or PCI slot for mechanical stability and is electrically connected to the platform via a 2x13 ribbon cable from MC4 card to a 2x8 header (J9E6) and 2x4 header (J9E8) on the CRB. Headers on MC4 are provided for both modem and audio sideband signals. MC4 provides four audio jacks and one modem jack. A set of four more audio jacks may be added by using the MC4 paddle card. MC4 paddle card also provides one jack each for S/PDIF IN and S/PDIF OUT. For additional information, see the Alpine Bay CRB schematics. A diagram of the MC4 interposer and paddle card on a platform is shown in Figure 18.

Figure 18. Mott Canyon 4 Interposer Card


A.1.1 Mott Canyon 4 Jumper Settings

The Mott Canyon (MC) 4 Interposer has the ability to select either Primary or Secondary HDA functionality for MDC0 and MDC1 connectors with two jumper options, J16 and J25. See Table 19 for details. MC supports an Intel® High Definition Audio modem-only codec.

The Intel® SM35 Express Chipset supports up to four SDATA_IN channels (0, 1, 2, and 3). MC4 supports three channels (0, 1, and 2) of codecs. Mapping of four Intel SM35 Express Chipset channels on the MC4 card can be done using strapping resistors on Alpine Bay CRB. Three jumpers, J27, J28, and J29 are used to select the appropriate SDATA_IN channel for MDC. The default and optional mapping of SDATA_IN signals are shown in Table 19. Please be aware that SDATA_IN channels 1 and 2 can also be overridden. If either SDATA_IN1 or SDATA_IN2 are not chosen properly on the evaluation platform, these lines will not be available to the Mott Canyon 4 Interposer Card. Proper operation of the Intel High Definition Audio interface requires that only one SDATA_IN line to be routed to one codec at a time.

Table 19. Mott Canyon 4 Configuration Jumper/Switches Settings

# Description Default Setting

Optional Setting RefDes

1 ACZ_SD_0 Destination

(MDC-0-1-2)

1-2 for MDC0 codec A

3-4 for MDC0 codec B




J27


(MDC-0-1-2)






J28


(MDC-0-1-2)






J29


# Description Default Setting

Optional Setting RefDes

4 MDC0 Primary Jumper

1-2 for secondary 2-3 for primary J16

5 MDC1 Primary Jumper

1-2 for secondary 2-3 for primary J25

6 3.3V Power Option 1-2 for mobile 2-3 for desktop J24

7 5.0V Power Option 2-3 for desktop 1-2 for mobile J32

8 MDC0 Docking

Emulation (Switch Enable)

1-2 for OFF 2-3 for ON J33

9 MDC0 Docking

Emulation (DOCK_RST#)

1-2 for normal 2-3 for ON J26

A.2 Port 80-83 Add-in Card

Port 80-83 Add-in card (not included with Development Kit; if needed, contact your Intel representative) plugs to the CRB through TPM header (J3E1). It also provides an additional 10-pin LPC header for LPC supported interfaces. The Port 80-83 card decodes the LPC bus BIOS POST codes and displays on four 7-segment display. The card was recently re-spun to support a low-cost CPLD. See Figure 19.

Figure 19. a) TPM header b) Port 80 c) Port 80 on TPM header in CRB

a) b) c)


Figure 20. Port 80-83 Add-In Card

EPLD

FWHLPC Header

CRB TPM Header

TPM Module Header Remote Display Header

Display Segment 1

Display Segment 2

Display Segment 3

Display Segment 4

A.3 Upham IV Board (PCI Express Interposer Card)

Intel’s Upham board plugs into the PCIe slots on the CRB. This card is not included in the Development Kit; contact your Intel representative for samples. The card supports the attachment of two independent PCIe mini cards (complied with PCIe mini card specification Rev. 1.0) with USB connection enabled for each. The USB interface is implemented using a separate cabling scheme. The interposer supports a Bluetooth module and allows the concurrent usage of Bluetooth and PCIe mini cards.

This interposer supports the SIM card functionality for the purpose of testing WWAN modules.


Figure 21. Upham IV Add-In Card

Table 20. Upham IV Default Jumper/Switches Settings

Jumper RefDes Default Setting Description Other Options

J1B1 1-2 Power to BT LDO from USB

Open (1-X) – Power Disabled

J4C1 1-X Channel data to Slot2 Closed (1-2) – Enable slot 2 Channel Data to BT through Opamp

J2C1 2-3 H/W Shutdown for BT Closed (1-2) – H/W Shutdown enable for BT

J4C2 1-X BT clock to Slot2 Closed (1-2) – Enable slot 2 Clock to BT clock through Opamp

J7D1 1-2

V3.3_aux or V3.3 select for mini PCIe slot 1

1-2 – V3.3_aux

2-3 – V3.3

Closed (1-2): V3.3_aux

Closed (2-3): Select V3.3

J4D1 1-X V3.3_aux or V3.3 select for mini PCIe

Closed (1-2): V3.3_aux


Jumper RefDes Default Setting Description Other Options

slot 2

1-2 – V3.3_aux

2-3 – V3.3

Closed (2-3): Select V3.3

J6C1 1-X Channel data to slot 0

Closed (1-2) – Enable slot 1 Channel Data to BT through Opamp

J6C2 2-3 BT/Pri_Clock to Slot 0 Closed (1-2) – Enable slot 1 Clock to BT clock through Opamp

J7B1 1-X Power to BT regulator Closed (1-2) - Enable 3.3V AUX power to BT regulator


B Important Recommendations to Utilize the Intel® SM35 Express Chipset Stepping A2 on Customer Platform Customers are advised to implement the instructions included in the documents below on both their prototype and production-based Intel Atom Processor Z6xx and Intel SM35 Express Chipset-based platforms so Intel’s SM35 Express Chipset A2 Stepping operates correctly (as it does on the CRB included in the Development Kit).

• Intel® Atom™ Processor Z6xx Series-based Platform Design Guide (Document Number 448203)

• Schematic: Oak Trail Platform, Alpine Bay—Customer Reference Board (CRB) (Document Number 448204; use Revision 1.5 or newer)

• Intel® SM35 Express Chipset, Reference Clock Board Layout and Component Selection Guidelines Technical Advisory (Document Number 464322)

• Intel® SM35 Express Chipset, SDIO Technical Advisory (Document Number 458825)

• Intel® SM35 Express chipset SATA Detection Sighting Alert (Document Number 453540)

• Intel® SM35 Express chipset PCH Sighting Report Revision 8 (Document Number 455964)

• Intel® SM35 Express Chipset CMOS RAM Support Update Technical Advisory (Document Number 472277)

• Oak Trail Platform Balanced USB Configuration Guide for Windows*7 Technical Advisory (Document Number 473481)

These documents can be downloaded from the Embedded Design Center Technical Documents page: http://edc.intel.com/Platforms/Atom-Z6xx/#hardware



C Terms and Abbreviations

Term Description

ACPI Advanced Configuration Power Interface

AHCI Advanced Host Controller Interface

AOAC Always On/Always Connected

ATX Advanced Technology Extended (a common power supply form factor)

BIOS Basic Input / Output System

cDMI CMOS Direct Media Interface

cDVO Type of interface between Intel Atom processor Z6xx and Intel SM35 Express Chipset

CPU Central Processing Unit

CRB Customer Reference Board (e.g., Alpine Bay); also known as “RVP”

DDR Double Data Rate

EC Embedded Controller

eMMC Embedded Multi-Media Card

FCBGA Flip Chip Ball Grid Array (type of package used for Intel SM35 Express Chipset)

GPIO General Purpose Input Output

HDA Intel® High Definition Audio

HDCP High-bandwidth Digital Content Protection

IDE Integrated Device Electronics

KBC Keyboard Controller

LED Light Emitting Diode

LNC Lincroft (i.e., Intel Atom Processor Z6750 / Z670)

LPC Low Pin Count

LVDS Low Voltage Differential Signaling

MDC Mobile Daughter Card

Mott Canyon 4 This add-in card enables Intel® High Definition Audio functionality

MPI Type of socket for the processor and the chipset

PBA Reference to part number

PCH Platform Controller Hub

PCI Peripheral Control Interface

PCIe Peripheral Control Interface Express


Term Description

PMIC Power Management Control Unit

PWM Pulse Width Modulation

RefDes Reference Designator

RNM Resistor Network Method

RTC Real Time Clock

Rx Receive

RVP Reference Validation Platform; also known as ‘CRB’

SATA Serial AT Attachment

SCU System Controller Unit

SDI Serial Digital Interface

SIM Systems Integration Management

SKU Stock Keeping Unit (Z670 and Z650 are different SKUs)

SMC System Management Controller

SPI Serial Peripheral Interface

TPM Test Point

Tx Transmit

Upham 4 PCIe to mini-PCIe add-in card with C-link

USB Universal Serial Bus

VID Voltage Identification Digital

WPT Whitney Point (i.e., the Intel SM35 Express Chipset)

XDP Extended Debug Port

§