Intel® Atom™ Processor 330 Series€¦ · Document Number: 320528-003 Intel® Atom™ Processor 330∆ Series Datasheet For systems based on Entry Level Desktop Platform for ‘08

Document Number: 320528-003

Intel® Atom™ Processor 330∆ SeriesDatasheet

For systems based on Entry Level Desktop Platform for ‘08

Revision 003

April 2010

2 Datasheet

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Datasheet 3

Contents

1 Introduction ..............................................................................................................6

1.1 Intel® Atom™ Processor 300 Series Features ..........................................................61.2 Terminology .......................................................................................................71.3 References .........................................................................................................8

2 Low Power Features ..................................................................................................9

2.1 Clock Control and Low-power States ......................................................................92.1.1 Thread Low-power State Descriptions........................................................ 10

2.1.1.1 Thread C0 State ....................................................................... 102.1.1.2 Thread C1/AutoHALT Powerdown State ........................................ 102.1.1.3 Thread C1/MWAIT Powerdown State............................................ 10

2.1.2 Package Low-power State Descriptions...................................................... 112.1.2.1 Normal State............................................................................ 11

2.1.3 Front Side Bus ....................................................................................... 11

3 Electrical Specifications ........................................................................................... 12

3.1 FSB and GTLREF ............................................................................................... 123.2 Power and Ground Pins ...................................................................................... 123.3 Decoupling Guidelines ........................................................................................ 13

3.3.1 VCCP Decoupling .................................................................................... 133.3.2 FSB AGTL+ Decoupling ........................................................................... 13

3.4 Voltage Identification and Power Sequencing......................................................... 143.5 Catastrophic Thermal Protection .......................................................................... 153.6 Reserved and Unused Pins.................................................................................. 153.7 FSB Frequency Select Signals (BSEL[2:0]) ........................................................... 163.8 FSB Signal Groups............................................................................................. 163.9 CMOS Asynchronous Signals ............................................................................... 183.10 Maximum Ratings.............................................................................................. 183.11 Processor DC Specifications ................................................................................ 193.12 AGTL+ FSB Specifications................................................................................... 23

4 Package Mechanical Specifications and Ball Information ......................................... 24

4.1 Package Mechanical Specifications ....................................................................... 244.1.1 Package Mechanical Drawings .................................................................. 254.1.2 Package Loading Specifications ................................................................ 254.1.3 Processor Mass Specifications................................................................... 25

4.2 Processor Pinout Assignment............................................................................... 254.3 Signal Description ............................................................................................. 31

5 Thermal Specifications and Design Considerations .................................................. 39

5.1 Thermal Specifications ....................................................................................... 395.1.1 Thermal Diode ....................................................................................... 405.1.2 Intel® Thermal Monitor........................................................................... 425.1.3 Digital Thermal Sensor............................................................................ 445.1.4 Out of Specification Detection .................................................................. 445.1.5 PROCHOT# Signal Pin ............................................................................. 44

6 Debug Tools Specifications ...................................................................................... 46

4 Datasheet

Figures

2-1 Thread Low-power States ......................................................................... 94-2 Package Mechanical Drawing ....................................................................254-3 Pinout Diagram (Top View, Left Side) ........................................................264-4 Pinout Diagram (Top View, Right Side) ......................................................27

Tables

2-1 Coordination of Thread Low-power States at the Package Level.....................103-2 Voltage Identification Definition ................................................................143-3 Processor VID Pin to VRD11 VID Pin Mapping .............................................153-4 BSEL[2:0] Encoding for BCLK Frequency....................................................163-5 FSB Pin Groups ......................................................................................173-6 Processor Absolute Maximum Ratings ........................................................183-7 Voltage and Current Specifications for the processor....................................193-8 FSB Differential BCLK Specifications ..........................................................203-9 AGTL+/CMOS Signal Group DC Specifications .............................................213-10 Legacy CMOS Signal Group DC Specifications .............................................223-11 Open Drain Signal Group DC Specifications ................................................224-12 Pinout Arranged By Signal Name...............................................................284-13 Signal Description...................................................................................315-14 Power Specifications for the Standard Voltage processor ..............................405-15 Thermal Diode Interface ..........................................................................415-16 Thermal Diode Parameters using Transistor Model.......................................41

Datasheet 5

Revision History

§

Revision Number

Description Date

-001 • Initial Release September 2008

-002 • Update pin-map• Add SSSE3• Changed A[35:2] to A[32:2]• Changed Vboot • Changed Ron and Rodt• Removed L2 Dynamic Cache Sizing

February 2009

-003 • Updated Table 3-7: Removed information on dI/dt April 2010

Introduction

6 Datasheet

1 Introduction

The Intel® Atom™ processor 330 series is built on 45-nanometer Hi-k process technology. This document contains electrical, mechanical and thermal specifications for the processor.

Note: In this document, the Intel Atom processor 330 series will be referred to as the processor. Intel chipsets shall be referred as GMCH and ICH respectively.

1.1 Intel® Atom™ Processor 300 Series Features• Available at 1.6 GHz,

• New dual-core processor for Entry Level Desktop Platform PCs with enhanced performance

• On die, primary 32-kB instructions cache and 24-kB write-back data cache, per core

• 533-MHz Source-Synchronous front side bus (FSB)

• Threading enabled

• On die 512-kB, 8-way L2 cache, per core: total of 1 MB cache

• Support for IA-32 and Intel® 64 architecture

• Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3) support

• Micro-FCBGA8 packaging technologies

• Thermal management support using TM1

• FSB Lane Reversal for flexible routing

• Supports C0 and C1 states only

• Execute Disable Bit support for enhanced security

This processor series represents a new family of processors designed from the ground-up on a ground-breaking new low-power microarchitecture. It is manufactured on industry-leading 45-nm process with Hi-K Metal Gate technology.

This processor series enables a new class of simple and affordable internet-centric computers called “antelopes” that is best suited for applications focused on internet usage models—communicate, listen, watch, play, share, and learn.

Datasheet 7

Introduction

1.2 Terminology

Term Definition

# A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

Front Side Bus (FSB)

Refers to the interface between the processor and system core logic (also known as the GMCH chipset components).

AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors.

CMOS Complementary metal-Oxide semiconductor.

Storage Conditions

Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core.

Intel® 64 Technology

64-bit memory extensions to the IA-32 architecture.

TDP Thermal Design Power

VCC The processor core power supply

VR Voltage Regulator

VSS The processor ground

Introduction

8 Datasheet

1.3 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document:

§

DocumentDocument Number

Intel® Atom™ Processors 200 Series Specification Update www.intel.com/design/processor/specupdt/319978.pdf

Intel® Atom™ Processors 200 Series Thermal and Mechanical Design Guidelines

www.intel.com/design/processor/designex/319979.pdf

AP-485, Intel® Processor Identification and CPUID Instruction Application Note

http://www.intel.com/design/processor/applnots/241618.htm

Voltage Regulator-Down (VRD) 11.0 - Processor POwer Delivery Design Guidelines

http://www.intel.com/design/processor/applnots/313214.htm

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture http://www.intel.com/products/processor/manuals/index.htm

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

Datasheet 9

Low Power Features

2 Low Power Features

2.1 Clock Control and Low-power StatesThe processor supports low power states at the thread level and the package level. A thread may independently enter the C1/AutoHALT and C1/MWAIT low power states. Package low power states include Normal, Stop Grant, and Stop Grant Snoop. When both threads are in a common low-power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P_LVLx I/O read to the chipset.

The processor implements two software interfaces for requesting low power states, MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured in a software programmable MSR.

Figure 2-1 shows the thread low-power states. Table 2-1 provides a mapping of thread low-power states to package low power states.

Figure 2-1. Thread Low-power States

C0

C1/MWAIT Core state

break

MWAIT(C1)

C1/Auto Halt

Halt break

HLT instruction

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interruptcore state break = (halt break OR Monitor event)

Low Power Features

10 Datasheet

NOTES:1. AutoHALT or MWAIT/C1.2. To enter a package state, both threads must be in a common low power state. If the

threads are not in a common low power state, the package state will resolve to the highest power C state.

2.1.1 Thread Low-power State Descriptions

2.1.1.1 Thread C0 State

This is the normal operating state for threads in the processor.

2.1.1.2 Thread C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a thread executes the HALT instruction. The processor thread will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information.

While in AutoHALT Powerdown state, the processor threads will process bus snoops and snoops from the other thread. The processor will enter a snoopable sub-state (not shown in Figure 2-1) to process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3 Thread C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor thread executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

Table 2-1. Coordination of Thread Low-power States at the Package Level

Thread StatePackage State2

C0 C11

C0 Normal Normal

C11 Normal AutoHalt

Datasheet 11

Low Power Features

2.1.2 Package Low-power State Descriptions

Note: The following state descriptions assume that both threads are in the a common low power state. For cases when only one thread is in a low power state, please see Section 2.1.1.

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor remains in the Normal state when the threads are in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.3 Front Side Bus

The processor has only one signaling mode, where the data and address busses and the strobe signals are operating in GTL mode. The reason to use GTL is to improve signal integrity.

§

Electrical Specifications

12 Datasheet

3 Electrical Specifications

This chapter contains signal group descriptions, absolute maximum ratings, voltage identification and power sequencing. The chapter also includes DC and AC specifications, including timing diagrams.

3.1 FSB and GTLREF

The processor supports two kinds of signalling protocol: Complementary Metal Oxide

Semiconductor (CMOS), and Advanced Gunning Transceiver Logic (AGTL+). For FSB

data and address bus, only AGTL+ is used.

The termination voltage level for the processor CMOS and AGTL+ signals is VTT = 1.10 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families.

The CMOS sideband signals are listed in Table 3-5.

The AGTL+ inputs, including the sideband signals listed in Table 3-5, require a reference voltage (GTLREF_MA, GTLREF_EA) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF_* must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (VTT). The appropriate chipset will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals.

The AGTL+ bus depends on incident wave switching. Timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system.

3.2 Power and Ground PinsFor clean, on-chip power distribution, the processor will have a large number of VTT (FSB AGTL+ reference voltage), VCCP (power) and VSS (ground) inputs. All power pins must be connected to VCCP power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCCP pins must be supplied the voltage stated in Table 3-7

Datasheet 13


3.3 Decoupling GuidelinesDue to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 3-7. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines.

3.3.1 VCCP Decoupling

VCC regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution For more details on decoupling recommendations, refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines.

3.3.2 FSB AGTL+ Decoupling

The processors integrate signal termination on the die. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation.


14 Datasheet

3.4 Voltage Identification and Power Sequencing

The VID specification for the processor is defined by the RS - Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines.

The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for processor are CMOS outputs driven by the processor VID circuitry. Table 3-2 specifies the voltage level corresponding to the state of VID[6:0]. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage level. For more details about VR design to support the processor power supply requirements, Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines.

VRD11 has 8 VID pins (VID[7:0]) compared to 7 VID pins for processor. VRD11 VID[n] should be connected to processor VID[n-1]. VRD11 VID[0] should be tied to Vss.

Table 3-2. Voltage Identification Definition

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCC (V)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCC (V)

0 1 0 0 0 0 1 1.2000 0 1 1 0 1 1 0 0.9375

0 1 0 0 0 1 0 1.1875 0 1 1 0 1 1 1 0.9250

0 1 0 0 0 1 1 1.1750 0 1 1 1 0 0 0 0.9125

0 1 0 0 1 0 0 1.1625 0 1 1 1 0 0 1 0.9000

0 1 0 0 1 0 1 1.1500 0 1 1 1 0 1 0 0.8875

0 1 0 0 1 1 0 1.1375 0 1 1 1 0 1 1 0.8750

0 1 0 0 1 1 1 1.1250 0 1 1 1 1 0 0 0.8625

0 1 0 1 0 0 0 1.1125 0 1 1 1 1 0 1 0.8500

0 1 0 1 0 0 1 1.1000 0 1 1 1 1 1 0 0.8375

0 1 0 1 0 1 0 1.0875 0 1 1 1 1 1 1 0.8250

0 1 0 1 0 1 1 1.0750 1 0 0 0 0 0 0 0.8125

0 1 0 1 1 0 0 1.0625 1 0 0 0 0 0 1 0.8000

0 1 0 1 1 0 1 1.0500 1 0 0 0 0 1 0 0.7875

0 1 0 1 1 1 0 1.0375 1 0 0 0 0 1 1 0.7750

0 1 0 1 1 1 1 1.0250 1 0 0 0 1 0 0 0.7625

0 1 1 0 0 0 0 1.0125 1 0 0 0 1 0 1 0.7500

0 1 1 0 0 0 1 1.0000 1 0 0 0 1 1 0 0.7375

0 1 1 0 0 1 0 0.9875 1 0 0 0 1 1 1 0.7250

0 1 1 0 0 1 1 0.9750 1 0 0 1 0 0 0 0.7125

0 1 1 0 1 0 0 0.9625 1 0 0 1 0 0 1 0.7000

0 1 1 0 1 0 1 0.9500

Datasheet 15


Power source characteristics must be stable whenever the supply to the voltage regulator is stable.

3.5 Catastrophic Thermal ProtectionThe processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCCP supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.

3.6 Reserved and Unused PinsAll RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See section Chapter 4.2 for a pin listing of the processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected.

Table 3-3. Processor VID Pin to VRD11 VID Pin Mapping

Processor VID pin map to VRD11 VID pin

6 7

5 6

4 5

3 4

2 3

1 2

0 1

0 (tie to VSS)


16 Datasheet

3.7 FSB Frequency Select Signals (BSEL[2:0]) Only 133 MHz is supported by the processor. The BSEL[2:0] signals need to be set accordingly to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3-4.

NOTE: All other bus selections reserved.

3.8 FSB Signal GroupsTo simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 3-5 identifies which signals are common clock, source synchronous, and asynchronous.

Table 3-4. BSEL[2:0] Encoding for BCLK Frequency

BSEL[2] BSEL[1] BSEL[0] BCLK Frequency

L L H 133 MHz

Datasheet 17


NOTES:1. Refer to Chapter 4 for signal descriptions and termination requirements.2. In processor systems where there is no debug port implemented on the system board,

these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

3. PROCHOT# signal type is open drain output and CMOS input.4. On die termination differs from other AGTL+ signals, refer to your Platform Design

Guidelines for up to day recommendations.

Table 3-5. FSB Pin Groups

Signal Group Type Signals1

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

BPRI#, DEFER#, PREQ#, RESET#, RS[2:0]#, TRDY#, DPWR#

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, BPM_2[3:0],

AGTL+ Source Synchronous I/O

Synchronous to assoc. strobe

AGTL+ Strobes Synchronous to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS Input Asynchronous IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#

Open Drain Output Asynchronous FERR#, THERMTRIP#, IERR#

Open Drain I/O Asynchronous PROCHOT#

CMOS Output Asynchronous VID[6:0], BSEL[2:0]

CMOS Input Synchronous to TCK

TCK, TDI, TMS, TRST#, TDI_M

Open Drain Output Synchronous to TCK

TDO, TDO_M

FSB Clock Clock BCLK[1:0]

Power/Other COMP[3:0], GTLREF_MA, GTLREF_EA, TEST2/DCLK, TEST1/ACLK, THERMDA, THERMDC, VCCA, VCCP, VTT,

VCC_SENSE, VSS, VSS_SENSE, VCCQ[1:0], COMP_2[3:0],

THRMDA_2, THRMDC_2

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB0#

A[32:17]# ADSTB1#

D[15:0]#, DBI0#, DINV[0]# DSTBP0#, DSTBN0#





18 Datasheet

3.9 CMOS Asynchronous SignalsCMOS input signals are shown in Table 3-5. Legacy output FERR#, IERR# and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than 4 BCLKs for the processor to recognize them. See Section 3.11 for the DC specifications for the CMOS signal groups.

3.10 Maximum RatingsTable 3-6 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

NOTES:1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long term reliability of the device. For functional operation, refer to the processor case temperature specifications.

3. This rating applies to the processor and does not include any tray or packaging. 4. Failure to adhere to this specification can affect the long term reliability of the processor.5. The VCC max supported by the process is 1.2 V but the parameter can change (burnin voltage is higher).

Table 3-6. Processor Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes1,5

TSTORAGE Processor Storage Temperature -40 85 °C 2,3,4

VCCP Any Processor Supply Voltage with Respect to VSS -0.3 1.1 V 6

VCCA PLL power supply -0.3 1.575 V

VinAGTL+ AGTL+ Buffer DC Input Voltage with Respect to VSS -0.1 1.1 V

VinAsynch_CMOS CMOS Buffer DC Input Voltage with Respect to VSS -0.1 1.1 V

Datasheet 19


3.11 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Chapter 4 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 3-9. DC specifications for the CMOS group are listed in Table 3-10.

Table 3-9 through Table 3-11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Unless specified otherwise, all specifications for the processor are at TJ = 90°C. Care should be taken to read all notes associated with each parameter.

NOTES:1. Specified at 90°C TJ. 2. Specified at the nominal VCC.3. Refer to the RS - Voltage Regulator-Down (VRD) 11.0 - Processor Power Delivery Design Guidelines for

design target capability.4. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical

data. These specifications will be updated with characterized data from silicon measurements at a later date.

5. This is the Vcc range, not the absolute Vcc for the core. The Vccp tolerance should be +/- 50mV, inclusive of ripple, VR tolerance and transient (droop and overshoot).

6. Since processor is soldered down with no loadline and no dynamic VID, there is no “socket load line slope (SKT_LL)”; no “socket load line tolerance band” but only “Tolerance Band (TOB)” of 50mV; no “maximum overshoot above VID (OS_AMP)”; no “maximum overshoot time duration above VID (OS_TIME)”; no “peak to peak ripple amplitude (RIPPLE)”; no “thermal compensation voltage drift (THERMAL_DRIFT)”; no “Maximum DC test (Current I_DC_MAX)”; no “minimum DC test *(Current I_DC_MIN)”; “Voltage Regulator Thermal Design Current (VR_TDC) of 3.64A; “current step rise time (I_RISE) of 5A/us”

7. ±50 mV tolerance

Table 3-7. Voltage and Current Specifications for the processor

Symbol Parameter Min Typ Max Unit Notes4

FSB Frequency

BCLK Frequency 132.6 133.33 133.5 MHz

VTT FSB AGTL+ termination voltage with respect to VSS

1.05 1.10 1.15 V

VCCP Vcc Core voltage with respect to VSS 0.7 1.20 V 6

VCC BOOT Default VCC voltage for initial power up 1.10 1.20 V 8

VCCA PLL Supply voltage 1.425 1.5 1.575 V

ITT ICC for VTT supply after VCC stableICC for VTT supply at startup

1.52.5

A 3

ICCDES ICC for processors recommended design target (estimated)

8 A 3

ICC ICC for processors

Processor Number

Core Frequency/Voltage

330 1.6 GHz @ VCC (AVID controlled) 8 A 1, 2

IAH, ICC Auto-Halt 4 A 1, 2

ICCA ICC for VCCA Supply 260 mA


20 Datasheet

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of

BCLK1. 3. For Vin between 0 V and VIH.4. Cpad includes die capacitance only. No package parasitics are included.5. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.6. Measurement taken from differential waveform.7. Measurement taken from single-ended waveform.8. “Steady state” voltage, not including Overshoots or Undershoots.9. Only applies to the differential rising edge (clock rising and clock# falling).

Table 3-8. FSB Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes1

VIH Input High Voltage 1.15 V 7, 8

VIL Input Low Voltage -0.3 V 7, 8

VCROSS Crossing Voltage 0.3 0.55 V 2, 7, 9

ΔVCROSS Range of Crossing Points 140 mV 2, 7, 5

VSWING Differential Output Swing 300 mV 6

ILI Input Leakage Current -5 +5 µA 3

Cpad Pad Capacitance 1.2 1.45 2.0 pF 4

Datasheet 21


NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.4. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the

signal quality specifications.5. GTLREF should be generated from VTT with a 1% tolerance resistor divider. The VTT referred to in these

specifications is the instantaneous VTT.6. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at

0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.7. Specified with on die RTT and RON are turned off. Vin between 0 and VTT.8. Cpad includes die capacitance only. No package parasitics are included.9. This is the external resistor on the comp pins.10. On die termination resistance, measured at 0.33*VTT.11. RCOMP resistance must be provided on the system board with 1% resistors.12. GTLREF_EA & GTLREF_MA resistor divider needs to be separate. This is for better FSB margin.

Table 3-9. AGTL+/CMOS Signal Group DC Specifications


VTT I/O Voltage 1.05 1.10 1.15 V 11

GTLREF_EA GTL Reference Voltage, end-agent

0.63 VTT V 5, 12, 13

GTLREF_MA GTL Reference Voltage, middle-agent

0.58 VTT V 5, 12, 13

RCOMP Compensation ResistorCOMP[0] & COMP[2]COMP[1] & COMP[3]

24.7549.5

2550

25.2550.5

Ω 9, 11

RODT Termination Resistor 55 Ω 10

VIH Input High Voltage GTLREF+0.10 VTT VTT+0.10 V 3,5

VIL Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4

VOH Output High Voltage VTT-0.10 VTT VTT V 5

RTT Termination Resistance 45 50 55 Ω 6

RON (GTL mode)

GTL Buffer on Resistance 8.5 Ω

ILI Input Leakage Current ±100 µA 7



22 Datasheet

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VTT referred to in these specifications refers to instantaneous VTT.3. Measured at 0.1*VTT. 4. Measured at 0.9*VTT. 5. For Vin between 0V and VTT. Measured when the driver is tri-stated.6. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are

included.7. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. Measured at 0.2 V.3. VOH is determined by value of the external pull-up resistor to VTT. Refer to platform design guide for

details.4. For Vin between 0 V and VOH.5. Cpad includes die capacitance only. No package parasitics are included.

Table 3-10.Legacy CMOS Signal Group DC Specifications


VTT I/O Voltage 1.05 1.10 1.15 V 9

VIH Input High Voltage 0.7*VTT VTT VTT+0.1 V 2

VIL Input Low Voltage CMOS -0.10 0.00 0.3*VTT V 2, 3

VOH Output High Voltage 0.9*VTT VTT VTT+0.1 V 2

VOL Output Low Voltage -0.10 0 0.1*VTT V 2

IOH Output High Current 1.5 4.1 mA 5

IOL Output Low Current 1.5 4.1 mA 4

ILI Input Leakage Current ± 100 µA 6

Cpad1 Pad Capacitance 1.6 2.1 2.55 pF 7

Cpad2 Pad Capacitance for CMOS Input

0.95 1.2 1.45 8

Table 3-11.Open Drain Signal Group DC Specifications


VOH Output High Voltage VTT-5% VTT VTT+5% V 3

VOL Output Low Voltage 0 0.20 V

IOL Output Low Current 16 50 mA 2

ILO Output Leakage Current ±200 µA 4


Datasheet 23


3.12 AGTL+ FSB SpecificationsRouting topology recommendations may be found in the appropriate platform design guides. Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation).

Table 3-9 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. It is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well- controlled. For more details on platform design, see the appropriate platform design guides.

§

Package Mechanical Specifications and Ball Information

24 Datasheet

4 Package Mechanical Specifications and Ball Information

This chapter provides the package specifications, pinout assignments, and signal description.

4.1 Package Mechanical SpecificationsThe processor will be available in 512 kB, 437 pins in FCBGA8 package.

Datasheet 25


4.1.1 Package Mechanical Drawings

4.1.2 Package Loading Specifications

Package loading is 10lb max static compressive.

4.1.3 Processor Mass Specifications

Processor mass is 1.8g.

4.2 Processor Pinout AssignmentFigure 4-3 and Figure 4-4 are graphic representations of the processor pinout assignments. Table 4-12 lists the pinout by signal name.

Figure 4-2. Package Mechanical Drawing


26 Datasheet

Figure 4-3. Pinout Diagram (Top View, Left Side)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A VSS RSVD VSS D[54]# D[56]# GTLREF_MA

VSS VCCQ0 VCCP VCCP VCCP RSVD A[35]#

A

B VSS VSS D[60]# D[52]# VSS D[59]# CMREF VSS VCCQ0 VCCP VCCP VCCP VSS A[33]#

B

C RSVD D[48]# D[55]# D[61]# DINV[3] D[58]# D[62]# VSS VTT VCCP VCCP VCCP VCCSENSE

A[22]#

C

D VSS D[63]# D[51]# RSVD VSS GTLREF_EA VCCA VSS VTT VCCP VCCP VCCP VSSSENSE

VSS D

E D[53]# DSTBN[3] VSS THRMDA THRMDC VSS VSS VSS VTT VCCP VCCP VCCP VTT VTT E

F D[50]# D[57]# DSTBP[3] THRMDC_2 VSS VSS VSS VTT VTT VCCP VCCP VCCP VTT VTT F

G VSS D[49]# D[40]# THRMDA_2 BSEL[2] BPM_2[0] VSS VTT VSS VCCP VCCP VCCP VSS VCCQ1

G

H D[46]# D[41]# VSS VSS BSEL[1] BPM2[1] VSS VTT VSS VCCP VCCP VCCP VSS VCCQ1

H

J D[47]# D[45]# D[38]# IGNNE# VSS BSEL[0] VSS VTT VSS VCCP VCCP VCCP VSS VTT J

K VSS DSTBN[2] DSTBP[2] BPM_2[2] BPM_2[3] VSS VSS VTT VSS VCCP VCCP VCCP VSS VTT K

L DINV[2] D[43]# VSS VSS COMP_2[0] VSS VSS VTT VSS VCCP VCCP VCCP VSS VTT L

M VSS D[36]# D[44]# RSVD VSS EXTBGREF VSS VTT VSS VCCP VCCP VCCP VSS VTT M

N D[35]# D[42]# D[39]# COMP_2[2] COMP_2[1] RSVD VSS VTT VSS VCCP VCCP VCCP VSS VTT N

P D[34]# D[37]# VSS COMP_2[3] RSVD VSS VSS VTT VSS VCCP VCCP VCCP VSS VTT P

R VSS D[33]# D[32]# RSVD VSS RSVD VSS VTT VSS VCCP VCCP VCCP VSS VTT R

T COMP[0] COMP[1] D[28]# VSS RSVD RSVD VSS VTT VSS VSS VSS VSS VSS VTT T

U D[19]# D[27]# VSS DPWR# RSVD VSS VSS VTT VTT VTT VTT VTT VTT VTT U

V VSS D[30]# D[26]# VSS RSVD VSS VSS VSS RSVD VTT BCLK[0] BCLK[1] VSS VSS V

W VSS D[25]# D[18]# D[31]# VSS D[21]# D[20]# VSS D[15]# D[1]# VSS D[5]# D[13]# VSS W

Y VSS VSS D24[]# DSTBN[1] DSTBP[1] DINV[1] D[22]# D[17]# D[8]# D[7]# D[0]# D[2]# D[9]# DSTBN[0]

Y

AA VSS VSS VSS D[16]# D[23]# VSS D[29]# D[14]# VSS D[4]# VSS D[11]# D[3]# AA

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet 27


Figure 4-4. Pinout Diagram (Top View, Right Side)

15 16 17 18 19 20 21

A VSS A[20]# A[32]# VSS RSVD VSS A

B A[34]# A[29]# A[30]# A[27]# ADSTB[1]# VSS VSS B

C A[28]# A[31]# VSS A[23]# A[17]# A[24]# RSVD C

D RESET# VID[1] RSVD VSS A[21]# A[26]# VSS D

E VSS VSS VID[5] VID[2] VSS A[25]# A[19]# E

F VID[0] IERR# VSS VSS A[18]# COMP[2] COMP[3] F

G VID[3] VID[4] PROCHOT# VID[6] REQ[2]# A[9]# VSS G

H BPM[2]# VSS THERMTRIP# VSS VSS A[4]# A[11]# H

J BPM[3]# PREQ# VSS BPM[1]# A[7]# A[15]# REQ[1]# J

K VSS TRST# BPM[0]# PRDY# A[14]# ADSTB[0]# VSS K

L RSVD TDO_M TMS VSS VSS A[12]# A[16]# L

M TDI_M TDO TCK RSVD A[10]# A[13]# VSS M

N FORCEPR# TDI VSS SLP# A[8]# A[5]# REQ[0]# N

P VSS VSS RSVD VSS VSS REQ[3]# A[3]# P

R LINT1 STPCLK# DPSLP# DPRSTP# REQ[4]# A[6]# VSS R

T LINT0 FERR# RSVD VSS DRDY# BR0# DEFER# T

U VSS VSS SMI# A20M VSS RS[2]# BPRI# U

V BR1# INIT# PWRGOOD VSS ADS HITM# VSS V

W D[10]# DINV[0] VSS RS[0]# TRDY# LOCK# VSS W

Y DSTBP[0] D[12]# RS[1]# DBSY# BNR# VSS VSS Y

AA VSS D[6]# HIT# VSS VSS VSS AA

15 16 17 18 19 20 21


28 Datasheet

Table 4-12.Pinout Arranged By Signal Name (Sheet 1 of 4)

Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

A[10]# M19 BCLK[0] V11 D[28]# T3 D[62]# C7

A[11]# H21 BCLK[1] V12 D[29]# AA8 D[63]# D2

A[12]# L20 BNR# Y19 D[3]# AA14 D[7]# Y10

A[13]# M20 BPM[0]# K17 D[30]# V2 D[8]# Y9

A[14]# K19 BPM[1]# J18 D[31]# W4 D[9]# Y13

A[15]# J20 BPM[2]# H15 D[32]# R3 DBSY# Y18

A[16]# L21 BPM[3]# J15 D[33]# R2 RSVD V5

A[17]# C19 BPRI# U21 D[34]# P1 DEFER# T21

A[18]# F19 BR0# T20 D[35]# N1 DINV[0]# W16

A[19]# E21 BR1# V15 D[36]# M2 DINV[1]# Y6

A[20]# A16 BSEL[0] J6 D[37]# P2 DINV[2]# L1

A[21]# D19 BSEL[1] H5 D[38]# J3 DINV[3]# C5

A[22]# C14 BSEL[2] G5 D[39]# N3 DPRSTP# R18

A[23]# C18 COMP[0] T1 D[4]# AA11 DPWR# U4

A[24]# C20 COMP[1] T2 D[40]# G3 DRDY# T19

A[25]# E20 COMP[2] F20 D[41]# H2 DSTBN[0]# Y14

A[26]# D20 COMP[3] F21 D[42]# N2 DSTBN[1]# Y4

A[27]# B18 D[0]# Y11 D[43]# L2 DSTBN[2]# K2

A[28]# C15 D[1]# W10 D[44]# M3 DSTBN[3]# E2

A[29]# B16 D[10]# W15 D[45]# J2 DSTBP[0]# Y15

A[3]# P21 D[11]# AA13 D[46]# H1 DSTBP[1]# Y5

A[30]# B17 D[12]# Y16 D[47]# J1 DSTBP[2]# K3

A[31]# C16 D[13]# W13 D[48]# C2 DSTBP[3]# F3

A[32]# A17 D[14]# AA9 D[49]# G2 FERR# T16

A[33]# B14 D[15]# W9 D[5]# W12 FORCEPR# N15

A[34]# B15 D[16]# AA5 D[50]# F1 GTLREF_MA A7

A[35]# A14 D[17]# Y8 D[51]# D3 HIT# AA17

A[4]# H20 D[18]# W3 D[52]# B4 HITM# V20

A[5]# N20 D[19]# U1 D[53]# E1 IERR# F16

A[6]# R20 D[2]# Y12 D[54]# A5 IGNNE# J4

A[7]# J19 D[20]# W7 D[55]# C3 INIT# V16

A[8]# N19 D[21]# W6 D[56]# A6 LINT0 T15

A[9]# G20 D[22]# Y7 D[57]# F2 LINT1 R15

A20M# U18 D[23]# AA6 D[58]# C6 LOCK# W20

RSVD U5 D[24]# Y3 D[59]# B6 RSVD P17

ADS# V19 D[25]# W2 D[6]# AA16 GTLREF_EA D6

ADSTB[0]# K20 D[26]# V3 D[60]# B3 BPM_2[0]# G6

Datasheet 29


ADSTB[1]# B19 D[27]# U2 D[61]# C4 BPM_2[1]# H6

BPM_2[2]# K4 TDO M16 VCC L10 VSS B13

BPM_2[3]# K5 EXTBGREF M6 VCC L11 VSS B20

TDI_M M15 THERMTRIP# H17 VCC L12 VSS B21

TDO_M L16 THRMDA E4 VCC M10 VSS C8

PRDY# K18 THRMDC E5 VCC M11 VSS C17

PREQ# J16 TMS L17 VCC M12 VSS D1

PROCHOT# G17 TRDY# W19 VCC N10 VSS D5

PWRGOOD V17 TRST# K16 VCC N11 VSS D8

REQ[0]# N21 VCC A10 VCC N12 VSS D14

REQ[1]# J21 VCC A11 VCC P10 VSS D18

REQ[2]# G19 VCC A12 VCC P11 VSS D21

REQ[3]# P20 VCC B10 VCC P12 VSS E3

REQ[4]# R19 VCC B11 VCC R10 VSS E6

RESET# D15 VCC B12 VCC R11 VSS E7

RS[0]# W18 VCC C10 VCC R12 VSS E8

RS[1]# Y17 VCC C11 VCCA D7 VSS E15

RS[2]# U20 VCC C12 VTT V10 VSS E16

RSVD D17 VCC D10 VCCQ0 A9 VSS E19

DPSLP# R17 VCC D11 VCCQ0 B9 THRMDC_2 F4

RSVD M18 VCC D12 VCCSENSE C13 VSS F5

RSVD T17 VCC E10 VID[0] F15 VSS F6

CMREF B7 VCC E11 VID[1] D16 VSS F7

RSVD A13 VCC E12 VID[2] E18 VSS F17

RSVD R6 VCC F10 VID[3] G15 VSS F18

RSVD N6 VCC F11 VID[4] G16 VSS G1

RSVD T6 VCC F12 VID[5] E17 THRMDA_2 G4

RSVD A3 VCC G10 VID[6] G18 VSS G7

RSVD C1 VCC G11 VSS A2 VSS G9

RSVD C21 VCC G12 VSS A4 VSS G13

VTT E13 VCC H10 VSS A8 VSS G21

VTT E14 VCC H11 VSS A15 VSS H3

VTT F13 VCC H12 VSS A18 VSS H4

VTT F14 VCC J10 RSVD A19 VSS H7

SLP# N18 VCC J11 VSS A20 VSS H9

SMI# U17 VCC J12 VSS B1 VSS H13

STPCLK# R16 VCC K10 VSS B2 VSS H16


Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

Signal Name Ball #


30 Datasheet

TCK M17 VCC K11 VSS B5 VSS H18

TDI N16 VCC K12 VSS B8 VSS H19

VSS J5 VSS P7 VSS W5 VTT N8

VSS J7 VSS P9 VSS W8 VTT N14

VSS J9 VSS P13 VSS W11 VTT P8

VSS J13 VSS P15 VSS W14 VTT P14

VSS J17 VSS P16 VSS W17 VTT R8

VSS K1 VSS P18 VSS W21 VTT R14

VSS K6 VSS P19 VSS Y1 VTT T8

VSS K7 VSS R1 VSS Y2 VTT T14

VSS K9 VSS R5 VSS Y20 VTT U8

VSS K13 VSS R7 VSS Y21 VTT U9

VSS K15 VSS R9 VSS AA2 VTT U10

VSS K21 VSS R13 VSS AA3 VTT U11

VSS L3 VSS R21 VSS AA4 VTT U12

VSS L4 VSS T4 VSS AA7 VTT U13

COMP_2[0] L5 RSVD T5 VSS AA10 VTT U14

VSS L6 VSS T7 VSS AA12 RSVD V9

VSS L7 VSS T9 VSS AA15 RSVD R4

VSS L9 VSS T10 VSS AA18 RSVD M4

VSS L13 VSS T11 VSS AA19 RSVD D4

RSVD L15 VSS T12 VSS AA20

VSS L18 VSS T13 VSSSENSE D13

VSS L19 VSS T18 VTT C9

VSS M1 VSS U3 VTT D9

VSS M5 VSS U6 VTT E9

VSS M7 VSS U7 VTT F8

VSS M9 VSS U15 VTT F9

VSS M13 VSS U16 VTT G8

VSS M21 VSS U19 VTT G14

COMP_2[2] N4 VSS V1 VTT H8

COMP_2[1] N5 VSS V4 VTT H14

VSS N7 VSS V6 VTT J8

VSS N9 VSS V7 VTT J14

VSS N13 VSS V8 VTT K8

VSS N17 VSS V13 VTT K14

VSS P3 VSS V14 VTT L8


Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

31 CDI/IBL Document # 379115


4.3 Signal Description

COMP_2[3] P4 VSS V18 VTT L14

RSVD P5 VSS V21 VTT M8

VSS P6 VSS W1 VTT M14

Table 4-13.Signal Description (Sheet 1 of 8)

Signal Name Type Description

A[32:3]# I/O A[32:3]# (Address) defines a 232-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction.In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[32:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted.

A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode.A20M# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/output Write bus transaction.

ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[32:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal loop, or deferred reply ID match operations associated with the new transaction.

ADSTB[1:0]# I/O Address strobes are used to latch A[32:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.SignalsAssociated StrobeREQ[4:0]#, A[16:3]#ADSTB[0]#A[32:17]#ADSTB[1]#

BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.

BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.


Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

Signal Name Ball #

CDI/IBL Document # 379115 32


BPM[0]#, BPM_2[0]#

O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all FSB agents.This includes debug or performance monitoring tools. Refer to the platform design guide for more detailed information.* BPM_2[3:0] refer to core #2.

BPM[1]#, BPM_2[1]#,

I/O

BPM[2]#, BPM_2[2]#

O

BPM[3]#, BPM_2[3]#

I/O

BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

BR[1:0]# I/O BR0# is used by the processor to request the bus.

BSEL[2:0] O BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. For processor, the BSEL is fixed to operate at 133-MHz BCLK frequency.

COMP[3:0], COMP_2[3:0]

PWR COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guide for more details on implementation.* COMP_2[3:0] refer to core #2.

D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents.The data driver asserts DRDY# to indicate a valid data transfer.D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.Quad-Pumped Signal GroupsData GroupDSTBN#/DSTBP#DINV#D[15:0]#00D[31:16]#11D[47:32]#22D[63:48]#33

Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents.



33 CDI/IBL Document # 379115


DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents.

DINV[3:0]# I DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.DINV[3:0]# Assignment To Data BusBus SignalData Bus SignalsDINV[3]#D[63:48]#DINV[2]#D[47:32]#DINV[1]#D[31:16]#DINV[0]# D[15:0]#

DPSLP# I DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the SCH chipset. This signal is not used for Entry Level Desktop platform ‘08 and tied to VTT.

DPRSTP# I DPRSTP# when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the SCH chipset. This signal is not used for Entry Level Desktop platform ‘08 and tied to VTT through a 1k Ohm resistor.

DPWR# I DPWR# is a control signal from the chipset used to reduce power on the processor data bus input buffers. This signal is not used for Entry Level Desktop platform ‘08 and tied to VTT.

DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.SignalsAssociated StrobeD[15:0]#DINV[0]#, DSTBN[0]#D[31:16]#DINV[1]#, DSTBN[1]#D[47:32]#DINV[2]#, DSTBN[2]#D[63:48]#DINV[3]#, DSTBN[3]#

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#.SignalsAssociated StrobeD[15:0]#DINV[0]#, DSTBP[0]#D[31:16]#DINV[1]#, DSTBP[1]#D[47:32]#DINV[2]#, DSTBP[2]#D[63:48]#DINV[3]#, DSTBP[3]#




34 Datasheet

FERR#/PBE# O FERR# (Floating-point Error)/PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*- type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event.For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction Application Note. For termination requirements, refer to the platform design guide.

CMREF PWR CMREF should be set the same as GTLREF_*.

EXTBGREF PWR EXTBGREF should be set at 2/3 VTT.

GTLREF_MA

PWR GTLREF Middle Agent. Refer to the platform design guide for details on GTLREF implementation. GTLREF_MA should have separate voltage divider resistor network to set the right reference voltage and cannot share the voltage divider resistor network with GTLREF_EA.

GTLREF_EA

PWR GTLREF End Agent. Refer to the platform design guide for details on GTLREF implementation. GTLREF_EA should have separate voltage divider resistor network to set the right reference voltage and cannot share the voltage divider resistor network with GTLREF_MA.

HIT#HITM#

I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, or INIT#. For termination requirements, refer to the platform design guide.



Datasheet 35


IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# I INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents.If INIT# is sampled active on the active to inactive transition of RESET#, processor reverses its FSB data and address signals internally to ease mother board layout for systems where the chipset is on the other side of the mother board.D[63:0] => D[0:63]A[32:3] => A[3:32] DINV[3:0]# is also reversed.

LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK# I/O Probe Ready signal used by debug tools to determine processor debug readiness.

PRDY# O Probe Request signal used by debug tools to request debug operation of the processor. Refer to the platform design guide for more implementation details.

PREQ# I Probe Request signal used by debug tools to request debug operation of the processor. Refer to the platform design guide for more implementation details.




36 Datasheet

PROCHOT# I/O, O (DP)

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#.For termination requirements, refer to the platform design guide. This signal may require voltage translation on the motherboard. Refer to the platform design guide for more details.

PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

RESET# I Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted.

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents.

RSVD Reserved/No

Connect

These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use.



Datasheet 37


SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. This signal is not used for Entry Level Desktop platform ‘08 and tied to VTT.

SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

STPCLK# I RSVD.

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Refer to the platform design guide for termination requirements and implementation details.

TDI, TDI_M I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. * TDI_M refers to core #2.

TDO, TDO_M O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. * TDO_M refers to core #2.

THRMTRIP# O The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. For termination requirements, refer to the platform design guide.

THRMDA, THRMDA_2

PWR Thermal Diode - Anode* THRMDA_2 refers to core #2.

THRMDC, THRMDC_2

PWR Thermal Diode - Cathode* THRMDC_2 refers to core #2.

TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Refer to the platform design guide for termination requirements and implementation details.

TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents.




38 Datasheet

§

TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Refer to the platform design guide for termination requirements and implementation details.

VCCA PWR VCCA provides isolated power for the internal processor core PLLs. Refer to the platform design guide for complete implementation details.

VCC PWR Processor core power supply

VSS GND Processor core ground node.

VID[6:0] O VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC) but these pins are not used in the Entry Level Desktop platform ‘08 as the VID is fixed at 1.1 V.

VTT PWR AGTL+ reference voltage

VCC_SENSE O VCC_SENSE is an isolated low impedance connection to processor core power (VCCP). It can be used to sense or measure voltage near the silicon with little noise.

VSS_SENSE O VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. Refer to the platform design guide for termination recommendations and more details.

VCCQ0, VCCQ1

PWR Connect this to VTT.



Datasheet 39

Thermal Specifications and Design Considerations

5 Thermal Specifications and Design Considerations

The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section Thermal Specifications. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsink attached to the exposed processor die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a system fan used to evacuate or pull air through the system. For more information on designing a component level thermal solution, please refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.3). Alternatively, the processor may be in a fan-less system, but would likely still use a multi-component heat spreader. Note that trading of thermal solutions also involves trading performance.

5.1 Thermal SpecificationsTo allow for the optimal operation and long-term reliability of Intel processor based systems, the system/processor thermal solution should be designed such that the processor remains within minimum and maximum case temperature (Tc) specification at the corresponding thermal design power (TDP) value listed in Table 5-14. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.3).

The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 5-14 instead of the maximum processor power consumption. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.2. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.


40 Datasheet

NOTES:1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the temperature indicated.

3. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications.

4. VCC is determined by processor VID[6:0].

5.1.1 Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal “diode”, with its collector shorted to ground. The thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor MSR and applied. See Section 5.1.2 for more details. See Section Section 5.1.2 for thermal diode usage recommendation when the PROCHOT# signal is not asserted.

The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change.

Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor Model Specific Register (MSR).

Table 5-14.Power Specifications for the Standard Voltage processor

SymbolProcessor Number

Core Frequency

and Voltage

Thermal Design Power

UnitTc

min(°C)

Tcmax(°C)

Notes

TDP 330 1.6 GHz & VCC 8.0 W 0 85.2 1, 3, 4

Symbol Parameter Min Typ Max Unit

PAH Auto Halt — — 2 W 2

Datasheet 41


Table 5-15 and Table 5-16 provide the diode interface and specifications. Transistor model parameters shown in Table 5-16 providing more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Contact your external sensor supplier for their recommendation. The thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.

NOTES:1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized across a temperature range of 50–100°C.3. Not 100% tested. Specified by design characterization.4. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

IC = IS * (e qVBE/nQkT –1)

where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin).

5. The series resistance, RT, provided in the Diode Model Table (Table 5-16) can be used for more accurate readings as needed.

When calculating a temperature based on the thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 5-16. In most sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode, the ideality value (also called ntrim) will be 1.000.

Table 5-15.Thermal Diode Interface

Signal Name Pin/Ball Number Signal Description

THERMDA E4 Thermal diode anode

THERMDC E5 Thermal diode cathode

Table 5-16.Thermal Diode Parameters using Transistor Model

Symbol Parameter Min Typ Max Unit Notes

IFW Forward Bias Current 5 200 μA 1

IE Emitter Current 5 200 μA 1

nQ Transistor Ideality 0.997 1.001 1.015 2,3,4

Beta 0.25 0.65 2,3

RT Series Resistance 2.79 4.52 6.24 Ω 2,5


42 Datasheet

Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processor diode ideality deviates from that of the ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation:

Terror(nf) = Tmeasured * (1 - nactual/ntrim)

where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device.

5.1.2 Intel® Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An under- designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence.

There is only one automatic modes called Intel Thermal Monitor 1 (TM1). This mode is selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation.

The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 be enabled on the processors.

When TM1 is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid

Datasheet 43


active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active.

The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 be enabled on the processors.

TM1 feature is referred to as Adaptive Thermal Monitoring features.

The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

PROCHOT# will not be asserted when the processor is in the Stop Grant power states; hence, the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the Stop Grant power state and the processor junction temperature drops below the thermal trip point.

If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.


44 Datasheet

5.1.3 Digital Thermal Sensor

The processor also contains an on die Digital Thermal Sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (the Normal package level low power state).

Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (TJ_max). It is the responsibility of softwa

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