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Intel® Celeron™ Processor-Based Transaction Terminal Sample DesignApplication Note
September, 1999
Order Number: 273281-001
Application Note
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron™ processor and Intel 440BX AGPset may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Contents1.0 Introduction ..................................................................................................................7
1.1 Key Terms and Abbreviations ...............................................................................71.2 Revision History ....................................................................................................7
2.0 Embedded Applications Overview......................................................................8
2.1 Influence of PC Technology ..................................................................................82.2 Celeron™ Processors in Embedded Applications.................................................9
3.0 Overview of Transaction Terminals..................................................................10
3.1 Transaction Terminal Implementation .................................................................103.2 Transaction Terminal Operating Systems ...........................................................11
3.2.1 Windows* CE .........................................................................................12
4.0 Transaction Terminal Sample Design Overview .........................................13
4.1 Core Components ...............................................................................................13
5.0 The Celeron™ Processor......................................................................................15
5.1 Using the Celeron™ Processor with the Intel® 440BX AGPset ..........................165.2 Data Integrity Features........................................................................................165.3 The Celeron™ Processor Execution Architecture...............................................17
5.3.1 The Celeron™ Processor Pipeline .........................................................175.3.2 The Bus Interface Unit............................................................................185.3.3 Fetch/Decode – The In-order Issue Front End Unit ...............................185.3.4 Dispatch/Execute – The Out-of-Order Core Unit....................................195.3.5 Retire – The In-Order Retirement Unit ...................................................19
6.0 Intel® 440BX AGPset ...............................................................................................20
6.1 82443BX System Controller ................................................................................206.2 Intel® 82371EB PCI ISA IDE Xcelerator (PIIX4E)...............................................21
6.2.1 IDE / Floppy............................................................................................216.2.2 XBUS, Power Management, and USB Host Controller ..........................22
7.0 Functional Description of Sample Design Hardware ................................25
7.1 In-Target Probe (ITP) ..........................................................................................257.2 Power Management and Voltage Regulation......................................................257.3 Cache ..................................................................................................................257.4 Networking ..........................................................................................................267.5 AGP Video...........................................................................................................26
7.5.1 Features of the 6900 HiQVideo Graphics Accelerator ...........................267.5.2 Implementation of the 69000 HiQVideo Graphics Accelerator...............277.5.3 Analog Devices AD725 RGB to NTSC/PAL Encoder with
Luma Trap Port ......................................................................................307.6 Audio ...................................................................................................................31
7.6.1 Ensoniq AudioPCI* 97 ES1371 Digital Controller ..................................317.6.2 Analog Devices AC ’97 AD1819 SoundPort* Codec..............................32
7.7 SMSC FDC37B78x Ultra I/O*..............................................................................337.7.1 Floppy Disk Controller (FDC) .................................................................33
Application Note 3
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.7.2 Serial Port Controller .............................................................................. 337.7.3 Infrared Interface.................................................................................... 347.7.4 Parallel Port Controller ........................................................................... 347.7.5 Keyboard and Mouse ............................................................................. 347.7.6 Design Note for Ultra I/O* ...................................................................... 357.7.7 Additional Serial Ports with SMSC 37C669 Super I/O*.......................... 36
7.8 Tritech Microelectronics TR88L803 Touch ScreenController............................................................................................................. 377.8.1 Implementation of the TR88L803........................................................... 377.8.2 LCD with Integrated Touch Screen ........................................................ 37
7.9 PCMCIA (Intel® Strataflash™ Memory and PC Card) Socket ............................387.9.1 Texas Instruments PCI1225 PC Card (PCMCIA) Controller .................. 38
7.9.1.1 Slot A: PCMCIA Socket with Texas Instruments TPS2206 PC Card Power-Interface Switch with Reset............. 38
7.9.1.2 Slot B: Intel® StrataFlash™ Memory.........................................387.9.2 Design Notes for the PCI1225 ............................................................... 39
7.10 ISA PCI Expansion Cards ................................................................................... 407.11 Clocking .............................................................................................................. 41
7.11.1 Cypress Semiconductor CY2280 ........................................................... 417.11.2 Cypress Semiconductor CY2318 ........................................................... 417.11.3 Clocking for 440BX Chipset ................................................................... 41
8.0 Design Considerations .......................................................................................... 43
9.0 Windows* CE ............................................................................................................. 44
9.1 Windows CE for Embedded Applications............................................................449.2 Windows CE Environment .................................................................................. 44
9.2.1 Kernel..................................................................................................... 449.2.2 Modularity............................................................................................... 459.2.3 OEM Adaptation Layer (OAL) ................................................................ 45
9.3 Windows CE OS Build Information ..................................................................... 469.3.1 Getting Started ....................................................................................... 469.3.2 Building a Windows CE OS with Platform Builder..................................469.3.3 Building a Windows CE OS with the CE Toolkit..................................... 479.3.4 Building a New Project ........................................................................... 48
9.3.4.1 Create a New Platform Directory...............................................489.3.4.2 Create a New Project Directory................................................. 489.3.4.3 Create a New Command Prompt Build Window ....................... 499.3.4.4 Build the Windows CE Operating System Image
for a New Project....................................................................... 499.3.4.5 Adding Files or Applications to the Windows CE
Operating System Image........................................................... 499.4 Windows CE Device Drivers ...............................................................................50
9.4.1 Design Note ........................................................................................... 509.4.2 Dynamic Link Libraries (DLLs) ............................................................... 509.4.3 Windows CE Device Driver Model ......................................................... 509.4.4 Interaction with Application Software ..................................................... 519.4.5 Incorporating Device Drivers ..................................................................519.4.6 ACTiSYS IR 2000B ................................................................................ 529.4.7 Audio ...................................................................................................... 52
4 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Figures
1 Stand-alone POS Terminal .................................................................................102 Back-end and Front-end Transaction Terminal...................................................123 Block Diagram of Transaction Terminal Platform Sample Design ......................134 Block Diagram of the Celeron™ Processor’s P6 Core........................................185 Fence Example ...................................................................................................436 Device Driver Architecture...................................................................................51
Tables
1 General Purpose Input and Output Pins .............................................................242 Power and Ground Requirements.......................................................................283 AD1819 Codec Filter Pins and Implementations.................................................324 SYSOPT Pin Settings..........................................................................................355 SYSOPT Setting Options ....................................................................................356 SYSOPT Settings................................................................................................367 SYSOPT Setting Options ....................................................................................368 IRQ and PCI Interrupt Implementations ..............................................................399 Multifunction (MFUNC[6:0]) Board Connections .................................................3910 Board Interrupt Configurations ............................................................................4011 Related Intel Documents .....................................................................................5512 Related Specifications, Technical Papers, and Reference Books ......................56
Application Note 5
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Application Note 7
1.0 Introduction
Transaction terminals include point-of-sale (POS), ATM, kiosk, and service terminals. This application note provides a sample transaction terminal design using the Intel Celeron™ processor and provides recommendations to enable shorter design cycles. This application note also describes various peripherals commonly used in transaction terminals (TTs) and how they interface to a Celeron processor platform.
Caution: This sample design has not been implemented in hardware. This document is for reference only. Customers are responsible for validating designs created using the information in this document.
1.1 Key Terms and Abbreviations
1.2 Revision History
AGP Accelerated Graphics Port
ATM Automatic teller machine
PIIX4E The Intel 82371EB PCI ISA IDE Xcelerator, which is one of two chips in the Intel 440BX AGPset used in this sample design. Also called the Southbridge.
POS Terminal Point-of-sale terminal
TT Transaction terminal
Revision Number Date Description
001 09/20/99 Initial Version.
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
2.0 Embedded Applications Overview
2.1 Influence of PC Technology
Embedded systems come in a variety of forms, including transaction terminals, industrial equipment, and telecommunication equipment.
Increasingly, high-performance embedded processors are being used in embedded applications, and PC technology is quickly filling the performance needs. Using desktop processors in the embedded applications with standard operating systems allows embedded designers to get their products to market quickly.
Transaction terminals represent a broad category of computing devices including electronic cash registers, PC-based point-of-sale (POS) terminals, handheld computers, back-office PCs, servers, automatic teller machines, and point-of-interaction kiosks and service terminals. These terminals are either stand-alone or connected to the corporate enterprise network. With increasing competition in the retail and financial industries, the ability to network these devices is an extremely high priority. Networking these applications provides the infrastructure for end customers, such as retailers, to achieve real-time collection and processing of sales data. Retailers can then use this information to better manage their business and optimize their operating efficiency. In many cases, connectivity expands beyond the store fronts and back-room inventory to the production assembly, financial institutions, credit card processing centers, warehouses, online E-commerce services, and alliance stores.
POS terminals, widely used in supermarkets, department stores, restaurants, convenience stores, and banks, are PC-like platforms with peripherals added to address various needs. The main function of a POS terminal is to process transactions such as receipt generation, scanning, weighing, and inventory management. A POS can be a stand-alone system or can be used in conjunction with back-office systems for inventory management, training, and advertising. POS terminal users may need to look up products, re-index merchandise by product code, description or stock number, or track layaway and backorders. When discounts are offered, the POS terminal can support multiple price levels.
Transaction terminals require high performance to support demanding front-end applications, such as “commercial-ready” multimedia, extensive peripheral connectivity, wireless and mobile devices. They also require the ability to access the enterprise network through an Intranet or the Internet using Windows NT-based servers. Performance upgrades are being driven by the growing requirements of distributed databases, loaded on the front end, and rich data type content such as video and high resolution graphics.
8 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
2.2 Celeron™ Processors in Embedded Applications
Intel Pentium®, Pentium II-Low Power and Celeron processors are now being used in embedded systems. The sample design discussed in this document uses the Celeron processor. The Intel family of processors for embedded applications now includes the 300A, 366 and 433 MHz Celeron processors, which include MMX™ technology. With support for embedded product life cycles, the Celeron processor—and supporting Intel chipsets—enable developers to meet the high performance requirements of today's value-driven embedded applications with the same technology used in today’s value desktop PCs.
Using the Celeron processor in embedded designs provides scalability and offers a wide performance range and an easily alterable platform.
Application Note 9
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
3.0 Overview of Transaction Terminals
A typical transaction terminal designed for a point-of-sale (POS) application is shown in Figure 1.
3.1 Transaction Terminal Implementation
Transaction terminals are PC-like platforms adapted for retail and service environments. They may include liquid-crystal display (LCD) touch screens, which are especially important in many retail and service environments where the operator must select numerous items quickly.
Unlike a desktop system, a transaction terminal may have an expanded number of serial and Universal Serial Bus (USB) ports. These additional serial ports are usually needed for peripherals such as bar code scanners, credit card readers, magnetic stripe readers, and pin pads.
USB keyboards, mice, and receipt printers can be implemented as hot plug-and-play peripherals. Some of the other peripherals common in transaction terminals include cash drawers, digital scales, and pole displays.
In most cases, transaction terminals must be available at all times. For this reason, hardware monitoring and the capability for fault recovery are crucial. Since transaction terminals are typically kept on at all times, the processor’s power management features should be used to place the terminals in a low-power mode when not used.
This sample design tested peripherals and Windows CE drivers to provide support for:
This sample design discusses the components used for a PCMCIA card, touch screen controller, LCD/touch screen, additional serial ports, infrared, and the AC ’97 audio codec.
Figure 1. Stand-alone POS Terminal
A6263-01
• Infrared (IrDA) • Modem
• Flash memory • LCD touch screen
• PCMCIA cards • Network interface cards.
• AC ’97-compliant audio codec
10 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
3.2 Transaction Terminal Operating Systems
In transaction terminal applications using the embedded Celeron processor, frequently used operating systems include DOS*, QNX*, Linux*, BeOS*, VxWorks*, pSOS*, and Windows* 3.1. In addition, Windows NT, Windows 95, and Windows 98 are now being used to meet the increasing performance needs of many embedded applications. These Windows operating systems have the advantage of having a large base of readily available applications, and features such as Desktop Management Interface (DMI), and support for interactivity. Another operating system solution that is gaining momentum in transaction terminal applications is Windows CE, which can be used in smaller applications that require a ROM-able operating system.
A typical transaction terminal implementation can include a high performance back-end system and a front-end system with less functionality. The hardware core of a transaction terminal is similar for ATMs, Kiosks, and POS terminals. In a traditional POS implementation, a company may have to develop and train people on two or more systems. At the machine level, or front-end, where functionality is limited, applications may be developed based on proprietary operating systems. At the back-end or supervisory level, applications are developed on open systems based on Windows 95 and Windows NT operating systems. Because these levels are often built on different platforms, the systems may not talk to each other, look the same, or share databases, graphics, and other application files.
An alternative to the configuration described above is to design a transaction terminal that uses an embedded Celeron processor with MMX technology running Windows 95, Windows 98, Windows NT, or Windows CE, and a based back-end system that uses a Pentium II or Pentium III processor with Windows NT. This configuration enables transaction terminal system designers to add functions such as inventory management and disaster recovery. In addition, the front-end transaction terminal can communicate with the back-end or supervisory level systems. This system allows sharing databases, graphics and applications. By using an off-the-shelf operating system, the added benefits are shorter design cycles and quicker time-to-market. Figure 2 illustrates this configuration.
Application Note 11
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
3.2.1 Windows* CE
All software for Windows CE is based on the Win32 application programming interface (API). Developers can write programs for Windows CE using familiar tools such as Visual C/C++*, or Visual Basic*. Windows CE helps in moving some embedded applications away from proprietary systems so that products have a shorter development cycle, fewer costs and less user training. Since Windows CE is ROM-able, a hard disk drive may not be necessary.
Because Windows CE, Windows 95, and Windows NT are based on the same Microsoft technologies, many of the same development tools and utilities can be used on both systems, allowing faster development and a similar look and feel.
For an application with reduced functionality, Windows CE can be used as the core OS because it requires a small footprint, unlike Windows NT. A Windows CE-based device with the kernel, the file system, and the registry can fit into 512 Kbytes of ROM.
Windows CE must be configured to meet the specific needs of the application. Functionality must be added to it in the form of installable device drivers. Windows CE has numerous components allowing for different configurations. Windows CE also uses Unicode characters to provide multilingual support.
Figure 2. Back-end and Front-end Transaction Terminal
A6262-01
PC Back Office System POS Back Office System
POS Workstations
OR
12 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
4.0 Transaction Terminal Sample Design Overview
Figure 3 is the block diagram for the transaction terminal sample design. Intel components are shown in gray shading. The design also includes several components from other vendors.
4.1 Core Components
As shown in Figure 3, the core components of this reference design are:
• Intel Celeron processor
• 82443BX “northbridge”
— DRAM interface
— PCI bus and connectors
— AGP port
• 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4E) “southbridge”
— IDE connector
— ISA bus and connector
— Universal Serial Bus host controller
• 82559 Ethernet Controller
• 69000 HiQVideo™ Accelerator with Integrated Memory
Figure 3. Block Diagram of Transaction Terminal Platform Sample Design
A7261-01
AGPLCD Connector PCI Connector
ISAConnector
Ultra I/O
PCI Connector Audio
DRAM
USB
69000Graphics
IDE
AD725
PIIX4SouthBridge
Intel® Celeron™ Processor
PCMCIA Controller
82443BXNorthBridge
82559Ethernet
Controller
COM3, COM4
Intel®StrataFlash™
Memory
Boot BlockFlash
PCI
ISA
Intel platform components
Components from other vendors
Application Note 13
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
• AC ’97 Audio Solution
— Ensoniq AudioPCI* ES1371
— AD1819 SoundPort* Codec
• SMSC FDC37B78x Ultra I/O*
• SMSC FDC37C669 Super I/O* for additional serial ports
• TriTech Microelectronics TR88L803 Touch Screen Controller
• Texas Instruments PCI1225 PC Card (PCMCIA) Controller
• Intel StrataFlash™ Memory
14 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
5.0 The Celeron™ Processor
This reference design supports the Celeron™ processor with MMX™ technology and an integrated 128-Kbyte L2 cache at a core clock rate of 300, 366, or 433 MHz. The Celeron processor has a system bus that runs at 66 MHz. For embedded applications, this processor is available in a 370-pin PPGA package.
The Intel Celeron processor is designed to provide high performance without sacrificing value, and is binary compatible with previous generations of Intel architecture processors. The Celeron processor provides enhanced performance for applications running on advanced operating systems such as Windows* NT, Windows CE, and UNIX*. The Celeron processor brings a balanced level of performance to the embedded market segment, integrating the best attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture and the capabilities of MMX™ technology. Celeron processors also include the latest features to simplify system management and lower the total cost of ownership for small business environments.
The 300A, 366 and 433 MHz chips feature Intel's dynamic execution P6 microarchitecture core with a 66 MHz multi-transaction system bus. The 128-Kbyte on-chip L2 cache operates at the same speed as the processor. MMX technology enhances the performance of embedded products that run software applications for transaction terminals, imaging, and video processing. In addition, applying MMX technology to networking software stacks can help dramatically improve the performance of communications applications. The imaging features, accelerated by MMX technology, enable exciting new capabilities for transaction terminals, such as incorporating JPEG images and video processing.
The Celeron processor is available in a scalable 370-pin plastic pin grid array (PPGA) package (49x9mm) for embedded applications.
While many embedded applications require ever-higher performance, they are also driven by value considerations. The Celeron processor meets emerging product requirements in these important application segments:
• In retail and financial transaction terminals, increased performance is required to support Internet technologies such as Java*, JPEG imaging, video, and audio.
• The Celeron processor and MMX technology single instruction multiple data (SIMD) instructions support the increased processing demands of graphics, imaging, and video.
• The Celeron processor in Socket 370 packaging provides scalability and flexibility to meet a variety of price/performance targets.
For additional information on the Celeron processor, refer to the Intel® Celeron™ Processor datasheet. Information on PGA370 can be found in 370-Pin Socket (PGA370) Design Guidelines. Note that external termination, power distribution, power decoupling, and adherence to PC layout rules is required as provided in the documents listed in Appendix A, “Related Resources”, in Table 1, “General Purpose Input and Output Pins” on page 24, and in the schematics in Appendix B.
Application Note 15
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
5.1 Using the Celeron™ Processor with the Intel® 440BX AGPset
The Celeron processor and the 440BX AGPset provide a performance-optimized solution for embedded product life cycles. The 440BX AGPset consists of two chips, the 82443BX and the 82371EB:
• The 82443BX, also called the northbridge, forms a bridge between the processor, memory, Accelerated Graphics Port (AGP), and PCI bus.
• The 82371EB is also called the PIIX4E (PCI ISA IDE Xcelerator) or southbridge.
The 440BX improves the performance of the Celeron processor with Quad Port Acceleration (QPA). By using four ports, QPA improves the bandwidth between the processor, SDRAM, PCI bus, and Accelerated Graphics Port (AGP).
The 440BX includes a number of other performance-enhancing features, including improved bus arbitration, deeper buffers, and an open-page memory architecture. Designing with the 440BX AGPset provides a cost-effective way to ensure that your embedded designs will be ready for future 100 MHz bus implementations.
5.2 Data Integrity Features
Data integrity is critical in many embedded applications. The Celeron processor supports Built-in Self Test (BIST) to provide single stuck-at fault coverage of the microcode and large logic arrays. In addition, BIST tests the instruction and data caches, Translation Lookaside Buffers, and ROMs. The processor also features an IEEE 1149.1 self-test port. For additional data integrity, the 440BX AGPset includes Error Correction Code (ECC) memory control.
16 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
5.3 The Celeron™ Processor Execution Architecture
The P6 family of processors succeeds the Pentium processor line of Intel processors. The P6 pro-cessors implement Intel’s dynamic execution microarchitecture, which incorporates a unique com-bination of multiple branch prediction, data flow analysis, and speculative execution. These features enable P6 family processors to deliver higher performance than the Pentium family of pro-cessors, while maintaining binary compatibility with all previous Intel architecture (IA) processors.
The Celeron, Pentium II, and Pentium III processors are aggressive P6 microarchitectural implementations of the 32-bit Intel architecture. They are designed with a dynamic execution architecture that provides the following features:
• out-of-order speculative execution to expose parallelism
• superscalar issue to exploit parallelism
• hardware register renaming to avoid register name space limitations
• pipelined execution to enable high clock speeds
• branch prediction to avoid pipeline delays
The microarchitecture is designed to execute legacy 32-bit Intel architecture code quickly, without additional effort from the programmer. The new Celeron processors also contain an integrated 128-Kbyte L2 cache and an Advanced Programmable Interrupt Controller (APIC). The APIC supports I/O and is 8259A compatible.
5.3.1 The Celeron™ Processor Pipeline
The Celeron processor pipeline contains three independent engines coupled with an instruction pool. The three engines are:
• Fetch/Decode - The in-order issue front end
• Dispatch/ Execute - The out-of-order core
• Retire - The in-order retirement unit
Figure 4 shows an overview of the Celeron processor’s architecture.
Application Note 17
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
5.3.2 The Bus Interface Unit
The bus interface unit is responsible for connecting the three internal units to external hardware. The bus interface unit communicates directly with the L2 (second level) cache supporting up to four concurrent cache accesses. The bus interface unit also controls a transaction bus to system memory, with a MESI snooping protocol for cache coherence.
5.3.3 Fetch/Decode – The In-order Issue Front End Unit
The front end supplies instructions in program order to the out-of-order core. It fetches and decodes Intel architecture-based processor macroinstructions, and breaks them down into simple operations called micro-ops (µops). It can issue multiple µops per cycle, in original program order, to the out-of-order core.
Because the core aggressively reorders and executes instructions out of program order, the most important consideration in performance tuning is to ensure that enough µops are ready for execution. Accurate branch prediction, instruction prefetch, and fast decoding are essential to getting the most performance out of the in-order front end.
Figure 4. Block Diagram of the Celeron™ Processor’s P6 Core
A7423-01
L2 CacheSystem Bus
L1 I-Cache
Fetch/Decode
Unit
Dispatch/Execute
Unit
RetireUnit
Bus Interface Unit
L1 D-Cache
LoadFetch Store
Instruction Pool
18 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
5.3.4 Dispatch/Execute – The Out-of-Order Core Unit
The core’s ability to execute instructions out of order is a key factor in exploiting parallelism. This feature enables the processor to reorder instructions so that if one µop is delayed while waiting for data or a contended resource, other µops that are later in program order may proceed around it. The processor employs several buffers to smooth the flow of µops. This implies that when one portion of the pipeline experiences a delay, that delay may be covered by other operations executed in parallel or by executing µops which were previously queued up in a buffer.
The out-of-order core buffers µops in a Reservation Station (RS) until their operands are ready and resources are available. The core may dispatch up to five µops each cycle. The core is designed to facilitate parallel execution. Load and store instructions may be issued simultaneously. Most simple operations, such as integer operations, floating-point add, and floating-point multiply, can be pipelined with a throughput of one or two operations per clock cycle. Long latency operations can proceed in parallel with short latency operations.
5.3.5 Retire – The In-Order Retirement Unit
For semantically-correct execution, the results of instructions must be processed in original program order. Likewise, any exceptions that occur must be processed in program order. When a µop completes and writes its result, it is retired. Up to three µops may be retired per cycle. The unit in the processor that buffers completed µops is the reorder buffer (ROB). The ROB updates the architectural state in order; that is, updates the state of instructions and registers in the program semantics order. The ROB also manages the ordering of exceptions.
Application Note 19
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
6.0 Intel® 440BX AGPset
The Intel 440BX AGPset (440BX) optimizes Celeron processor performance for 3-D and video applications. As Intel’s second-generation AGPset with Intel Quad Port Acceleration (QPA), the Intel 440BX AGPset improves the performance of the system bus by increasing the width and depth of buffers to the system bus, Accelerated Graphics Port, SDRAM, and PCI bus. The 440BX AGPset is compatible with ATA/66 HDD. This makes the 440BX AGPset an excellent design solution for next-generation performance embedded systems. The new 440BX AGPset supports the emerging set of visual computing applications, including 3-D and video applications for design, data visualization, multimedia, and education. The 440BX integrates many power management features that enable power savings when the system resources are idle.
The 440BX consists of two chips: the 82443BX System Controller and the 82371EB PCI ISA IDE Xcelerator (PIIX4E). These components are described in the following sections.
6.1 82443BX System Controller
The 82443BX is the Host-to-PCI northbridge. It connects the Celeron processor to memory, the Accelerated Graphics Port (AGP), and the PCI bus. It also contains an optimized DRAM controller and data path and power management functions.
The 82443BX functions and capabilities include:
• 64-bit GTL+ based system data bus interface
• 32-bit system address bus support
• 64/72-bit main memory interface with optimized support for SDRAM
• 32-bit PCI bus interface with integrated PCI arbiter
• AGP interface with up to 133 MHz data transfer capability
• Extensive data buffering between all interfaces for high throughput and concurrent operations
The physical interface design is based on the Gunning Transceiver Logic (GTL+) specification and is compatible with the Intel 440BX AGPset solution. The 82443BX provides an optimized 72-bit DRAM interface (64-bit data plus ECC). This interface supports 3.3 V DRAM technologies.
Special termination and careful routing is required on the high-speed GTL+ technology data bus signal lines. GTL+ is a low output swing, incident wave switching, open-drain bus with external pull-up resistors that provide both the high logic level and termination at the end of the bus. This termination is included in this design. Additional details can be found in the Pentium® II Processor AGTL+ Guidelines (see Appendix A for document locations). Analog signal simulation of the Intel Celeron processor system bus, including trace lengths, is highly recommended when designing a system. Information on thermal and EMI requirements can be found in Pentium® II Processor Thermal Design Guidelines and Pentium® II Processor Electro-Magnetic Interference Guidelines. Power requirements are described in the Pentium® II Processor Power Distribution Guidelines. Detailed layout rules can also be found in the design schematics in Appendix B.
20 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
6.2 Intel® 82371EB PCI ISA IDE Xcelerator (PIIX4E)
The 82371EB PCI ISA IDE Xcelerator (PIIX4E), or southbridge, is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an enhanced power management function.
This device is compatible with the Intel 82443BX. The PIIX4E also allows complete plug-and-play compatibility. It supports two IDE connectors (Ultra DMA/33) to be used with up to four IDE devices in bus master mode.
As a PCI-to-ISA bridge, the PIIX4E integrates many common I/O functions found in ISA-based PC systems: two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers. The PIIX4E also contains full support for both PC/PCI and Distributed DMA protocols implementing PCI-based DMA. The Interrupt Controller has edge- or level-sensitive programmable inputs and fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and serial interrupts. Chip select decoding is provided for the BIOS, a real time clock, a keyboard controller, a second external microcontroller, and two programmable chip selects. The PIIX4E provides full plug-and-play compatibility.
The PIIX4E supports Enhanced Power Management, including full Clock Control, Device Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM, or Suspend to Disk. It fully supports operating system directed power management via the Advanced Configuration and Power Interface (ACPI) specification. PIIX4E integrates both a System Management Bus (SMBus) host and slave interface for serial communication with other devices.
For PCI devices, the PIIX4E is PCI device #7 (IDSEL connected to pin AD18 through a 110 Ω resistor per PCI Local Bus Specification, Revision 2.1).
The PIIX4E’s interrupt control unit provides interrupt handling to all ISA devices on the board including the SMSC FDC37B78x Ultra I/O* (floppy disk, serial ports, parallel port control), and the SMSC 37C669 Super I/O* (2 serial ports).
The following sections describe these features in greater detail. For the complete specification for this product, refer to the 82371EB PCI-TO-ISA/IDE Xcelerator (PIIX4E) datasheet
6.2.1 IDE / Floppy
The PIIX4E supports two IDE connectors for up to four IDE devices, providing an interface for IDE hard disks and CDROMs. Up to four IDE devices can be supported in bus master mode. The PIIX4E contains support for “Ultra DMA/33” synchronous DMA compatible devices. This design uses one IDE connector with support for up to two devices.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
6.2.2 XBUS, Power Management, and USB Host Controller
The PIIX4E contains a Universal Serial Bus (USB) Host Controller that is compatible with the Universal Host Controller Interface (UHCI). The Host Controller’s root hub has two programmable USB ports. Follow these guidelines when implementing these functions.
• X-Bus Signals
XOE# and XDIR# are connected as control signals to the X-Bus transceiver, with XOE# connected to G# and XDIR# connected to DIR of the transceiver. The internal RTC of the PIIX4E is used; therefore RTCALE and RTCCS# become general purpose outputs (GPO25 and GPO24, respectively) by programming the General Configuration Register (GENCFG) in Function 0, Offset B0h–B3h.
• Power Management Signals
SUSA# of the PIIX4E is connected to the PWR_DWN# signal of the clock generator. SUSA# is asserted during power management suspend states, POS, STR, and STD suspend states. PWR_DWN# is an active low control input to the clock generator to power down the device.
CPU_STP# and PCI_STP# of the PIIX4E are asserted low to disable the processor and PCI clock outputs respectively. They are connected to CPU_STOP# and PCI_STOP# of the clock generator.
SUSC# of the PIIX4E is first inverted and then connected directly to PS_ON# of the ATX power supply. Therefore when SUSC# is asserted, during STD suspend state, all power rails including 3.3 V, 5 V, -5 V, 12 V, and -12 V power rails, are turned off. This is used for the remote-off function. The inverter described above must be connected to a Standby Power rail.
RSMRST# connection requires a minimum time delay of one millisecond from the rising edge of the standby power supply voltage. A simple RC circuit is used to provide this time delay (t = RC, in the design this is ~2.7 KΩ * 10 µF ~ 2.7 ms) and a Schmitt trigger circuit is used to drive the signal on the board.
• USB Interface
The following are general layout guidelines for the USB interface:
— Any unused USB ports should be terminated with 15 Kbyte pull-down resistors on both P+/P- data lines.
— 27 Ω series resistors should be placed as close as possible to the PIIX4E (<1 inch). These series resistors are for source termination of the reflected signal.
— 47 pF caps must be placed as close to the PIIX4E as possible and on the PIIX4E side of the series resistors on the USB data lines (P0+, P1+). These caps aid in signal quality (rise/fall time) and help to minimize electromagnetic interference (EMI).
— 15 KΩ ±5% pull-down resistors should be placed on the USB side of the series resistors on the USB data lines (P0+ and P1+), and are REQUIRED for signal termination by USB specification. The stub length should be as short as possible.
— The trace impedance for the P0+, P1+ signals should be 45 Ω (to referenced ground) for each USB signal P+ or P-. The impedance is 90 Ω between the differential signal pairs P+ and P- to match the 90 Ω USB twisted pair cable impedance. Note that the twisted pair characteristic impedance of 90 Ω is the series impedance of both wires, resulting in an individual wire presenting a 45 Ω impedance. The trace impedance can be controlled by carefully selecting the trace width, trace distance from power or ground planes, and physical proximity of nearby traces.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
— USB data lines must be routed as “critical signals” (i.e., hand routing is preferred). The P+/P- signal pair must be routed together and not parallel with other signal traces to minimize crosstalk. Doubling the space from the P+/P- signal pair to adjacent signal traces helps prevent crosstalk. Do not worry about crosstalk between the two P+/P- signal traces. The P+/P- signal traces must also be the same length. This will minimize the effect of common mode current on EMI. (Common mode current is caused by differential signals whose currents are not perfectly matched.)
The following are general layout guidelines for the USB power and ground lines:
— Ferrite beads are placed on each power and ground line to minimize EMI. They should be placed as close as possible to the USB connector.
— Voltage divider circuits are used to drive the status of the SUB power line to the OC[1:0]# inputs. OC[1:0]# signals are 3.3 V inputs and have a leakage current of maximum + 1 µA.
— Fuses are used on each power line for overcurrent protection.
Refer to the Intel® 440BX PCIset Design Guide for sample layout topologies.
• IDE Interface
The PIIX4E provides two standard IDE interfaces. One (the primary IDE interface) is included in this design. The primary IDE controller is connected as described in the Intel® 440BX PCIset Design Guide. The secondary IDE controller is not used on the board. Hence, all inputs to the secondary IDE controller are pulled to the inactive state with a 10 KΩ resistor. All outputs and bidirectional pins are left floating.
A hard drive active LED circuit is connected to the HD_ACT# signal of the primary IDE connector. If the secondary IDE controller is used, an OR-gate between HD_ACT1# and the HD_ACT2# should be used to drive the LED circuit.
Proper operation of the IDE circuit depends on the total length of the IDE bus. The total signal length of the IDE drivers to the end of the IDE cables should not exceed 18". Therefore, the PIIX4E should be located as close as possible to the IDE connectors to allow the IDE cable to be as long as possible. When the distance between the PIIX4E and the ATA connectors exceeds four inches, the series termination resistors should be placed within one inch of the PIIX4E. Designs that place the PIIX4E within four inches of the ATA connectors can place the series resistors anywhere along the trace. The capacitance of each pin of the IDE connector on the host should be below 25 pF when the cables are disconnected from the host.
• Clocks
Refer to the Intel® 440BX PCIset Design Guide for layout topologies.
• General purpose input and output pins
Fifteen general purpose inputs and fifteen general purpose outputs are provided on the board. Table 1 lists the pins and provides sharing information:
Application Note 23
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Table 1. General Purpose Input and Output Pins
GPO Pin Muxed With GPI Pin Muxed With
GPO0 1 None GPI1 2 None
GPO8 3 None GPI2 4 REQA#
GPO9 5 GNTA# GPI3 6 REQB#
GPO10 7 GNTB# GPI4 8 REQC#
GPO11 9 GNTC# GPI5 10 APICREQ#
GPO12 11 APICACK# GPI7 12 None
GPO15 13 APICCS# GPI13 14 None
GPO21 15 SUS_STAT2# GPI14 16 None
GPO24 17 RTCCS# GPI15 18 None
GPO25 19 RTCALE GPI16 20 None
GPO26 21 KBCCS# GPI17 22 None
GPO27 23 None GPI18 24 None
GPO28 25 None GPI19 26 None
GPO29 27 IRQ9OUT# GPI20 28 None
GPO30 29 None GPI21 30 None
NOTE: All GPIO pins in the sample design are always available. Pins that are multiplexed with other signals are not used for their alternate function and are therefore always available for GPIO.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.0 Functional Description of Sample Design Hardware
This section describes additional hardware components used in the sample design (the Celeron processor is described in Section 5.0 and the Intel 440BX AGPset is described in Section 6.0). For more detailed information about the transaction terminal design, refer to the schematics located in Appendix B
7.1 In-Target Probe (ITP)
The design includes an in-target probe (ITP), also called a Pentium II processor debug port. This is a 30-pin interface that communicates directly to the processor, allowing access to the processor’s registers and signals. Using this debug utility allows easier debugging of low-level code such as BIOS and drivers.
The connectors for the ITP are provided by AMP Incorporated. Debuggers can be purchased through a variety of vendors.
7.2 Power Management and Voltage Regulation
A Semtech SC1185 programable synchronous DC/DC converter, dual low dropout regulator controller is used to provide the 1.5 V, 2.5 V, and core supplies. The VIDx pins on the Celeron processor select the core voltage to be supplied by the SC1185 device. PCB Layout guidelines for the SC1185 are included in the schematics in Appendix B. Voltage and temperature are monitored with sensors and the system shuts down whenever critical problems are detected. Voltage outputs are monitored by the reset and power good circuitry with the Linear Technology LTC1326 triple supply monitor. Processor temperature is monitored with a Maxim MAX1617 device.
As a design alternative, a National Semiconductor LM79 hardware monitor chip can be used instead of the LTC1326 triple supply monitor. In addition to voltage outputs, the LM79 chip can monitor fan RPM and chassis intrusion.
7.3 Cache
The concept of level two (L2) cache developed from the need to have data and instructions available to the processor locally. With the high clock rates of newer generation processors, there is enough time to allow for a code fetch and data to arrive from system DRAM for the processor to use before a stall occurs. With faster processors, the need for L2 cache is even greater; the processor may be so fast that, without cache, the processor core stalls while waiting for code and data to arrive from the system DRAM. While the processor is stalled waiting for instructions, it cannot perform other tasks.
The Celeron processors offer dual 16-Kbyte, 4-way set associated level one (L1) caches, with the addition of an integrated 128-Kbyte L2 cache. This architecture greatly lessens bus utilization and increases the overall throughput of the system.
Application Note 25
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.4 Networking
The 82559 Ethernet controller is used for the network interface in this design. The 82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer device is Intel’s leading solution for PCI board LAN designs. It is designed for use in Network Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems, and networking system products. The 82559 combines a low power and small package design, which is ideal for power and space constrained environments.
The 82559 supports the following:
• Advanced Configuration and Power Interface (ACPI) 1.20 A-based power management
• wake on Magic Packet
• wake on interesting packet
• advanced System Management Bus (SMB)-based manageability
• Wired for Management (WfM) 2.0 compliance
• IP checksum assist
• PCI 2.2 compliance
• PC 98, PC 99, and Server 99 compliance
7.5 AGP Video
The 69000 HiQVideo™ Graphics Accelerator with integrated memory is used in this design.
The 69000 is a portable graphics accelerator that integrates high performance memory technology for the graphics frame buffer. Based on the HiQVideo graphics accelerator core, the 69000 combines flat panel controller capabilities with low-power, high performance integrated memory. The 69000 solution integrates 2 Mbyte SDRAM for use in frame buffering. This memory supports up to an 83 MHz clock, allowing a high memory bandwidth. The 69000 is connected to the AGP port in this design.
7.5.1 Features of the 6900 HiQVideo Graphics Accelerator
• High Performance Integrated Memory
The 69000 incorporates 2 Mbyte of proprietary integrated SDRAM for the graphics/video frame buffer. The integrated SDRAM memory can support up to 83 MHz operation, increasing the available memory bandwidth for the graphics subsystem.
• HiQColor Technology
The 69000 integrates HiQColor technology based on the proprietary Temporal Modulated Energy Distribution (TMED) algorithm, HiQColor technology is a process that allows the display of 16.7 million true colors of STN panels without using Frame Rate Control (FRC) or dithering. TMED also reduces the need for the panel tuning associated with current FRC-based algorithms. The TMED algorithm eliminates flaws normally associated with dithering and FRC such as shimmer, Mach banding, and other motion artifacts.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
• Versatile Panel Support
The HiQVideo family of graphics accelerators support a wide variety of monochrome and color single-panel, single-drive (SS) and dual-panel, dual drive (DD), standard and high-resolution, passive STN, and active matrix TFT/MIM LCD, and EL panels. With HiQColor technology, up to 256 gray scales are supported on passive STN LCDs. Up to 16.7 million different colors can be displayed on passive STN LCDs and on 24-bit active matrix LCDs.
The 69000 offers a variety of programmable features to optimize display quality. Vertical centering and stretching are provided for handling modes with fewer than 480 lines on 480-line panels. Horizontal and vertical stretching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800x600, 1024x768 and 1280x1024 panels.
• Television NTSC/PAL Flicker Free Output
The 69000 uses a flicker reduction process, which makes text of all fonts and sizes readable by reducing the flicker and jumping lines on the display. The 69000 uses a line buffer and digital filters to average adjacent vertical lines for odd/even display. The chip also uses both horizontal and vertical interpolation to make both graphics and text appear smooth on a standard television. This process reduces the effect of flicker on NTSC displays.
7.5.2 Implementation of the 69000 HiQVideo Graphics Accelerator
The 69000 HiQVideo Accelerator provides VGA and LCD output on the board. Using the Analog Devices AD725 RGB to NTSC/Pal Encoder, the board also provides TV-out capability.
The 69000 is connected to the AGP port (IDSEL connected to AD16 through a 100 Ω resistor) and uses PCI interrupt INTA#.
An RGB monitor is always populated on the board. Therefore, when a TV encoder such as the AD725 is added, the RGB signals must be buffered. This is accomplished using an AD8073 video amplifier with high input impedances on each color signal. They are configured for a gain of two, which is normalized by the divide-by-two termination scheme used for the RGB monitor. However, since the RGB signals shift to ground during the horizontal sync period, the AD8073 requires a -5 V supply.)
The board provides an interface to LCD screens with up to 36-bit color. Panel Connector 1 supports 8-bit monochrome to 24-bit color LCD panels. The board also supports 36-bit LCD panels using both Panel Connector 1 and Panel Connector 2.
All panel interface signals from the graphics controller are 3.3 V. Level-shifting buffers should be added between the outputs from the graphics controller and the inputs of a 5.0 V flat panel if the 69000’s VOL and VOH do not meet the requirements for the panel’s VIL and VIH. The signals involved include pins P[35:0], SHFCLK, LP, FLM and M. The included schematics do NOT include these level shifters. The design assumes 3.3 V panels.
To ensure full compatibility with older CRT displays, 3.3 V to 5.0 V level-shifting buffers are added between the 69000’s HSYNC and VSYNC outputs and the display’s HSYNC and VSYNC inputs.
Power and ground signals to the 69000 are as specified in the 69000 HiQVideo Accelerator with Integrated Memory datasheet (see Appendix A). Table 2 lists all power and ground requirements, and their implementation on the board.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Proper layout of the 69000 is important to getting optimal performance.
The power plane attached to the core power supply should be as wide as practical for high-current carrying capacity and low inductance.
Decoupling capacitors should ideally be placed as close as possible to the 69000. This means that the best decoupling will occur if the capacitors are placed directly underneath the component. If a single-sided board is required and capacitors cannot be placed underneath the component, then decoupling is recommended at the corners of the 69000. Placing the capacitors at the corners minimizes decoupling trace lengths from the BGA package, reducing EMI.
Avoid placing audio components near a switching power supply.
Digital signals should be isolated from analog circuitry as much as possible to keep digital and analog currents from crossing. Ground currents from digital signals are noisy and should be isolated from the audio signals. Do not run dynamic digital signals such as clock, address, or data lines in or close to the analog area.
Table 2. Power and Ground Requirements
Pin Name Description Requirement Implementation
DACVCC Analog power for the internal RAMDAC
DACVCC should be isolated from all other VCC pins and should not be greater than CORVCC
Isolated from all other VCC pins through ferrite beads with filtering caps
DACGND Analog ground for the internal RAMDAC
DACGND should be common with digital ground but must be tightly coupled to DACVCC
Tied to analog GND
MCKVCCAnalog power for the internal memory clock synthesizer (MCLK)
MCKVCC must be at the same voltage level as CORVCC
Coupled to MCKGND through RC network
MCKGNDAnalog ground for the internal memory clock synthesizer (MCLK)
MCKVCC/MCKGND pair must be INDIVIDUALLY decoupled
Tied to digital GND through ferrite bead
DCKVCCAnalog power pins for the internal dot clock synthesizer (DCLK)
DCKVCC must be at the same voltage level as CORVCC
Coupled to DCKGND through RC network
DCKGNDAnalog ground pins for the internal dot clock synthesizer (DCLK)
DCKVCC/DCKGND pair must be INDIVIDUALLY decoupled
Tied to digital GND through ferrite bead
GND Digital ground Tied to digital GND
CORVCCDigital power for the graphics controller internal logic (a.k.a. the “core” VCC)
MEMGND Embedded memory ground Tied to 3.3 V plane with filtering caps
RGND Internal reference GND Should be tied to GND Tied to digital GND
IOVCC I/O power TIed to 3.3 V plane with filtering caps
MEMVCC Power for embedded memory
Tied to 3.3 V plane with filtering caps
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
All analog circuitry should be placed as close to I/O connectors as possible and should be isolated to as small an area as possible. Analog components and circuitry should reside over a separate ground and power plane with a gap between digital and analog planes made as wide as possible (25–50 mils is the acceptable minimum, 100 mils is ideal). The two plane pairs should be separated by a 2–3 mm gap. This means using at least a four-layer board with ground and power planes forming an internal high capacitive sandwich. This creates an effective series resistance (ESR) and effective series inductance (ESL) bypass capacitor.
Analog signals should reside over, or be referenced to, the analog ground plane as much as possible. Vias should be kept to a minimum. All analog signal traces should be as wide as possible for lower impedance.
Internal power and ground planes should be solid with no traces routed on them. The analog power plane containing the voltage regulator should coincide with the analog ground plane as much as possible. Analog ground shielding should be used on the external layers, especially near a low level input (such as a microphone).
The analog and digital planes should be connected at one point only through a 0 Ω resistor or a ferrite bead. This maintains the proper reference potential for each ground plane. On the board this should be placed as close as possible to the 69000. This allows analog and digital ground return currents from the 69000 to flow through the analog and digital ground plane, respectively.
There should not be any digital or analog traces crossing the gap between the analog and digital planes.
IC leads should have pads and vias that go directly to the appropriate plane for power and ground.
A separate small digital partition should be used for the crystal oscillator. This partition serves to keep noise from coupling onto the analog signals.
For information on how to interface to LCD Panels for the 69000 HiQVideo accelerator series, refer to 69000 HiQVideo Accelerator with Integrated Memory datasheet (see Appendix A).
A jumper on VEESAFE has been added to allow VEESAFE to be driven by a scaled version of VDDSAFE (scaled by a 1 KΩ potentiometer) for newer panels that have a low voltage requirement for VEESAFE. It is important that the potentiometer be fed from VDDSAFE rather than some other voltage source so that the resulting VEESAFE will meet the same power sequencing requirements as the panel. The sequencing of VEESAFE is the same for VDDSAFE. The current requirement for a low-voltage VEESAFE is intended to be 1 mA maximum.
Application Note 29
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.5.3 Analog Devices AD725 RGB to NTSC/PAL Encoder with Luma Trap Port
The Analog Devices AD725 is an RGB to NTSC/PAL encoder that may be populated on the board to add TV OUT capability. Follow these guidelines for implementation on the board.
• RIN, BIN, and GIN are analog inputs that should be terminated by 75 Ω resistors to ground in close proximity to the IC.
• The AD725 is a mixed signal part. It has separate pins for analog and digital +5 V and ground power supplies. Both the analog and digital ground pins should be tied to the ground plane by a short, low inductance path. Each power pin should have a bypass capacitor of 0.1 µF and a larger tantalum capacitor of 10 µF.
• The outputs have a DC bias that must be AC-coupled for proper operation. This is done on the board by placing a 220 µF tantalum capacitor and 75 Ω resistor in a series on each output.
• On the board, an RGB monitor is always populated. Therefore, when a TV encoder such as the AD725 is added, the RGB signals must be buffered. This is accomplished by an AD8073 video amplifier with high input impedances on each RGB signal. The signals are configured for a gain of two, which is normalized by the divide by two termination scheme used for the RGB monitor. However, since the RGB signals go to ground during horizontal synchronization, the AD8073 requires a -5 V supply.
• A jumper is placed on pin 5 of the AD725. Placing a jumper on pins 1–2 enables the AD725. A jumper on pins 2–3 disables the AD725.
• A jumper is also placed on pins 1 and 12. Placing a jumper on pins 1–2 enables NTSC, placing a jumper on 2–3 enables PAL. It is important that the oscillator circuit, placed on pin 3 of the AD725, also be changed when switching from NTSC to PAL (a 14.318180 MHz crystal is already placed for NTSC). The crystal must be changed from 14.318180 MHz to 17.734475 MHz for PAL.
• Proper layout of the AD725 circuitry is required for optimal performance.
• All passive components should be placed as close as possible to the AD725.
• A “fence” should be formed around the analog signals. No digital signals should be routed under or above the analog power and ground planes.
• The filter circuits for the video output signals (CMPS, LUMA and CRMA) should be placed as close as possible to the connector. Long lengths of closely-spaced parallel analog signals should be avoided. Wherever analog signals run in parallel, separated by less than 15 mils for longer than 250 mils, run a ground line between the video input traces of approximately 12 mils in width.
• The three analog inputs (RIN, GIN, BIN) should be terminated to ground by a 75 Ω resistor close to the respective pins.
• Layout guidelines should be followed as in the 69000 HiQVideo Accelerator with Integrated Memory datasheet (see Appendix A).
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.6 Audio
The audio solution on the board is compliant with the AC ’97 Component Specification, v1.0 . It features an Ensoniq AudioPCI* 97 ES1371 digital controller and an Analog Devices AC ’97 SoundPort* Codec AD1819 connected through the 5-wire AC ’97 link.
The AC ’97 audio architecture provides legacy support as well as a migration path to digital audio. Sound Blaster* emulation is provided, as well as a MIDI data interface. The AD1819 provides an analog front end for high performance audio, modem, and DSP applications.
AC ’97 defines a high quality two-chip audio architecture (an AC ’97 digital controller and AC ’97 codec), advancing the migration to digital audio, while maintaining support for analog audio sources and analog interconnect for backwards compatibility. The two-chip audio solution, comprises a digital audio controller and a high quality analog component that includes digital-to-analog converters (DACs), analog-to-digital converters (ADCs), a mixer, and I/O. The architecture supports a wide range of high quality audio solutions, from a 2-channel mix of digital and analog audio, to multi-channel digital audio. The system is capable of achieving greater than 90 dB SNR performance.
7.6.1 Ensoniq AudioPCI* 97 ES1371 Digital Controller
The Ensoniq AudioPCI 97 ES1371 digital controller supports simultaneous stereo audio, and host-based wave table music synthesis through the integration of an AC ’97 2.0-compatible link and a PCI interface, in addition to audio legacy compatibility. The controller includes digital AC-link converters, WDM digital mixing acceleration, and variable sample rate conversion.
The PCI interface handles up to two digital audio streams, a modem, and handset streams. The digital audio streams are sample-rate converted and mixed to a common rate before being transmitted over the AC ’97 2.2-compatible link to an AC ’97 codec.
The sample rates are completely independent from the incoming and outgoing streams. The controller includes a variable sample rate converter that allows instantaneous support for sample rates ranging from 7 KHz to 48 KHz, with a resolution of 1 Hz.
SoundBlaster* emulation is provided through the combination of hardware digital mixing, software SoundBlaster trapping, and host-generated wave table music synthesis.
The primary interface for communicating MIDI data to and from the host is the hardware MPU-401 interface. The MPU-401 interface includes a built-in 64 byte FIFO for communication to the host bus.
The ES1371 digital controller is PCI device number 16 (IDSEL connector to AD27 through a 220 Ω resistor). It is also PCI bus master #4 (connected to PCI bus master pins REQ4# and GNT4#) and uses PCI interrupt INTC# on the board.
Note: The MIDI/JOYSTICK interface is not implemented on the board.
Application Note 31
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.6.2 Analog Devices AC ’97 AD1819 SoundPort* Codec
The AD1819 SoundPort codec is designed to meet all requirements of the Audio Codec Component Specification, v1.03. The AD1819 supports multiple codec configurations (up to three per AC link), a DSP serial mode, variable sample rates, modem sample rates and filtering, and built-in Phat Stereo 3-D enhancement.
The AD1819 is an analog front end for high performance audio, modem, or DSP applications.
The main architectural features of the AD1819 are the high quality analog mixer section, two channels of sigma-delta ADC conversion, two channels of sigma-delta DAC conversion, and data direct scrambling (D2S) rate generators. The AD1819’s left channel ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.
The AD1819 codec is connected to the ES1371 through the 5-wire AC ’97 link. The RESET# signal of the 5- wire AC ’97 link is connected to PCI RESET (RST#) on the board.
The board implements microphone, video, line, and CDROM inputs as well as line, mono and line level outputs. The AD1819 provides interfaces for PC beep, phone input, and auxiliary inputs that are not implemented on the board.
There are various filter pins on the AD1819. These pins are listed below with their implementation on the board.
Note: Proper board layout of the AC ’97 audio components is important to achieving optimal performance. Avoid placing the audio components near a switching power supply.
To keep digital and analog signal currents from crossing, digital signals should be isolated from analog circuitry as much as possible. Ground currents from digital signals are noisy and should be isolated from the audio signals. Do not run dynamic digital signals such as clock, address or data lines in or around the analog area.
All analog circuitry should be placed as close to I/O connectors as possible and should be isolated to as small an area as possible. Analog components and circuitry should reside over a separate ground and power plane with as wide a gap as possible between digital and analog planes (25–50 mil is acceptable and 100 mil is ideal). The two plane pairs should be separated by a 2–3 mm gap. This means using at least a four-layer board with ground and power planes forming an internal high capacitive sandwich. This gives an effective low ESR and ESL bypass capacitor.
Table 3. AD1819 Codec Filter Pins and Implementations
Pin Name TQFP I/O Description Board Implementation
AFILT1 29 O Antialiasing Filter Capacitor - ADC Right Channel 270 pF ceramic capacitor-to-analog ground
AFILT2 30 O Antialiasing Filter Capacitor - ADC Left Channel 270 pF ceramic capacitor-to-analog ground
FILT_R 31 O AC-Coupling Filter Capacitor -ADC Right Channel 1 µF tantalum capacitor-to-analog ground
FILT_L 32 O AC-Coupling Filter Capacitor -ADC Left Channel 1 µF tantalum capacitor-to-analog ground
RX3D 33 O 3D Phat Stereo Enhancement -Resistor 47 nF capacitor-to-analog ground
CX3D 34 I 3d Phat Stereo Enhancement - 100 nF capacitor connected to RX3D
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Analog signals should reside over, or be referenced to, the analog ground plane as much as possible. Vias should be kept to a minimum. All analog signal traces, especially VREFOUT and analog power lines on the AD1819, should be as wide as possible for lower impedance connections.
Internal power and ground planes should be solid with no traces routed on them. The analog power plane containing the voltage regulator should coincide with the analog ground plane as much as possible. Analog ground shielding should be used on the external layers, especially near the microphone input.
The analog and digital planes should be connected at one point only, through a 0-Ω resistor or a ferrite bead. This maintains the proper reference potential for each ground plane. On the board, this should be placed as close as possible to the AD1819 and its voltage regulator. This allows the AD1819’s analog and digital ground return currents to flow through the analog and digital ground plane respectively.
Note: No digital or analog traces should cross the gap between the analog and digital planes.
IC leads should have pads and vias that go directly to the appropriate plane for power and ground. A separate small digital partition should be used for the crystal oscillator. This partition serves to keep noise from coupling onto the analog signals.
7.7 SMSC FDC37B78x Ultra I/O*
The Standard Microsystems Corporation (SMSC) FDC37B78x Ultra I/O provides keyboard, mouse, and floppy disk port control on the board. It also provides two serial ports: COM1 is shared with the touch screen interface, and COM2 is shared with the infrared interface. The Ultra I/O resides on the ISA bus and provides twelve IRQ options with full 16-bit address decode.
The FDC37B78x Ultra I/O provides support for the ISA plug-and-play Standard, v1.0a. The I/O address, DMA channel, and IRQ channel of each FDC37B78x logical device can be programmed through internal configuration registers. There are 480 I/O address location options, 12 IRQ options or serial IRQ options, and four DMA channel options for each logical device.
7.7.1 Floppy Disk Controller (FDC)
The FDC37B78x provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the formatter/controller, digital data separator, write precompensation, and data rate selection logic for an IBM PC XT/AT-compatible FDC. The true CMOS 765B core is 100% compatible with the IBM PC XT/AT in addition to providing data overflow and underflow protection. The FDC is also compatible with the 82077AA using SMSC's proprietary floppy disk controller core.
7.7.2 Serial Port Controller
The FDC37B78x incorporates two full function UARTs. They are compatible to the NS16450, the 16450 ACE registers, and the NS16C550A. The UARTs perform the necessary serial-to-parallel conversion on received characters and the parallel-to-serial conversion on transmitted characters. The data rates are programmable from 460.8 Kbaud to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized
Application Note 33
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
interrupts. Each UART contains a programmable baud rate generator that is capable of dividing the input clock or crystal by any number in the range of 1 to 65535. The second UART supports IrDA 1.0, HP-SIR, ASK-IR, and Consumer IR infrared modes of operation.
7.7.3 Infrared Interface
The SMSC FDC37B78x provides infrared support, including support for Consumer IR and IrDA, v1.0. The interface provides a two-way wireless communications port. Possible IR implementations for the second UART in this chip (logical device 5) include IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 pins TXD2 and RXD2, or can optional use pins IRTX and IRRX.
Serial communication baud rates up to 115.2 Kbps are provided for through IrDA, v1.0. The Amplitude Shift Keyed IR allows an asynchronous baud rate of up to 19.2 Kbaud.
COM1 is shared with the touch screen. Three 3-pin jumpers are provided to switch from COM1 to touch screen and vice versa. Placing a jumper on pins 1–2 on all three jumpers enables the touch screen. Placing a jumper on pins 2–3 enables COM1.
COM2 is shared with the infrared interface. IRTX2 and IRRX2 of the Ultra I/O directly connect TXD and RXD of the TEMIC TFDU4100 infrared transceiver respectively. The functionality of this COM port must be switched in the BIOS. The board uses the FDC37B78x's alternate IRTX2 and IRRX2 pins, allowing BIOS to switch from COM2 to the infrared interface.
7.7.4 Parallel Port Controller
The parallel port controller is compatible with the IBM PC XT/AT. It supports the optional PS/2-type bi-directional parallel port (SPP) mode, the enhanced parallel port (EPP) mode, and the extended capabilities port (ECP) mode.
7.7.5 Keyboard and Mouse
The universal keyboard controller uses an 8042 microcontroller processor core.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.7.6 Design Note for Ultra I/O*
Each power pin must be individually decoupled with a 0.1 µF capacitor. Since the real time clock on the Ultra I/O* is not used, VBAT must be tied to ground. If not grounded, this pin may float and confuse the internal circuitry that is trying to detect whether power is valid.
The Ultra I/O provides a BIOS interface. This is not implemented on the board; therefore ROMCS# must be pulled high to disable the ROM buffers and avoid interference with the boot ROM.
The SYSOPT pin is latched on the falling edge of RESET_DRV or on VCC Power On Reset to determine the configuration register’s base address. The SYSOPT pin is used to select the CONFIG PORT’s I/O address at power-up. Once powered up, the configuration power base address can be changed through configuration registers. See Table 4 for SYSOPT settings.
Note: If using TTL RS232 drivers, use a 1 KΩ pull-down resistor. If using CMOS RS232 drivers, use 10 KΩ pull-down resistor. The board uses TTL drivers, therefore SYSOPT should be pulled down with a 10 KΩ pull-up resistor. Therefore, the CONFIG PORT and INDEX PORT for the FDC37B78x are located at 0x0370h after reset.
The setting on SYSOPT must be different than SYSOPT on the SMSC FDC37C669 Super I/O in order for the two chips to configure at different addresses. On the board, the FDC37C669 SYSOPT is pulled low with a 1 KΩ resistor. Therefore, the FDC37C669 is located at 0x0370h in memory after reset. The two options are shown in Table 5.
Table 4. SYSOPT Pin Settings
Port Name SYSOPT = 0 (1 KΩ pull-down resistor)
SYSOPT = 1 (10 KΩ pull-up resistor)
Board Setting
CONFIG PORT 0x03F0h 0x0370h
INDEX PORT 0x03F0h 0x0370h
DATA PORT INDEX PORT + 1 INDEX PORT + 1
Table 5. SYSOPT Setting Options
Option FDC37B78x SYSOPT Pin FDC37C669 SYSOPT Pin
A SYSOPT = 1 (pulled HIGH with 10 KΩ resistor)
SYSOPT = 0(pulled LOW with 1 KΩ resistor)
B SYSOPT = 0(pulled LOW with 1 KΩ resistor)
SYSOPT = 1(pulled HIGH with 10 KΩ resistor)
Application Note 35
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.7.7 Additional Serial Ports with SMSC 37C669 Super I/O*
An additional Super I/O, SMSC 37C669 is used on the board to add two extra serial ports, COM3 and COM4. The parallel, IDE, and floppy interfaces are not used on this design. This configuration was chosen over separate 16550’s to limit cost and conserve board space.
Note: Each power pin must be individually decoupled with 0.1 µF capacitors.
All inputs to unused devices (i.e., parallel, IDE and floppy) are pulled to their inactive state. The value of the pull-up/pull-down resistor is chosen to keep the inputs within 0.5 V of the supply rails in order to minimize current consumption. Each pin has 10 µA of current leakage.
The FDC37C669 provides 11 decoded address lines, AEN, plus one chip-select input. Since the FDC37C669 can only decode the lower 11 address bits and AEN, an address decoder is needed for A[15:11]. An external gate such as an OR gate could be used to decode addresses A[15:11]. The output of the OR-gate is low when A[15:11] are low, thereby asserting the FDC37C669 chip select. Instead of the external address decoder, this design uses one of the two programmable chip select lines on the PIIX4E. The registers that control PCS0#, the first programmable chip select output of the PIIX4E, must be properly initialized by BIOS. The PCS0# output is tied to the Super I/O’s chip select. This chip select, AEN, and 11-bit address decode provides the full 16-bit ISA decode necessary.
At the trailing edge of a hardware reset, the SYSOPT input is latched to determine the configuration base address. Refer to Table 6 for SYSOPT settings.
Note: If you are using TTL RS232 drivers, use a 1 KΩ pull-down resistor. If using CMOS RS232 drivers, use a 10 KΩ pull-down resistor. The board uses TTL drivers, therefore SYSOPT should be pulled down with a 1 KΩ resistor or pulled up with a 10 KΩ resistor. SYSOPT is pulled low on the board; therefore the FD37C669 is located at 0x03F0h in memory after Reset.
The setting on SYSOPT must be different than SYSOPT on the FDC37B78x Ultra I/O in order for the two chips to configure at different addresses. The two options are listed in Table 7.
Table 6. SYSOPT Settings
Port Name SYSOPT = 0(1 KΩ pull-down resistor)
SYSOPT = 1(10 KΩ pull-up resistor)
INDEX Base I/O Address 0x03F0 0x0370
Table 7. SYSOPT Setting Options
Option FDC37B78x SYSOPT Pin FDC37C669 SYSOPT Pin
A SYSOPT = 1 (pulled HIGH with 10 KΩ resistor)
SYSOPT = 0(pulled LOW with 1 KΩ resistor)
B SYSOPT = 0(pulled LOW with 1 KΩ resistor)
SYSOPT = 1(pulled HIGH with 10 KΩ resistor)
NOTE: On the board, SYSOPT on the FDC37B78x is pulled HIGH and SYSOPT on the FDC37C669 is pulled LOW.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.8 Tritech Microelectronics TR88L803 Touch ScreenController
TriTech Microelectronics TR88L03 Touch Screen Controller is used to implement a touch screen solution. The TR88L03 is a fully integrated pen input processor with two multiplexed A/D input channels. The chip uses a serial interface, and there is no user configuration required.
The low-power TR88L803 contains all the circuitry required to interface the low cost 4- and 5-wire resistive digitizers to applications and provide pen input capability. The TR88L803 uses 10-bit ADCs to resolve 1024 levels. When clocked at 4 MHz, the TR88L803 is designed to simplify pen interfacing by integrating all pen input tasks required to present X, Y position data to the main application at 200 coordinate pairs per second. The TR88L803 provides standard asynchronous serial output or synchronous serial output. The TR88L803, with enhanced noise filtering, is ideally suited for operation in electrically noisy environments.
7.8.1 Implementation of the TR88L803
The touch screen controller shares resources with COM1 on the board. To use either COM1 or the touch screen, the board must be jumpered correctly.
The TR88L803’s serial data output is connected to the serial port TX pin through two general-purpose transistors. The transistors are properly biased to provide the necessary signal level swing for the TX pin. The negative signal level is derived with the RX pin of the serial port. RX is not used since data is unidirectional for the touch screen controller.
The touch screen controller provides two independent ADC input channels under the ADC multiplex mode. Control pin MUX_SEL multiplexes the internal ADC between serving the digitizer inputs (X+, X-, Y+, Y-) and the two independent ADC input channels. These channels are not implemented on the board; therefore ADC_1 and ADC_2 are tied to the analog ground through a 10-KΩ resistor and MUX_SEL is tied to ground.
The touch screen controller provides a 4-wire interface for the Dynapro* touch screen.
Mixed signal layout guidelines should be followed as discussed in the LCD/Video and Audio sections.
7.8.2 LCD with Integrated Touch Screen
The touch screen controller provides a four-wire interface for the Dynapro touch screen. The LCD interface consists of two connectors: Flat Panel Connector 1 and Flat Panel Connector 2. The Flat Panel Connector 1 provides an interface to LCD screens with up to 24-bit color. For 36-bit color, both Flat Panel Connector 1 and Flat Panel Connector 2 must be used.
Application Note 37
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.9 PCMCIA (Intel® Strataflash™ Memory and PC Card) Socket
This reference design uses the Texas Instruments PCI1225 PC Card Controller, supporting both an external PCMCIA card socket as well as on-board Intel® StrataFlash™ memory. The controller operates on a 3.3 V core and is PCI interface compatible with 3.3 V and 5.0 V PCI signaling environments. Supporting up to five general purpose I/Os, the controller is compliant with both the PCI Local Bus Specification, Revision 2.1 and 1995 PC Card Standards. The Fujitsu Takamisawa Americas 565P068-G/J-4V socket is compatible with PCMCIA card type I, II, and III.
7.9.1 Texas Instruments PCI1225 PC Card (PCMCIA) Controller
The Texas Instruments PCI1225 is a PCI-to-PC card controller that supports two independent PC card sockets, compliant with the 1995 PC Card Standards. The 1995 PC Card Standards retain the 16-bit PC card specification defined in PCMCIA, v2.1, and defines the new 32-bit PC card, called CardBus*, capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination of 16-bit and CardBus PC cards in the two sockets, powered at 5 V or 3.3 V.
The PCI1225 is compliant with the PCI Local Bus Specification, Revision 2.1 and with the PCI Bus Power Management Interface Specification. The PCI1225 can act as either a PCI master or slave device with PCI bus mastering initiated during CardBus PC card bridging transactions.
7.9.1.1 Slot A: PCMCIA Socket with Texas Instruments TPS2206 PC Card Power-Interface Switch with Reset
Slot A of the PCI1225 is connected to a PCMCIA socket for PCMCIA cards on the board. The Texas Instruments TPS2206 provides voltage regulation, over-current and over-temperature protection for the PCMCIA socket. The TPS2206 also accommodates 3.3 V/5 V systems by first powering-up the PCMCIA card with 5 V, then polling it to determine its 3.3 V compatibility.
The TPS2206 also provides a reset to the PCMCIA card. This reset is triggered by a PCI RESET signal (RST#) on the board.
7.9.1.2 Slot B: Intel® StrataFlash™ Memory
Capitalizing on two-bit-per-cell technology, Intel StrataFlash memory products provide 2x the bits in 1x the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include more density in less space, the lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide high performance with sustained bursting. The PCI1225 can also be programmed to accept fast posted writes to improve system bus utilization.
General purpose inputs and outputs are provided to implement sideband functions. Many other features are designed into the PCI1225, such as socket activity LEDs.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
A CMOS process is used to achieve low system power consumption while operating at PCI clock rates up to 33 MHz. Power consumption is further reduced by several low-power modes.
7.9.2 Design Notes for the PCI1225
The Texas Instruments PCI1225 is a PCI-to-PC card controller. The controller provides two PC card slots. Slot A is connected to a PCMCIA socket for PCMCIA cards on the board. Slot B of the PC card controller provides the interface to Intel StrataFlash memory.
The PCI1225 PC card controller is PCI bus master #3 (connected to PCI bus master pins REQ3# and GNT3#) on the board. It is also PCI device number 5 (IDSEL connected to AD16).
The PCI1225 provides the user with flexibility in determining the interrupt implementation. The interrupt mode is selected via bits [2:1] of the Device Control Register at PCI offset 92h. Other registers that must also be configured are described below. The interrupt implementations are listed in Table 8.
The board implements parallel IRQ and PCI interrupts. In this interrupt mode, the PCI1225 routes the legacy interrupts, IRQ[15:2], via the seven multifunction terminals MFUNC[6:0]. The parallel IRQ and PCI interrupt modes are selected by programming bits [2:1] of the Device Control Register at PCI offset 92h to a value of 01b. When this mode is selected, the multifunction terminals must be configured through the Multifunction Routing Register at PCI offset 8Ch.
The PCI interrupts INTA# and INTB# are available only on terminals MFUNC0 and MFUNC1, respectively. A maximum of five IRQ interrupts can be implemented through multifunction terminals MFUNC[6:2].
The multifunction terminals are connected on the board as listed in Table 9.
Table 8. IRQ and PCI Interrupt Implementations
Interrupt Mode PCI Offset 92h Bits 2:1
Parallel PCI Interrupts Only 00
Parallel IRQ and PCI Interrupts 01
Serial IRQ and Parallel PCI Interrupts 10
Serial IRQ and PCI Interrupts 11
Table 9. Multifunction (MFUNC[6:0]) Board Connections
Terminal Pin Connection on Board
MFUNC0 INTC#
MFUNC1 INTD#
MFUNC2 IRQ4
MFUNC3 IRQ5
MFUNC4 IRQ9
MFUNC5 IRQ10
MFUNC6 IRQ15
Application Note 39
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.10 ISA PCI Expansion Cards
There are two PCI expansion slots on this sample design, allowing for add-in card peripherals to enhance any design. There is also one ISA expansion slot in the design. With the variety of peripherals in this design that would ordinarily be implemented through an add-in card, two extra PCI slots and one extra ISA slot allows for functionality that has not been added.
• ISA Bus/Expansion Slots
As described in the Intel® 440BX PCIset Design Guide (order number 290613), pull-up and pull-down resistors should be placed as follows:
— 10 KΩ pull-ups on SD[15:0] and SA[19:0]
— 1 KΩ pull-up on IOCHRDY and REFRESH#
— 10 KΩ pull-up on IRQx (10 KΩ pull-up on IRQ8, MEMR#, MEMW#, IOR#, IOW#, LA[23:17], SMEMR#, SMEMW#, SBHE#, and BALE
— 330 Ω on ZEROWS#, MASTER#, MEMCS16#, and IOCS16#
— 4.7 KΩ on IOCHK#
— 5.6 KΩ pull-down resistors on DRQx
• PCI Bus/Expansion Slots
As described in the Intel® 440BX PCIset Design Guide, place pull-up signal resistors on the following:
— 2.7 KΩ pull-up resistors to 5 V on PIRQ[D:A]#, SDONE, SBO#, FRAME#, TRDY#, STOP#, IRDY#, DEVSEL#, PLOCK#, PERR#, SERR#, REQ64# and ACK64# and PAR
— 10 KΩ pull-ups to 3.3 V on GNT[3:0]#, PHLD# and PHLDA#
There are two PCI expansion slots on the board: Slot 0 is PCI device #17; Slot 1 is PCI device #18 (IDSEL connected to AD28 and AD29 through a 220 Ω resistor respectively). Each slot is connected to PCI bus master arbitration pins REQ# and GNT#. Slot 0 is connected to GNT0# and REQ0#, and Slot 1 is connected to GNT1# and REQ1#.
Note: For layout considerations when placing series resistors, refer to the Intel® 440BX PCIset Design Guide.
Interrupts on the board are configured as indicated in Table 10 to minimize interrupt latency.
Note: Refer to the PCI Local Bus Specification, Revision 2.1, for routing guidelines (see Appendix A).
Table 10. Board Interrupt Configurations
Device Interrupt Pin
LCD / Video Controller AC ’97 Audio PCMCIA† PCI Slot 0 PCI Slot 1
0 INTA# INTB# INTC# INTD# INTA#
1 X X INTD# INTA# INTB#
2 X X X INTB# INTC#
3 X X X INTC# INTD#
† The PCMCIA controller also uses legacy ISA IRQs. Refer to Section 7.9, “PCMCIA (Intel® Strataflash™ Memory and PC Card) Socket” on page 38 for more information.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
7.11 Clocking
Improper layout of the clock lines on the board can cause cross-coupling with other signal lines. It is recommended that the clock line spacing (air gap) be at least two times the trace width of any surrounding traces. It is also strongly recommended that the clock spacing be at least four times the trace width of any strobe line.
7.11.1 Cypress Semiconductor CY2280
The CY2280 is a clock synthesizer/driver that outputs four processor clocks at 2.5 V. There are eight PCI clocks that run at one-half or one-third the processor clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. The CY2280 possesses power-down, processor stop, and PCI stop pins for power management control. The signals are synchronized on-chip and ensure glitch-free transitions on the outputs.
The CY2280 outputs are designed for low EMI emissions. For further information, please refer to the following URL:
http://www.cypress.com/cypress/prodgate/timi/cy2280.htm.
7.11.2 Cypress Semiconductor CY2318
The CY2318 is a 3.3 V SDRAM buffer designed to distribute high speed clocks in PC systems and SDRAM modules. There are on-chip PLLs that lock to an input clock. It can be used to drive up to four SDRAM DIMMs. An I2C interface can be used to disable unused output clocks. For more information please refer to the following URL:
http://www.cypress.com/cypress/prodgate/modu/cy2318nz.htm.
7.11.3 Clocking for 440BX Chipset
The Intel 440BX chipset uses several techniques from the mobile and desktop markets to reduce power consumption — hence power dissipation — in a Celeron processor-based embedded system.
In the 440BX there are three main states used in clocking:
• Clock Stopped: CLKRUN# is being monitored for a restart, the clock is stopped.
• Imminent Clock Stop: The system has indicated the clock is about to be halted utilizing the CLKRUN# line.
• Clock Running: The clock is running and the PCI system bus is operational.
The 440BX is a CLKRUN# master unit and behaves according to the protocols specified for a master control device. The PIIX4E companion device to the chipset controls system clocks and is the CLKRUN# central resource. In designing a system, the main system clock should originate from a master clock oscillator, and for the processor and 82443BX, be from the same buffer driver output.
The signal paths must be setup to minimize clock skew and the resulting system instabilities. Trace length matching, along with proper terminations to minimize reflected energy, will result in better system performance and less overall noise that could otherwise affect system reliability.
Application Note 41
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
When the Intel 440BX chipset is used in a system application, the designer may elect to take advantage of the different clocking schemes and modes available to enhance system power and performance. There are five low power clocking modes available:
• Chip Standby: The 440BX, processor, and PCI buses are idle.
• Dynamic Stop Clock: Assists the processor in transitioning in and out of clock stop from system run.
• Powered On Suspend: All system phase locked loops (PLL) are shut down. The real time clock (RTC) and suspend clock (SUSCLK) are running. DRAM refresh is accomplished by using SUSCLK.
• Suspend to Ram (STR): The processor and L2 cache are clocked off. RTC and SUSCLK are running. The DRAM refreshes using SUSCLK.
• Suspend to Disk (STD): The processor and L2 cache, DRAM, and PCI interface are clocked off.
In clocking the main system, the PCI bus clock is derived from the main processor clock and is one half its frequency. For SDRAM, the clock is synchronized with BXDCLKO and BXDCLKRD.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Application Note 43
8.0 Design Considerations
High-speed designs such as the design in this application note require careful PCB layout and signal routing for trouble-free operation. Detailed routing notes and guidelines can be found in the schematics in Appendix B. Decoupling capacitors are shown where needed in the schematics. Decoupling capacitors provide a short between power and ground for high frequency noise signals.
• If a part is removed from the design, the outputs can be left unconnected, but the inputs should be pulled either high or low through an appropriate resistor.
• When changing jumper settings, first power down the board.
• Trace widths on all power and ground signals should be ~10 mil.
A fence is a line routed out of a plane such that a given area is isolated from the rest of the plane except at a single point of contact, conceptually the “gate” in the fence. A fence minimizes noise originating from the digital signaling onto the analog signals. This provides higher quality video or audio. An example is shown in Figure 5. The heavy black line is the routed area. The width of the gate or opening can be up to 75% of the length of the integrated circuit or signals in question. The width of the routed fence should conform to the separation routing between power planes (i.e., 25 mils minimum).
Figure 5. Fence Example
Plane (e.g., VCC)
Fenced area
Routed “fence”
Overlying
Chip/Signals “gate”
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
9.0 Windows* CE
Windows CE can have a similar look and feel as Microsoft Windows 98 or Windows NT. Experienced Windows programmers can write CE applications with little additional training, since Windows CE applications use Win32 Application Programming Interface (API) calls that are almost identical to those used in applications written for Windows 98/NT. A variety of interfaces are supported for embedded applications. The hardware configuration for an embedded system can include peripherals such as a keyboard, mouse, touch screen, and others. It is often easier for users to use commands and keys that are similar to those on their desktop PC in their office or home. A similar environment in the embedded product segment eliminates the need for retraining personnel, since they are already familiar with the look and feel of the system.
With Windows CE, the PC is used to prototype peripherals and develop device drivers; all develop-ment is done on the PC. If the target platform is also Intel architecture, the large knowledge base for Intel architecture can be utilized for hardware expertise, programmers, training materials, and sample code. Intel architecture is very efficient for all Windows operating systems. Since a lot of optimization effort has already been spent on the PC, reuse of PC developments can result in faster time-to-market. This is possible if the architecture of the Windows CE target is the same as the PC. The Windows CE Embedded Toolkit includes PC chipset and peripheral support, including basic VGA drivers and S3 accelerated drivers.
There are some differences between programming for the desktop and programming in Windows CE. Since Windows CE programs are required to have a small memory footprint, an important aspect of its programming is the need to manage with limited memory. Since memory usage must be minimized, having knowledge of memory allocations with Windows CE is important.
Embedded systems may stay powered-on for long periods of time. Programmers need to keep this in mind to ensure that the programs run flawlessly for long durations. Modifications must be made to the OEM Adaptation Layer. Since different solutions are possible for different applications, the applications’ varying needs can be met.
9.1 Windows CE for Embedded Applications
Windows CE is designed to be a multi-threaded, preemptive, multitasking operating system for platforms with limited resources. This is to say that multiple processes can be running simultaneously, each assigned a specific priority. Each process can have multiple threads. This allows a process to have more than one flow of execution running concurrently. Windows CE is designed as a modular operating system that can be customized to contain only the modules needed by the application. Refer to Appendix A for the URL for Microsoft’s Windows CE Toolkit (ETK) for Visual C++* and the newer CE development tool, Platform Builder. Platform Builder for Windows CE includes a version of the C++ compiler optimized for embedded systems. It also has a more graphical user interface and wizards that automate many of the CE build steps.
9.2 Windows CE Environment
9.2.1 Kernel
The Windows CE kernel contains the core operating system functionality that must be present on all Windows CE-based platforms. It includes support for memory management, process management, exception handling, multitasking and multithreading.
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Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
The kernel is provided as the file Nk.lib. The OEM Adaptation Layer must be developed to create the platform-specific Nk.exe module. For an overview of the OEM Adaptation Layer, refer to Section 9.2.3.
The kernel is designed specifically for small, fast, embedded devices. The kernel supports only a single 4 Gbyte address space (a 2 Gbyte virtual address and a 2 Gbyte physical address range). Of the 2 Gbyte virtual address space, 1 Gbyte is divided into 33 slots, each of which is 32 Mbytes. The kernel protects each process by assigning it to a unique open slot in memory. Within each slot, memory regions are allocated for the following:
• 64 Kbytes of reserved space
• Executable files, code, and data sections
• The primary thread’s stack, and the process’ default heap
• Dynamic-link libraries (DLLs) loaded from RAM
• DLLs loaded from ROM
The kernel protects applications from accessing memory outside of their allocated slot by generating an exception. Applications can check for and handle such exceptions by using the “try and except” Windows CE functions. The system is limited to 32 processes, but the number of threads running in a process is limited only by the amount of available memory.
9.2.2 Modularity
Windows CE is built from a number of discrete modules; therefore the size (footprint) of the operating system software can be controlled by selecting only the applicable modules. Several of these modules are also further divided into components. By selecting a minimum set of modules and components, the ROM and RAM requirements needed to support the end product can be minimized.
Refer to Understanding Modularity in Microsoft Windows CE (see Appendix A).
9.2.3 OEM Adaptation Layer (OAL)
A developer can adapt Windows CE for a specific target platform by creating a thin layer of code that resides between the kernel and the target platform. To avoid confusion with the Windows NT Hardware Abstraction Layer (HAL), Windows CE refers to this interface as the OEM Adaptation Layer, or OAL.
In addition to managing functions such as timing and power, the primary purpose of the OAL is to expose the target platform's hardware to the kernel. That is, each hardware interrupt request line (IRQ) is associated with one interrupt service routine (ISR). When interrupts are enabled and an interrupt occurs, the kernel calls the registered ISR for that interrupt. The ISR, the kernel mode portion of interrupt processing, is kept as short as possible. Its responsibility is primarily to direct the kernel to schedule and launch the appropriate interrupt service thread (IST). The IST, implemented in the device driver software module, gets or sends data and control codes to the hardware and acknowledges the device interrupt.
Application Note 45
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
9.3 Windows CE OS Build Information
9.3.1 Getting Started
When installing all the necessary software (either Platform Builder or Visual C++, SDK, and ETK), it is advisable to install support for only x86-based processors to save disk space. Find the correct build environment for the project you are going to develop. In Platform Builder this will be the CEPC platform. Wizards are used to automate many steps in building a CE platform. Several examples are provided in the Visual C++ and the CE toolkits (e.g., Maxall, Minshell). Newer versions of CE support faster downloading of the target system via an ethernet cable. A specially configured low-cost PC called a PC reference platform can be used as a CE target system for initial software development before final hardware becomes available. Details can be found in the CEPC reference platform document listed in Appendix A. PC based CE target system emulation is also possible with the Windows CE DDK.
9.3.2 Building a Windows CE OS with Platform Builder
After installing Platform Builder and X86 support, start Platform Builder, then follow these steps:
1. Choose File - New to create a new platform workspace. Each workspace uses several hundred megabytes of disk space, so make sure there is plenty of space available on the destination drive.
2. Give the workspace a name, and click OK.
3. Choose the CEPC board support package. The closest choice for this design’s platform is the Maxall platform.
4. Click Finish.
Make sure that the Win32 (X86) Debug or Release option is selected in the command bar.
There are several build options and drivers that are selected with environment variables. These dependencies are included in the *.bib files associated with the platform. To view the *.bib files click on the Parameter view tab at the bottom of the left window. Click on the Component tab to return to the component view.
The generic vga8 driver works with a wider variety of VGA controller chips. The environment variable, CEPC_DDI_VGA8BPP, controls VGA device driver selection and should be added and set to 1 to use the basic VGA driver instead of the default S3 trio VGA driver. To change or add environment variables, select Platform, Settings, then click the Environment tab.
You must also copy the VGA driver file ddi_vga8 to the workspace. You can copy by dragging the ddi_vga8 file from the right catalog Windows display folder to the workspace window on the left.
To build the platform, select Build and then Build Platform. It takes several minutes to compile all of the programs and build the new CE OS image. Monitor the build process by watching the output window that appears in the center of the screen and verify that there are no errors.
If no errors occur, the new OS image is contained in the file NK.BIN. This is the file that is downloaded to the target system. Prior to downloading the board, the programs ESHELL, CETERM, and CESH must be running with the appropriate cable and network download options and the cables must be properly connected. A floppy disk drive can be used to load the CE bootstrap loader on the target system. Applications for the new platform can be developed using the project feature of Platform Builder. In addition to the project build step, new applications will require an entry in the platform’s *.bib file to include the application’s module(s) in the OS build
46 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
process. An SDK for applications programming can also be generated using Platform Builder. Additional details can be found in the Windows CE Platform Builder 2.12 Getting Started Guide listed in Appendix A.
9.3.3 Building a Windows CE OS with the CE Toolkit
In Windows CE 2.1 and higher there are two preconfigured platforms called Maxall or Minshell. In Windows CE Toolkit 2.0 the various platform demos are named DEMOX, where X is an integer. After accessing the desired build environment for your system, type “blddemo” to build the image for that project. This places the image in the release directory. After building the image, load it into the target system using the Parallel Port Transfer Tool (PPSH) or in newer versions the CE Shell Utility (CESH) and ESHELL. A floppy disk drive can be used to load the CE bootstrap loader on the target system. CETERM is used to monitor debug messages from the target system. The configurations included with the Windows CE Embedded Toolkit for Visual C++ contain all the modules and components needed to build different versions of a Windows CE operating system.
Blddemo.bat, a build batch file included in the directory %_PUBLICROOT%\Common\Oak\Misc, automates the Build Tools required to generate the platform for your Windows CE operating system. For each configuration, a build batch file %_TGTPROJ%.bat (for example Minkern.bat) specifies the environment variables required for your Windows CE project. The following procedure describes how to configure your build environment and use Blddemo.bat to create the Windows CE operating system image for the operating system configuration.
To build a Windows CE operating system configuration:
1. If the configuration includes the Windows CE debug shell utility (CESH), invoke the Microsoft WinDbg debugging program shortcut for your platform (e.g., x86 Debugger).
2. Invoke the new command prompt build window shortcut that you created in Preparing to Build a Windows CE Operating System configuration.
3. As an optional step, modify your command prompt build window to add scroll bars. Scroll bars let you scroll back through the commands that the various batch files and tools execute. Click on the MS DOS icon in the top-left corner of the window, then click on Properties. Click on Layout and change the screen buffer size and height setting to 1000. This modification sets a 1000-line screen buffer so you can see up to 1000 of the most recent lines in that command window. After clicking OK, select the Modify shortcut that started the window to make this change permanent.
4. Set any additional environment variables for the configuration build in your command prompt build window. For example, if you want to build the Windows CE kernel with remote debugging enabled, use the following command:
set IMGNODEBUGGER=
To compile a configuration so that debugging messages are enabled, use the following command to set the environment variable WINCEDEBUG to debug:
set WINCEDEBUG=debug
For information on configuration-specific environment variables, see the corresponding description of the Windows CE operating system configuration in Section 9.3.3.
5. Enter the build batch file command to build the configuration blddemo.
After the build batch file is done processing, the current directory should still be the %_WINCEROOT% directory.
Application Note 47
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
6. Verify that the build batch file command completed successfully by checking whether the Nk.bin file exists in the directory %_FLATRELEASEDIR% (by default, \Wince211\Release). Nk.bin contains the binary image of the operating system for your selected platform.
9.3.4 Building a New Project
This section provides a tutorial that describes how to build the Windows CE operating system image based on the Maxall configuration. In this section, you will:
• Create a new platform directory
• Create a new project directory
• Create a new command prompt build window
• Build the Windows CE operating system image for your new project
This tutorial assumes that you have installed the Embedded Development Kit in the default directory established by the setup program.
9.3.4.1 Create a New Platform Directory
To create a new platform directory, copy the Wince211\Platform\Cepc directory and all of its contents, including the subdirectories and their contents, into a new platform directory. The platform name should be no more than eight characters in length.
From a Command Prompt window, type the following commands to copy the \Cepc directory from its default location and create \MyPlat, your new platform directory:
cd \Wince211\Platform
xcopy Cepc MyPlat /E /V /I
9.3.4.2 Create a New Project Directory
The Windows CE Embedded Toolkit for Visual C++ 5.0 (Embedded Toolkit) contains typical configurations of the Windows CE operating system. Use the Maxall configuration as the template for your MyProj build.
1. From a Command Prompt window, type the following commands to copy the \Maxall directory (including all subdirectories and contents) into a new project directory named \MyProj. The project name should be no more than eight characters in length.
cd \Wince211\Public
xcopy Maxall MyProj /E /V /I
2. Rename the \MyProj\Maxall.bat file. The name of this batch file should always match the name of your project directory. Type the following commands to rename the project batch file:
cd \Wince211\Public\MyProj
rename MAXALL.BAT MYPROJ.BAT
48 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
9.3.4.3 Create a New Command Prompt Build Window
The Embedded Toolkit includes a collection of shortcuts for the Minshell configuration. Each shortcut opens a command prompt build window specific to a supported processor. Use the x86 Minshell command prompt build window shortcut as a template for your shortcut. Your project and hardware development platform directories must first be created before you launch this shortcut.
1. In the Windows CE Embedded Development Kit program group, select the x86 Minshell shortcut.
2. Make a copy of the shortcut and rename it “x86 MyProj”.
3. In the tab shortcut for the icon's properties, modify the target command line parameters that follow the Wince.bat command. These modifications are case sensitive.
Wince.bat <cputype> <cpu> <os> <project> <platform>
For your build, the last part of the command line (starting with Wince.bat) must read as follows:
Wince.bat x86 I486 CE MYPROJ MYPLAT
4. Click OK to save the modified shortcut.
9.3.4.4 Build the Windows CE Operating System Image for a New Project
1. Invoke the x86 Build MyProj shortcut that you have previously created.
2. Enter the following command to build a complete version of Windows CE:
blddemo
After Blddemo.bat has finished processing, the current directory should still be the \Wince211 directory.
3. Be sure the build completed successfully by verifying that the Windows CE operating system image, called Nk.bin, exists in the \Wince211\Release directory. The build process sets this directory using the environment variable %_FLATRELEASEDIR%.
If Nk.bin does not exist, then the build of the Windows CE operating system image was not completed successfully. Before rebuilding, refer to “Preparing Your Development Workstation for Subsequent Projects” in the Windows CE Embedded Toolkit.
If Nk.bin exists, the Windows CE operating system image for MyProj was built successfully, and you can now run this image on your PC-based hardware development platform.
9.3.4.5 Adding Files or Applications to the Windows CE OperatingSystem Image
1. Copy the file or application to the \Wince211\Public\<projectname>\Oak\Files directory.
2. Edit the project.bib file in the same directory. Add a reference to the end of the file to include the files/app formatted:
filename.ext $(_FLATRELEASEDIR)\filename.ext S
3. Build the image by calling the blddemo utility.
Application Note 49
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Note: The filename.ext should be replaced with the name of your file or application. The S signals the image builder to make the file a system file. Other switches are H (hidden) and U (uncompressed), and can be used in combinations (e.g., SH = hidden system file).
9.4 Windows CE Device Drivers
Device drivers are programs that provide an interface between the operating system software and platform hardware. In previous versions of Microsoft operating systems, these device drivers were implemented as special system executable files that run at the same privilege level as the operating system kernel. In Windows CE, device drivers are implemented as DLLs and run at the same privilege level as the user code.
9.4.1 Design Note
Some third party vendors such as System Design Group (www.systemdesign.com) and Annasoft systems (www.annasoft.com) have additional Windows CE device drivers for bootstrap loading, flash memory, the 69000 VGA controller, and the audio chips. Some of these are also listed at the Driver Repository for Windows CE Platforms website listed in Appendix A.
9.4.2 Dynamic Link Libraries (DLLs)
DLLs are software function libraries like their predecessor, the static library. When a static library is linked to a program, the library functions used by the program are copied into the final executable image. This increases the size of the program. When a program is linked with a DLL, the library functions used by the program are not copied into the final executable image; only a function “stub” is copied. This function stub serves to identify the DLL and the function within the DLL that is being called upon. The actual DLL code is loaded into a separate memory space and the link between the program and the library function is created by the operating system when the function call is made. In addition, multiple programs can use DLLs simultaneously, reducing the memory requirements of each program.
9.4.3 Windows CE Device Driver Model
Windows CE has two types of device drivers as viewed from a software perspective: built-in and installable. Built-in drivers are typically for hardware that is native to the Windows CE target platform and are linked directly with the operating system image at build time. Some examples of this include keyboard, touch screen panel, battery, notification LED, PC card adapter, and audio hardware. Installable drivers are typically used for hardware that can be added to the platform. This type of driver is loaded by the operating system and exists as a stand-alone DLL. Some examples of this include modems, printers, digital cameras and PCMCIA cards. In either case, the terms built-in and installable relate to whether or not a particular device driver is linked directly with the operating system image or loaded at run time as a stand-alone DLL.
For Windows CE drivers, Microsoft provides a layer of source code known as the Model Device Driver (MDD) component. The MDD component defines the interface to the operating system for a given type of device driver and is common to all platforms that use that type of device. The MDD also defines the interface to the platform-specific driver code. This platform-specific driver code is referred to as the Platform Device Driver (PDD) component. The PDD component implements the interface to the hardware device. These two layers are compiled, then linked together to form the complete driver DLL.
50 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Whether or not a given type of device driver is built-in or installable is pre-determined by the MDD/OS interface defined by Microsoft for that type of device. For built-in drivers, Microsoft has defined a set of custom MDD/OS interfaces. For installable drivers, Microsoft has defined a set of common MDD/OS interfaces.
Note: It is not required to implement Windows CE device drivers as MDD and PDD components. They may be implemented as a single, monolithic entity providing that the MDD/OS interface, as defined by Microsoft for a given device, is used. See Figure 6.
9.4.4 Interaction with Application Software
Installable device drivers are viewed as a special file in the file system by the application software. The interface exposed to the application corresponds to the standard Win32 file I/O functions such as OpenFile, ReadFile, DeviceIOControl, and others. The file system recognizes filenames as being special devices when they consist of exactly three uppercase letters, a single digit, and a colon ( : ). An example of this would be “COM1:”, which references the first serial port available on the platform.
Built-in device drivers are accessed by application software using API calls that Microsoft has implemented in the Windows CE operating system for each device.
9.4.5 Incorporating Device Drivers
Use Platform Builder’s GUI interface or CE toolkit to manually include the new drivers in the project directory and add them to the Windows CE image. In CE toolkit, first take the compiled driver or file and place it in the following directory:
%_WINCEROOT%\public\maxall\files
Figure 6. Device Driver Architecture
A6176-01
GWE Subsystem
MDD Layer(Audio, touch,
keyboard)
PDD Layer
MonolithicDriver
(display,battery,
LED
Device Manager
MDD Layer(PC card,
Serial)
PDD Layer
MonolithicDriver
HARDWARE
Application Note 51
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Note: Maxall can be changed to the name of your project directory.
Edit the project.bib file in the same directory to include your file(s) and run blddemo.
A serial or network cable is needed to monitor debug messages and the appropriate communication’s programs must be running on the CE host system. The image must be downloaded to test the target board.
Refer to Microsoft’s web site for information on new releases.
9.4.6 ACTiSYS IR 2000B
To configure the ACTiSYS IR 2000B component:
1. Disable port 2 in the BIOS.
2. Set the environment variable to use nscfir.dll instead of irsir.dll.
3. Add the following to the Maxall.bat file or to the batch file that is used:
set IMGNSCFIR=1
4. To set up the registry correctly, modify the platform.reg file.
5. Find the following path and verify the following keys:
[HKEY_LOCAL_MACHINE\Comm\NscIrda1\Parms]
“BoardType”=dword:0
“DongleType”=dword:4
“ConfigBase”=dword:398
Note: The above keys are important keys; however other keys should also be checked for compatibility with your system (e.g., Bus Number and IRQ).
9.4.7 Audio
The card used in the sample design is the Creative Ensoniq* AudioPCI card. This configuration is valid for equivalent parts on the board, such as the Ensoniq ES1371 and an AC ’97 codec. The following steps are required to configure the digital controller.
1. Include these driver files in the build:
wavepdd.cpp
wavepdd.h
ensoniq.h
2. Edit the following source files:
a. Makefile
b. Make a directory in %_WINCEROOT%\platform\cepc\drivers for the driver.
1. Name the directory. (In our design it is called it “ES1371WaveDev.”)
2. Copy files into directory.
3. Edit file %_WINCEROOT%\platform\cepc\drivers\dirs to include this directory.
4. Remove references to the WaveDev in “dirs” file
c. Run “blddemo” from %_WINCEROOT%.
52 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
3. Set up configurations in VC++ to compile for Intel Architecture:
a. Load Application.
Check the Configuration list dialogue box for the desired configuration.
b. Under “Build” menu, select “Configurations.”
c. Click on the Add button.
d. Choose a matching configuration from “Copy Settings from”:
• For debug, select “Win32 (WCE xxxx) Debug.”
• For release, select “Win32 (WCE xxxx) Release.”
(xxxx signifies don't care)
e. Choose a platform:
• Choose WCE x86 to compile for target.
• Choose WCE x86em to compile for emulator.
f. Click on OK.
g. Click on Close.
Application Note 53
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Appendix A Related Resources
Table 11. Related Intel Documents
Document Order Number URL
Celeron™ and Pentium® II Processor
Celeron™ Processor at 266 MHz, 300 MHz, 300A MHz, 333 MHz, 366 MHz and 400 MHz datasheet 243658 http://www.intel.com/design/celeron/
datashts/243658
Intel® Celeron™ Processor Specification Update 243748 http://www.intel.com/design/celeron/specupdt/243748.htm
370-Pin Socket (PGA370) Design Guidelines 244410 http://developer.intel.com/design/celeron/applnots/244410.htm
Pentium® II Processor AGTL+ Guidelines 243330 http://developer.intel.com/design/PentiumII/applnots/243330.htm
Pentium® II Processor Developer’s Manual 243502 http://www.linear.com/aboutltc/functions/microprocessor.html
Pentium® II Processor Thermal Design Guidelines 243331 http://developer.intel.com/design/intarch/applnots/273331.htm
Pentium® II Processor Power Distribution Guidelines 243332 http://developer.intel.com/design/PentiumII/applnots/243332.htm
Pentium® II Processor Design for EMI 243334 http://developer.intel.com/design/PentiumII/applnots/243334.htm
VRM 8.2 DC-DC Converter Design Guidelines 243773http://developer.intel.com/design/pentiumII/xeon/designgd/243773.htm
Write Combining Memory Guidelines 244422 http://developer.intel.com/design/pentiumII/applnots/244422.htm
P6 Family of Processors - Hardware Developer’s
Manual244001 http://developer.intel.com/design/
pentiumII/manuals/244001.htm
Intel® 440BX AGPset
Intel® 440BX AGPset Desktop Design Guide 290634 http://developer.intel.com/design/chipsets/designex/290634.htm
Intel® 440BX AGPset Design Guide Update 290634 http://developer.intel.com/design/chipsets/designex/29064104.htm
Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet 290633 http://developer.intel.com/design/
chipsets/datashts/290633.htm
Intel 440BX AGPset: 82443BX Host Bridge Controller Specification Update 290639 http://developer.intel.com/design/
chipsets/specupdt/290639.htm
Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet 290562 http://developer.intel.com/design/
chipsets/datashts/290562.htm
Intel® 82371EB (PIIX4) Specification Update 290635 http://developer.intel.com/design/chipsets/specupdt/290635.htm
Application Note 55
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Table 12. Related Specifications, Technical Papers, and Reference Books
Document Location/URL
PCI Local Bus Specification, Revision 2.1 http://www.pcisig.com/specs.html
Accelerated Graphics Port Interface Specification 2.0 http://www.intel.com/pc-supp/platform/agfxport/index.htm
Pentium Pro and Pentium II System Architecture http://www.mindshare.com
PCI System Architecture http://www.mindshare.com
AGP System Architecture http://www.mindshare.com
SEMTECH SC1185 DC/DC Converter Datasheet http://www.semtech.com
MAXIM MAX1617 Remote Temperature Sensor http://www.maxim-ic.com
Cypress CY2280 Clock Synthesizer/Driver and CY2318 SDRAM Buffer Datasheets http://www.cypress.com
Standard Microsystems Corporation - Ultra I/O and Super I/O Controller Datasheets http://www.smsc.com/main/document.html
Texas Instruments PCI1225 PC Card Controller http://www.ti.com/sc/docs/products/analog/pci1225.html
Creative Labs ES1373 AC97 Digital Controller Datasheet http://www.creative.com
Analog Devices AD1819 AC97 SoundPort Codec http://products.analog.com/products/info.asp?product=AD1819
69000 HiQVideo Accelerator with Integrated Memory datasheet
http://www.chips.com/design/graphics/mobilegraphics/datashts/ds_69000.htm
Application Notes for the HiQVideo Family http://www.chips.com/design/graphics/mobilegraphics/applnots/
Designing with Flash Memory in Windows CE Applications http://developer.intel.com/design/flash/isf/wince/wince1.htm
Understanding Modularity in Microsoft Windows CE http://www.microsoft.com/windowsce/embedded/resources/techpap.asp
Introducing the Windows CE Embedded Toolkit http://www.microsoft.com/windowsce/embedded/resources/techpap.asp
Driver Repository for Windows CE Platforms http://www.microsoft.com/windowsce/embedded/resources/driverrep.asp
Windows CE Driver for Intel 82559 Ethernet Controller http://developer.intel.com/platforms/applied/software/559ce211.htm
Windows CE Driver for 69000 VGA Controller http://www.annasoft.com/vdk69000.htm
Windows CE Platform Builder http://www.microsoft.com/windowsce/Embedded/resources/pb.asp
Windows CE Platform Builder 2.12 Getting Started Guide http://msdn.microsoft.com/library/techart/guide.htm
Windows CE Developer Documentation http://www.microsoft.com/windowsce/Embedded/download/212doc.asp
Windows CE Developer’s Handbook http://www.sybex.com
Windows CE PC Hardware Reference Platform http://www.microsoft.com/windowsce/Embedded/resources/refplat/cepcconfig.asp
56 Application Note
Intel® Celeron™ Processor-Based Transaction Terminal Sample Design
Appendix B Schematics
B.1 Transaction Terminal Baseboard Schematics
Schematics are provided for the following items:
• Embedded Celeron Processor
• 440BX part 1 and 2
• SDRAM DIMM sockets 0 and 1
• ISA/PCI pullups
• Clocks and buffers
• 82559 Ethernet Controller
• PCI slots 0 and 1
• Reset and Powergood
• ATX power connector
• DC/DC Converter
• 69000 VGA Video part 1 and 2
• AC ’97 Audio part 1 and 2
• PCI1225 PCMCIA Controller
• StrataFlash
• PIIX4E part 1 and 2
• IDE connector
• USB connectors
• Ultra I/O
• ISA connector
• COMx, DB25, floppy
• Touch screen controller
• Super I/O (extra serial ports)
• Flash BIOS
• Unused gates
Application Note 57
5 5
4 4
3 3
2 2
1 1
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CC
BB
AA
Celeron Processor Based Transction Terminal Sample Design
Title Page
Table of Contents
Title Page,Table Of Contents, & Revision History
Transaction Terminal Block Diagram
CPU Part One & ITP Port
CPU Part Two
Intel disclaims all liability,
including liability for infringement
of any proprietary rights, relating to
use of information in this
specification. Intel does not warrant
or represent that such use will not
infringe such rights.
Copyright Intel Corporation 1999
No license, express or implied, by
estoppel or otherwise, to any
intellectual property rights is
granted herein.
THIS SCHEMATIC IS PROVIDED "AS IS"
WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF
MERCHANTABILITY, FITNESS FOR ANY
PARTICULAR PURPOSE, OR ANY WARRANT
OTHERWISE ARISING OUT OF PROPOSAL,
SPECIFICATION OR SAMPLE.
Page 1
Page 2
Page 3
Page 4
Page 5
6/16/1999
Revision History
8/15/1999
Revision A -- Initial release.
Routing Guidelines/Restrictions
440BX Part One
440BX Part Two & Clock
PIIX4 Part One
PIIX4 Part Two
IDE Interface
Ethernet Port
PCI & ISA Termination
Reset and Powergood
ATX Power Connector
DC to DC Convertor
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 16
Page 17
Page 18
Page 19
Page 20
69000 Video Controller - Part One
DIMM 0 Interface
GTL+ Bus Termination
Clock
ISA Connector
Touch Screen
Additional Serial Ports
Flash BIOS
Unused Devices
Page 21
Page 22
Page 23
Page 24
Page 25
Page 26
Page 27
Page 28
Page 29
Page 31
Page 32
Page 33
Page 34
I/O Connectors
Page 30
DIMM 1 Interface
PCI Connectors
AC 97 Audio - Part One
69000 Video Controller - Part Two
AC 97 Audio - Part Two
PCMCIA Controller
StrataFlash
USB Connector
Ultra I/O
Page 15
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Routing Guidelines/Restrictions
6/16/1999
PWB must be routed using eight (8) layers, with the following stackup:
Layer 1: Signal, V1P5 Bus, V2P5 Bus
Layer 2: GND
Layer 3: Power -- V3P3 Plane
Layer 4: Signal
Layer 5: Signal
Layer 6: Split Power Plane -- V5P0 Plane, V2P0 Island
Layer 7: GND
Layer 8: Signal
Trace impedance mst be 65 ohms, +/- 10%
>>
>>
Top and bottom (outer) layers must be no less than 1/2 oz copper before plating, inner layers must be 1 oz copper.
>>
>>
A clock trace must not alternate layers.
>>
A clock trace must be separated by a minimum of 25 mils from any other trace, including serpentines,
11 mils is OK when going betwen pins or balls.
The CPU clock length must be between 1" and 9", and 460 mils shorter than the BX clock. The BX clock and all PCI
clocks must be matched in length, except for the PMC clock which must be 2" shorter than all other PCI clocks.
>>
Total board thickness must be .062".
>>
>>
Board material must be FR-4.
>>
GND layers must not be split.
Adjacent signal layers must be orthogonal.
>>
No right angles are to be used when routing, and serpentines must use curves.
>>
>>
Vias for decoupling capacitors must be kept as close as possible to the capacitor pad.
General Routing Requirements
GTL+ Bus Specific Routing Requirements
V1P5
L1
L2
L3
L4
CPU
BX
56
Ohm
L1
1.5"
4.5"
L3
0.0"
1.0"
L4
0.0"
2.0"
L5
0.0"
0.1"
L5
Minimum space between traces is 10 mils, this includes adjacent layers.
>>
>>
Minimum space between GTL+ traces and other types of traces is 25 mils, this includes adjacent layers.
GTL+ address, data, and control lines must be routed as separate groups and treated as different signal types.
>>
Minimum trace width for L5 (V1P5) power bus bus is 150 mils.
>> Memory Bus Specific Routing Requirements
>>
Minimum space between traces is 10 mils, this includes adjacent
layers.
Minimum space between memory traces and other types of traces
is 25 mils, this includes adjacent layers.
>>
Memory address, data, and control lines must be routed as
separate groups and treated as different signal types.
>>
>>
Minimum trace width is 5 mils.
>>
Minimum trace width is 5 mils.
>>
The MD, DQM, CS#, CKE, SRAS#, SCAS#, WE#, and MA signals
(between BX and DIMMs) must be between 1" and 3" in length,
matched to within 600 mils.
>>PCI Bus Specific Routing Requirements
The PIIX4E must be the last device on the PCI bus.
Clock Specific Routing Requirements
Series terminating resistors must be kept as close to the driving pin as possible.
>>
SDRAM_CLK[1:0] must be matched in length, and between 1" and 3" in length.
>>
>>
>>
Trace length between BX-DCLK0 and SDRAM clock driver (signal REF) must be between 1" and 6".
>>
Place IDE conector within 3" of PIIX4E.
IDE Specific Routing Requirements
Place IDE series terminating resistors within 500 mils of
PIIX4E.
>>
Address Signals: A#[31:3]
>>
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#, PRDY#, ADS#,
BNR#, BP[3:2]#, BPM[1:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#
>>
Data Signals: D#[63:0]
GTL+ GROUPS -- CPU PPGA370 Names
Control Signals:
>>
>>
Address Signals: MAA[13:0]
DClK, SMBDATA, SMBCLK, CSA[1:0]#,
WE_A#, SCAS_A#, SRAS_A#
Data Signals: MD#[63:0]
>>
Memory Bus GROUPS -- DIMM Names
>>
Control Signals:
Daisy chain signals going to more that on point, do not use stubs.
>>
CPU
V2P0 Island (Layer 6)
V1P5 Power Bus Bar (Layer 1)
Remainder of layer 6 is V5P0 Power Plane.
BX
General Placement Requirements
GTL+ groups must be matched in length by 750 mils or less.
>>
>>
Groups must be matched in length by 750 mils or less.
>>
PCI bus max length must be less than 4".
>>
Groups must be matched in length by 750 mils or less.
>>
Address/Data Signals: AD[31:0]
BUSMD1#, C/BE[3:0]#, REQ1#, GNT1#,
INT[A:D]#, PCIRST#, FRAME#, TRDY#,
IRDY#, STOP#, DEVSEL#, SERR#, PERR#,
PAR, LOCK#
>>
PCI Bus GROUPS
Control Signals:
Place major components and connectors
as shown in the Mechanical drawings.
>>
>>
Rotate the CPU and BX chips so as
to minimize the length of the
connections between the two, and
place as shown in the diagram to
the right:
>>
All unrelated signals and power planes must be kept away from the switching circuits.
Power Supply Specific Routing Requirements
>>
All traces associated with the input power/ground connectors, and the capacitors connected to these connectors, must be routed with minimum length and maximum width.
>>
See the Power Supply schematic sheet for complete restrictions.
>>
The diagram below depicts the placement
requirements for the SC1185 switching
regulator circuits. A GND plane penninsula
is used to contain the high current and noisy
switching components. All of the bold
traces and vias shown have high current and
low impedance requirements. These trace
widths should be 200 mils minimum. The
channel which connects the GND penninsula to
the main GND plane must be 500 mils in width.
L
in
in
in
in
GATE
GND PLANE PENNINSULA
Output PWR vias
Input PWR via
C
L
Qin
Output PWR via
GND Vias
out
out
Q
C
out
AGND TRACE
GATE
SC1185
CHIP
CC
>>
No other signals may be routed underneath the GND plane penninsula.
No other power planes may exist underneath the GND plane penninsula.
>>
GND Vias
CLKOUT, from the SDRAM clock driver to the BX, must be between 3.5" and 5.5" in length, and 2.5" longer
than SDRAM_CLK[1:0].
A
Cel
eron
Pro
cess
or B
ased
TT
Ref
eren
ce
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
334
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
A A
B B
C C
D D
E E
44
33
22
11
CPU, ITP Port, & Clock
6/16/1999
>>
Do not populate.
SMBus address set to 0011000B.
>>
>>
Route THERMDP and THRMDN as a pair, maintaining 10 mil spacing between each other and 20 mil spacing
from any other trace. Provide a ground traces to isolate the pair from other traces.
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
434
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
HA
#21
HA
#25
HD
#1
HD
#7
HD
#19
HD
#45
HD
#49
RS
#2
HA
#18
HD
#6
HD
#10
HD
#31
HD
#47
HR
EQ
#2
HA
#3
HD
#2
HD
#14
HD
#20
HD
#25
HD
#44
HD
#39
HD
#43
HD
#54
HD
#55
HD
#56
HA
#23
HD
#0
HD
#16
HD
#35
HD
#36
HD
#41
HD
#52
HR
EQ
#3
HA
#10
HA
#24
HD
#38
HD
#50
HD
#61
HD
#63
HA
#9
HA
#14
HD
#3H
D#4
HD
#18
HA
#5
HA
#22
HD
#15
HD
#26
HD
#30
HD
#33
HA
#16
HD
#11
HD
#21
HD
#46
HD
#53
HR
EQ
#0
HA
#27
HD
#13
HD
#24
HD
#28
HD
#37
HD
#40
HD
#57
HR
EQ
#4
HA
#12
HA
#13
HD
#5
HD
#9
HD
#60
HA
#6
HA
#26
HA
#29
RS
#0
HA
#19
HA
#30
HA
#8
HA
#17
HA
#31
HD
#22
HD
#23
HA
#4
HA
#28
HD
#8
HD
#32
HD
#58
HA
#11
HD
#12
HD
#29
HD
#34
HD
#51
HD
#59
HD
#62
RS
#1
HA
#7
HA
#15
HA
#20
HD
#17
HD
#27
HD
#42
HD
#48
HR
EQ
#1
SM
BC
LK10
,12,
13,1
4,15
,17
SM
BD
AT
A10
,12,
13,1
4,15
,17
HD
#[63
:0]
6,7
BR
EQ
0#6,
7
HR
EQ
#[4:
0]6,
7
SLP
#10
,17
AD
S#
6,7
RS
#[2:
0]6,
7
BN
R#
6,7
HT
RD
Y#
6,7
HIT
#6,
7
H_I
GN
NE
#10
,17
HA
#[31
:3]
6,7
HLO
CK
#6,
7
DB
SY
#6,
7
H_N
MI
10,1
7
100/
66#
14
BP
RI#
6,7
DE
FE
R#
6,7
HIT
M#
6,7
H_I
NIT
#10
,17
PW
RG
OO
D_2
P5
18
DR
DY
#6,
7
FE
RR
#10
,17
DB
RE
SE
T#
18
TH
ER
M_A
LER
T#
10
H_I
NT
R10
,17
ST
PC
LK#
10,1
7 HR
ES
ET
#6,
7
CP
U_B
CLK
14
PX
4_S
MI#
10
H_A
20M
#10
,17
PIC
CLK
14
V3P
3
V2P
5V
2P5
VC
MO
S
VC
MO
S
VC
MO
S
VC
MO
S
VC
MO
S
VC
MO
S
VC
MO
S
V2P
5
VC
MO
S
V2P
5
VC
MO
S
VC
MO
S V1P
5V
2P5
V2P
5V
2P5
VC
MO
S
V1P
5
VC
OR
E
R21
150
R22
150
TP
11
R9
510
R1
220
C1
10pF
50V
SK
1
PG
A-3
70 S
OC
KE
T
U1A
Cel
eron
AK
8A
H12
AH
8A
N9
AL1
5A
H10
AL9
AH
6A
K10
AN
5A
L7A
K14
AL5
AN
7A
E1 Z6
AG
3A
C3
AJ1
AE
3A
B6
AB
4A
F6
Y3
AA
1A
K6 Z4
AA
3A
D4
AN
29A
N31
AH
14A
N17
AK
20A
N19
AN
25A
L27
AN
27
AL2
5A
L23
AE
33A
E37
AG
37A
G33
M36 L37
J37
AK
26A
J35
AH
30A
G35
AJ3
3A
C35
AE
35
AH
28A
L31
AL2
9
C37
AG
1S
35E
27
E21
C35
E35
G33
E3
7A
L33
AN
35A
K32
AN
33A
N37
A35 X
4
W1
T4
N1
M6
U1
S3
T6
J1 S1
P6
Q3
M4
Q1
L1 N3
U3
H4
R4
P4
H6
L3 G1
F8
G3
K6
E3
E1
F12
A5
A3
J3 C5
F6
C1
C7
B2
C9
A9
D8
D10
C15
D14
D12
A7
A11
C11
A21
A15
A17
C13
C25
A13
D16
A23
C21
C19
C27
A19
C23
C17
A25
A27
E25
F16
AK
18A
H16
AH
18A
L19
AL1
7
AH
26A
H22
AK
28
W37
J33
J35
L35
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#1
0A
#11
A#1
2A
#13
A#1
4A
#15
A#1
6A
#17
A#1
8A
#19
A#2
0A
#21
A#2
2A
#23
A#2
4A
#25
A#2
6A
#27
A#2
8A
#29
A#3
0A
#31
BR
O#
AD
S#
BN
R#
BP
RI#
LOC
K#
DE
FE
R#
TR
DY
#D
BS
Y#
DR
DY
#
HIT
#H
ITM
#
A20
M#
FLU
SH
#IG
NN
E#
INIT
#LI
NT
0/IN
TR
LIN
T1/
NM
IP
RE
Q#
PW
RG
OO
DS
MI#
SLP
#S
TP
CLK
#
BS
EL#
FE
RR
#IE
RR
#
TH
ER
MT
RIP
#T
HE
RM
DP
TH
ER
MD
N
CP
UP
RE
S#
ED
GC
TR
LR
eser
ved
Res
erve
d
VC
OR
ED
ET
BP
M0#
BP
M1#
BP
2#B
P3#
TC
KT
DI
TM
ST
RS
T#
TD
OP
RD
Y#
RE
SE
T#
D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#1
0D
#11
D#1
2D
#13
D#1
4D
#15
D#1
6D
#17
D#1
8D
#19
D#2
0D
#21
D#2
2D
#23
D#2
4D
#25
D#2
6D
#27
D#2
8D
#29
D#3
0D
#31
D#3
2D
#33
D#3
4D
#35
D#3
6D
#37
D#3
8D
#39
D#4
0D
#41
D#4
2D
#43
D#4
4D
#45
D#4
6D
#47
D#4
8D
#49
D#5
0D
#51
D#5
2D
#53
D#5
4D
#55
D#5
6D
#57
D#5
8D
#59
D#6
0D
#61
D#6
2D
#63
RE
Q#0
RE
Q#1
RE
Q#2
RE
Q#3
RE
Q#4
RS
#0R
S#1
RS
#2
BC
LKP
ICC
LK
PIC
D0
PIC
D1
R7
330
R10
330
U2
MA
X16
17
1 2 3 4 5 6 7 8910111213141516
NC
1V
CC
DX
PD
XN
NC
2A
DD
1G
ND
GN
DN
C5
AD
D0
ALE
RT
#S
MB
DA
TA
NC
4S
MB
CLK
ST
BY
#N
C3
R18
1K
R6
330
R5
330
R8
330
R11
51
R13
150
R27
1K
R3
330
C2
.1uF
16V
R12
330
R24
56
R26
220
P1
ITP
Inte
rfac
e
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
RE
SE
T#
DB
RE
SE
T#
TC
KT
MS
PO
WE
RO
ND
BIN
ST
#G
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DB
CLK
GN
DG
ND
GN
DT
DI
TD
OT
RS
T#
BS
EN
#P
RE
Q0#
PR
DY
0#P
RE
Q1#
PR
DY
1#P
RE
Q2#
PR
DY
2#P
RE
Q3#
PR
DY
3#
R2
430
R23
220
R15
10K
R14
330
R16
1K
C3
2200
pF50
V
R20
47
R17
1K
R4
430
R19
47
TP
21
R25 15
0
A A
B B
C C
D D
E E
44
33
22
11
Place one cap near every two VREF pins.
Minimize GTLREF length, and 25 mils minimum width.
Isolate from other traces with a ground barrier trace.
6/16/1999
CPU Power
>>
>>
Place caps near pin AB36
>>
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
534
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
GT
LRE
F7
VID
020
VID
120
VID
220
VID
320
V2P
5
VC
OR
E
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
E
VC
OR
EV
CO
RE
VC
OR
E
VC
OR
E
V1P
5
VC
OR
E
VC
OR
E
VC
OR
EV
CO
RE
VC
OR
E
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
E
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
VC
OR
EV
CO
RE
V1P
5
VC
MO
S
C40
0.1u
FC
3922
uFC
410.
1uF
C4
1uF
10V
C32
4.7u
F10
V
U1C
Cel
eron
E23
E29
E31
F10
G35
G37
L33
N33
N35
N37
Q33
Q35
Q37
S33
S37
U35
U37
V4
W3
W35
X6
Y1
E21
E27
R2
S35
X2
AH
20A
H4
A29
A31
A33
AA
33A
A35
AC
1A
C37
AF
4A
K16
AK
24A
K30
AL1
1A
L13
AL2
1A
N11
AN
13A
N15
AN
21A
N23
B36
C29
C31
C33
Res
26R
es27
Res
28R
es29
Res
30R
es31
Res
32R
es33
Res
34R
es35
Res
36R
es37
Res
38R
es39
Res
40R
es41
Res
42R
es43
Res
44R
es45
Res
46R
es47
Vco
rede
tR
es49
Res
50R
es51
Res
52
RE
S1
RE
S2
RE
S3
RE
S4
RE
S5
RE
S6
RE
S7
RE
S8
RE
S9
RE
S10
RE
S11
RE
S12
RE
S13
RE
S14
RE
S15
RE
S16
RE
S17
RE
S18
RE
S19
RE
S20
RE
S21
RE
S22
RE
S23
RE
S24
RE
S25
C33
4.7u
F10
V
C5
1uF
10V
L1 22uH
R29
150
R28
75
C6
1uF
10V
C7
1uF
10V
C37
.1uF
16V
C36
.1uF
16V
C35
.1uF
16V
C34
.1uF
16V
C38
22uF
25V
C8
1uF
10V
C24
4.7u
F10
V
C12
1uF
10V
U1B
Cel
eron
A37
AB
32A
C33
AC
5A
D2
AD
34A
F32
AF
36A
G5
AH
2A
H34
AJ1
1A
J15
AJ1
9A
J23
AJ2
7A
J3A
J7A
K36
AK
4A
L1A
L3A
M10
AM
14A
M18
AM
2A
M22
AM
26A
M30
AM
34A
M6
AN
3B
12B
16B
20B
24B
28B
32B
4B
8D
18D
2D
22D
26D
30D
34D
4E
11E
15E
19E
7F
20F
24F
28F
32F
36G
5H
2H
34K
36L5 M
2M
34P
32P
36Q
5R
34T
32T
36U
5V
2V
34X
32X
36Y
37Y
5Z
2Z
34A
J31
Y33
AL3
5A
M36
AL3
7A
J37
W33
U33
AA
37A
A5
AB
2A
B34
AD
32A
E5
AF
2A
F34
AH
24A
H32
AH
36A
J13
AJ1
7A
J21
AJ2
5A
J29
AJ5
AJ9
AK
2A
K34
AM
12A
M16
AM
20A
M24
AM
28A
M32
AM
4A
M8
B10
B14
B18
B22
B26
B30
B34 B
6C
3D
20D
24D
28D
32D
36 D6
E13
E17 E
5E
9F
14 F2
F22
F26
F30
F34 F
4H
32H
36 J5 K2
K32
K34
M32 N
5P
2P
34R
32R
36 S5 T2
T34
V32
V36 W5
X34
Y35
Z32
E33 F18 K
4R
6V
6A
D6
AK
12A
K22
AD
36 Z36
AB
36
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
VID
0V
ID1
VID
2V
ID3
PLL
1P
LL2
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
EV
CC
_CO
RE
VC
C_C
OR
E
VR
EF
0V
RE
F1
VR
EF
2V
RE
F3
VR
EF
4V
RE
F5
VR
EF
6V
RE
F7
VC
C_1
.5V
CC
_2.5
VC
C_C
MO
S
C11
1uF
10V
C10
1uF
10V
C9
1uF
10V
C13
1uF
10V
C25
4.7u
F10
V
C27
4.7u
F10
V
C26
4.7u
F10
V
C17
1uF
10V
C16
1uF
10V
C15
1uF
10V
C14
1uF
10V
C19
1uF
10V
C23
1uF
10V
C21
1uF
10V
C18
1uF
10V
C22
1uF
10V
C20
1uF
10V
C28
4.7u
F10
V
C31
4.7u
F10
V
C30
4.7u
F10
V
C29
4.7u
F10
V
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
GT
L+ T
ER
MIN
AT
ION
RE
SIS
TO
RS
GTL+ Termination
6/16/1999
>>
Place one CAP near every four pullups.
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
634
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
HD
#60
HD
#52
HD
#58
HD
#61
HD
#49
HD
#63
HD
#54
HD
#56
HD
#62
HD
#50
HD
#51
HD
#53
HD
#55
HD
#57
HD
#59
HD
#1
HD
#6
HD
#33
HD
#17
HD
#2
HD
#14
HD
#0
HD
#4
HD
#3
HD
#7
HD
#19
HD
#41
HD
#29
HD
#34
HD
#31
HD
#44
HD
#25
HD
#43
HD
#26
HD
#12
HD
#9
HD
#38
HD
#8
HD
#13
HD
#18
HD
#32
HD
#23
HD
#47
HD
#15
HD
#46
HD
#37
HD
#42
HD
#24
HD
#28
HD
#39
HD
#36
HD
#35
HD
#16
HD
#20
HD
#11
HD
#27
HD
#22
HD
#45
HD
#30
HD
#10
HD
#5
HD
#40
HD
#48
HD
#21
HR
EQ
#0
HR
EQ
#2H
RE
Q#1
HR
EQ
#3
RS
#1R
S#2
RS
#0
HA
#31
HA
#4
HA
#13
HA
#11
HA
#29
HA
#28
HA
#15
HA
#27
HA
#17
HA
#24
HA
#25
HA
#9
HA
#30
HA
#7
HA
#10
HA
#5H
A#2
1
HA
#18
HA
#12
HA
#19
HA
#16
HA
#6
HA
#20
HA
#22
HA
#26
HA
#3
HA
#23
HA
#8
HA
#14
HD
#[63
:0]
4,7
HA
#[31
:3]
4,7
HR
EQ
#[4:
0]4,
7
RS
#[2:
0]4,
7
HT
RD
Y#
4,7
BP
RI#
4,7
DB
SY
#4,
7
DE
FE
R#
4,7
DR
DY
#4,
7
BR
EQ
0#4,
7
BN
R#
4,7
AD
S#
4,7
HIT
#4,
7
HIT
M#
4,7
HLO
CK
#4,
7
HR
ES
ET
#4,
7
V1P
5
V1P
5V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5 V1P
5 V1P
5 V1P
5
V1P
5V
1P5
V1P
5
V1P
5
V1P
5V
1P5
V1P
5V
1P5
V1P
5
V1P
5 V1P
5V
1P5
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5
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V1P
5
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5
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5
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5 V1P
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5
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5
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5
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5
V1P
5
V1P
5
V1P
5
V1P
5 V1P
5
V1P
5
V1P
5
V1P
5V1P
5
V1P
5V1P
5
V1P
5
V1P
5V
1P5
V1P
5
V1P
5
V1P
5
V1P
5
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5
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5
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5 V1P
5
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5
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5
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5
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5
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5V
1P5
V1P
5V
1P5
V1P
5V
1P5
V1P
5V
1P5
V1P
5V
1P5
V1P
5V
1P5
V1P
5V
1P5
R35
56
R43
56R
3956R
3156
C57
.1uF
16V
C56
.1uF
16V
C60
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16V
C61
.1uF
16V
C58
.1uF
16V
C59
.1uF
16V
C65
.1uF
16V
C63
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16V
C67
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C62
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R10
456
R10
256
C68
.1uF
16V
C69
.1uF
16V
C64
.1uF
16V
C66
.1uF
16V
R12
056
R96
56
R10
856
R10
656
R12
256
R94
56
R11
856
R12
156 R
133
56
R13
256
R98
56
R11
656
R11
456
R11
256
R11
056
R10
056
R97
56
R11
756
R99
56R95
56
R10
356
R10
556
R11
556
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956
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156
R11
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156
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356
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756
R55
56R
5956
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56R
5156
R44
56
R56
56
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56
R76
56R52
56
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56
R60
56R36
56
R88
56
R68
56
R92
56
R72
56R
6656
R70
56R
7456
C42
.1uF
16V
R38
56R
4256
R62
56
R45
56 R53
56
R77
56 R85
56
R57
56
R46
56
R61
56
R89
56
R37
56R
4156R
3356
R73
56
R93
56R69
56R
6756
R63
56
R71
56R
7556
R81
56
R65
56
R49
56R
5056
R14
156
R14
056
R13
956
R13
856
R54
56R
5856
R64
56
R48
56
R32
56
C43
.1uF
16V
R80
56
C44
.1uF
16V
C45
.1uF
16V
C46
.1uF
16V
R87
56R79
56
R91
56
C48
.1uF
16V
C47
.1uF
16V
R83
56
R13
156
R34
56
R13
756
R13
656
R13
556
R13
456
R82
56
R90
56R
8656R
7856
C51
.1uF
16V
C52
.1uF
16V
C50
.1uF
16V
C49
.1uF
16V
C55
.1uF
16V
C53
.1uF
16V
C54
.1uF
16V
R30
56
R12
556
R12
956
R12
856
R12
756
R12
456
R12
356
R12
656
R13
056
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
440BX - Part One
6/16/1999
>>
Do not populate.
Minimize REFVCC length, and 25 mils minimum width.
Isolate from other traces with a ground barrier
trace.
>>
GCLKOUT and G_CLK_FB must be same length
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
734
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
GF
RA
ME
#G
DE
VS
EL#
GIR
DY
#G
ST
OP
#G
TR
DY
#
GP
AR
SU
ST
AT
#
C/B
E#1
AD
9
AD
12
AD
17
AD
24
GA
D11
GA
D18
GA
D23
GA
D29
AD
25
GC
/BE
#3
AD
28
GA
D8
GA
D14
GA
D27
GC
/BE
#1
GA
D6
GA
D30
AD
10
AD
4
AD
22
GA
D31
G_C
LK_F
B
AD
14
AD
23
AD
29
GA
D17
AD
15
GA
D3
G_R
EQ
#
GA
D1
GA
D21
GA
D25
AD
3
AD
11
AD
13
AD
16
AD
19
GA
D12
GA
D19
C/B
E#2
GA
D0
AD
20
AD
26
GA
D10
GA
D15
GA
D28
AD
5
GC
/BE
#2
AD
30
GA
D9
GA
D13
GA
D16
GA
D26
G_G
NT
#
AD
18
GC
/BE
#0
AD
8
AD
21
AD
31
C/B
E#3
AD
6
SU
ST
AT
#
AD
27
GA
D5
GA
D24
C/B
E#0
GA
D4
GA
D22
AD
0A
D1
AD
2
AD
7
GA
D2
GA
D7
GA
D20
HD
#16
HA
#5
HD
#10
HD
#35
HD
#51
HD
#1
HA
#12
HA
#14
HD
#42
HA
#25
HD
#17
HD
#0
HA
#6
HD
#24
HD
#40
HA
#28
HR
EQ
#3
HD
#56
HA
#4
HD
#9
HD
#34
HD
#50
HD
#63
HA
#11
HA
#13
HD
#41
HD
#48
HA
#22
HD
#23
HD
#39
HD
#55
HA
#24
HR
EQ
#2
HD
#7
HD
#21
HD
#8
HD
#33
HD
#37
HD
#49
HR
EQ
#0
HD
#62
HA
#23
HD
#15
HA
#3
HA
#10
HD
#47
HA
#21
HR
EQ
#1
HD
#6
HD
#22
HD
#38
HD
#54
HD
#61
HD
#4
HD
#20
HD
#32
HA
#17
HD
#45
RS
#2
HD
#14
HD
#59
HA
#9
RS
#0
HD
#46
HA
#20
HA
#31
HD
#5
HD
#53
HD
#44
HD
#60
HD
#19
HD
#3
HD
#31
RS
#1HA
#16
HA
#27
HD
#58
HA
#8
HD
#13
HD
#26
HD
#29
HA
#19
HA
#30
HD
#11
HD
#27
HD
#36
HD
#52
HD
#2
HD
#18
HD
#30
HA
#15
HD
#43
HA
#26
HD
#57
HD
#28
HA
#7
HD
#12
HD
#25
HA
#18
HA
#29
HR
EQ
#4
AD
[31:
0]9,
15,1
6,23
,25
C/B
E#[
3:0]
9,15
,16,
23,2
5
FR
AM
E#
9,15
,16,
17,2
3,25
DE
VS
EL#
9,15
,16,
17,2
3,25
IRD
Y#
9,15
,16,
17,2
3,25
TR
DY
#9,
15,1
6,17
,23,
25S
TO
P#
9,15
,16,
17,2
3,25
PA
R9,
15,1
6,17
,23,
25S
ER
R#
9,15
,16,
17,2
1,23
,25
PH
OLD
#9,
17P
HO
LDA
#9,
17
PR
EQ
0#16
,17
PR
EQ
1#16
,17
PR
EQ
2#15
,17
PR
EQ
3#17
,25
PG
NT
0#16
,17
PG
NT
1#16
,17
PG
NT
2#15
,17
PW
RO
K3P
310
,18
PC
I_C
LK0
14
HD
#[63
:0]
4,6
HA
#[31
:3]
4,6
HR
ES
ET
#4,
6A
DS
#4,
6B
NR
#4,
6B
PR
I#4,
6
DB
SY
#4,
6D
EF
ER
#4,
6D
RD
Y#
4,6
HIT
#4,
6H
ITM
#4,
6H
LOC
K#
4,6
HT
RD
Y#
4,6
BR
EQ
0#4,
6R
S#[
2:0]
4,6
HR
EQ
#[4:
0]4,
6
BX
_HC
LK14
PC
IRS
T#
9,15
,16
GT
LRE
F5
LOC
K#
16,1
7
PR
EQ
4#17
,23
PG
NT
4#17
,23
GC
/BE
#[3:
0]21
GA
D[3
1:0]
21
GF
RA
ME
#21
GD
EV
SE
L#21
GIR
DY
#21
GP
AR
21
GT
RD
Y#
21G
ST
OP
#21
GC
LKO
UT
21
PG
NT
3#17
,25
V3P
3
V5P
0
V3P
3
V3P
3
V1P
5V
3P3
V3P
3
R14
88.
2K
RP
28.
2K
1 2 3 45678
8244
3BX
492
BG
A
HO
ST
INTE
RFA
CE
U3-
1
C13
M26
B8
A7
E11
K21
C10
C15
D19
D20
E21
D9
G25
C11
A18
A22
B19
D18
D21
A3
B23
C21
C19
M25
H22
A21
G23
B22
H24
A19
C20
D22
H23
H26
B18
G24
C17
B21
L23
F26
E20
E17
A20
D17
E19
J26
B20
G26
E18
B17
C16
K23
A17
G22 L24
F22
K22
B16
F23
D16
A16
F24
B15
H25
A15
D14
F25
D15
L22
B13
K26
C14
E14
E23
D13
A13
L26
D12
B12
E26
B14
E25
E13
L25
D11
D25
A12
B11
D26
A11
J22
B7
B25
C12
C8
C26
B10
A10
A25
A9
A8
C25
B9
J23
A24
D24
C23
K24
B24
C24
K25
A23
E22
D23 J25
N23
B26
P22
AE
22A
E23
M23
E16
M24
F17
AB
22
HD
44#
CR
ES
ET
#
HD
61#
HD
56#
HD
57#
AD
S#
HD
60#
HD
28#
HD
15#
HD
14#
HD
2#
HD
58#
HA
3#
HD
59#
HD
19#
HD
3#
HD
18#
HD
16#
HD
4#
PC
IRS
T#
CP
UR
ST
#
HD
5#
HD
17#
TE
ST
IN#
HA
4#
HD
6#
HA
5#
HD
0#
BN
R#
HD
20#
HD
7#
HD
1#
HA
6#
BP
RI#
HD
21#
HA
7#
HD
22#
HD
8#
DB
SY
#
HA
8#
HD
9#
HD
23#
HD
10#
HD
24#
HD
11#
DE
FE
R#
HD
12#
HA
9#
HD
13#
HD
25#
HD
26#
DR
DY
#
HD
27#
HA
10#
HIT
#
HA
11#
HLO
CK
#
HD
29#
HA
12#
HD
30#
HD
31#
HA
13#
HD
32#
HT
RD
Y#
HD
33#
HD
34#
HA
14#
HD
35#
HIT
M#
HD
36#
RS
#0
HD
37#
HD
38#
HA
15#
HD
39#
HD
40#
RS
#1
HD
41#
HD
42#
HA
16#
HD
43#
HA
17#
HD
45#
RS
#2H
D46
#
HA
18#
HD
47#
HD
48#
HA
19#
HD
49#
HR
EQ
#0
HD
50#
HA
20#
HD
51#
HD
52#
HA
21#
HD
53#
HD
54#
HA
22#
HD
55#
HD
62#
HA
23#
HD
63#
HR
EQ
#1
HA
24#
HA
25#
HA
26#
HR
EQ
#2
HA
27#
HA
28#
HR
EQ
#3
HA
29#
HA
30#
HA
31#
HR
EQ
#4
HC
LKIN
BR
EQ
0#
RE
SV
AR
ES
VB
RE
SV
C
GT
LRE
FA
GT
LRE
FB
VT
TA
VT
TB
RE
SV
D
C71
10pF
50V
R14
410
K
PCI INTERFACE
AGP INTERFACE
8244
3BX
492
BG
A
PCI ARB & PWR MGT
U3-
2
A6
E2
N4
J4
T5
C7
AC
2
K6 F3
L1
F10
L4N3
G3
E1
D8
M3
L2
E7
W3
F5
K1
E4
K2
D7
AB
2
K4 F4
D10C
4
M2
K3
E10F
2
K5
G5J1
W5
J2
M1
H2
AB
5
H1
E8J5
N2
H3
F1
H5
B6
H4
B2
G1
V5
G2
D6
G4
E9
D1
P2
D3
AE
3
D2
Y4
C1
P4
A2
W4
C3
P3
B3
R1
D4
Y1
E5
V4
A4
Y2
D5
AE
2
B4
U2
B5
L5
A5
L3
E6
AD
3
C6
AD
2A
D1
AC
3A
C1
AB
4A
B1
AA
5A
A3
AA
4A
A2
AA
1
AD
4
Y5
AF
3
Y3
AC
4
C2
W1
V2
W2
U5
V1
U4
U3
U1
T3
T4
T2
T1
U6
R3
R4
R2
M4
P5
N5
PR
EQ
0#/IO
RE
Q#
FR
AM
E#
AG
PR
EF
V
C/B
E0#
GA
DS
TB
-B
PR
EQ
1#
GA
DS
TB
-A
AD
0
DE
VS
EL#
ST
2
PR
EQ
2#
ST
0
SB
-ST
B
C/B
E1#
IRD
Y#
PR
EQ
3#
PIP
E#
ST
1
PG
NT
0#/IO
GN
T#
GF
RA
ME
#
TR
DY
#
SB
A0
C/B
E2#
AD
1
PG
NT
1#
GC
/BE
0#
AD
2
ST
OP
#
PR
EQ
4#
C/B
E3#
SB
A1
AD
3
PG
NT
2#
PLO
CK
#
AD
4
PA
R
AD
5
GD
EV
SE
L#
AD
6
SB
A2
AD
7
GA
D0
AD
8
PG
NT
3#
AD
9
SB
A3
AD
10
SE
RR
#
AD
11
PH
OLD
#
AD
12
PC
LKIN
AD
13
GIR
DY
#
AD
14
PH
LDA
#
AD
15
PG
NT
4#
AD
16
SB
A4
AD
17
WS
C#
AD
18
GC
/BE
1#
AD
19
SB
A5
AD
20
GT
RD
Y#
AD
21
SB
A6
AD
22
SB
A7
AD
23
GS
TO
P#
AD
24
GC
/BE
2#
AD
25
GP
AR
AD
26
GA
D1
AD
27
GC
/BE
3#
AD
28
GR
EQ
#
AD
29
GG
NT
#
AD
30
GA
D2
AD
31
GA
D3
GA
D4
GA
D5
GA
D6
GA
D7
GA
D8
GA
D9
GA
D10
GA
D11
GA
D12
GA
D13
SU
ST
AT
#
GA
D14
BX
-PW
RO
K
GA
D15
CLK
RU
N#
RE
FV
CC
GA
D16
GA
D17
GA
D18
GA
D19
GA
D20
GA
D21
GA
D22
GA
D23
GA
D24
GA
D25
GA
D26
GA
D27
GA
D28
GA
D29
GA
D30
GA
D31
RB
F#
GC
LKO
UT
GC
LKIN
C70
.1uF
16V
R14
511
0
R14
610
K
D1
200m
A3
1
2
C72
.1uF
16V
R14
7
1K
R14
322
R14
222
RP
3
8.2K
2 3 4 5 7 8 9 10
1 6
R1
R2
R3
R4
R5
R6
R7
R8
P1
P2
R14
910
0K
R15
1
100
R15
0
150
RP
18.
2K
2 3 4 5 7 8 9 10
1 6
R1
R2
R3
R4
R5
R6
R7
R8
P1
P2
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
6/16/1999
440BX Part Two & Clock
Place as close as possible to pin AD25
>>
Place decoupling caps around BX, at a minimum the four corners if routing
prevents even distribution.
>>
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
834
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
MD
0M
D1
MD
2M
D3
MD
4M
D5
MD
6M
D7
MD
8M
D9
MD
10M
D11
MD
12M
D13
MD
14M
D15
MD
16M
D17
MD
18M
D19
MD
20M
D21
MD
22M
D23
MD
24M
D25
MD
26M
D27
MD
28M
D29
MD
30M
D31
MD
32M
D33
MD
34M
D35
MD
36M
D37
MD
38M
D39
MD
40M
D41
MD
42M
D43
MD
44M
D45
MD
46M
D47
MD
48M
D49
MD
50M
D51
MD
52M
D53
MD
54M
D55
MD
56M
D57
MD
58M
D59
MD
60M
D61
MD
62M
D63
MA
A0
MA
A1
MA
A2
MA
A3
MA
A4
MA
A5
MA
A6
MA
A7
MA
A8
MA
A9
MA
A1
0M
AA
11
MA
A1
2M
AA
13
DQ
MA
0D
QM
A1
DQ
MA
2D
QM
A3
DQ
MA
4D
QM
A5
DQ
MA
6D
QM
A7
MD
[63:
0]12
,13
DQ
MA
[7:0
]12
,13
MA
A[1
3:0]
12,1
3
CS
A0#
12C
SA
1#12
SC
AS
_A#
12,1
3
SR
AS
_A#
12,1
3
WE
_A#
12,1
3
CS
A2#
13C
SA
3#13
CS
B0#
12C
SB
1#12
CS
B2#
13C
SB
3#13
DC
LKW
R14
BX
DC
LKO
14
CK
E0
12,1
3C
KE
112
,13
CK
E2
12,1
3C
KE
312
,13
V3P
3
V3P
3V
3P3
V3P
3V
3P3
V3P
3V
3P3
V3P
3V
3P3
C81
22pF
50V
8244
3BX
492
BG
A
U3-
4
B1 F7
F9
F18
F20 G
6G
21 J6 J21
L11
L13
L14
L16
M12
M15
N11
N16
N22
N26 P
1P
11P
16R
12R
15 T11
T13
T14
T16 V6
V21 Y
6Y
21A
A7
AA
9A
A18
AA
20A
E1
AE
26A
F2
AF
14
A1
A14
A26
C5
C9
C18
C22
E3
E12
E15
E24
F6
F8
F19
F21
H6
H21
J3 J24
L12
L15
M5
M11
M13
M14
M16
M22
N1
N12
N13
N14
N15
N24
P12
P13
P14
P15
P26
R5
R11
R13
R14
R16
R22
T12
T15
V3
V24
W6
W21
AA
6A
A8
AA
19A
A21
AB
3A
B12
AB
15A
B24
AB
25A
D5
AD
9A
D18
AD
22A
F1
AF
13A
F26
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
CV
CC
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
ME
MO
RY
INT
ER
FA
CE
8244
3BX
492
BG
A
U3-
3
AE
21
AF
25
AF
17
AD
21
AD
16
AF
22
AB
14
AC
16
AB
16
AF
15A
E15
AE
11
AD
17
AC
15A
D15
AB
17
AE
17
AE
16
AE
25
AE
18
AC
6
AD
24
AD
19
AC
17
AD
26A
C24
AC
26
AB
18
AB
23
AA
10
AF
18
AB
19
AD
13A
C13
AF
20
AC
25A
B26
AE
19
AC
20U
23
AE
14A
C14
AB
20
AF
19
AA
22A
A24
AC
18
AE
13
AA
23
AD
14
AC
19
AC
22A
F23
AE
20
AE
24A
D23
AF
6
AD
20
AC
23A
F24
AF
21
AF
12
AA
26
AB
13
AC
21
AF
16A
A17
AC
10
AE
12A
C12
AF
11A
D25
AB
21
AD
7
AD
12T22
AA
25
AE
7
Y22
AF
4
AC
8
T23
AD
8
AF
10
AF
8
T26
AE
8A
F9
R24
AD
10
AD
11
AE
10
R25
AB
11
AE
4
AC
11
P23
Y23
Y24
Y26
N25
W22
AF
5
V22
AC
5
V23
Y25
V25
AE
5
U22
U25
AB
6
U26
W23 T24
AD
6
T25
W24
U21
AE
6
R23
W26
R26
P24
W25
P25
AB
7
V26
AC
7
U24
AF
7A
B8
AB
9A
C9
AE
9A
B10
MA
B11
#
MA
A13
MA
A0
MA
B12
#
MA
B0#
MA
B13
CS
A0#
/RA
SA
0#
MA
B1#
MA
A1
CS
A1#
/RA
SA
1#C
SA
2#/R
AS
A2#
ME
CC
0
MA
B2#
CS
A3#
/RA
SA
3#C
SA
4#/R
AS
A4#
MA
B3#
MA
A2
CS
A5#
/RA
SA
5#
CS
B0#
/RA
SB
0#
MA
B4#
MD
35
CS
B1#
/RA
SB
1#
MA
B5#
MA
A3
CS
B2#
/RA
SB
2#C
SB
3#/R
AS
B3#
CS
B4#
/RA
SB
4#
MA
B6#
CS
B5#
/RA
SB
5#
ME
CC
1
MA
A4
MA
B7#
DQ
MA
0/C
AS
A0#
DQ
MA
1/C
AS
A1#
MA
B8#
DQ
MA
2/C
AS
A2#
DQ
MA
3/C
AS
A3#
MA
A5
MA
B9#
MD
24
DQ
MA
4/C
AS
A4#
DQ
MA
5/C
AS
A5#
MA
B10
MA
A6
DQ
MA
6/C
AS
A6#
DQ
MA
7/C
AS
A7#
MA
A7
DQ
MB
1/C
AS
B1#
ME
CC
2
DQ
MB
5/C
AS
B5#
MA
A8
CK
E0/
FE
NA
CK
E1/
GC
KE
MA
A9
CK
E2/
CS
A6
CK
E3/
CS
A7
MD
36
MA
A10
CK
E4/
CS
B6
CK
E5/
CS
B7
MA
A11
SC
AS
A#
ME
CC
3
SC
AS
B#
MA
A12
SR
AS
A#
SR
AS
B#
MD
13
WE
A#
WE
B#
ME
CC
4D
CLK
WR
DC
LK0
MD
37
ME
CC
5
MD
25
ME
CC
6
MD
38
ME
CC
7
MD
0
MD
39
MD
26
MD
40
MD
14
MD
41
MD
27
MD
42M
D43
MD
28
MD
44
MD
15
MD
45
MD
29
MD
46
MD
1
MD
47
MD
30
MD
48
MD
16
MD
49
MD
31
MD
50
MD
2
MD
51
MD
32
MD
52
MD
17
MD
53
MD
33
MD
54M
D55
MD
34
MD
56
MD
18
MD
57
MD
3
MD
58
MD
19
MD
59
MD
4
MD
60
MD
20
MD
61M
D62
MD
21
MD
63
MD
5
MD
22
MD
6
MD
23
MD
7M
D8
MD
9M
D10
MD
11M
D12
C73
.1uF
16V
C74
.1uF
16V
C75
.1uF
16V
C76
.1uF
16V
C77
.1uF
16V
C78
.1uF
16V
C79
.1uF
16V
C80
.1uF
16V
R15
222
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PIIX4 Part One
6/16/1999
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
934
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
XD
5X
D6
XD
7
XD
0X
D1
XD
2X
D3
XD
4
SD
2
SA
0
SD
2
SA
7
PD
D2
AD
20
AD
24
C/B
E#2
C/B
E#3
SA
2
PD
D11
PD
D15
AD
15
AD
23
AD
25
LA2
0
SD
9
SA
6
SA
18
AD
13
AD
28
C/B
E#0
SD
0
SA
5
SA
13
AD
2
AD
5
AD
30
SD
4
C/B
E#1
PD
A1
PD
A2
LA2
3
SD
12
PD
D3
AD
1
PD
D4
PD
D12
PD
D14
SD
1
SD
7
SA
14
SA
19
AD
9
LA1
9
SD
4S
D5
AD
3
AD
19
AD
26
AD
29
SD
5
SD
3
PD
D0
SD
6
SD
8
SA
10
SA
11
SA
12
SA
15
PD
D9
AD
6
SD
6
SD
11
SD
14
AD
21
LA1
7
AD
16
SD
13
SA
8
PD
D8
PD
D13
SD
1
AD
18
LA1
8
SA
1
SD
10
AD
12
SD
7
LA2
1
SA
3
AD
11
AD
22
PD
A0
PD
D1
SA
16
PD
D7
AD
8
AD
0
SA
17
AD
27
AD
31
SD
3
LA2
2
SA
4
AD
7
AD
17A
D18
SD
0
SD
15
SA
9
PD
D5
PD
D6
AD
4
PD
D10
AD
10
AD
14
AD
[31:
0]7,
15,1
6,23
,25 C
/BE
#[3:
0]7,
15,1
6,23
,25
DE
VS
EL#
7,15
,16,
17,2
3,25
IRD
Y#
7,15
,16,
17,2
3,25
PA
R7,
15,1
6,17
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25
SE
RR
#7,
15,1
6,17
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23,2
5
FR
AM
E#
7,15
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3,25
TR
DY
#7,
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TO
P#
7,15
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17,2
3,25
PC
IRS
T#
7,15
,16
PH
OLD
#7,
17
PD
D[1
5:0]
11
PD
RE
Q11
PC
S1#
11
PC
S3#
11
PD
A[2
:0]
11
PD
DA
CK
#11
PIO
RD
Y11
PD
IOW
#11
SD
[15:
0]17
,28,
29,3
2
SA
[19:
0]17
,28,
29,3
2,33
LA[2
3:17
]17
,29
SM
EM
W#
17,2
9
BA
LE17
,29
XO
E#
10
XD
IR#
10
XD
[7:0
]33
ME
MW
#17
,29,
33
AE
N28
,29,
32
ME
MR
#17
,29,
33
IOR
#17
,28,
29,3
2
PH
OLD
A#
7,17
SY
SC
LK29
IOC
HR
DY
17,2
8,29
SM
EM
R#
17,2
9
ZE
RO
WS
#17
,29
SB
HE
#17
,29
PD
IOR
#11
IOC
S16
#17
,29
RE
FR
ES
H#
17,2
9
RS
TD
RV
11,2
8,29
,32
IOC
HK
#17
,29
IOW
#17
,28,
29,3
2
V5P
0
PCI
SIGNALS
IDE
SIGNALS
IDE
SIGNALS
ISA/EIO
SIGNALS
PIIX4
U4A PIIX
4
C8
G16C
6
G19D
4
G18D
2
C17
C10
G17E
5
A17A
5
Y15
A3
F18B
5
B17B
6
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1V
3B
12 F17
A12
A18A
6
F16D
5
T14
C5
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C16
W14
B16
W3
D16
U13
E15
V13
U2
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T11
T12
T2
F20
W2
W11
Y2
B15
T1
Y11
V1
W16
T10
T16
D14
Y17
W10
V17
E18
Y18
U9
W18
C14
Y19
V9
W19
B10
Y9
A14
T8
E20
W8
C13
U7
V7
A13
Y7
D18
V6
C12
Y6
A10
T5
D12
W5
D20
U4
B13
V4
D13
C20
B14
D9
E14
B20
A15
C15
A20
D15
C9
A19B
9
B19A
9
C19D
8
D19E
8
D17B
8
E19A
8
E17D
7
F19C
7B
7A
7D
6E
6E
4C
4B
4A
4D
3E
3C
3B
3E
2C
2B
2A
2D
1E
1C
1B
1
C18
H16
B18
H17
E10
A11
B11
C11
Y12
V15
U15
W4
U3
T7
U10
Y1
W7
V12
Y3
W12
W1
Y5
T4
T3
Y4
C/B
E#0
PD
A0
C/B
E#1
PD
DA
CK
#
C/B
E#2
PD
A1
C/B
E#3
SD
A0
CLO
CK
RU
N#
PD
A2
DE
VS
EL#
SD
DA
CK
#
FR
AM
E#
GP
O1/
LA17
IDS
EL
PD
RE
Q
IRD
Y#
SD
A1
PA
R
SD
RE
Q
PC
IRS
T#
SD
0P
HO
LD#
PD
IOR
#
PH
OLD
A#
SD
A2
SE
RR
#
PD
IOW
#
ST
OP
#
GP
O2/
LA18
TR
DY
#
PIO
RD
Y
SA
0
SD
IOR
#
GP
O3/
LA19
SD
IOW
#
SD
1
SIO
RD
Y
GP
O4/
LA20
SD
D0
GP
O5/
LA21
SD
2
GP
O6/
LA22
SA
1
GP
O7/
LA23
SD
3
PD
D0
SD
4
SA
2
SD
5
SD
D1
SD
6
SA
3
SD
7S
D8
SA
4
SD
9
SD
D2
SD
10
SA
5
SD
11
PD
D1
SD
12
SA
6
SD
13
SD
D3
SD
14
SA
7
SD
15
AD
0
SA
8
SD
D4
SA
9
PD
D2
SA
10
SD
D5
SA
11S
A12
SD
D6
SA
13
PD
D3
SA
14
SD
D7
SA
15
AD
1
SA
16
SD
D8
SA
17
PD
D4
SA
18
SD
D9
SA
19
SD
D10
PD
D5
SD
D11
AD
2
SD
D12
PD
D6
SD
D13
SD
D14
PD
D7
SD
D15
AD
3
PD
D8
AD
4
PD
D9
AD
5
PD
D10
AD
6
PD
D11
AD
7
PD
D12
AD
8
PD
D13
AD
9
PD
D14
AD
10
PD
D15
AD
11A
D12
AD
13A
D14
AD
15A
D16
AD
17A
D18
AD
19A
D20
AD
21A
D22
AD
23A
D24
AD
25A
D26
AD
27A
D28
AD
29A
D30
AD
31
DS
3S#
DS
3P#
DS
1S#
DS
1P#
RE
Q0#
RE
Q1#
RE
Q2#
RE
Q3#
ME
MC
S16
#M
EM
R#
ME
MW
#S
ME
MR
#
SM
EM
W#
SY
SC
LKG
PO
0/B
ALE
GP
I0/IO
CH
K#
RE
FR
ES
H#
IOC
S16
#Z
ER
OW
S#
SB
HE
#R
ST
DR
VIO
R#
IOW
#IO
CH
RD
YA
EN
R15
6
4.7K
R15
411
0
R15
3
110
R15
522
C82
47pF
50V
R15
7
110
R15
8
110
U5
74A
LS2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11
A1
A2
A3
A4
A5
A6
A7
A8
G DIR
B1
B2
B3
B4
B5
B6
B7
B8
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
6/16/1999
PIIX4 Part Two
Minimize VREF length, and 25 mils minimum width.
Isolate from other traces with a ground barrier
trace.
>>
Trace lenghts between crystal and chip must be matched and less than 500
mils. Trace widths must be 100 mils minimum.
>>
Trace lenghts between capacitors and crystal be matched and less than
300 mils. Trace widths must be 100 mils minimum. Capacitor connections
to GND go directly to plane.
>>
>>
Trace must be routed directly over a GND plane.
Do not route any other traces under the clock circuitry.
>>
Clear CMOS
GPIO HEADER
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1034
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DR
Q1
DR
Q3
DR
Q0
GP
I17
GP
I13
DR
Q6
GP
I2G
PI3
DR
Q7
DR
Q2
GP
I14
GP
I1
GP
I15
GP
I7
DR
Q5
GP
I19
GP
I20
GP
I21
GP
I3
GP
I21
GP
O28
GP
I5
GP
I17
GP
O10
GP
O12
GP
I2
GP
I18
GP
I14
GP
O11
GP
O9
GP
O21
GP
O0
GP
O30
GP
I19
GP
I15
GP
O25
GP
I16
GP
O15
GP
O24
GP
O29
GP
O8
GP
I7G
PI1
3
GP
O26
GP
O27
GP
I4
GP
I20
GP
I1
GP
O9
GP
O1
0G
PO
11
GP
O1
2
GP
O2
5G
PO
24
GP
O2
6
GP
I16
GP
I18
GP
I4
GP
O1
3G
PI5
GP
O15
GP
O21
US
BP
1-27
OC
0#27
US
BP
0-27
US
BP
0+27
US
BP
1+27
IRQ
0
PW
RO
K3P
37,
18
DR
Q[3
:0]
17,2
8,29
DR
Q[7
:5]
17,2
9
IRQ
317
,28,
29,3
2
IRQ
517
,25,
28,2
9,32
IRQ
717
,28,
29,3
2
IRQ
917
,25,
29
DA
CK
2#28
,29
DA
CK
3#28
,29
TC
28,2
9,32
FE
RR
#4,
17H
_IG
NN
E#
4,17
H_I
NT
R4,
17K
BD
A20
GA
TE
28
ST
PC
LK#
4,17
H_A
20M
#4,
17K
BD
RS
T#
28
US
BC
LK14
RE
F0
14,2
9,32
PC
I_C
LK1
14
DA
CK
5#29
DA
CK
6#29
DA
CK
7#29
DA
CK
0#28
,29
BIO
SC
S#
33
TH
ER
M_A
LER
T#
4
OC
1#27
IRQ
1411
,17,
28,2
9
DA
CK
1#28
,29
SM
BD
AT
A4,
12,1
3,14
,15,
17
PX
4_S
MI#
4
PIR
QA
#15
,16,
17,2
1
SM
BA
LER
T#
15
H_I
NIT
#4,
17
IRQ
1017
,25,
28,2
9,32
IRQ
1117
,29,
32
PIR
QB
#16
,17
IRQ
417
,25,
28,2
9,32
IRQ
1217
,28,
29
IRQ
1517
,25,
28,2
9
XD
IR#
9
IRQ
117
,28
H_N
MI
4,17
SLP
#4,
17
IRQ
617
,28,
29,3
2
SM
BC
LK4,
12,1
3,14
,15,
17
PIR
QD
#16
,17,
25
XO
E#
9
PW
RB
TN
#18
RS
MR
ST
#19
SP
KR
19
CP
U_S
TO
P#
14P
CI_
ST
OP
#14
SU
SA
#14
PIR
QC
#16
,17,
23,2
5
PW
RO
N#
19
V3P
3
V3P
3SU
S
V3P
3
V3P
3SU
S
V3P
3SU
S
V3P
3
V5P
0
V3P
3
V3P
3SU
S
V3P
3
V3P
3
V3P
3
V3P
3V
3P3
V3P
3V
3P3
V3P
3
V3P
3
V3P
3V
3P3
V3P
3V
3P3
V3P
3
V3P
3SU
S
V3P
3SU
SV
3P3
V3P
3SU
SV
3P3S
US
V3P
3
V3P
3SU
S
V3P
3SU
SV
3P3S
US
R18
7
1K
R17
9
4.7K
R18
0
4.7K
R17
34.
7K
R17
8
4.7K
JP1
HE
AD
ER
15X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
R18
2
4.7K
D3
200m
A
31
2
D4
200m
A
31
2
R18
3
4.7K
R18
1
4.7K
BT
1
R17
14.
7K
U6A
74H
CT
14D
12
R18
4
4.7K
R17
2
10K
R18
8
1K
J1 JUM
PE
R
1
2
3R
167
4.7K
R16
6
4.7K
R17
4
1K
C83
.1uF
16V
R16
4
4.7K
R16
5
4.7K
R16
3
4.7K
R18
54.
7K
R18
64.
7K
C84
1uF
10V
DMA/IRQ
SIGNALS
USB
SIGNALS
POWER
MGMT.
CPU
INTERFACE
SYSTEM
X-BUS
PIIX4
U4B
PIIX
4
D10
K5
E7
T6
E13
N16
J9R15J10
R16
J11
P15
J12
J4
K9
R7
K10
R6
K11
G6
K12
N18
L9
F14L10
F15
L11F5 L12
G4
M9E16M10
E11
M11E12
M12
N3
J5
E9
F6
M16
P19
M5
R5
T19
R1
G5
L2 F2
V20
F3
J3 F4
R2
L5
K20
K3
K16
K4
W20
H1
T17
H4
M19
H5
T18
G3
V19
H19
H20
U19
U18
M17
K19
U20
L17
P16
U6
T20
L18
R19
L19
N17
J20
P18
P1
L20
U14
P20 J1
8T9
N20
M20V
2
M18
K17W9
V18
R17W6
R18U
8
U5
V8
Y10 Y
8
Y16
Y20V5
U1
U16
U12T15
W13
U17 T13
V16
V14
W17 Y14
W15 M
1N
2P
3N
1P
2P
4
V10 J1
7H
18K
18 J19
R3
R4
P5
G1
M4
M3
M2 L1 K2
K1
R20
N19 L16
P17 L3
V11
D11
F1
H2
G2
H3
J1 J2 J16
N4
L4 N5
VSS
VCCSUSB
VSS
VCCP
VSS
VCCSUS
VSSVCCVSS
VCCSUS
VSS
VCCP
VSS
N/C
VSS
VCCP
VSS
VCC
VSS
VCCP
VSS
N/C
VSS
VCCPVSS
VCC
VSSVCCP VSS
GP
O0
VSSVCCPVSS
VCC
VSSVCCP
VSS
N/C
VSSUSB
VCCP
VCC
N/C
GP
I1
N/C
N/C
GP
O8
GP
O17
/CP
U_S
TP
#
GP
O27
GP
I13
GP
O28
EX
TS
MI#
GP
O29
/IRQ
9Out
GP
I14
GP
O30
GP
O18
/PC
I_S
TP
#
GP
I15
SLP
#
GP
I16
GP
O19
/ZZ
GP
I17
SU
SA
#
GP
I18
GP
O20
/SU
S_S
TA
T1#
GP
I19
CP
UR
ST
GP
I20
GP
O21
/SU
S_S
TA
T2#
GP
I21
GP
O15
/SU
SB
#
GP
I8/H
CT
#
IRQ
0/G
P01
4
GP
I9/B
AT
LOW
#
GP
O16
/SU
SC
#
RS
MR
ST
#
FE
RR
#
PW
RB
T#
IGN
NE
#
GP
I10/
LID
DR
EQ
1
SM
BD
AT
A
INIT
SM
BC
LK
INT
R
GP
I11/
SM
BA
LER
T#
IRQ
1G
PI1
2/R
I#A
A20
GA
TE
#N
MI
DA
CK
0#
SM
I#S
TP
CLK
#
IRQ
3
RC
IN#
A20
M#
DR
EQ
2
PW
RO
KS
PK
R
IRQ
4
TE
ST
#C
ON
FIG
1
DA
CK
1#
CO
NF
IG2
IRQ
5
DR
EQ
3
IRQ
6
DA
CK
2#
IRQ
7
DR
EQ
5
IRQ
8/G
PI6
DA
CK
3#
IRQ
9
DR
EQ
6
IRQ
10
DA
CK
5#
IRQ
11
DR
EQ
7
IRQ
12
DA
CK
6#
IRQ
14
DA
CK
7#
IRQ
15
DR
EQ
0
RE
QA
#/G
PI2
RE
QB
#/G
PI3
RE
QC
#/G
PI4
GN
TA
#/G
PO
9G
NT
B#/
GP
O10
GN
TC
#/G
PO
11
TC
AP
ICA
CK
#/G
PO
12A
PIC
CS
#/G
PO
13A
PIC
RE
Q#/
GP
15
SE
RIR
G/G
PI7
PIR
QA
#P
IRQ
B#
PIR
QC
#P
IRQ
D#
XO
E#/
GP
O23
XD
IR#/
GP
O22
BIO
SC
S#
RT
CA
LE/G
PO
25R
TC
CS
#/G
PO
24K
BC
CS
#/G
PO
26
RT
CX
2R
TC
X1
VB
AT
SU
SC
LK48
Mhz
OS
CP
CIC
LK
US
BP
1+U
SB
P1-
US
BP
0+U
SB
P0-
OC
0#O
C1#
VR
EF
MC
CS
#
PC
S0#
PC
S1#
R16
9
4.7K
R17
0
4.7K
R16
8
4.7K
D2
200m
A3
1
2
R15
94.
7KR
160
4.7K
R16
1
4.7K
R16
2
4.7K
Y1
32.7
68kH
z
C86
22pF
50V
C85
22pF
50V
R17
6
4.7K
R17
7
4.7K
R17
5
4.7K
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Drive Activity
6/16/1999
IDE Interface
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1134
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PD
D7
PD
D5
PD
D3
PD
D1
PD
D6
PD
D4
PD
D2
PD
D0
PD
D8
PD
D9
PD
D10
PD
D11
PD
D12
PD
D13
PD
D14
PD
D15
PD
A2
PD
A0
PD
A1
RS
TD
RV
9,28
,29,
32
PD
D[1
5:0]
9
PD
RE
Q9
PIO
RD
Y9
PD
IOW
#9
PD
IOR
#9
PD
DA
CK
#9
PD
A[2
:0]
9
PC
S3#
9
PC
S1#
9
IRQ
1410
,17,
28,2
9
V5P
0
V5P
0
V5P
0
V5P
0
Q1
2N70
021
3 2
R20
233
R20
433
R20
633
R20
833
R19
233
R19
133
R20
133
R19
833
R19
633
R19
433
R20
733
R20
533
R20
333
R21
433
R21
033
R20
933
R21
633
R21
533
R21
133
R21
333
R21
833
R19
333
R19
533
R22
1
75 R22
2
75
R20
0
1K
R22
0
5.6K
R19
733
R19
933
R21
247
R18
9
1K
J2 IDE
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
D5 RE
DQ
2
2N70
021
3 2
R22
3
10K
R21
933
R21
733
R19
010
K
A A
B B
C C
D D
E E
44
33
22
11
Memory Socket 0
DIM
M S
OC
KE
T 0
SLA
VE
AD
DR
ES
S= 1
0100
00b
**N
OTE
ON
ALL
DIM
M S
OC
KE
TS**
Pin
147
sho
uld
be p
ulle
d to
a h
igh
stat
eto
acc
omm
odat
e re
gist
ered
DIM
Ms.
A
Cel
eron
Pro
cess
or T
T S
ampl
e D
esig
n
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1234
Mon
day,
Aug
ust 0
9, 1
999
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DC
LK13
MA
A1
MA
A4
MD
40
MD
46
MD
18
MD
32
MD
17
DQ
MA
2
MA
A5
MA
A6
MD
9
MD
38M
D39
MD
19M
D20
MD
2
MD
7
DQ
MA
1
DQ
MA
3
MA
A9
MA
A1
3
MD
12
MD
36M
D37
MD
26
MD
5
ME
CC
4
MD
21
MD
49
MD
57M
D58
MA
A2
MD
13
MD
33
MD
54
ME
CC
0
ME
CC
7
ME
CC
1
DC
LK15
MD
48
MD
0
MD
10M
D25
MD
4
MD
6
DQ
MA
4D
QM
A5
MA
A7
MD
35
MD
42
MD
47
MD
22M
D23
MD
51
DQ
MA
0
ME
CC
2
MA
A1
0
MA
A1
1M
AA
12
MD
27M
D28
MD
29M
D30
MD
52
MD
61
ME
CC
5
MD
45
MD
56
MD
62M
D63
MA
A0
MA
A3
MD
34
MD
43M
D44
MD
60
DC
LK12
DC
LK14
MD
11
MD
14M
D15
MD
1
DQ
MA
6D
QM
A7
MA
A8
MD
16
MD
50
MD
3
ME
CC
3
MD
41
MD
24
MD
53
MD
55
MD
59
MD
8
MD
31
ME
CC
6
DC
LK[1
5:0]
13,1
4
MD
[63:
0]8,
13
MA
A[1
3:0]
8,13
DQ
MA
[7:0
]8,
13
ME
CC
[7:0
]13
SM
BD
AT
A4,
10,1
3,14
,15,
17S
MB
CLK
4,10
,13,
14,1
5,17
CS
B0#
8C
SB
1#8
SC
AS
_A#
8,13
SR
AS
_A#
8,13
WE
_A#
8,13
CS
A1#
8C
SA
0#8
CK
E0
4,10
,13,
14,1
5,17
CK
E1
4,10
,13,
14,1
5,17
V3P
3V
3P3
V3P
3
SD
RA
M D
IMM
J3
6
2640
2 3 4 5 7 8 9 10 11
22
24 25
105
106
108
10928 29 46 47
4190102
124
112
18
2332
8596107116
110
27 111
30 114
115
31 48
42 125
79 163
80
164
8161
63147
50 51
52 53
112
113
130
131
45 129
128
132 44
4354646878
127138148152162
62146
49597384
143157168
133
33 117 34 118 35 119 36 120 37 121 38 122 3912313 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100
101
103
104
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
126
21134
135
136
137
165
166
167
82 83
145
VCC
VCCVCC
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8
CB
1
NC
NC
CB
4C
B5
NC
NC
DQ
MB
0D
QM
B1
DQ
MB
2D
QM
B3
VCCVCCVCC
VCC
VSSVSS
VCC
VSSVSS
VSSVSSVSSVSS
VCC
/WE
0/C
AS
/S0
/S1
/RA
S
NC
NC
CK
0C
K1
CK
2C
K3
NC
NC
NC
NC
CK
E1
RE
GE
NC
NC
CB
2C
B3
DQ
MB
4D
QM
B5
DQ
MB
6D
QM
B7
/S2
/S3
CK
E0
A13
NC
VSSVSSVSSVSSVSS
VSSVSSVSSVSSVSS
NC
NC
VCCVCCVCCVCC
VCCVCCVCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
(A
P)
BA
0B
A1
A11
DQ
9D
Q10
DQ
11D
Q12
DQ
13D
Q14
DQ
15
DQ
32D
Q33
DQ
34D
Q35
DQ
36D
Q37
DQ
38D
Q39
DQ
40D
Q41
DQ
42D
Q43
DQ
44D
Q45
DQ
46D
Q47
DQ
16D
Q17
DQ
18D
Q19
DQ
20D
Q21
DQ
22D
Q23
DQ
24D
Q25
DQ
26D
Q27
DQ
28D
Q29
DQ
30D
Q31
DQ
48D
Q49
DQ
50D
Q51
DQ
52D
Q53
DQ
54D
Q55
DQ
56D
Q57
DQ
58D
Q59
DQ
60D
Q61
DQ
62D
Q63
A12
CB
0
NC
NC
CB
6C
B7
SA
0S
A1
SA
2
SD
AS
CL
NC
A A
B B
C C
D D
E E
44
33
22
11
DIM
M S
OC
KE
T 1
SLA
VE
AD
DR
ES
S =
101
0001
b
**N
OTE
ON
ALL
DIM
M S
OC
KE
TS**
Pin
147
sho
uld
be p
ulle
d to
a h
igh
stat
eto
acc
omm
odat
e re
gist
ered
DIM
Ms.
Memory Socket 1
A
Cel
eron
Pro
cess
or T
T S
ampl
e D
esig
n
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1334
Mon
day,
Aug
ust 0
9, 1
999
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
MD
0M
D16
MD
1M
D17
MD
2M
D18
MD
3M
D19
MD
4M
D20
MD
5M
D21
MD
6M
D22
MD
7M
D23
MD
8M
D24
MD
9M
D25
MD
10M
D26
MD
11M
D27
MD
12M
D28
MD
13M
D29
MD
14M
D30
MD
15M
D31
MD
32M
D48
MD
33M
D49
MD
34M
D50
MD
35M
D51
MD
36M
D52
MD
37M
D53
MD
38M
D54
MD
39M
D55
MD
40M
D56
MD
41M
D57
MD
42M
D58
MD
43M
D59
MD
44M
D60
MD
45M
D61
MD
46M
D62
MD
47M
D63
ME
CC
1M
EC
C2
ME
CC
3M
EC
C4
ME
CC
5M
EC
C6
ME
CC
7
ME
CC
0
MA
A0
MA
A1
MA
A2
MA
A3
MA
A4
MA
A5
MA
A6
MA
A7
MA
A8
MA
A9
MA
A1
0M
AA
13
MA
A1
1M
AA
12
DC
LK8
DC
LK10
DC
LK11
DC
LK9
DQ
MA
7
DQ
MA
2D
QM
A1
DQ
MA
0
DQ
MA
5D
QM
A6
DQ
MA
4D
QM
A3
SM
BD
AT
A4,
10,1
2,14
,15,
17S
MB
CLK
4,10
,12,
14,1
5,17
CS
B2#
8C
SB
3#8
WE
_A#
8,12
SC
AS
_A#
8,12
SR
AS
_A#
8,12
DC
LK[1
5:0]
12,1
4
DQ
MA
[7:0
]8,
12
MA
A[1
3:0]
8,12MD
[63:
0]8,
12
CS
A3#
8C
SA
2#8
ME
CC
[7:0
]12
CK
E2
4,10
,13,
14,1
5,17
CK
E3
4,10
,13,
14,1
5,17
V3P
3V
3P3
V3P
3
V3P
3
SD
RA
M D
IMM
J4
6
2640
2 3 4 5 7 8 9 10 11
22
24 25
105
106
108
10928 29 46 47
4190102
124
112
18
2332
8596107116
110
27 111
30 114
115
31 48
42 125
79 163
80
164
8161
63147
50 51
52 53
112
113
130
131
45 129
128
132 44
4354646878
127138148152162
62146
49597384
143157168
133
33 117 34 118 35 119 36 120 37 121 38 122 3912313 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100
101
103
104
55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
126
21134
135
136
137
165
166
167
82 83
145
VCC
VCCVCC
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8
CB
1
NC
NC
CB
4C
B5
NC
NC
DQ
MB
0D
QM
B1
DQ
MB
2D
QM
B3
VCCVCCVCC
VCC
VSSVSS
VCC
VSSVSS
VSSVSSVSSVSS
VCC
/WE
0/C
AS
/S0
/S1
/RA
S
NC
NC
CK
0C
K1
CK
2C
K3
NC
NC
NC
NC
CK
E1
RE
GE
NC
NC
CB
2C
B3
DQ
MB
4D
QM
B5
DQ
MB
6D
QM
B7
/S2
/S3
CK
E0
A13
NC
VSSVSSVSSVSSVSS
VSSVSSVSSVSSVSS
NC
NC
VCCVCCVCCVCC
VCCVCCVCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
(A
P)
BA
0B
A1
A11
DQ
9D
Q10
DQ
11D
Q12
DQ
13D
Q14
DQ
15
DQ
32D
Q33
DQ
34D
Q35
DQ
36D
Q37
DQ
38D
Q39
DQ
40D
Q41
DQ
42D
Q43
DQ
44D
Q45
DQ
46D
Q47
DQ
16D
Q17
DQ
18D
Q19
DQ
20D
Q21
DQ
22D
Q23
DQ
24D
Q25
DQ
26D
Q27
DQ
28D
Q29
DQ
30D
Q31
DQ
48D
Q49
DQ
50D
Q51
DQ
52D
Q53
DQ
54D
Q55
DQ
56D
Q57
DQ
58D
Q59
DQ
60D
Q61
DQ
62D
Q63
A12
CB
0
NC
NC
CB
6C
B7
SA
0S
A1
SA
2
SD
AS
CL
NC
A A
B B
C C
D D
E E
44
33
22
11
Stuff only to enable
spread spectrum
clocking.
Clock & Clock Buffers
6/16/1999
>>
Trace lenghts between crystal and chip must be matched and less than 500
mils. Trace widths must be 100 mils minimum.
Trace lenghts between capacitors and crystal be matched and less than
300 mils. Trace widths must be 100 mils minimum. Capacitor connections
to GND go directly to plane.
>>
Trace must be routed directly over a GND plane.
>>
>>
Do not route any other traces under the clock generator circuitry.
Stuff only to enable
stopping of clocks
DCLKn should all be matched in
length within 50 mils.
DCLKWR should be 2.5 inches
longer than DCLKn.
Do not route any other traces under the clock generator circuitry.
>>
>>
Trace must be routed directly over a GND plane.
>>
Clock chip can support up to four DIMMs
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Dei
sgn
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1434
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DC
KLR
0
DC
KLR
2D
CK
LR3
DC
KLR
10D
CK
LR11
DC
LKB
XF
B_R
DC
KLR
4D
CK
LR5
DC
KLR
12D
CK
LR13
DC
KLR
14D
CK
LR15
DC
KLR
6D
CK
LR7
DC
KLR
8D
CK
LR9
DC
LK9
DC
KLR
1
DC
LK4
DC
LK6
DC
LK7
DC
LK1
DC
LK10
DC
LK11
DC
LK5
DC
LK2
DC
LK13
DC
LK0
DC
LK8
DC
LK15
DC
LK12
DC
LK14
DC
LK3
PC
I_C
LK2
15
PC
I_C
LK5
25P
CI_
CLK
416
PC
I_C
LK3
16
PC
I_C
LK1
10
CP
U_B
CLK
4B
X_H
CLK
7
US
BC
LK10
RE
F0
10,2
9,32
RE
F1
28
PIC
CLK
4
100/
66#
4P
CI_
CLK
623
PC
I_C
LK7
PC
I_C
LK0
7C
PU
_ST
OP
#10
PC
I_S
TO
P#
10S
US
A#
10
DC
LK[1
5:0]
12,1
3
DC
LKW
R8
SM
BD
AT
A4,
10,1
2,13
,15,
17S
MB
CLK
4,10
,12,
13,1
5,17
BX
DC
LKO
8
V2P
5
V2P
5
V3P
3V
3P3
V2P
5
V3P
3
V3P
3
V3P
3V
3P3
V3P
3 V3P
3
V3P
3
V2P
5
V3P
3
V3P
3V
3P3
V2P
5
V3P
3
V3P
3V
3P3
V3P
3
V2P
5
V2P
5
V3P
3
V3P
3
V3P
3
V2P
5
V3P
3
C10
30.
01uF
50V
R25
40
R25
00
U8
CY
2318
NZ
4
6
5
3
8
10
9 13
15
14
7
17
19
18 31
22
32
12
35
26
36 40
27
41
16
44
30
45 21
34
28
20
3943
232933374246
11 38 24 251 2 47 48
SD
RA
M0
VSS
SD
RA
M1
VDD
SD
RA
M2
VSS
SD
RA
M3
SD
RA
M4
VSS
SD
RA
M5
VDD
SD
RA
M6
VSS
SD
RA
M7
SD
RA
M8
VSS
SD
RA
M9
VDD
SD
RA
M10
VSS
SD
RA
M11
SD
RA
M12
VSS
SD
RA
M13
VDD
SD
RA
M14
VSSSD
RA
M15
SD
RA
M16
VSS
SD
RA
M17
VDD
VSSVSS
VDDVDDVDDVDDVDDVDD
CLK
_IN
OE
SD
AT
AS
CLK
NC
NC
NC
NC
R25
10
R23
60
R23
40
R23
30
C10
40.
01uF
50V
R25
20
R25
50
R24
233
R24
333
R25
60
C10
50.
01uF
50V
R25
70
R25
80
R25
90
R26
00
R24
9
0
TP
31
C10
633
uF
R26
10
R26
20
R25
347
R26
30
C88
.01u
F16
V
C94
22uF
25V
C90
.01u
F16
V
C91
.01u
F16
V
C92
.01u
F16
V
R24
133
C93
.01u
F16
V
C89
.01u
F16
V
R22
4
10K
R22
6
10K
R22
8
10K
R22
9
10K
R23
0
10K
R22
7
10K
R26
40
C99
10pF
50V
R23
233
R23
533
C98
10pF
50V
R23
733
R23
833
R23
933
R23
133
R24
033
R24
733
R24
433
R24
633
C96
.01u
F16
V
C95
.01u
F16
V
U7
CY
2280
15 39
30
216
48
31
46
12
41
1
37
18
33
29
19 20
7
24
2
32
40
34
47
38
8
43
39 1036 1135 13 14 16 17 22 23 45 44
2827 26 25 4 542
VDDPCI VSSVDDPCI
CP
U_S
TO
P#
VDDUSBVSS
VDDREF
PC
I_S
TO
P#
VDDAPIC
VSS
VDDCPU
RE
F0
VDDCPU
VSS
AVDD
PW
R_D
WN
#
AVDD VSS
PC
ICLK
_F
VSS
RE
F1
VSS
CP
UC
LK0
VSS
RE
F2
VSS
PC
I_C
LK1
VSS
CP
UC
LK1
PC
I_C
LK2
CP
UC
LK2
PC
I_C
LK3
CP
UC
LK3
PC
I_C
LK4
PC
I_C
LK5
PC
I_C
LK6
PC
I_C
LK7
US
BC
LK0
US
BC
LK1
AP
IC0
AP
IC1
SE
L_S
S#
SE
L0S
EL1
SE
L100
XT
ALI
NX
TA
LOU
T
RE
SE
RV
ED
R24
833
R26
50
C87
22uF
25V
C97
.01u
F16
V
R22
5
1K
Y2
14.3
18M
Hz
R24
5
TB
D
C10
00.
01uF
50V
R26
60
R26
70
C10
10.
01uF
50V
C10
20.
01uF
50V
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Link Integrity
100MBit
6/16/1999
Ethernet Port
>>SMBus address is determined by serial EPROM.
Trace lenghts between crystal and chip must be matched and less than 500
mils. Trace widths must be 100 mils minimum.
>>
Trace lenghts between capacitors and crystal be matched and less than
300 mils. Trace widths must be 100 mils minimum. Capacitor connections
to GND go directly to plane.
>>
>>
Trace must be routed directly over a GND plane.
Do not route any other traces under the clock circuitry.
>>
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1534
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
C/B
E#3
C/B
E#1
C/B
E#2
C/B
E#0
AD
1
AD
10
AD
7
AD
17
AD
9
AD
14A
D13
AD
0
AD
16
AD
4
AD
15
AD
17
AD
12
AD
21
AD
18
AD
28
AD
30
AD
26
AD
31
AD
25
AD
3
AD
11
AD
19
AD
24
AD
20
AD
8
AD
6
AD
2
AD
29
AD
23
AD
27
AD
22
AD
5
AD
[31:
0]7,
9,16
,23,
25
C/B
E#[
3:0]
7,9,
16,2
3,25
PR
EQ
2#7,
17
PC
I_C
LK2
14P
IRQ
A#
10,1
6,17
,21
FR
AM
E#
7,9,
16,1
7,23
,25
TR
DY
#7,
9,16
,17,
23,2
5IR
DY
#7,
9,16
,17,
23,2
5
DE
VS
EL#
7,9,
16,1
7,23
,25
SE
RR
#7,
9,16
,17,
21,2
3,25
PA
R7,
9,16
,17,
23,2
5
PG
NT
2#7,
17
PC
IRS
T#
7,9,
16
ST
OP
#7,
9,16
,17,
23,2
5
SM
BD
AT
A4,
10,1
2,13
,14,
17S
MB
ALE
RT
#10
SM
BC
LK4,
10,1
2,13
,14,
17
V5P
0
V5P
0
V3P
3
V3P
3V
3P3
V3P
3V
3P3
V3P
3V
3P3
V3P
3V
3P3
V3P
3
V3P
3
V3P
3
V3P
3
D7
GR
EE
N
C12
3
22pF
50V
C12
2
22pF
50V
R28
6
1K
R28
5
1K
R28
8
1K
R28
7
1KC12
1
.1uF
16V
C11
8
.01u
F16
V
C10
9
.1uF
16V
C10
7
4.7u
F10
V
R28
9
1K
Y3
25M
Hz
R29
0
110
R27
1
50
R27
0
50
C11
7
.01u
F16
V
C12
0
1000
pF30
00V
C10
8
4.7u
F10
V
R28
01K
R28
1
110
C11
0
.1uF
16V
C11
9
.01u
F16
V
U10
123 4
5
76
8
CS
SK
DI
DO
GND
NC
OR
G
VCC
R27
3
75
R28
3
575
C11
2
.1uF
16V
C11
1
.1uF
16V
J5
RJ4
5
1 2 3 4 5 6 7 8 9 10
TD
PT
DN
RD
PS
HS
HR
DN
SH
SH
CH
AS
SIS
CH
AS
SIS
R27
6
75
R27
2
75
R27
7
75
R28
4
600
C11
4
.1uF
16V
C11
3
.1uF
16V
R27
4
75
R27
5
75
TP
41
C11
6
.01u
F16
V
TP
61
R28
2
1K
8255
9
U9
N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3 L1 L2 K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8
M4 L3 F3
C4
C3 J3 G1
H2
C2
F2
G3 F1
H1
A4
H3 J2 A2 J1 C8
A9
A6
B9
G2
N11
P11
C13
C14
E13
E14
F14
F13
F12
G12
H14
H13
H12
J14
J13
J12
K14
L14
L13
L12
M14
M13
P13
N13
M12
M11
P10
N10
M10
P9
P7
A12
C11
B11
C5
N9
M8
M9
A10
C9
B10
A13
B12
D12
D13
D14
C12
B13
B14
G5G6H5H6H7H8J5J6J7J8J9J10E12K5K6K7K8K9K10J11K4K11L4L5L9L10
E5E6E7E8E9E10F5F6F7F8F9F10G7G8G9G10H9H10D4D5D6D7D8D11E4E11F4F11H11L6L11G11
A3A7E1K3N6P2G13K13N8P12A11
B3B7E2K2M6N1G14K12N12P8C10
A1
A14
D9
D10
G4
H4
J4 L7 L8 P1
P14
N14
AD
0A
D1
AD
2A
D3
AD
4A
D5
AD
6A
D7
AD
8A
D9
AD
10A
D11
AD
12A
D13
AD
14A
D15
AD
16A
D17
AD
18A
D19
AD
20A
D21
AD
22A
D23
AD
24A
D25
AD
26A
D27
AD
28A
D29
AD
30A
D31
C/B
E0#
C/B
E1#
C/B
E2#
C/B
E3#
RE
Q#
GN
T#
CLK
INT
AR
ST
FR
AM
E#
TR
DY
#IR
DY
#S
TO
P#
IDS
EL
DE
VS
EL#
PE
RR
#S
ER
R#
PA
R
CLK
RU
N#
ALT
RS
T#
PM
E#
ISO
LAT
E#
VIO
X1
X2
TD
PT
DN
RD
PR
DN
FLD
0F
LD1
FLD
2F
LD3
FLD
4F
LD5
FLD
6F
LD7
FLA
0/P
CIM
OD
E#
FLA
1/A
UX
PW
RF
LA2
FLA
3F
LA4
FLA
5F
LA6
FLA
7
FLA
9/M
RS
TF
LA10
FLA
11/M
INT
FLA
12/M
CN
TS
MF
LA13
/EE
DI
FLA
14/E
ED
0F
LA15
/EE
SK
FLA
16
EE
CS
LILE
D#
AC
TLE
D#
SP
EE
DLE
D#
CS
TS
CH
G
FLC
SF
LOE
#F
LWE
#
SM
BC
KS
MB
DS
MB
ALR
T#
TE
ST
TO TI
TE
XE
CT
CK
VR
EF
RB
IAS
100
RB
IAS
10
VCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCCVCC
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
VCCPPVCCPPVCCPPVCCPPVCCPPVCCPPVCCPLVCCPLVCCPLVCCPLVCCPT
VSSPPVSSPPVSSPPVSSPPVSSPPVSSPPVSSPLVSSPLVSSPLVSSPLVSSPT
A1
A14 D
9D
10 G4
H4 J4 L7 L8 P1
P14
FLA
8/IO
CH
RD
Y
R26
8
50
R26
9
50
TP
51
R27
81K
L2
1 23 4 5 6 78910111213141516
R27
9
110
C11
5
.1uF
16V
D6
OR
AN
GE
A A
B B
C C
D D
E E
44
33
22
11
PCI SLOT 0
PCI SLOT 1
PCI Connectors
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1634
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PC
I_T
DI
PC
I_T
MS
PC
I_T
CLK
PC
I_T
RS
T
AC
K64
#
PIR
QD
#
PC
I_T
CLK
LOC
K#
IRD
Y#
DE
VS
EL#
PIR
QB
#
PC
I_T
MS
PA
R
FR
AM
E#
PC
IB2
SD
ON
E
PIR
QA
#
PC
IRS
T#
ST
OP
#
SB
O#
PIR
QC
#
TR
DY
#
PC
I_T
DI
RE
Q64
#
PC
I_T
RS
T
AD
17
AD
13
PC
I_T
MS
AD
11
AD
16
AD
28
AD
12
AD
24
AD
14
AD
28
AD
22
AD
7
AD
4
AD
9
AD
29
AD
6A
D7
AD
24
AD
31
AD
21
AD
4
AD
0
AD
8
PC
IA2
AD
9
AD
1
AD
27
AD
29
AD
15
AD
25
AD
15
AD
13
AD
20
AD
30
AD
6
AD
8
AD
11
AD
2A
D1
AD
10
AD
26
AD
18
AD
25
AD
3
AD
29
AD
28
AD
2
AD
19A
D18
AD
5
AD
17
AD
22
AD
27
AD
21
PC
I_T
CLK
AD
23
AD
5
AD
23
AD
31A
D30
AD
14
AD
16
AD
0
PC
I_T
DI
AD
26
AD
20
AD
12A
D10
AD
19
AD
3
PC
I_T
RS
T
C/B
E#0
C/B
E#1
C/B
E#3
C/B
E#3
C/B
E#1
C/B
E#0
C/B
E#[
3:0]
C/B
E#2
C/B
E#2
PE
RR
#
SE
RR
#
DE
VS
EL#
7,9,
15,1
7,23
,25
IRD
Y#
7,9,
15,1
7,23
,25
PC
I_C
LK3
14
PR
EQ
0#7,
17
PIR
QA
#10
,15,
17,2
1P
IRQ
C#
10,1
7,23
,25
SE
RR
#7,
9,15
,17,
21,2
3,25
PE
RR
#17
,21,
25
C/B
E#[
3:0]
7,9,
15,2
3,25
AD
[31:
0]7,
9,15
,23,
25
LOC
K#
7,17
AC
K64
#17
PG
NT
1#7,
17
PC
IRS
T#
7,9,
15
PG
NT
0#7,
17
FR
AM
E#
7,9,
15,1
7,23
,25
TR
DY
#7,
9,15
,17,
23,2
5
ST
OP
#7,
9,15
,17,
23,2
5
SD
ON
E17
SB
O#
17
PC
I_C
LK4
14
PIR
QB
#10
,17
PIR
QD
#10
,17,
25
PR
EQ
1#14
RE
Q64
#17
PA
R7,
9,15
,17,
23,2
5
V3P
3V
5P0
V3P
3V
5P0
V5P
0
V5P
0
V3P
3V
3P3
V3P
3V
12P
0V
12P
0
V5P
0
V-1
2P0
V-1
2P0
V5P
0
V3P
3
V5P
0
AD
[31:
0]
R29
3
4.7K
R29
2
4.7K
R29
5
220
R29
6
220
R29
4
4.7K
R29
1
4.7K
C14
20.
01uF
C13
010
uF
C14
30.
01uF
C14
40.
01uF
C14
50.
01uF
C13
20.
1uF
C13
10.
1uF
C13
310
uFC
139
10uF
C12
410
uFC
138
0.01
uFC
134
0.1u
FC
136
0.1u
FC
141
0.1u
FC
140
0.1u
FC
126
0.1u
FC
128
0.01
uFC
129
0.01
uFC
125
0.1u
FC
127
0.1u
F
J7 PC
I Con
n
A8
A1
A9
A10
A2
B1
A3
A4
B60
A5
A6
B36
A7
A11
B61
A12
A13
B2
A14
A15
B37
A16
A17
B3
A18
B38
A19
B62
A20
B4
A21
B39B
5
B40B
6
B41B
7
B42B
8
B43B
9
B44
A22
B10
A23
B45
A24
B11
A25
B12
A26
B13
A27
B14
A28
B46
A29
B15
A30
B16
A31
B47
A32
B17
A33
B18
A34
B48
A35
B19
A36
B20
A37
B49
A38
B21
A39
B22
A40
B52
A41
B23
A42
B24
A43
B53
A44
B25
A45
B26
A46
B54
A47
B27
A48
B28
A49
B55
A52
B29
A53
B30
A54
B56
A55
B31
A56
B32
A57
B57
A58
B33
A59
B34
A60
B58
A61
B35
A62
B59
V5P
0
TR
ST
NC
V5P
0
V12
P0
V-1
2P0
TM
ST
DI
AC
K64
V5P
0IN
TA
V3P
3
INT
C
NC
V5P
0
GN
DG
ND
TC
K
NC
RS
T
DE
VS
EL
V5P
0G
NT
GN
D
GN
D
GN
D
NC
V5P
0
AD
[30]
TD
O
V3P
3
LOC
K
V5P
0
PE
RR
V5P
0
V3P
3
INT
B
SE
RR
INT
D
V3P
3
PR
SN
T1
C/B
E1
AD
[28]
NC
AD
[26]
AD
[14]
GN
D
PR
SN
T2
AD
[24]
GN
D
IDS
EL
GN
D
V3P
3
NC
AD
[22]
GN
D
AD
[20]
GN
D
GN
D
CLK
AD
[18]
AD
[12]
AD
[16]
GN
D
V3P
3
RE
Q
FR
AM
E
AD
[10]
GN
D
V5P
0
TR
DY
AD
[31]
GN
D
GN
D
ST
OP
AD
[29]
V3P
3
GN
D
SD
ON
E
AD
[08]
SB
O
AD
[27]
GN
D
AD
[25]
PA
R
AD
[07]
AD
[15]
V3P
3
V3P
3
C/B
E3
AD
[13]
V3P
3
AD
[11]
AD
[23]
GN
D
GN
D
AD
[09]
AD
[05]
C/B
E0
AD
[21]
V3P
3
AD
[19]
AD
[06]
AD
[03]
AD
[04]
V3P
3
GN
D
AD
[17]
AD
[02]
GN
DA
D[0
0]
C/B
E2
V5P
0
GN
D
RE
Q64
AD
[01]
V5P
0
IRD
Y
V5P
0
V5P
0
J6 PC
I Con
n
A8
A1
A9
A10
A2
B1
A3
A4
B60
A5
A6
B36
A7
A11
B61
A12
A13
B2
A14
A15
B37
A16
A17
B3
A18
B38
A19
B62
A20
B4
A21
B39B
5
B40B
6
B41B
7
B42B
8
B43B
9
B44
A22
B10
A23
B45
A24
B11
A25
B12
A26
B13
A27
B14
A28
B46
A29
B15
A30
B16
A31
B47
A32
B17
A33
B18
A34
B48
A35
B19
A36
B20
A37
B49
A38
B21
A39
B22
A40
B52
A41
B23
A42
B24
A43
B53
A44
B25
A45
B26
A46
B54
A47
B27
A48
B28
A49
B55
A52
B29
A53
B30
A54
B56
A55
B31
A56
B32
A57
B57
A58
B33
A59
B34
A60
B58
A61
B35
A62
B59
V5P
0
TR
ST
NC
V5P
0
V12
P0
V-1
2P0
TM
ST
DI
AC
K64
V5P
0IN
TA
V3P
3
INT
C
NC
V5P
0
GN
DG
ND
TC
K
NC
RS
T
DE
VS
EL
V5P
0G
NT
GN
D
GN
D
GN
D
NC
V5P
0
AD
[30]
TD
O
V3P
3
LOC
K
V5P
0
PE
RR
V5P
0
V3P
3
INT
B
SE
RR
INT
D
V3P
3
PR
SN
T1
C/B
E1
AD
[28]
NC
AD
[26]
AD
[14]
GN
D
PR
SN
T2
AD
[24]
GN
D
IDS
EL
GN
D
V3P
3
NC
AD
[22]
GN
D
AD
[20]
GN
D
GN
D
CLK
AD
[18]
AD
[12]
AD
[16]
GN
D
V3P
3
RE
Q
FR
AM
E
AD
[10]
GN
D
V5P
0
TR
DY
AD
[31]
GN
D
GN
D
ST
OP
AD
[29]
V3P
3
GN
D
SD
ON
E
AD
[08]
SB
O
AD
[27]
GN
D
AD
[25]
PA
R
AD
[07]
AD
[15]
V3P
3
V3P
3
C/B
E3
AD
[13]
V3P
3
AD
[11]
AD
[23]
GN
D
GN
D
AD
[09]
AD
[05]
C/B
E0
AD
[21]
V3P
3
AD
[19]
AD
[06]
AD
[03]
AD
[04]
V3P
3
GN
D
AD
[17]
AD
[02]
GN
DA
D[0
0]
C/B
E2
V5P
0
GN
D
RE
Q64
AD
[01]
V5P
0
IRD
Y
V5P
0
V5P
0
C13
50.
1uF
C13
70.
01uF
A A
B B
C C
D D
E E
44
33
22
11
PCI Pullups
ISA/PCI Pullups
ISA Pullups
Note IRQ8 Pull-up
is on PIIX4 page
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Dei
sgn
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1734
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SA
5
SD
9
DR
Q0
SA
13
SA
17
SA
19
LA2
1
DR
Q5
SA
4
SD
8
SA
0
SD
7
SD
12
SA
18
DR
Q3
SA
3
SA
16
SD
15
SA
12
DR
Q7
SD
6
SD
11
SA
10
SD
2
SA
2
SD
14
SA
1
SA
11
DR
Q2
SD
0
SD
5
DR
Q2
SA
9
LA1
8
LA2
0
DR
Q5
DR
Q1
SD
1
SD
10
SA
7
SD
13
SA
15
LA1
9
LA2
3
SD
4
DR
Q7
SA
8
DR
Q0
DR
Q3
DR
Q1
SA
6
LA1
7
DR
Q6
SA
14
LA2
2
SD
3
DR
Q6
PE
RR
#16
,21,
25
PIR
QB
#10
,16
PIR
QD
#10
,16,
25
PR
EQ
0#7,
16P
RE
Q1#
7,16
PR
EQ
2#7,
15P
RE
Q3#
7,25
SD
ON
E16
SB
O#
16R
EQ
64#
16A
CK
64#
16 PG
NT
3#7,
25
PG
NT
4#7,
23
PG
NT
2#7,
15
PH
OLD
A#
7,9 PG
NT
1#7,
16
PH
OLD
#7,
9
LOC
K#
7,16
PG
NT
0#7,
16
PR
EQ
4#7,
23
IRQ
710
,28,
29,3
2
IOC
HR
DY
9,28
,29
ST
OP
#7,
9,15
,16,
23,2
5
PA
R7,
9,15
,16,
23,2
5
DR
Q2
10,2
8,29
ME
MR
#9,
29,3
3IO
W#
9,28
,29,
32
IRQ
610
,28,
29,3
2
BA
LE29
DE
VS
EL#
7,9,
15,1
6,23
,25
PIR
QA
#10
,15,
16,2
1
IRQ
510
,25,
28,2
9,32
DR
Q0
10,2
8,29
DR
Q1
10,2
8,29
ME
MW
#9,
29,3
3
SB
HE
#9,
29
TR
DY
#7,
9,15
,16,
23,2
5
IRQ
1510
,25,
28,2
9
LA[2
3:17
]9,
29
IRQ
410
,25,
28,2
9,32
MA
ST
ER
16#
29
DR
Q7
10,2
9
SM
EM
R#
9,29
IRD
Y#
7,9,
15,1
6,23
,25
IRQ
1410
,11,
28,2
9
IRQ
310
,28,
29,3
2
RE
FR
ES
H#
9,29
SM
EM
W#
29
FR
AM
E#
7,9,
15,1
6,23
,25
IRQ
110
,28
IRQ
1210
,28,
29
DR
Q6
10,2
9
IOC
HK
#9,
29
SE
RR
#7,
9,15
,16,
21,2
3,25
PIR
QC
#10
,16,
23,2
5
IRQ
1110
,29,
32
DR
Q[3
:0]
10,2
8,29
ME
MC
S1
6#29
DR
Q5
10,2
9
IRQ
1010
,25,
28,2
9,32
SA
[19:
0]9,
28,2
9,32
,33
IOC
S16
#9,
29
DR
Q[7
:5]
10,2
9
IRQ
910
,25,
29
DR
Q3
10,2
8,29
ZE
RO
WS
#9,
29
SD
[15:
0]9,
28,2
9,32
IOR
#9,
28,2
9,32
V5P
0
V3P
3
V5P
0
RP
28
5.6K
18
27
36
45
RP
25
10K
18
27
36
45
RP
23
10K
18
27
36
45
RP
26
10K
18
27
36
45
RP
20
10K
18
27
36
45
RP
19
10K
18
27
36
45
RP
15
10K
18
27
36
45
RP
18
10K
18
27
36
45
RP
16
10K
18
27
36
45
RP
8
10K
18
27
36
45
RP
14
10K
18
27
36
45
RP
10
10K
18
27
36
45
RP
13
10K
18
27
36
45
RP
6
10K
18
27
36
45
RP
4
10K
18
27
36
45
RP
17
10K
18
27
36
45
R29
82.
7KR
297
2.7K
RP
27
10K
18
27
36
45
R30
110
K
RP
11
10K
18
27
36
45
RP
12
2.7K
18
27
36
45
RP
24
1K
18
27
36
45
RP
7
2.7K
18
27
36
45
RP
5
2.7K
18
27
36
45
RP
9
2.7K
18
27
36
45
RP
22
1K
18
27
36
45
RP
29
5.6K
18
27
36
45
RP
21
10K
18
27
36
45
C14
710
uF
R30
010
KR
299
10K
C14
6.1
uF
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
6/16/1999
Reset Circuitry
RESET AND POWER GOOD CIRCUITRY
ATX POWER SWITCH CIRCUITRY
POWER OK
S2
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1834
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PW
RB
TN
#10
PW
RO
K3P
37,
10
PW
RG
OO
D_2
P5
4
DB
RE
SE
T#
4
DC
PW
RO
K20
AT
X_P
W_O
K19
V3P
3SU
SV
3P3S
US
V1P
5
V5P
0
V2P
5
V5P
0
V5P
0
V5P
0
V5P
0
V3P
3
V3P
3
V2P
5
Q3
2N70
021
3 2
C15
1.1
uF16
VRE
SE
T S
WIT
CH
R30
5
10K
R30
9
4.64
K
R31
1
3.57
K
C14
9
1uF
10V
U11
A
74LC
T14
12
14 7
R31
3
4.53
K
C15
00.
1uF
R31
4
10K
S1
PO
WE
R S
WIT
CH
U13
LTC
1326
1 2 3 4
8 7 6 5
VC
C3
VC
C5
VC
CA
GN
D
PB
R#
SR
ST
#R
ST
#R
ST
Q5
2N70
021
3 2R30
8
1K
R31
0
10K
D8 R
ED
R30
4
75R30
3
75
R30
710
K
Q4
2N70
021
3 2
R30
2
4.7K
C14
8.1
uF16
V
U12
LTC
1326
1 2 3 4
8 7 6 5
VC
C3
VC
C5
VC
CA
GN
D
PB
R#
SR
ST
#R
ST
#R
ST
C15
30.
01uF
R30
6
2.2K
C15
210
uF
R31
22.
2K
A A
B B
C C
D D
E E
44
33
22
11
Note Cap Direction
Power Indicators
SPEAKER HEADER
Place at ATX Connector
Place at ATX Connector
Place at ATX Connector
Place at ATX Connector
Place at ATX Connector
Note Cap Direction
NOTE 1: Locate Fan Header next to Processor Assembly
Note 2: Connect V5_0 feed for analog supplies AVDD1 and CLKAVDD1 at one point only on PCB
Note 3: Place power connector decoupling at ATX connector
NOTE 4: Note direction of caps on -12V, -5V supplies.
Place at ATX Connector
ATX Power Connector
Note: Add screen marking for V5_0 LED, V3_3 LED
Fan
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
1934
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SP
KR
10
RS
MR
ST
#10
PW
RO
N#
10A
TX
_P
W_O
K18
V-5
P0
V5P
0
V12
P0
V-1
2P0
V5P
0
V5P
0V
3P3
V3P
3SU
S
V5P
0
5VS
B
5VS
BV
3P3
V3P
3SU
S
C17
5
10uF
C17
110
0uF
JP2
1x4
1 2 3 4
J8
AT
X P
OW
CO
NN
8 9 10
12 14 18 19 20
3 5 7
13 15 16 17
4 61 211
PW
_OK
5VS
BV
12P
0
V-1
2P0
PS
_ON
V-5
P0
V5P
0V
5P0
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
V5P
0
V5P
0
V3P
3V
3P3
V3P
3
D9
LGS
260-
DO
2
13
IN
NCOUT
D10
LGS
260-
DO
2
13
IN
NCOUT
C16
50.
1uF
C16
047
0pF
C15
40.
1uF
C16
20.
1uF
C15
70.
1uF
C16
80.
1uF
C16
147
0pF
C16
910
0uF
C16
610
0uF
C15
810
0uF
C15
610
0uF
C15
910
0uF
C17
0
100u
F
C16
4
100u
F
C16
7
100u
F
C15
510
0uF
C16
3
100u
F
U15
A
74LC
T14
12
14 7
U14
A
74LC
T14
12
14 7
C17
210
uF
TP
8
1TP
J9
JUM
P3
1
2
3
C17
3
47uF
C17
4
10uF
R31
5
220
R31
7
2.7K
R31
6
124
J10
AM
P17
398
1-3
123
123
TP
7
1T
P
U16 LT
117-
3.3
123
4
Adj
/GN
D
Out
InO
utT
ab
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
>>
Keep near pin 4.
Itt listed at 2.7A max.
CMOS current input listed at 500 mA max.
>>Keep near pin 3.
>>
Route this as a 500 mil bus bar.
Minimize the loop formed by the two FETs and the input capacitors.
>>
Place close to FETs.
>>
Place all output caps around CPU.
>>
>>
Run parallel.
>>
Run parallel.
Place close to SC1185, pins 8 and 9.
>>
>>
>>
Minimize distance between decoupling cap and
pins 5 and 1 of SC1185.
Hi Frequency Decoupling caps
Route this as a 200 mil bus bar.
DC to DC Convertor
6/16/1999
Place inductor close
to FET junction.
>>
Minimize DH and DL
trace lengths.
>>
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2034
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
VID
15
VID
25
VID
35
VID
05
DC
PW
RO
K
V3P
3
V1P
5
V1P
5
V3P
3
V2P
5
V5P
0
VC
OR
E
V2P
5
V12
P0
V5P
0
R32
5
2.2
C19
8
4700
pF50
V
C20
6
22uF
25V
R32
62.
2
R31
9
10
R32
8.0
05
C19
9
.1uF
16V
R32
32.
2
L3 1.7u
H
L4 1.7u
H
C20
0
.1uF
16V
R32
7.0
05
R31
8
1K/1
%
R32
4.0
05
C18
7
22uF
25V
C18
5
.1uF
16V
U17
SC
1185
5 6 22 21 20 1916 11224249 8 17
718
15 11
10
131423 3
VC
CR
EF
VID
0V
ID1
VID
2V
ID3
EN
AG
ND
PG
ND
LG
AT
E2
GA
TE
1LD
OS
2
CS
+C
S-
VO
_SE
NS
E
PW
RG
OO
D
VID
4
BS
TH
DH
PG
ND
H
DL
BS
TL
LDO
V
LDO
S1
C18
4
1500
uF6.
3V
C18
3
1500
uF6.
3V
C18
6
1uF
10V
C18
8
1500
uF6.
3V
C20
4
.1uF
16V
C20
2
22uF
25V
Q9
12A
1
3 2
Q8
12A
1
3 2
R32
1
10
C20
3
1uF
10V
C19
5
1uF
10V
C19
6
1uF
10V
C19
1
1500
uF6.
3V
C19
2
1500
uF6.
3V
C19
3
22uF
25V
C19
4
1uF
10V
C20
8
.1uF
16V
C20
7
1uF
10V
C19
7
1uF
10V
C19
0
1500
uF6.
3V
C17
7
1uF
10V
C17
8
.1uF
16V
C17
6
.1uF
16V
C20
1
1500
uF6.
3V
R32
0
ZE
RO
Q7
20A
1
3 2
Q6
20A
1
3 2
R32
2
1K
C20
5
1500
uF6.
3V
C17
9
1uF
10V
C18
2
1500
uF6.
3V
C18
9
.1uF
16V
C18
0
22uF
25V
C18
1
22uF
25V
A A
B B
C C
D D
E E
44
33
22
11
PLACE THESE CAPS CLOSE TO POWER PINS (CORVCC, IOVCC, MEMVCC)
BIOS EXPANSION ROM
1%
AC
TIV
ITY
LE
D
1/4 W
1/4 W
6900 Video Controller - Part One
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n50
00 W
. Cha
ndle
r B
lvd.
Cha
ndle
r A
Z. 8
5226
C
2134
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DA
CV
CC
DA
CV
CC
GA
D6
GA
D22
GC
/BE
#3
RM
D0
P7
P27
GA
D18
GA
D29
GC
/BE
#1
RM
D1
P5
P18
P21
P28
MC
KV
CC
DC
KG
ND
P3
P33
GA
D14
GA
D20
GA
D28
MC
KG
ND
GA
D8
P1
P4
P10
P15
P24
P31
MC
KG
ND
RM
D5
GA
D3
GA
D5
GA
D23
GA
D30
GC
/BE
#2
RM
D2
P2
P30
DC
KV
CC
GA
D12
RM
D3
GA
D11
GA
D17
GA
D26
RM
D6
P19
P32
GA
D4
GA
D10
P6
P25
P17
RM
D4
RM
D0
GA
D16
GA
D7
GA
D9
GA
D27
P9
MC
KV
CC
DC
KG
ND
GA
D1
GA
D19
GA
D24
GC
/BE
#0
P12
P20
P29
RM
D[7
:0]
GA
D21
P22
P35
RM
D1
DC
KV
CC
GA
D15
GA
D25
RM
D4
RM
D5
RM
D6
GA
D0
GA
D2
GA
D31
P0
P16
RM
D3
GA
D16
RM
D7
P11
P13
P14
P23
P34
RM
D7
RM
D2
GA
D13
P8
P26
DA
CV
CC
GC
/BE
#[3:
0]7
GA
D[3
1:0]
7P
[23:
0]22
P[3
5:24
]22
FLM
22
PE
RR
#16
,17,
25
VS
YN
C22
GP
AR
7
GR
EE
N22
GS
TO
P#
7
M22
GC
LKO
UT
7
DD
CD
AT
A22
SE
RR
#7,
9,15
,16,
17,2
3,25
EN
AB
KL
22
DD
CC
LK22
EN
AV
DD
22
BLU
E22
SH
FC
LK22
PC
IRS
T23
,24,
25
HS
YN
C/C
SY
NC
22
LP22
RE
D22
GF
RA
ME
#7
PIR
QA
#10
,15,
16,1
7
GT
RD
Y#
7G
IRD
Y#
7
GD
EV
SE
L#7
V3P
3
V12
P0
V5P
0
AV
CC
V5P
0
V3P
3
V3P
3
V5P
0
V3P
3
V3P
3
V3P
3
C21
8
0.1u
F ta
nt.
PCI SIGNALS
CRT INTERFACE
MISC SIGNALS
BIOS ROM INTERFACE
LCD INTERFACE
VIDEO INTERFACE
U18
6900
0
U2 T3
R4
U1T2
R3 T1
R2
R1
P2
N3
P1
N2
M4
M3
N1 J1 J2 H1 J3 J4 H2
G1
H3
G3 F2
E1 F3
D1
E2 F4
E3
P3
M2
K3 F1
G2
C1
D2
M1
K2
K1
K4 L1 L4 L2 L3 A4
D18
C19
B20
C18
A20
B19
A19
B18
C17
D16
B10
C10 A
9B
9A
8C
9
B8
A7
C8
B7
A6
C7
B6
A5
D15
B16
A17
C15
A16
B15
C14
A15
B14
C13
A14
B13
D12
C12
A13
B12 L19
L20
W6
V7
Y6
W7
V8
Y7
W8
U9
V9
Y8
W9
Y9
V10
W10
Y10
U10
U11
Y11
W11
V11
Y12
Y13
V12
U12
W13
Y14
V13
W14
Y15
V14
W15
Y16
V15
Y17
W16
U15
Y5
W5
Y4
V6
V5
W4
U6
V16
W17
Y18
V17
R18
U20
T19
R17
T18
U19
V20
T17
U18
V19
W20
W19
U17
V18
Y19
W18
U5
Y2
B3
A2
C4D5
A3B4
D7G4P4U14U7J9J10J11J12K9K10K11K12L9L10L11L12
D9W12H4N4U8U13W1D13H17N17
A1B5C2C5D3D4D8Y20
A10
A11
A18
B11
B17
C11
C16
C20
D10
D11
D19
D20
E17
E18
E19
E20
F17
F18
F20
F19
G18
G19
G20
H18
H19
H20
J17
J18
J19
J20
K17
K18
K19
K20
L17
L18
M17
M18
M19
M20
N18
N19
N20
P18
P19
P20
R19
R20
T20
W3
V4
Y3
U3
V2
V3
U4
E4
C3
A12
D17 D
6U
16 B1
B2
V1 T4
W2
C6
Y1M12M11M10M9P17G17D14
AD
0A
D1
AD
2
AD
4A
D3
AD
5A
D6
AD
7A
D8
AD
9A
D10
AD
11A
D12
AD
13A
D14
AD
15A
D16
AD
17A
D18
AD
19A
D20
AD
21A
D22
AD
23A
D24
AD
25A
D26
AD
27A
D28
AD
29A
D30
AD
31C
/BE
0#C
/BE
1#C
/BE
2#C
/BE
3#
IDS
EL
RE
SE
T#
BU
SC
LKP
AR
FR
AM
E#
IRD
Y#
TR
DY
#S
TO
P#
DE
VS
EL#
PE
RR
#S
ER
R#
INT
#
CF
G0
CF
G1
CF
G2
CF
G3
CF
G4
CF
G5
CF
G6
CF
G7
CF
G8
CF
G9
CF
G10
CF
G11
CF
G12
CF
G13
CF
G14
CF
G15
RM
D0
RM
D1
RM
D2
RM
D3
RM
D4
RM
D5
RM
D6
RM
D7
RM
A0
RM
A1
RM
A2
RM
A3
RM
A4
RM
A5
RM
A6
RM
A7
RM
A8
RM
A9
RM
A10
RM
A11
RM
A12
RM
A13
RM
A14
RM
A15
RM
A16
RM
A17
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
SH
FC
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DCKVCCDCKVCC
DCKGNDDCKGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
CORVCCCORVCC
IOVCCIOVCCIOVCCIOVCCIOVCC
MEMVCCMEMVCCMEMVCC
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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B B
C C
D D
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44
33
22
11
PA
NE
L C
ON
NE
CT
OR
PA
NE
L C
ON
NE
CT
OR
2(3
6-B
it)
1-2 ENABLE TV OUT
2-3 DISABLE TV OUT
TV
OU
T
1-2 NTSC
2-3 PAL
NOTE: FOR PAL
CRYSTAL MUST
ALSO BE CHANGED
INS
TA
LL F
OR
TV
OU
TC
AP
AB
ILIT
Y.
IF P
OP
ULA
TE
DP
LAC
E C
LOS
E T
O C
RT
CIR
CU
IT
CR
T C
ON
NE
CT
OR
USED TO
CONTROL
VOLTAGE TO
FLAT PANEL
69000 Video Controller - Part 2
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2234
Titl
e
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eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SH
FC
LKC
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DS
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FLM
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P3
P12
P1
P9
P4
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P5
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P26
P28
P32
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P35
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P27
P33
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21
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42 43
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22
11
5-WIRE AC97 LINK’
THE ES1371 IS
PCI DEVICE #16
AC 97 Audio - Part One
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2334
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
C/B
E#0
AD
9
AD
14A
D13
AD
20
AD
17
AD
22
AD
4
AD
8
AD
10
AD
24
AD
30
AD
1
AD
29
AD
19
AD
23
AD
2A
D3
AD
27
AD
18
AD
25
AD
0
AD
27
AD
31
AD
5
AD
12
C/B
E#3
AD
15
AD
26
AD
11
AD
6
C/B
E#1
AD
7
AD
21
C/B
E#2
AD
16
AD
28
PC
IRS
T21
,24,
25P
CI_
CLK
614
C/B
E#[
3:0]
7,9,
15,1
6,25
AD
[31:
0]7,
9,15
,16,
25
PC
IRS
T21
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25A
CR
ES
ET
#21
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25
DE
VS
EL#
7,9,
15,1
6,17
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QC
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17,2
5
XT
AL0
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F24
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DY
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9,15
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17,2
5
PA
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17,2
5
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15,1
6,17
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NT
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17
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24
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AM
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17,2
5
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EQ
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17
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AT
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RR
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9,15
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17,2
1,25
BIT
_CLK
24
V5P
0
C29
2
22pF
R37
01M
EG
ES1371
PCI SIGNALS
MIDI
AC97 LINK
U27
ES
137
1
89919293949697983457891013242728293032333438394041434445468284 99 14 23 35 22 15 18 16 20 2 19 87 86 21 81
12
25
37
50
62
74
85
100
4742363126171161
79 78 77 76 73 72 71 70 68 69 60 5859 61 56 55 54 53 52 49 63 66 65 8848
5157646775
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9095
AD
[31]
AD
[30]
AD
[29]
AD
[28]
AD
[27]
AD
[26]
AD
[25]
AD
[24]
AD
[23]
AD
[22]
AD
[21]
AD
[20]
AD
[19]
AD
[18]
AD
[17]
AD
[16]
AD
[15]
AD
[14]
AD
[13]
AD
[12]
AD
[11]
AD
[10]
AD
[9]
AD
[8]
AD
[7]
AD
[6]
AD
[5]
AD
[4]
AD
[3]
AD
[2]
AD
[1]
AD
[0]
RS
T#
CLK
C/B
E[3
]#C
/BE
[2]#
C/B
E[1
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[0]#
PA
RF
RA
ME
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RD
Y#
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Y#
ST
OP
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SE
LD
EV
SE
L#
RE
Q#
GN
T#
SE
RR
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TA
#
VDD
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VDD
VDD
VDD
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VDD
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GNDDGNDDGNDDGNDDGNDDGNDDGNDDGNDDGNDD
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4JY
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K5
JYS
TK
6JY
ST
K7
MID
I_IN
MID
I_O
UT
BC
LK
SY
NC
SD
AT
A_I
N
SD
AT
A_O
UT
GP
IO(3
)G
PIO
(2)
GP
IO(1
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PIO
(0)
I2S
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LKIN
I2S
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LKIN
XT
AL0
_BU
FX
TA
L0X
TA
LI
NC
I2S
_SE
RIN
GNDDGNDDGNDDGNDDGNDD
GNDDGNDD
GNDDGNDD
C28
5
0.1u
F
R36
91k
Y6
24.5
76 M
Hz
12
C29
1
22pF
C28
6
0.1u
F
C28
4
0.1u
F
C28
3
0.1u
F
C28
7
0.1u
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C28
8
0.1u
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R36
8
220
C28
9
0.1u
F
A A
B B
C C
D D
E E
44
33
22
11
MICROPHONE
LINE INPUT
LINE OUTPUT
5-WIRE AC97 LINK
ALL RESISTORS AND CAPACITORS ARE 1/8 W
SEE APPLICATION NOTE FOR LAYOUT GUIDELINES
MONO OUT
AUX INPUT
CDROM AUDIO HEADER
2mm
pitch
keyed
plug LINE LEVEL OUT
AC 97 Audio - Part Two
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2434
Titl
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Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
LIN
E_I
N_L
LIN
E_O
UT
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LIN
E_O
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_L
LIN
E_I
N_R
VR
EF
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T
MO
NO
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T
LNLV
L_O
UT
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LVL_
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T_L
CD
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D_G
ND
CD
_R
MIC
1
AU
X_L
AU
X_R
MO
NO
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T
AU
X_R
AU
X_L
CD
_L
CD
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D
CD
_R
LNLV
L_O
UT
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LNLV
L_O
UT
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XT
AL0
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F23
BIT
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23S
DA
TA
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23S
YN
C23
SD
AT
A_O
UT
23A
CR
ES
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#21
,23,
25
V5P
0
V5P
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V12
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0
C31
0
470p
F N
PO
JP8
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AD
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2
1 2
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5
1uF
C29
6
1uF
C29
7
1uF
U28
MC
78M
05C
DT
13
2
Vin
+5V
GND
JP9
1x4
1234
C32
4
270p
F N
PO
FB
60
HZ
0805
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4
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G L G R
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LIN
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R37
61k R
380
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k
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270p
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Do
Not
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all
FB
66
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J16
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OR
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8
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6
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O
AD1819A
U29 AD
1819
A
12 13 14 15 16 17 18 19 2021 22 23 2437 3941
29303132333428
2725
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1
9
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4
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40 43 441158 106 3245 46 47 48
35 36
PC
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PH
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VID
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X3D
VR
EF
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TV
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FAVdd1
AVdd2
DVdd1
DVdd2
AVss1
AVss2
DVss1
DVss2
NC
NC
NC
RE
SE
T#
SD
AT
A_O
UT
SD
AT
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C
BIT
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XT
L_O
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CS
0C
S1
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CH
AIN
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LIN
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_L
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UT
_R
C30
7
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stal
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all
R38
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R37
1
Do
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Inst
all
C32
6
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4
1uF
C29
3
1uF
C31
3
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tant
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R38
61k
C33
1
470p
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PO
C33
0
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O
C29
8
1uF
C30
3
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R38
8
47.5
k
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71k
R37
40.
0
C32
9
1uF
A A
B B
C C
D D
E E
44
33
22
11
(FLASH)
THE PCI1225 IS
PCI DEVICE #5
PCI1225 PC Card Controller
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2534
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
LAT
CH
CLO
CK
DA
TA
AD
7
B_D
5B
_D6
B_A
11
A_A11
A_CD2#
AD
15
AD
9
A_IORD#
A_A1
C/B
E#3
AD
24
AD
20
AD
2
B_C
E1#
B_A
18
B_A
19
B_A
16
B_A
12 B_B
VD
2(S
PK
R#)
A_D11
A_CE1#
A_A9
A_A24
A_D8A_D9
AD
31
C/B
E#2
AD
13
AD
8
B_A
2
A_A22
A_RESET
AD
28A
D27
AD
10
AD
4
B_D
3
B_D
1
A_D5A_D6
A_OE#
A_REG#
A_A2
AD
30
AD
22
AD
3
B_D
13
B_D
7
B_A
9
B_D
9
B_D
2
A_D4
A_A17
A_A8
A_A19
CLO
CK
AD
17A
D16
C/B
E#0
AD
5
B_A
5
A_A13
A_A16
A_A5A_A4
A_BVD1(STSCHG#/RI#)
A_D15
AD
25
AD
29
AD
19
AD
12
B_W
E#
B_I
NP
AC
K#
B_A
1
A_CD1#
A_CE2#
A_READY(REQ#)
A_WP(IOIS16#)
LAT
CH
AD
26
AD
16
B_A
8
B_W
P(I
OIS
16#)
A_D13
A_A18
A_D2
AD
11
AD
18
AD
6
B_D
12
B_A
7B
_A6
B_C
D2#
B_D
0
B_D
8
A_D7
A_VS1#
DA
TA
AD
21
C/B
E#1
B_D
11
B_C
E2#
B_A
20
B_A
4
B_D
10
A_A3
A_WAIT#
B_D
14
B_O
E#
B_A
17
B_A
21
B_R
EA
DY
(IR
EQ
#)
A_D14
A_IOWR#
A_A14
A_BVD2(SPKR#)
A_D1
B_A
15
B_A
3
B_W
AIT
#
A_D12
A_A15
A_A23
A_D0
AD
1
B_C
D1#
B_D
15
B_A
13
B_A
14
A_A21
A_A12
A_A7
AD
23
AD
0
B_D
4
B_A
24
A_A10
A_A20
A_A25
A_A6A
D14
B_A
10
B_A
22
B_A
23
B_B
VD
1(S
TS
CH
G#/
RI#
)
A_D3
A_WE#
A_VS2#
A_INPACK#
A_A0
A_D10
AD
[31:
0]7,
9,15
,16,
23
PC
IRS
T21
,23,
24P
CI_
CLK
514
C/B
E#[
3:0]
7,9,
15,1
6,23
PA
R7,
9,15
,16,
17,2
3D
EV
SE
L#7,
9,15
,16,
17,2
3F
RA
ME
#7,
9,15
,16,
17,2
3P
GN
T3#
7,17
IRD
Y#
7,9,
15,1
6,17
,23
PR
EQ
3#7,
17S
ER
R#
7,9,
15,1
6,17
,21,
23S
TO
P#
7,9,
15,1
6,17
,23
TR
DY
#7,
9,15
,16,
17,2
3
B_A
[24:
1]26
B_D
[15:
0]26
PC
IRS
T21
,23,
24
PIR
QC
#10
,16,
17,2
3
IRQ
410
,17,
28,2
9,32
IRQ
1010
,17,
28,2
9,32
IRQ
910
,17,
29
PIR
QD
#10
,16,
17
IRQ
1510
,17,
28,2
9
IRQ
510
,17,
28,2
9,32
PE
RR
#16
,17,
21
B_C
E1#
26B
_CE
2#26
B_O
E#
26
B_W
E#
26
V3P
3
V3P
3V
5P0
V3P
3
V3P
3
V5P
0V
12P
0
V5P
0
R39
143
K
C33
810
uFC
345
1uF
C34
10.
1uF
C34
00.
1uF
PCI BUS
PC CARD
PC CARD
SLOT A
SLOT B
TI_
PC
I122
5
U32
1
234 56
7
89101112
13
1415
1617 1819 2021
22
232624 25 27 2829 30
31
323334 3536 3738
39 4041 4243
44
45 464748 4950 5152 5354 55 5657 585960 6162 63
64
656667 6869 707172 737475
76 7778 7980 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125126
127
128
129
130
131132133
134
135
136
137138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Vccp
AD
10A
D9
AD
8
C/B
EO
#
AD
7
Vcc
AD
6A
D5
AD
4A
D3
AD
2
GND
AD
1A
D0
B_C
D1#
B_D
3
B_D
11
B_D
4
B_D
12
B_D
5
GND
B_D
13
B_D
7B
_D6
B_D
14B
_D15
B_C
E1#
B_A
10
B_C
E2#
Vcc
B_O
E#
B_I
OR
D#
B_A
11
B_I
OW
R#
B_A
9
B_A
17Vccb
B_A
8
B_A
18
B_A
13
B_A
19
B_A
14
GND
B_A
20
B_W
E#
B_A
21
B_A
16
B_A
22
B_A
15
B_A
23
B_A
12
B_A
24
B_A
7
B_A
25
B_V
S2#
B_A
6
B_R
ES
ET
B_A
5B
_A4
B_I
NP
AC
K#
B_A
3
B_R
EG
#
Vcc
B_A
2B
_A1
B_A
0
B_V
S1#
B_R
EA
DY
(IR
EQ
#)
B_W
AIT
#
B_B
VD
2(S
PK
R#)
B_B
VD
1(S
TS
CH
G#/
RI#
)
B_W
P(I
OIS
16#)
B_C
D2#
GND
B_D
0
B_D
8
B_D
1
B_D
9
B_D
2
B_D
10
A_CD1#
A_D3
A_D11
A_D4
Vcc
A_D12
A_D5
A_D13
A_D6
A_D14
A_D7
A_D15
A_CE1#
A_A10
GND
A_CE2#
A_OE#
A_IORD#
A_A11
A_IOWR#
A_A9
A_A17
A_A8
A_A18
A_A13
A_A19
A_A14
A_A20
A_WE#
A_A21
A_A16
Vcc
A_A22
A_A15
A_A23
A_A12
A_A24
A_A7
Vcca
A_A25
A_VS2#
A_A6
A_RESET
A_A5A_A4
A_INPACK#
A_A3
GND
A_REG#
A_A2A_A1A_A0
A_VS1#
A_READY(REQ#)
A_WAIT#
A_BVD2(SPKR#)A_BVD1(STSCHG#/RI#)
A_WP(IOIS16#)
A_CD2#
A_D0
A_D8
Vcc
A_D1
A_D9
A_D2
A_D10
Vcci
SP
KR
OU
T
LAT
CH
CLO
CK
DA
TA
GND
MF
UN
C0
MF
UN
C1
SU
SP
EN
D#
MF
UN
C2
MF
UN
C3
MF
UN
C4
MF
UN
C5
MF
UN
C6
C/B
E3#
RI_
OU
T#/
PM
E#
Vcc
AD
25
PR
ST
#
GND
GN
T#
RE
Q#
AD
31A
D30
AD
11
AD
29A
D28
Vcc
AD
27A
D26
Vccp
AD
24
PC
LK
GND
IDS
EL
AD
23A
D22
AD
21A
D20
Vcc
AD
19A
D18
AD
17A
D16
C/B
E2#
FR
AM
E#
GND
IRD
Y#
TR
DY
#
DE
VS
EL#
ST
OP
#
PE
RR
#
SE
RR
#
Vcc
PA
R
C/B
E1#
AD
15A
D14
AD
13
GND
AD
12
R39
243
K
C34
30.
1uF
C33
90.
1uF
R39
01K
C34
20.
1uF
U31
TI_
TP
S22
06
91011 2021228 23
345 6 14 18 1215 16 17 1 2 30 24 7
AV
CC
AV
CC
AV
CC
BV
CC
BV
CC
BV
CC
AV
PP
BV
PP
DA
TA
CLO
CK
LAT
CH
RE
SE
TR
ES
ET
#
OC
#
GN
D
3.3V
3.3V
3.3V 5V 5V 5V 12
V12
V
U30
PC
MC
IA_S
ocke
t
292827262524232212118102113142019464748495053545556
303132234566465663738394041
636236677426044459166158591533
4357
6813435
51175218
A_A0A_A1A_A2A_A3A_A4A_A5A_A6A_A7A_A8A_A9A_A10A_A11A_A12A_A13A_A14A_A15A_A16A_A17A_A18A_A19A_A20A_A21A_A22A_A23A_A24A_A25
A_D0A_D1A_D2A_D3A_D4A_D5A_D6A_D7A_D8A_D9A_D10A_D11A_D12A_D13A_D14A_D15
A_BVD1(STSCHG#/RI#)A_BVD2(SPKR#)A_CD1#A_CD2#A_CE1#A_CE2#A_INPACK#A_IORD#A_IOWR#A_OE#A_READY(REQ#)A_REG#A_RESETA_WAIT#A_WE#A_WP(IOIS16#)
A_VS1#A_VS2#
GNDGNDGNDGND
VccVccVpp2Vpp1
R38
9
220
R39
3
1K
C33
61u
F
C33
50.
1uF
C33
41u
F
C33
70.
1uF
C33
30.
1uF
C34
40.
1uF
C33
20.
1uF
A A
B B
C C
D D
E E
44
33
22
11
StrataFlash
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2634
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
CE
H#
B_C
E2#
B_A
24
B_C
E1#
B_A
24
RP
#R
P#
RP
#B
_OE
#B_O
E#
B_O
E#
B_O
E#
B_W
E#B_W
E#
B_W
E#
B_W
E#
RP
#
B_A
11
B_A
19
B_A
4
B_A
21
B_A
6
B_A
10
B_A
11
B_A
8
B_A
13
B_A
14
B_A
1
B_A
19
B_A
5B
_A5
B_A
15
B_A
6
B_A
13
B_A
11
B_A
[23:
1]
B_A
7
B_A
9B
_A9
B_A
17
B_A
20
B_A
16
B_A
11
B_A
8
B_A
8
B_A
6
B_A
9
B_A
3
B_A
1
B_A
23
B_A
2B
_A1
B_A
22
B_A
5
B_A
3B
_A3
B_A
4
B_A
12
B_A
13
B_A
3
B_A
17
B_A
23
B_A
15
B_A
13
B_A
2
B_A
14
B_A
22
B_A
21
B_A
4
B_A
18
B_A
19
B_A
5
B_A
[23:
1]
B_A
10
B_A
2
B_A
17
B_A
16
B_A
20
B_A
20
B_A
18
B_A
22
B_A
6
B_A
9
B_A
7B
_A7
B_A
22
B_A
21
B_A
14
B_A
20
B_A
23
B_A
7
B_A
[23:
1]
B_A
23
B_A
1
B_A
12
B_A
19
B_A
10
B_A
15
B_A
16
B_A
21
B_A
18
B_A
10
B_A
2
B_A
17
B_A
12
B_A
18
B_A
12
B_A
4
B_A
16
B_A
15
B_A
14
B_A
8B
_D7
B_D
3
B_D
7B
_D14
B_D
15
B_D
[7:0
]
B_D
15
B_D
1B
_D0
B_D
6
B_D
9
B_D
4
B_D
[7:0
]
B_D
12B
_D11
B_D
5
B_D
2
B_D
[15:
8]
B_D
2
B_D
9
B_D
1
B_D
4
B_D
13
B_D
8
B_D
11
B_D
0
B_D
10B
_D3
B_D
8
B_D
5
B_D
14B
_D6
B_D
10
B_D
13B_D
12
B_D
[15:
0]25
B_C
E2#
25
B_O
E#
25B
_WE
#25
B_A
[24:
1]25 B
_CE
1#25
V5P
0
V5P
0V
5P0
V5P
0
V5P
0V
5P0
V5P
0
U33
28F
XX
0J5
A5A7A2
A4
J4 J5
H8
D2
D7
F8
G6
G8
H6
D8
G5
D6
H4
B8
J3C
8G
3C
7F
3B
7G
7C
6H
7B
6J6
A6
H5
B5
G4
B4
H3
C4
H2
A3
G2
B3
C3
B2
D3
B1
C1
C2
D1
F6
F1
G1
C5
H1
VPENGNDVCC
CE
0
VCCq GND
D0
CE
1
A1
CE
2
D1
A0
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
D8
A8
D9
A9
D10
A10
D11
A11
D12
A12
D13
A13
D14
A14
D15
A15
A16
A17
A18
A19
A20
A21
A22
BY
TE
#W
E#
OE
#R
P#
ST
S
C34
60.
1uF
U35
28F
XX
0J5
A5A7A2
A4
J4 J5
H8
D2
D7
F8
G6
G8
H6
D8
G5
D6
H4
B8
J3C
8G
3C
7F
3B
7G
7C
6H
7B
6J6
A6
H5
B5
G4
B4
H3
C4
H2
A3
G2
B3
C3
B2
D3
B1
C1
C2
D1
F6
F1
G1
C5
H1
VPENGNDVCC
CE
0
VCCq GND
D0
CE
1
A1
CE
2
D1
A0
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
D8
A8
D9
A9
D10
A10
D11
A11
D12
A12
D13
A13
D14
A14
D15
A15
A16
A17
A18
A19
A20
A21
A22
BY
TE
#W
E#
OE
#R
P#
ST
S
U34
28F
XX
0J5
A5A7A2
A4
J4 J5
H8
D2
D7
F8
G6
G8
H6
D8
G5
D6
H4
B8
J3C
8G
3C
7F
3B
7G
7C
6H
7B
6J6
A6
H5
B5
G4
B4
H3
C4
H2
A3
G2
B3
C3
B2
D3
B1
C1
C2
D1
F6
F1
G1
C5
H1
VPENGNDVCC
CE
0
VCCq GND
D0
CE
1
A1
CE
2
D1
A0
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
D8
A8
D9
A9
D10
A10
D11
A11
D12
A12
D13
A13
D14
A14
D15
A15
A16
A17
A18
A19
A20
A21
A22
BY
TE
#W
E#
OE
#R
P#
ST
S
U36
28F
XX
0J5
A5A7A2
A4
J4 J5
H8
D2
D7
F8
G6
G8
H6
D8
G5
D6
H4
B8
J3C
8G
3C
7F
3B
7G
7C
6H
7B
6J6
A6
H5
B5
G4
B4
H3
C4
H2
A3
G2
B3
C3
B2
D3
B1
C1
C2
D1
F6
F1
G1
C5
H1
VPENGNDVCC
CE
0
VCCq GND
D0
CE
1
A1
CE
2
D1
A0
D2
A2
D3
A3
D4
A4
D5
A5
D6
A6
D7
A7
D8
A8
D9
A9
D10
A10
D11
A11
D12
A12
D13
A13
D14
A14
D15
A15
A16
A17
A18
A19
A20
A21
A22
BY
TE
#W
E#
OE
#R
P#
ST
S
R39
4
1K
C34
80.
1uF
C35
0
0.1u
F
C34
9
0.1u
F
TP
11
1T
P
TP
91
TP
TP
10
1T
P
C34
747
uF
TP
121
TP
A A
B B
C C
D D
E E
44
33
22
11
NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+).
Must be 45 Ohm Matched
Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm.
8Ohm/100MHz/500mA
8Ohm/100MHz/500mA
PCB Trace 45 Ohm Matched, Routed Together
Stripline width 0.015 (1 oz) 44.88/45.45
Ohm
Poly-Fuse
Poly-Fuse
NOTE 2: Protect differential traces w/ guard traces or
double space to any other signal.
Place As Close as Possible to PIIX4
Place As Close as Possible to PIIX4
PCB Trace 45 Ohm Matched, Routed Together
Stripline width 0.015 (1 oz) 44.88/45.45
Ohm
NOTE 3: Place ferrites at connector.
NOTE 4: Poly-fuse min 1.5A
max 5A.
BOTTOM of Stacked USB Connector
TOP of Stacked USB Connector
Poly fuses should be in range
of 1.5A to 5A
Place these caps within 1 inch
of USB Connector stack
USB Connectors
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
2734
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Z1_
VC
CZ
0_V
CC
Z1_
GN
D
Z0+
Z0_
GN
D
Z1-
Z1+
Z0-
US
BV
FIL
1
US
BV
FIL
2
US
BV
FIL
1U
SB
VF
IL2
US
BP
1-10
US
BP
0+10
US
BP
0-10
US
BP
1+10
OC
0#10
OC
1#10
V5P
0
J18
US
B S
tack
1 2 3 4 5 6 7 8
9 10 11 12
VC
C0
D0-
D0+
GN
D0
VC
C1
D1-
D1+
GN
D1
GN
DG
ND
GN
DG
ND
FB
67B
LM41
A8
00S
12 12
F4
SM
D25
0-00
2
FB
68B
LM41
A8
00S
12 12
C35
50.
01uF
F5
SM
D25
000
2
FB
70B
LM41
A8
00S
1 21 2
FB
69
BLM
41A
800
S
1 21 2
C35
310
0uF
C35
70.
1uF
C35
80.
01uF
C35
40.
1uF
C35
947
pF
C36
1
47pF
R40
327
C35
610
0uF
R40
115
K
C35
2
0.01
UF
C36
2
47pF
C36
047
pF
R40
215
K
R39
927
R40
5
15K
R40
027
R39
7
15K
R39
510
K
R40
427
R40
6
15K
C35
1
0.01
UF
R39
8
15K
R39
610
K
AA
BB
CC
DD
EE
44
33
22
11
PULL romCs# high so as not to interfere with boot rom!
This disables the ROM buffers.
BIOS needs to enable and
configure IRQs
IR TRANSCEIVER
Alternate IR pins
allow switch between
COM2 and Infrared Mode
to be configured in
BIOS
PULLING UP SYSOPT
CONFIGURES 78x TO 370h
Ultra I/O
A
Celeron P
rocessor Based T
T S
ample D
esign
Intel Em
bedded Microprocessor D
ivision
5000 W. C
handler Blvd.
Chandler A
Z. 85226
C
2834
Title
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
SD
0S
D1
SD
2S
D3
SD
4S
D5
SD
6S
D7
SA
0S
A1
SA
2S
A3
SA
4S
A5
SA
6S
A7
SA
8S
A9
SA
10
SA
11
SA
12
SA
13
SA
14
SA
15
IRR
X2
IRT
X2
SD
[15:0]9,17,29,32
SA
[19:0]9,17,29,32,33
AE
N9,29,32
IOC
HR
DY
9,17,29R
ST
DR
V9,11,29,32
DA
CK
3#10,29
DA
CK
2#10,29
DR
Q0
10,17,29D
RQ
110,17,29
DR
Q2
10,17,29D
RQ
310,17,29
DA
CK
0#10,29
DA
CK
1#10,29
TC
10,29,32IO
R#
9,17,29,32IO
W#
9,17,29,32
RE
F1
14
RX
D0
31T
XD
031
RT
S0#
30C
TS
0#30
DT
R0#
31D
SR
0#30
DC
D0#
30R
I0#30
RX
D1
30T
XD
130
RT
S1#
30C
TS
1#30
DT
R1#
30D
SR
1#30
DC
D1#
30R
I1#30
PD
R0
30P
DR
130
PD
R2
30P
DR
330
PD
R4
30P
DR
530
PD
R6
30P
DR
730
-SLC
TR
IN30
-INIT
30-A
LF30
-ST
RO
BE
30-B
US
Y30
-AC
K30
PE
30S
LCT
30-E
RR
30
KB
DA
20GA
TE
10K
BD
RS
T#
10
DR
AT
E0
30H
DE
N30
-IND
EX
30-T
RK
030
-WP
T30
-MO
TE
B30
-MO
TE
A30
-DR
VS
B30
-DR
VS
A30
-DS
KC
HG
30-S
TE
P30
-DIR
30-S
IDE
130
-WD
AT
A30
-WG
AT
E30
-RD
AT
A30
IRQ
110,17
IRQ
310,17,29,32
IRQ
410,17,25,29,32
IRQ
510,17,25,29,32
IRQ
610,17,29,32
IRQ
710,17,29,32
IRQ
1210,17,29
IRQ
1010,17,25,29,32
IRQ
1510,17,25,29
IRQ
1410,11,17,29
V5P
0
V5P
0
V5P
0
V5P
0
V5P
0
V5P
0
FB
72
BLM
41A8
00S
12
12
C369
470pF
FB
73
BLM
41A800S
12
12
TOP
BOTTOM
J19
PS
2 ST
AC
K
1314151617
T1
T2
T3
T4
T5
T6
B1
B3
B4
B5
B6
B2
GN
DG
ND
GN
DG
ND
GN
D
KB
DA
TA
NC
GN
DK
B_V
CC
KB
_CLK
NC
MD
AT
A
GN
DM
_VC
CM
_CLK
NC
NC
FB
74
BLM
41A8
00S
12
12
C373
470pF
FB
75
BLM
41A800S
12
12
FB
71
BLM
41A8
00S
1 21 2
C372
470pFC
371470pF
C370
470pF
RP
30
2.2k
1 82 73 64 5
R410
10K
F6
SMD250-002
C367
.1uF
Floppy
Uarts
Parallel
ISA/Host
U37
FD
C37B
78X
8377
8485
78
86 7087
79
8889
80
90
96
91
81
92
82
71
113
72
97
73
7
75
98
76
115
99 16100
116
101
48102
117
103
56
95 114
9474
110
119
111
11107
118
108
104
106
123
105
55
109
124
10126
58
127
1212840
125
8122
60
120
9
57
17
63
5
34
3
41
15
59
14
42
13
39
1
66
2
68 2335 4436 243738 25 4526
62
27 462829 473031 4932
93
33 505152
12169
112
43645322 615418
64
65
67
192021
IRQ
1G
P10
IRQ
3IR
Q4
GP
11
IRQ
5
KD
AT
IRQ
6
GP
12
IRQ
7IR
Q8
GP
13
IRQ
10
PD
0
IRQ
11/RO
MC
S#
GP
14
IRQ
12
GP
15
KC
LK
TX
D1
MD
AT
PD
1
MC
LK
VSS
KB
DR
ST
#
PD
2
A20M
RT
S1#/S
YS
OP
PD
3
RD
AT
A#
PD
4
CT
S1#
PD
5
VSSP
D6
DT
R1#
PD
7
DA
CK
1#
SLC
TIN
#
DS
R1#
PIN
IT#
VSS
ALF
#
DC
D1#
ST
RO
BE
#
WG
AT
E#
BU
SY
RI1#
AC
K#
VSS
PE
RX
D2/IR
RX
SLC
T
DR
Q0
ER
RO
R#
TX
D2/IR
TX
WD
AT
A#
RT
S2#
DA
CK
2#
CT
S2#
HD
SE
L#
DT
R2#
SE
R/IR
Q15
DS
R2#
DIR
#
DC
D2#
DA
CK
3#
RI2#
ST
EP
#
DR
Q1
DS
KC
HG
#
TC
DS
0#
SA
11
MT
R0#
IOR
#
WR
TP
RT
#
DR
Q2
TR
K0#
IOW
#
IND
EX
#
PC
I_CLK
/IRQ
14/GP
50
DR
VD
EN
0
XT
L1
DR
VD
EN
1
XT
L2
SA
0
SA
12
SD
0
SA
13
SA
1
SA
14S
A15
SA
2
SD
1
SA
3
VCC
SA
4
SD
2
SA
5S
A6
SD
3
SA
7S
A8
SD
4
SA
9
VCC
SA
10
SD
5S
D6
SD
7
VCCVTR
RX
D1
AE
NIO
CH
RD
YR
ES
ET
_DR
V
CLO
CK
14
DR
Q3
DA
CK
0#
CLK
32OU
T
DS
1#
MT
R1
VBAT
AVSS
POWERONBUTTON_INPME#/IRQ9
R407
10K
U38
TF
DU
4100-TR
3
123 45
67
8
IRE
D A
nodeIR
ED
Cathode
Txd
Rxd
NC
Vcc1/S
DS
CG
ND
R408
14
C365
0.1uF
C368
4.7uF tant.
R409
47
C364
0.1uFC
3660.1uF
C374
0.1uF
C363
0.1uF
AA
BB
CC
DD
EE
44
33
22
11
ISA Slot(s)
Note Cap Direction
Note Cap Direction
ISA Connector
A
Celeron P
rocessor Based T
T S
ample D
esign
Intel Em
bedded Microprocessor D
ivision
5000 W. C
handler Blvd.
Chandler A
Z. 85226
C
2934
Title
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
SA
7
SA
15
SD
12
SA
19
SA
12
SD
11S
D10
SA
5
SD
8
SA
[19:0]
SA
16
SA
8
SD
14S
D13
SD
1
LA2
1
SD
[15:0]
SA
0
SA
3S
A4
SA
10
LA2
3
SA
2
SA
6
SA
13
SD
0
SD
4
LA2
2
LA[23:17]
SA
14
SD
15
LA1
8
SA
17
LA2
0
SD
7
SA
1
SD
3
SD
5S
D6
SA
9
SA
11
SA
18
SD
9
LA1
7
SD
2
LA1
9
SA
[19:0]9,17,28,32,33
SD
[15:0]9,17,28,32LA
[23:17]9,17
IRQ
1110,17,32
AE
N9,28,32
DA
CK
1#10,28
IRQ
310,17,28,32
DR
Q3
10,17,28
IRQ
1010,17,25,28,32
DA
CK
2#10,28
RS
TD
RV
9,11,28,32
DA
CK
6#10
IRQ
1210,17,28
IRQ
610,17,28,32
DR
Q7
10,17
DR
Q6
10,17D
AC
K7#
10
DA
CK
0#10,28
IRQ
1410,11,17,28
RE
F0
10,14,32
TC
10,28,32
SB
HE
#9,17
DR
Q0
10,17,28
ME
MC
S16
#17
ME
MR
#9,17,33
SM
EM
W#
17
MA
ST
ER
16#
17
DA
CK
5#10
IOW
#9,17,28,32
IOC
S16#
9,17
SM
EM
R#
9,17
ZE
RO
WS
#9,17
IOC
HK
#9,17
DR
Q5
10,17
IRQ
1510,17,25,28
SY
SC
LK9
DA
CK
3#10,28
IRQ
710,17,28,32
ME
MW
#9,17,33
DR
Q2
10,17,28
IRQ
910,17,25
IOC
HR
DY
9,17,28
IRQ
510,17,25,28,32
RE
FR
ES
H#
9,17D
RQ
110,17,28
BA
LE17
IRQ
410,17,25,28,32
IOR
#9,17,28,32
V-12P
0V
12P0
V-5P
0
V-5P
0
V12P
0V
-12P0
V5P
0
V5P
0
C384
0.1uFC
3760.1uF
C383
0.1uFC
3800.1uF
C378
0.1uFC
375
10uF
C382
0.1uFC
37910uF
C377
10uF
C381
10uF
J20
ISA
Conn A
B01
C01
B02
A02
B03
C02
B04
A03
B05
C03
B06
C04
B07
A04
B08
B09
C05
B10
A05
B11
C06
B12
A06
B13
C07
B14
B15
A07
B16
C08
B17
C09
B18
A08
B19
C10
B20
A09
B21
C11
B22
B23
C12
B24
A10
B25
C13
B26
A11
B27
C14
B28
B29
A12
B30
C15
B31
C16
D01
A13
D02
C17
D03
A14
D04
A15
D05
C18
D06
A16
D07
D08
A17
D09
A18
D10
A19
D11
D12
A20
D13
A21
D14
A22
D15
D16
A23
D17
A24
D18
A01
A25
A26
A27
A28
A29
A30
A31
GN
D
SB
HE
RS
TD
RV
SD
7V
5P0
LA23
IRQ
9S
D6
-5V
LA22
DR
Q2
LA21
-12V
SD
5
0WS
+12V
LA20
GN
D
SD
4
SM
EM
W
LA19
SM
EM
R
SD
3
IOW
LA18
IOR
DA
CK
3
SD
2
DR
Q3
LA17
DA
CK
1
ME
MR
DR
Q1
SD
1
RE
FR
ES
H
ME
MW
CLK
SD
0
IRQ
7
SD
8
IRQ
6IR
Q5
SD
9
IRQ
4
IOC
HR
DY
IRQ
3
SD
10
DA
CK
2
AE
N
TC
SD
11
BA
LEV
5P0
SA
19
OS
C
SD
12
GN
D
SD
13
MC
S16
SA
18
IOC
S16
SD
14
IRQ
10
SA
17
IRQ
11
SA
16
IRQ
12
SD
15
IRQ
15
SA
15
IRQ
14D
AC
K0
SA
14
DR
Q0
SA
13
DA
CK
5
SA
12
DR
Q5
DA
CK
6
SA
11
DR
Q6
SA
10
DA
CK
7
SA
9
DR
Q7
V5P
0
SA
8
MA
ST
ER
SA
7
GN
D
IOC
HC
K
SA
6S
A5
SA
4S
A3
SA
2S
A1
SA
0
AA
BB
CC
DD
EE
44
33
22
11
COM0/COM1
FLOPPY
COM1
COM0
Pin 5 is the Key
PARALLEL
I/O Connector
A
Celeron P
rocessor Based T
T S
ample D
esign
Intel Em
bedded Microprocessor D
ivision
5000 W. C
handler Blvd.
Chandler A
Z. 85226
C
3034
Title
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
SP
_RI0
SP
_DT
R0
SP
_DC
D0
SP
_RX
D0
SP
_CT
S0
SP
_TX
D0
SP
_DS
R0
SP
_RT
S0
SP
_CT
S1
SP
_DS
R1
SP
_TX
D1
SP
_RI1
SP
_DT
R1
SP
_RX
D1
SP
_DC
D1
SP
_RT
S1
PD
R6
-INIT
PD
R0
PD
R7
PD
R4
PD
R5
SLC
T
PD
R3
-ER
R
-ST
RO
BE
-ALF
-AC
K
PD
R1
-BU
SY
PE
PD
R2
-PA
LF
PP
DR
7
-PS
LCT
IN
PP
DR
1
PP
SLC
T
-PP
ER
R
-PS
TR
OB
E
PP
DR
0
PP
E
PP
DR
5
PP
DR
3
PP
DR
2
-PP
BU
SY
PP
DR
6
-PP
INIT
-PP
AC
K
PP
DR
4
-RD
AT
A28
-WP
T28
-IND
EX
28
-SID
E1
28-D
SK
CH
G28
HD
EN
28
-MO
TE
A28
-DIR
28
DR
AT
E0
28
-DR
VS
A28
-WG
AT
E28
-WD
AT
A28
-ST
EP
28
RX
D0_J
31
TX
D0_J
31C
TS
0#28
DT
R0#_J
31R
I0#28
DC
D0#
28D
SR
0#28
RT
S0#
28
-TR
K0
28
RX
D1
28
RI1#
28D
TR
1#28
RT
S1#
28
CT
S1#
28
DS
R1#
28
TX
D1
28
DC
D1#
28
-MO
TE
B28
-DR
VS
B28
PD
R4
28
PD
R7
28
-ST
RO
BE
28
PE
28
PD
R2
28
PD
R5
28
-INIT
28
-BU
SY
28
PD
R0
28
PD
R3
28
PD
R6
28
-SLC
TR
IN28
-ER
R28
SLC
T28
-ALF
28
-AC
K28
PD
R1
28
V-12P
0
V5P
0
V5P
0V
5P0
V12P
0V
12P0
V-12P
0V
-12P0
V12P
0
V-12P
0
V5P
0
V12P
0
V5P
0
V5P
0
U39
GD
75232SO
P
120
234567891012 13 14 15 16 17 18 1911
+12VV
5P0
RA
1R
A2
RA
3D
Y1
DY
2R
A4
DY
3R
A5
-12VR
Y5
DA
3R
Y4
DA
2D
A1
RY
3R
Y2
RY
1
GN
D
JP10
FLO
PP
Y H
EA
DE
R 17X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
J21
SE
RIA
L ST
AC
K
141813171216111510 594837261
141813171216111510 594837261
U40
GD
75232SO
P
120
234567891012 13 14 15 16 17 18 1911
+12VV
5P0
RA
1R
A2
RA
3D
Y1
DY
2R
A4
DY
3R
A5
-12VR
Y5
DA
3R
Y4
DA
2D
A1
RY
3R
Y2
RY
1
GN
D
C394
470pF
C399
470pF
RP
34
4.7K
1 82 73 64 5
C397
470pF C393
470pFC
396470pF
J22
DB
25
13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
C398
470pF
C395
470pF
C420
220pF
C419
220pF
C403
220pF
C417
220pF
C418
220pF
C400
470pF
C404
220pF
C415
220pF
C421
220pF
C422
220pF
C391
220pF
C392
220pF
C402
220pF
C414
220pF
C387
0.1uFC
3900.1uF
C386
0.1uF
C416
220pF
C389
0.1uFC
3880.1uF
C385
0.1uF
C401
220pF
C407
470pF
C411
470pF
C406
470pF
C413
220pF
C408
470pF
C410
470pF
C405
470pF
C412
470pF
R413
1K
RP
32
4.7K
1 82 73 64 5
RP
31
4.7K
1 82 73 64 5
C409
470pF
RP
36
33
18
27
36
45
RP
33
4.7K
1 82 73 64 5
RP
39
22
18
27
36
45 R411
4.7K
RP
35
22
18
27
36
45
RP
38
1K
18273645
RP
37
33
18
27
36
45
R412
22
A A
B B
C C
D D
E E
44
33
22
11
THESE JUMPERS ARE USED TO
SWITCH BETWEEN COM0 AND TOUCH
SCREEN. PLACE A JUMPER ON 1-2
FOR TOUCH SCREEN 2-3 FOR COM0
Touch Screen Controller
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
3134
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
TX
D0
28
RX
D0
28
DT
R0#
28
DT
R0#
_J30
RX
D0_
J30
TX
D0_
J30
V3P
3
V3P
3
V3P
3
C42
622
pF
U41 TR
88L8
03
1 2 3 4 5 6 7 8910111213141516
AV
D
VR
EF
AD
C_1
AD
C_2
VD
D
TX
D
VS
S
XT
ALI
NX
TA
L_O
UT
MU
X_S
EL
PD
_RS
T
AV
SX+X-
Y+Y-
Y7
1.84
32 M
Hz
12
C42
9
0.1
uF
C42
40.
1 uF
R41
4
100
K
J23
CO
N4
1234
C42
522
pF
C42
8
1uF
tant
.
R41
7
10K
+C
427
1uF
tant
.
R41
6
10K
Q13
PN
2222
R41
5
0 oh
m
R41
8
10K
R41
9
10K
+
C42
3
1uF
tant
.
R42
1
10K
R42
0
820
Q12
PN
2222
J26 JU
MP
3
1
2
3
J25 JU
MP
3
1
2
3
J24 JU
MP
3
1
2
3
A A
B B
C C
D D
E E
44
33
22
11
COM3
COM4
ADDRESS
DECODE
PLACE CLOSE TO VCC PINS
THIS SUPER I/O IS USED SOLELY TO
ADD SERIAL PORTS TO THE BOARD.
PULLING DOWN SYSOPT
CONFIGURES 669 TO 3F0h
Additional Serial Ports
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
3234
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
nDS
KC
HG
69IR
RX
269
DA
CK
C
nTR
K00
nRD
AT
A
SA
2
IRQ
IN
69P
E
SD
6
SA
0
SA
9
nRD
AT
A
SA11
nWR
TP
RT
69P
E
nAC
K
IRQ
IN
nTR
K00
SA
1
SA
3
SA
10
69B
US
Y
69B
US
Y
nDS
KC
HG
SA
7 69D
AC
KC
SD
3
SD
5
SA
5
SD
1
SD
4
SA
6
SA
8
69IR
RX
2
nWR
TP
RT
69D
AC
KA
nIN
DE
X
SD
2
SA14SA15
nIN
DE
X
SA
4
nER
RO
R
nER
RO
R
69D
AC
KA
69D
AC
KB
SLC
T
nAC
K
SA12
SLC
T
SD
0
69D
AC
KB
SA13
SD
7
SD
[15:
0]9,
17,2
8,29
AE
N9,
28,2
9
PW
RO
K5
33
SA
[19:
0]9,
17,2
8,29
,33
IOR
#9,
17,2
8,29
IOW
#9,
17,2
8,29
RE
F0
10,1
4,29
IRQ
510
,17,
25,2
8,29
TC
10,2
8,29
IRQ
1010
,17,
25,2
8,29
RS
TD
RV
9,11
,28,
29
IRQ
710
,17,
28,2
9
IRQ
1110
,17,
29
IRQ
410
,17,
25,2
8,29
IRQ
310
,17,
28,2
9
IRQ
610
,17,
28,2
9
+12
V
-12V
V5P
0
V5P
0
V5P
0
-12V+1
2V
V5P
0
V5P
0
C43
947
0pF
RP
40
10K
18
27
36
45
C44
047
0pF
U43
74H
C40
75D
12 345
6
7
8
9
10
11 12 13
14
2A2B 1A1B1C
1Y
GND
2C
2Y
3Y
3A 3B 3C
VCC
C44
147
0pF
C44
247
0pF
C44
347
0pF
C43
547
0pF
C44
647
0pF
C43
0
0.1u
F
C44
547
0pF
R42
2
1K
U44
GD
7523
2SO
P
120
2 3 4 5 6 7 8 9 101213141516171819 11
+12V
V5P
0R
A1
RA
2R
A3
DY
1D
Y2
RA
4D
Y3
RA
5-1
2VR
Y5
DA
3R
Y4
DA
2D
A1
RY
3R
Y2
RY
1
GN
D
J27
SE
RIA
L S
TA
CK
14 18 13 17 12 16 11 15 105 9 4 8 3 7 2 6 1
14 18 13 17 12 16 11 15 105 9 4 8 3 7 2 6 1
C44
747
0pF
U42
FD
C37
C66
9
46 21 52 99 22 36 963544 451572
6476795
1 18 2 4 35 7 8 9 10 11 12 13 14 16 17 7879 8081828384 85 8889 9091929386 87
48 49 50 51 53 54 55 56 28 29 30 31 32 33 34 41 42 43 97 19 37 38 39 4027 57
73 74 75 76 77 59 60 61 62 63 64 65 66 68 69 70 71 100
2324 25 26 2094
58
98
AE
N
DR
Q_A
DR
Q_B
DR
Q_C
nDA
K_A
nDA
K_B
nDA
K_C
TC
nIO
RnI
OW
VCCVCC
GNDGNDGNDGND
DR
VD
EN
0D
RV
DE
N1
nMT
R0
nDS
1nD
S0
nMT
R1
nDIR
nST
EP
nWD
AT
AnW
GA
TE
nHD
SE
LnI
ND
EX
nTR
K00
nWR
TP
RT
nRD
AT
AnD
SK
CH
G
RX
D1
TX
D1
nDS
R1
nRT
S1
nCT
S1
nDT
R1
nRI1
nDC
D1
RX
D2/
IRR
X
TX
D2/
IRT
X
nDS
R2
nRT
S2/
SY
SO
PT
nCT
S2
nDT
R2
nRI2
nDC
D2
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
IRQ
_A
IRQ
_CIR
Q_D
IRQ
_EIR
Q_F
nCS
RE
SE
T
nSLC
TIN
nIN
ITnE
RR
OR
nAU
TO
FD
nST
RO
BE
SLC
TP
EB
US
YnA
CK
PD
0P
D1
PD
2P
D3
PD
4P
D5
PD
6P
D7
IOC
HR
DY
IRQ
IN
nID
EE
N/IR
Q_H
NH
DC
S0/
IRR
X2
nHD
CS
1/IR
TX
2IC
LK
DR
V2/
nAD
RX
/IRQ
_B
PWRGD/nGAMECS
NC
C43
247
0pF
C43
1
0.1u
F
U45 GD
7523
2SO
P
120
2 3 4 5 6 7 8 9 101213141516171819 11
+12V
V5P
0R
A1
RA
2R
A3
DY
1D
Y2
RA
4D
Y3
RA
5-1
2VR
Y5
DA
3R
Y4
DA
2D
A1
RY
3R
Y2
RY
1
GN
D
C43
647
0pF
C43
747
0pFC
433
470p
FC
434
470p
F
C43
847
0pF
C44
447
0pF
A A
B B
C C
D D
E E
44
33
22
11
BIOS
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
3334
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SA
2
SA
13
SA
16
SA
11
XD
0
SA
4
SA
17
SA
14
XD
3
SA
7S
A8
SA
12
SA
6
XD
1X
D2
SA
9
SA
15
XD
4
XD
7
SA
0
XD
6
SA
1
SA
3
SA
5
SA
10
XD
5
SA
[19:
0]9,
17,2
8,29
,32
ME
MR
#9,
17,2
9
PW
RO
K5
32
BIO
SC
S#
10
XD
[7:0
]9
ME
MW
#9,
17,2
9
V5P
0
V12
P0
V5P
0V
12P
0
C44
90.
1uF
U46
28F
002B
C
1231 139
3730 3825 39
24
23
21 22
26
1020
2719
2818
3217
3316
3415
3514 8 7 36 6 5 4 3 2 1 40
11
NC
VC
C
NC
WE
#N
C
VC
C
NC
DQ
0
GN
D
OE
#
GN
D
A0
CE
#
DQ
1
RP
#
A1
DQ
2A
2
DQ
3A
3
DQ
4A
4
DQ
5A
5
DQ
6A
6
DQ
7A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17
VP
P
J29
HD
R3
1
2
3
C45
00.
1uF
J28
1x3
1
2
3
C44
80.
1uF
A A
B B
C C
D D
E E
44
33
22
11
Make these connections Cutable
Make these connections Cutable
Make these connections Cutable
Make these connections Cutable
Make these connections Cutable
Make these connections Cutable
Unused Gates
A
Cel
eron
Pro
cess
or B
ased
TT
Sam
ple
Des
ign
Inte
l E
mbe
dded
Mic
ropr
oces
sor
Div
isio
n
5000
W. C
hand
ler
Blv
d.C
hand
ler
AZ
. 852
26
C
3434
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
V5P
0
V3P
3
5VS
B
V5P
0
V5P
0
V5P
0
U47
B
74H
CT
14
34
14 7
U47
A
74H
CT
14
12
14 7
C45
10.
1uF
U50
C
74A
CT
05
56
14 7
U50
A
74A
CT
05
12
14 7
U50
B
74A
CT
05
34
14 7
U51
D
74H
CT
14D
98
U51
E
74H
CT
14D
1110
U49
A
74LC
T14
12
14 7
U20
F
74A
CT
04
1312
14 7
U48
A
74LC
T14
12
14 7
U22
D74
HC
T12
5
1211
14
13
7
U51
A
74H
CT
14D
12
14 7
U51
C
74H
CT
14D
56
14 7
U51
B
74H
CT
14D
34
14 7
U22
C74
HC
T12
5
98
14
10
7