Interactive two-dimensional design of barrier-controlled MOS transistors

1550 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8 , AUGUST 1980

tions to the two-dimensional dc and transient problems,” Ph.D. lation to electric field and temperature,” IEEE Trans. Electron dissertation, University of Southampton, Southampton, England, Devices, vol. ED-22, pp. 1045-1047, 1975. 1976. [33] H. Brooks, “Theory of the electrical properties of germanium and

[31] .I. F. Hart, E. W. Cheney, C. L. Lawson, H. J. Maehly, et al . , silicon,” in Advances in Electronics and Electron Physics, vol. I , Computer Approximations. New York: Wiley, 1968. 1955, pp. 85-182.

[32] C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and [ 3 4 ] P. P. Debye and E. M. Conwell, “Electrical properties of n-type hole drift velocity measurements in silicon and their empirical re- germanium,” Phys. Rev., vol. 93, pp. 693-706, 1954.

Interactive Two-Dimensional Design of Barrier- Controlled MOS Transistors

SALLY LIU, BERNARD HOEFFLINGER, MEMBER, IEEE, AND DONALD 0. PEDERSON, FELLOW, IEEE

Absrruct-An interactive program has been developed for the graphic generation and the solution of two-dimensional impurity, carrier, potential, and field distributions in small-geometry MOS transistor con- figurations. Emphasis is placed on conversational operation and three-dimensional display on a graphics terminal with a generation rate, for any self-consistent two-dimensional solution, of less than few min- utes for each computation and drawing. Although this limited the approach to a solution of the potential problem only, the barrier- controlled characteristics in weak inversion and weak injection (punchthrough) are produced efficiently and provide quantitative data for slopes, threshold voltages, and punchthrough voltages, as well as their two-dimensional dependence on device geometry, doping, and terminal voltages. Examples are presented for NMOS transistors with various enhancement and buried channel implants. The program is useful both as a pre-selector for structures to be simulated with a more elaborate two-dimensional potential and transport program and as a generator of parameters for a device model in a circuit simulator.

W I. INTRODUCTION

ITH DECREASING transistor dimensions, it has become more difficult to describe MOS transistors with

equations that are simple enough for hand calculations or pro- grammable calculators and yet retain sufficient accuracy to provide useful information about the device characteristics [ l ] . Since transistor models are used widely in circuit simulators, device models compatible with these simulators have

Manuscript received December 5, 1979; revised March 27, 1980. This work was supported in part by Nixdorf Computer, Pederborn, and the Bundesministerium fur Forschung und Technologie, Bonn, Germany, and by Hewlett-Packard Company and Signetics Corporation. S. Liu and D. 0. Pederson are with the Department of Electrical Engi-

neering and Computer Science, University of California, Berkeley, CA 94720.

B. Hoefflinger is with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, on leave from the University of Dortmund, Dortmund, Germany.

received widespread attention. Current-charge-voltage equations with sets of “device parameters” are often used [2], [3]. Look-up tables for current, capacitance, and voltage have become a feasible alternative when dealing with large circuits [4] , [S I . Both types of transistor representations require either available device data with parameters extracted from them [ 6 ] , [7], or parameter estimates obtained from one- dimensional or pseudo-one-dimensional physical models of the transistors [ 11 .

For the design of a new generation of transistors, an im- proved form of computer-oriented modeling is required. The numerical solution of the two-dimensional potential and transport equations can describe integrated field-effect transistors, and significant contributions to this problem have evolved over the past ten years [ 8 ] - [ l o ] . In this activity, initially, idealized impurity distributions and boundaries have been assumed to facilitate solutions. However, with very small device geometries, modern process simulators show extremely inhomogeneous two-dimensional impurity distribution and shaped boundaries, which must then be considered in the potential and transport solution.

One way in attacking this complex problem is the use of very capable maxicomputers, selecting a sample situation, and developing a solution with every possible effect included. Yet what is needed even here is a more limited computer program which is efficient enough to offer quick solutions at the designer’s desk. In particular, a rapid interactive design capacity needs to be established including two-dimensional device geometries, impurity distributions, and solutions for at least the most important device characteristics.

In the work reported here, program TWIST (Two-dimensional Interactive Simulation of MOS Transistors) is developed based on a minicomputer together with a graphics terminals.

0018-9383/80/C 800-1550$00.75 0 1980 IEEE

LIU e t a l . : DESIGN OF BARRIER-CONTROLLED MOS TRANSISTORS 1 5 5 1

The program with this environment offers the desired hgh- speed interactive features and also handles the three-dimensional representation of all data. For proper comprehension and interpretation of the results, a two-dimensional solution is available to the designer at the terminal within a few min- utes. At present, this requirement limits the solution to that of the two-dimensional impurity and potential distribution, in other words, to the handling of the weak-inversion or weak- injection approximation for an MOS transistor. Although the speed of computation can be very slow and the high-speed graphics display may not be available, as is shown in [ l 11 , even a desk-top calculator program can handle this problem.

The present paper describes a two-dimensional model of MOSFET’s and the associated Fermi-level approximation in Section 11, algorithms and program structure in Section 111, and some examples in Section IV.

It is demonstrated that weak-inversion characteristics as well as weak-injection punchthrough characteristics, where the control of a potential barrier is essential, can be simulated in a highly illustrative and efficient way. Available results include the weak-inversion characteristics and the weak-injection punchthrough characteristics, and in particular, their dependence upon geometry, impurity distribution, and drain voltage. Since VLSI devices are geared towards low-voltage low-power application, these Characteristics are becoming most critical. In the concluding section, Section V, an identification is made of the position of this program in a CAD “tool box” of process simulators [ 121, [ 131 as well as large-size two-dimensional device simulators [14], [15] and circuit-oriented simulators P I 4 5 1 .

11. TWO-DIMENSIONAL POTENTIAL MODEL Several assumptions have to be made to prepare a solution

of the two-dimensional Poisson equation. One is the problem of quasi-Fermi-level assignment. This is treated in Section 11-A. Another assumption is related to initialization, which is necessary for a two-dimensional solution. This aspect de- termines convergence speed to a large degree. An approach anticipating major two-dimensional effects is proposed in Sections 11-B and 11-C.

.4. Potential Distribution Under Weak-Inversion andlor Weak-Injection Conditions

A self-consistent solution of the two-dimensional Poisson equation takes the electrons and holes into account based upon the Boltzmann approximation. However, a restriction is made that electron flow takes place only because of diffusion. This yields an electron quasi-Fermi level EFN which is re- gionally constant and is located either at the source, the substrate, or the drain bias. This aspect is illustrated in Fig. 1, which shows schematically the band diagram of an enhancement n-channel transistor. The electron quasi-Fermi level EFN is at the source level until, at any given depth y , the partial derivative of the electron energy in the x direction becomes negative, in other words, the partial derivative of the potential cp becomes positive, a further deviation by kT/q is considered to be the boundary of the drain-controlled depletion region. Beyond this point EFN is assigned to the drain level. In the free-carrier distribution, this transition will cause

Seutral Substrate

Fig. 1. Schematic band diagrams of an enhancement n-channel MOSFET.

the electron density to drop abruptly where drain control sets in. Actually, any electron density, injected from the source, would drop linearly (in the absence of recombination) to the boundary of drain control.

In the weak-inversion and/or the weak-injection regime, the drain current is mainly a diffusion current injected from the source across the regional potential barrier and collected by the drain. So the current is formulated as

where WB is the “base width,” qB and q s ~ c are the local barrier and the source potentials, respectively. Given a self- consistent potential distribution, knowing the regional barrier potential at the interface, in the buried-channel or the saddle potential at the punchthrough ridge, and its “base width,” the drain diffusion current can be calculated. In small structures, this barrier may just be a point on the potential profile. The “base width” and the depth of the cross section should then be calculated to be that length, over which the potential differs by one or two kT/q from the barrier. Although this leaves the base width ambiguous to some extent, the most significant factor in the current is the exponential term. As is shown in Section IV, the larger part of design optimization rests on the control of the various local barrier potential.

B. Field-Line Model for a Surface-Channel Transistor As mentioned earlier, the convergence of any two-dimen-

sional iteration procedure depends strongly upon the initialization. Initialization is performed by assigning the initial values under some assumptions. The regions close to the source and the drain are critical in this respect. Approxima- tions used to initialize the surface potential in these regions can be:

a) one-dimensional depletion layer same as the source-

b) same as a), but including junction curvature effects on

c) one-dimensional depletion layer with enhanced field

d) approximate the variation of surface potential versus the

and/or the drain-substrate junction;

the width of the depletion layer [ 161 ;

gradient to simulate a graded surface junction [17] ;

distance from the junction as

cps = a (X - X,)” (2)

where n > 2 is an empirical fitting parameter [ 101 . The theory proposed here is based on the consideration of

1552 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980

(C) Fig. 2. (a) Field-line distribution at the surface close to the junction of an enhancement n-channel MOSFET. (b) Potential distribution along field lines, AA', BB', and CC'. (c) Electric-field distribution along field lines AA', BB', and CC'.

the field-line distribution. It is used in the program TWIST to allocate the surface-depletion regions close to the source and the drain junctions. Fig. 2(a) is intended to illustrate the situation. Field lines are drawn schematically in the region close to the drain for the condition VD > VG. Very close to the ' drain, field lines are very short and are terminated directly on the gate with the field in the silicon having a very Fiignificant x-component. For increasing distance x from the junction, the field falls off very rapidly with an additional drop along each field line due to the impurity space charge. ,Oxide thickness, junction depth and impurity concentration enter into the field distribution with the significant property that field lines terminate mostly on the gate and not, as gener- ally assumed in recent literature, on analytical models, on the hpurit ies alone. This region is bounded by a field line result- ing in zero field at the surface. For the following considerations, the corresponding coordinate X D at the interface is .defined as where cps(XD) = V,. This condition is also shown as Case BB' in the schematic plot of potential and field along given field lines as in Fig. 2@) and (c), respectively. Outside of line BB', the field lines have gate- and drain-controlled sections as illustrated by the line string between C and C'. As shown in Fig,' 2(b), a potential minimum is encountered along this line. When this assumes the special value, cp = 0, gate- and drain- controlled regions are separated by a neutral substrate region. The domain BB'C'Cis difficult to handle in simple terms.

However, the high-field region inside BB' is found to be tractable in the following way. Field lines are circular only in the immediate vicinity of the drain junction. With increasing distance, they become elliptical with the long axis parallel to the gate. Suppose that neutral drain depth is YD for a given drain bias VD and that line BB' emerges from this depth. Its length hOM in the silicon is such that

v=.vD t vB1- vG =- qNEFF 2ESi

(3)

For a linear approximation,

x, = d m . (4)

For all Y < Y D and X < X,, field lines are approximated so that a line emerging at Y and cutting the interface at X will have a length ho such that

ho = d m and

Y @ = -

X (6)

where

For a given X < X D

ho = X d M . In this region X < X D

with

v- v, TOX + - ho

EH,OX = €OX

ESi

This approximation for the surface potential in the high-field region takes into account the oxide thickness ToX, the junction depth via Yo , and the effective impurity concentration NEFF. It simulates the steep field increase near the drain, which is critical in the numerical analysis, as initializations like case d) above brought out. Outside of BB', linear extrapola- tion of cps t o the one-dimensional value cpso can provide ade- quate initialization. Nonetheless, a more sophisticated ap- proash may be appropriate, in particular, if the situation of merged punchthrough is encountered. At this time, array initialization as explained in Section I11 proved to be more important.

The buried-channel configuration is essentially different. However, a basically similar approach is presented in the following section.

C. Field-Line Model for a Buried-Channel Transistor Fig. 3(a) shows the schematic cross section of an n-type

buried-channel transistor. Again, field lines have been inserted schematically for the vicinity of a source or a drain junction. In comparison with the surface-channel case, the apparent difference is that the field lines in both the gate- and the drain- controlled regions are directed towards the interface. These field lines would actually be elliptical, with the short axis along

4 i I B'

(C) Fig. 3. (a) Field-line distribution at the surface close to the junction of

a depletion n-channel MOSFET. (b) Potential distribution along two field lines. (c) Field distribution along two field lines.

the interface. A circular approximation exaggerates the length X D of drain control. The potential and the field along two different field lines are shown schematically in Fig. 3(b) and (c). The length in the silicon is approximated as

If the implanted dose in the silicon is Qz and the associated depth in Y B , an effective implanted density N I M p is defined as

The associated space-charge causes a voltage drop VC along ho

and a voltage across the insulator

The total voltage difference between gate and drain is assumed to be

v = VD + VBZ- VC (17)

where VBz is the voltage built into the n+-n junction. Drain control is limited to a field line of maximum length XOM

So far, if

the drain-controlled surface potential initialization has been extended to X , 5 YB only. This- proved to be sufficiently good for a start, because the essential problem, a sharply rising field close to the drain, is covered well by the model. For

Mini-Computer

Fig. 4. System setup block diagram.

any A. < hOM, V consists of four components

with

&OX EH, OX = &Si EH, Si.

The surface potential

He re

111. PROGRAM DESCRIPTION Program TWIST requires 65K 16-bit words on a Hewlett-

Packard 1000 F-series computer of whch 32K are used for the EMA (Extended Memory Area) feature of the HPlOOO system to handle the data arrays. The present system setup is shown in Fig. 4. The HP2648A graphics terminal provides interactive communication with the user, and three-dimensional displays of the simulation results. These results also can be drawn on a four-color plotter HP9872A and/or a graphics hard copy unit.

The following device structures can be handled:

a) conventional MOSFET's with uniform substrate; b) enhancement and depletion MOSFET's with single or

c) MOSFET's with nonsymmetric channel implant. double channel implants;

The oxide covering the device to be simulated may have non- uniform thickness. The gate electrode can be arbitrarily located. A typical cross section is shown in Fig. 5(a).

A general program flowchart is shown in Fig. 5(b). The mesh is set up based upon the geometry specifications. Up to three ion-implantation steps can be used to tailor the impurity profile. The two-dimensional impurity redistribution, due to later high-temperature process steps, is generated using analytical expressions [ 181 . The error function in the expression is evaluated by its polynomial approximation. After the bias condition is given, the potential is initialized self-consistently along the direction vertical t o the surface. The user may modify the initial potential distribution but the autoinitializa- tion has performed well in most cases tried to date. Fig. 6 shows the initial and final negative potential distributions, which are directly proportional to the electron energy, of a

1 5 5 4 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980

set-up mesh . geometry info i

generate impurity process info profile

initialization

' modification user mods

2-3 self-consistent i

Y I device charact

(b) Fig. 5. (a) Typical cross section of the simulated MOSFET structure.

(b) Flowchart of program TWIST.

(b) Fig. 6 . (a) Auto-initialized negative potential distribution. (b) Re-

sultant negative potential distribution.

O.8-pn1 device with channel implant, and biased at V, = 0.1 V, VD = 5 V, VS = V, = 0 V. The self-consistent two-dimensional potential distribution is then solved using an iterative approach. The resultant potential, field, and free-carrier distributions can be displayed either quantitatively in two dimensions or graphically in three dimensions. The surface- and the punchthrough-barrier potentials, the injection locations, and the surface-depletion regions are characterized.

A. Basic Equations The program has been tailored to achieve high-speed simula-

tion of low-current operation of MOSFET's, i.e., either weak inversion or weak injection. Under the condition of weak inversion and/or weak injection, the transport equation can be ignored. Negligible electron-hole recombinations are assumed. The equations describing the physical mechanism within the device are

v 2 q = - - 4 [ N D - N A tP- n] (23) esi

n = e ( q / k T ) ('P-9FN) (24)

( 2 5 )

NSUB

p = NsUBe-(q/kT)('P-9FP).

The first equation is the Poisson equation for potential cp. The last two equations are the electron and the hole densities using Boltzmann statistics. The variables ~ F N and q ~ p are the quasi- Fermi levels for the electrons and holes, respectively.

B. Boundary Conditions The potential in the neutral substrate is selected to be the

reference potential in the program. The potentials in the neutral source and drain regions are

qSRC/DRN = VBZ vAPP (26)

where VBz is the built-in voltage across the source- or the drain-substrate junction. VApp is the reverse-bias voltage ap- plied to the junction. Fig. 7 is the cross section of a device with boundary conditions specified. The two boundary planes at the left and the right are allocated at a point where the potential distribution can be well characterized by the one- dimensional Poisson equation. The potentials at these two planes are the one-dimensional self-consistent solution of Poisson equation, with boundary conditions such that the potentials at points A and B are ~ ~ S R C ~ R N , respectively, and the potentials at points C and D are zero. The lower boundary plane is allocated inside the neutral substrate where the potential is zero. The top boundary plane consists of the gate electrode and the uncovered oxide. The boundary condition at the gate electrode is well defined by the gate voltage. The boundary condition at the uncovered oxide is defined such that the surface field has zero vertical component, equivalent to assuming there is no space charge resting on top of the oxide.

C. Potential Initialization In the initialization of low VDS case, the whole structure is

divided into five vertical domains based on the field distribution, as shown in Fig. 8(a)

LIU et al.: DESIGN OF BARRIER-CONTROLLED MOS TRANSISTORS 1 5 5 5

E y & : 0 cp;. / / E,=. 0 ~ ” G

SOURC

SUBSTRATE I

cp =: 0 I D IC

Fig. 7. Boundary conditions.

SOURCE ~ DRAl I DOMAIN 1

DOMAIN ! I DOMCI 4

CONTROLLED CONTROLLED SOURCE DRAIN

DEPLETlOh DEPL ETlON

(a)

(b) Fig. 8. (a) Cross section of a MOSFET, divided into five domains for

potential initialization. (b) Cross section of a MOSFET, divided into four domains for potential initialization at high VDS.

1) channel domain 2) source domain 3) drain domain 4) source-controlled depletion domain 5 ) drain-controlled depletion domain.

In the channel, the source, and the drain domains, the potential distributions are described by the one-dimensional Poisson equation, while in the source- and drain-controlled depletion domains, the potentials are two-dimensional functions of both x and y coordinates. The widths of the.source- and the drain- controlled depletion domains are estimated using the equations described in Section I1 based on the field-line model.

The self-consistent one-dimensional solutions are obtained for the channel, the source, and the drain domains. By using the potential solutions in these three domains as boundary conditions, the potentials in the source- and the drain- controlled depletion domains are assigned using the equation

for cp(x,y) lying between cpl ( y ) and cp2(y), and x between x1 and x2, where cpsl and cps2 are the surface potentials at the two boundary planes, respectively, and cpl and cp2 the potentials in the substrate. Whenever the expression gives a value beyond ( P ~ ( Y ) , CP (X, Y ) is clamped to ~2 (Y).

The potentials in the channel, the source, and the drain domains are solved with the following initial conditions:

a) In the source and the drain domains, the initial potentials are assigned based on the assumption of an abrupt junction

with a uniform substrate, and all of the depletion region is allocated in the substrate.

b) In the channel domain, the surface potential, of either enhancement or depletion channel is estimated using the approximate closed-form solutions of Poisson equation. The depth of the surface-depletion region is allocated and the potential assigned accordingly.

For devices with very short channel length and a moderate drain bias, the channel domain does not even exist. The drain- controlled and the source-controlled depletion domains merge together, as shown in Fig. 8(b). The following scheme is de- signed to initialize this extreme situation:

a) Clamp the drain-controlled depletion domain up to the source junction if falling beyond.

b) Assign the potential in the drain-controlled depletion domain using (27).

c) Define the middle point of the overlapping region as the boundary of the source-controlled depletion domain.

d) Use the already assigned potentials at the boundaries of the source-controlled depletion domain as boundary condition and assign the potential accordingly.

D. Iteration Scheme The Poisson equation in a five-point finite difference format

is solved by iteration. The Gauss-Seidel algorithm with a modified alternating direction implicit method is used. The mesh is always scanned column by column along the hori- zontal direction. But the scanning direction is alternated every other iteration loop to ensure the most recent iteration results are used to update the potential at the currently scanned mesh point. Using the potentials of the four nearest neighbors as boundary conditions, Newton-Raphson iteration is used to solve the potential at each point. Because the correlation is quite localized, the points which converge quickly are de- tected and skipped in the later iteration loops to enhance the computational speed. Typically, by the third iteration, about half of total mesh points are bypassed. More than two thirds of the mesh points are bypassed in the latest iteration loops. The computation time per iteration loop varies due to the by- pass scheme. The average computation time per two- dimensional iteration loop ranges from 1-2 s for a 50 by 50 mesh setup with 2-mV resolution.

IV. THE DESIGN OF SMALL-GEOMETRY MOSFET’s USING “TWIST”

Three examples are shown in this section to demonstrate the features of program TWIST.

Case 1): Enhancement MOSFET with Shallow Channel Implant

An enhancement MOSFET is chosen with drawn gate length of 1 pm. The actual channel length between the metallurgical junctions is 0.8 pm. The channel is implanted with boron of effective range in silicon = 0 pm, dose = 10” cm-2, the source and the drain are implanted with phosphorus of effective range = 0 pm, dose = 10’’ cm-’. The implants are followed by a drive-in step of 160 min at 960°C. The impurity profile is shown in Fig. 9(a). The junctions can be well identified, the side diffusions consume approximately one fifth of the mask channel length. Fig. 9(b) shows the negative potential distribu-

1 5 5 6 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8 , AUGUST 1980

DRAIN

(dl (e) Fig. 9. (a) Impurity distribution of an enhancement n-channel

MOSFET. @) Overall negative potential distribution. (c) Close-up look at the injection potential barrier. (d) Close-up look of the free- carrier distribution close to the source. (e) Magnitude of the electric field.

tion at the bias of V, = 0.1, V, = 5 , Vs = 0, and V, = 0. T h s is a situation with weak-punchthrough injection. Fig. 9(c) is a close-up look at the barrier where the saddle point in the potential profile is present. The close-up look of the free-carrier distribution close to the source junction is plotted on log scale in Fig. 9(d). The free carriers piled up around the injection barrier illustrate the punchthrough condition. Fig. 9(e) shows the distribution of the magnitude of the electrical field. The injection point can be identified as the location of minimum field.

Case 2): Comparison with Measured MOS Transistors The subthreshold current was simulated and measured for

NMOS transistors with T o x = 425 A and drawn gate lengths L = 2 pm. Arsenic source-drain junction depths were 0.225 pm, the substrate impurity concentration was 7 X 1014 CITY-^, the implanted channel dose was 3 X 10" cm-'. Simula1.ed and measured current for a substrate bias V, = - 2 V are shown in Fig. 10. The magnitude of the current, the slcpe,

tURREiuT VERSUS V G S W i T H P A R A M E T E R VDS

1 0 , . , , , , , . , , , , , 7 , I , , ,

and their dependence on VDs were simulated. The computed data show buried punchthrough components at large Vos which were. not observed in the experiments. These com-

LIU et al.: DESIGN OF BARRIER-CONTROLLED MOS TRANSISTORS 1557

B A H R I E R PSTENT~AL V E X S U S V G S WiTH PARAVETER VDS

A -0. 716

c -0.065 . 4 0

. 30.

. 2 B ~ *

.10 .

0. 0 m 1 N N N N N N i B r n I O - N N N I r n O I

, i

R vos-e. 1v 0 V O S P 1 "

V G S (Volts)

x v3s-zv T "Js-3"

Fig. 11. Barrier height versus VGS with parameter VDS, of the buried n-channel MOSFET.

a A R R i E R P O T E Y T T A L VERSClS L 3 S W i T H P A R A M E T E R VGS

. 7Or_, I

VL IS < ' g o i t s >

R VGS-m. 0" 0 YCS=O. 2" x vcs-0.5v

Fig. 12. Barrier height versus VDS with parameter VGS, of the buried n-channel MOSFET.

ponents are very sensitive to channel lengths. Increasing the simulated length by 0.1 pm would have a dramatic effect in improving the agreement.

Case 3): Buried-Channel MOSFET A buried-channel MOSFET similar to [15] was simulated

with a metallurgical channel length of 0.8 pm. Results are presented in Figs. 11 and 12. Three-dimensional plots are given in Fig. 13, where Fig. 13(a) shows a close-up of the impurity distribution including a double channel implant of shallow As and deeper B. Fig. 13@) shows a close-up of the buried potential barrier for VDS = 5 V. It is interesting to note that t h s barrier has a shape very similar to the punchthrough situation in Fig. 9(c). This indicates that in all submicrometer structures, barrier-control situations like the ones shown are very likely and that they are critical to the device operation. The magnitude of the buried barrier p ~ , is plotted in Fig. 11 as a function of VGS with VDS as a parameter and in Fig. 12 as a function of VDs with VGS as a parameter. An attempt was made to approximate the results with a barrier model

p ~ = p o + A X V G S t B X V ~ s - c x V ~ s x VDS. (28)

An acceptable match was obtained. Other simulations have shown that the VGS, VDS dependence of buried barriers fol- lows the rule that the slope of the p~(V,s) decreases as VDs increases and that the slope of p~(V,s) decreases as VGS increases with good applicability of the above approximation.

21 10

0. 0 0.571

(b) Fig. 13. (a) Impurity distribution of the buried-channel MOSFET.

(b) Close-up look at the injection potential barrier.

T h ~ s indicates that in small MOS transistor operations the drain-induced barrier lowering can be modeled by a linear dependence of barrier height on VDS or an exponential dependence of current on VDS as suggested by Troutman E191 with the refinement of a VGS X VDS term in the expression for the barrier potential p ~ . These characteristics merit further attention, because they relate t o the critical transition from pentode-like to triode-like characteristics in submicrometer transistors.

V. CONCLUSION A minicomputer-based two-dimensional simulation program

TWIST has been developed whch handles the weak-inversion and the weak-injection regimes of MOS transistors. These regimes are becoming increasingly important in low-voltage low-power MOS LSI designs. The use of program TWIST has been illustrated with particular attention to the problem of barrier control in small MOS transistors by different channel implants,

The conversational features of TWIST are such that the designer can go, with a few iterations, from a raw device idea to a detailed device structure, for which he has optimized threshold slope as well as their dependence on length and drain voltage and the punchthrough characteristics. These modes of operation are called barrier-controlled modes and the details of these potential barriers have been shown. Other quantities and their two-dimensional distributions, such as free carriers and electric fields, have also been presented. These are important with respect to device capacitances and device breakdown. Other two-dimensional problems have also been simulated, such as isolation between MOS transistors, DMOS transistors, and high-voltage structures, e.g., planar DMOS transistors and MOS guard-ring configuration.

1 5 5 8 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8 , AUGUST 1 9 8 0

The use of this program allows fairly optimized device structures to be developed which then merit more elaborate simulation involving the solution of the full potential and transport problem, which presently consumes approximately 50 times more computation time than the approach presented here. In a working hierarchy of CAD tools, structural and impurity parameters should be obtained from process simulators [12], [13]. TWIST can then be used to optimize all aspects of barrier control and actually obtain device parameters for models like (28). At that point, full two-dimensional transport solution would be justified [14], [ 151, with the derivation of device parameters suitable for circuit-oriented simulators P I 4 5 1 .

ACKNOWLEDGMENT The work reported here started with a calculator program

developed by J. Tihanyi at Siemens A.G., Munich, Germany. His assistance is gratefully acknowledged. The preliminary minicomputer version was developed by H. Krey, E. Habekotte, and E. Salten at the University of Dortrnund, Germany. Fur- ther contributions have been made by D. A. Hodges, A. R. Newton, and E. Cohen from the University of California at Berkeley, and A. Dejenfield, J. Moll, J. Manoliu, K. Runch- warger, E. Sun from Integrated Circuit Laboratory, Hewlett- Packard Co.

REFERENCES

[ l ] B. Hoefflinger, H. Sibbert, and G. Zimmer, “Model and perfor- mance of hot-electron MOS transistors for VLSI,” IEEE J. Solid State Circuits, vol. SC-14, no. 2, pp. 44-51, Apr. 1979.

[2] L. W. Nagel, “SPICE2, A computer program to simulate semi-

Memo ERL-M520, May 1975. conductor circuits,” University of California, Berkeley, ERL

[ 31 H. Sibbert, “Modellierung und Netzwerkanalyseprogramm fur MOS-Schaltungen mit hoher Leistungsfahigkeit,” Ph.D. dissertation, University of Dortmund, Dortmund, Germany, 1977.

[4] S. P. Fan, M. Y. Hsueh, A. R. Newton, and D. 0. Pederson, “MOTIS-C: A new circuit simulator for MOS LSI circuits,” in Proc. IEEE Int. Symp. Circuits and Systems, pp. 700-703, Apr. 1977.

[SI A. R. Newton, “The simulation of large-scale integrated circuits,” University of California, Berkeley, ERL Memo ERL-M78/52, July 1978.

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Documents

Interactive two-dimensional design of barrier-controlled MOS transistors