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INTERCONNECTED SYSTEMS
Jan C. WillemsK.U. Leuven, Flanders, Belgium
Mini-symposium, TU Delft October 15, 2008
– p. 1/106
Outline
◮ Open, connected, and modular
◮ [Classical dynamical systems]
◮ [Input/output systems]
◮ Modeling by tearing, zooming, and linking
◮ [On canceling poles and zeros]
◮ [DAEs]
◮ Signal flow graphs
◮ Bond graphs
◮ Circuit diagrams
◮ [Control as interconnection]
– p. 2/106
Systems
– p. 3/106
– p. 4/106
Features
◮ open
◮ interconnected
◮ modular
◮ dynamic
– p. 5/106
Features
◮ open
◮ interconnected
◮ modular
◮ dynamic
Aim:
develop a suitable mathematical language
aimed at computer-assisted modeling.
Modeling ⇔ Describing reality accurately
– p. 5/106
Open, connected, modular
– p. 6/106
Open
SYSTEM
ENVIRONMENT
Boundary
Systems interact with their environment
– p. 7/106
Connected
Systems consist of an architecture of interconnected subsystems
– p. 8/106
Modular
Systems are modular: composed of‘building blocks’
��������
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��
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SYSTEM
x
���������
���������
– p. 9/106
The development of the notion
of a dynamical system
– p. 10/106
Theme
– p. 11/106
First things first
1. Get the physics right
2. The rest is mathematics
R.E. KalmanOpening lecture
IFAC World CongressPrague, July 4, 2005
– p. 12/106
First things first
1. Get the physics right
2. The rest is mathematics
R.E. KalmanOpening lecture
IFAC World CongressPrague, July 4, 2005
Prima la fisica, poi la matematica
– p. 12/106
The missing link
◮ Get the physics right
◮ Translate the physics into mathematics
◮ The rest is mathematics
What are the ‘right’ concepts?
What is the ‘natural’ generalization?
What are the ‘relevant’ questions?
– p. 13/106
Closed dynamical systems
– p. 14/106
Closed dynamical systems
K.1, K.2, & K.3
;d2
dt2w(t)+1w(t)
| ddt w(t)|2
= 0
; with x = (w,
ddt w) ;
ddt x = f (x)
– p. 15/106
Closed dynamical systems
K.1, K.2, & K.3
;d2
dt2w(t)+1w(t)
| ddt w(t)|2
= 0
; with x = (w,
ddt w) ;
ddt x = f (x)
ddt x = f (x) ; ‘dynamical systems’, flows
; flows as paradigm of dynamics ; closed systems
Motion determined by initial conditions: a (inadequate)paradigm for modeling dynamics. Very frequently inmathematics and physics (chaos theory, synchronization,flows on manifolds, classical Hamiltonian mechanics, ... )
– p. 15/106
Inputs and outputs
– p. 16/106
Input/output systems
SYSTEMstimulus response
causeinput
effectoutput
Transfer functions, impedances, convolutions,Volterra series, ...
– p. 17/106
Input/output systems
SYSTEMstimulus response
causeinput
effectoutput
Oliver Heaviside (1850-1925)
Norbert Wiener (1894-1964)
and the many electrical circuit theorists
– p. 17/106
Mathematical description
SYSTEMstimulus response
causeinput
effectoutput
y(t) =∫ t
0 or −∞ H(t − t ′)u(t ′) dt ′
– p. 18/106
Mathematical description
SYSTEMstimulus response
causeinput
effectoutput
y(t) =∫ t
0 or −∞ H(t − t ′)u(t ′) dt ′
y(t) = H0(t)+∫ t
−∞H1(t − t ′)u(t ′) dt ′+
∫ t
−∞
∫ t ′
−∞H2(t − t ′,t ′− t ′′)u(t ′)u(t ′′) dt ′dt ′′ + · · ·
Awkward nonlinear — far from the physicsFail to deal with ‘initial conditions’.
– p. 18/106
Input/state/output systems
Around 1960: aparadigm shift to
ddt x = f (x,u), y = g(x,u)
Rudolf Kalman (1930- )
◮ open
◮ ready to be interconnectedoutputs of one system7→ inputs of another
◮ deals with initial conditions
◮ incorporates nonlinearities, time-variation
◮ models many physical phenomena
◮ · · ·
This framework turned out to be very effective and useful!– p. 19/106
Theme of this lecture
We are accustomed to view an open dynamical system as aninput/output structure (with or without the state)
outputsI/O SYSTEMinputs
– p. 20/106
Theme of this lecture
We are accustomed to view an open dynamical system as aninput/output structure (with or without the state)
outputsI/O SYSTEMinputs
Is this an appropriate abstractionof models of physical systems?
– p. 20/106
Theme of this lecture
and interconnection as output-to-input assignment
– p. 21/106
Theme of this lecture
and interconnection as output-to-input assignment
– p. 21/106
Theme of this lecture
and interconnection as output-to-input assignment
Feedback
Series
Parallel
– p. 21/106
Theme of this lecture
and interconnection as output-to-input assignment
Feedback
Series
Parallel
Is this an appropriate abstraction ofinterconnection of physical systems?
– p. 21/106
An example
– p. 22/106
Tearing
(pressure, flow) (pressure, flow)
– p. 23/106
Tearing
(pressure, flow) (pressure, flow)
(p’,f’)(p,f)
– p. 23/106
Tearing
(pressure, flow) (pressure, flow)
(p’,f’)(p,f)
21 3
– p. 23/106
Zooming
Subsystems 1 and 3 (tanks ):
(pressure, flow) (pressure, flow)
– p. 24/106
Zooming
Subsystems 1 and 3 (tanks ):
(pressure, flow) (pressure, flow)
– p. 24/106
Zooming
Subsystems 1 and 3 (tanks ):
(pressure, flow) (pressure, flow)
p’, f’p, fh
– p. 24/106
Zooming
Subsystems 1 and 3 (tanks ):
(pressure, flow) (pressure, flow)
p’, f’p, fh
A ddt h = f + f ′,
B f =
√
|p− p0−ρh| if p− p0 ≥ ρh,
−√
|p− p0−ρh| if p− p0 ≤ ρh,
C f ′ =
√
|p′− p0−ρh| if p′− p0 ≥ ρh,
−√
|p′− p0−ρh| if p′− p0 ≤ ρh,
– p. 24/106
Zooming
Subsystem 2 (pipe ):
p’, f’p, f
– p. 25/106
Zooming
Subsystem 2 (pipe ):
p’, f’p, f
f = − f ′, p− p′ = α f
– p. 25/106
Linking
Interconnection laws:
p, f p’, f’
– p. 26/106
Linking
Interconnection laws:
p, f p’, f’
p = p′, f + f ′ = 0
– p. 26/106
Linking
Interconnection laws:
p, f p’, f’
p = p′, f + f ′ = 0
Leads to the complete model:
– p. 26/106
A1ddt h1 = f1 + f ′1,
B1 f1 =
√
|p1− p0−ρh1| if p1− p0 ≥ ρh1,
−√
|p1− p0−ρh1| if p1− p0 ≤ ρh1,(blackbox 1)
C1 f ′1 =
√
|p′1− p0−ρh1| if p′1− p0 ≥ ρh1,
−√
|p′1− p0−ρh1| if p′1− p0 ≤ ρh1,
f2 = − f ′2, p2− p′2 = α f2, (blackbox 2)
A3ddt h3 = f3 + f ′3,
C f3 =
√
|p3− p0−ρh3| if p3− p0 ≥ ρh3,
−√
|p3− p0−ρh3| if p3− p0 ≤ ρh3,(blackbox 3)
C3 f ′3 =
√
|p′3− p0−ρh3| if p′3− p0 ≥ ρh3,
−√
|p′3− p0−ρh3| if p′3− p0 ≤ ρh3,
p′1 = p2, f ′1 + f2 = 0, p′2 = p3, f ′2 + f3 = 0. (interconnection)
pleft = p1, fleft = f1, pright = p′3, fright = f ′3. (manifest variable assignment)
– p. 27/106
NB
This tableau of equations is the endpoint of a straightforwardfirst-principles-modeling procedure.
◮ Unclear (and, in fact, irrelevant) input/output structurefor the terminal variables,both in the overall system and in the subsystems
◮ Many variables, indivisibly, at the same terminal
◮ Interconnection = variable sharing
◮ No signal flows, no output-to-input assignment
– p. 28/106
NB
This tableau of equations is the endpoint of a straightforwardfirst-principles-modeling procedure.
◮ Unclear (and, in fact, irrelevant) input/output structurefor the terminal variables,both in the overall system and in the subsystems
◮ Many variables, indivisibly, at the same terminal
◮ Interconnection = variable sharing
◮ No signal flows, no output-to-input assignment
These remarks pertain to every physical interconnection.And, ultimately, every interconnection is physical.
– p. 28/106
Behavioral systems
– p. 29/106
Behavioral approach
A dynamical system
:⇔ a family of time trajectories, ‘the behavior’
Interconnection ⇔ ‘variable sharing’
Control ⇔ interconnection
Modeling of interconnected physical systems is the strongestcase for ‘behaviors’.
– p. 30/106
Terminals
We consider systems that interact with their environmentthrough terminals
– p. 31/106
Terminals
We consider systems that interact with their environmentthrough terminals
There are manyelectrical, mechanical, hydraulic, thermal,civil engineering, pneumatic, ... connectionsthat can be viewed this way,exactly, literally.
For mechanical systems, think of interconnections asscrewing, gluing, welding, ...Hinges, hooks, etc. ought to be thought of as devices(modules).
– p. 31/106
Terminals
We consider systems that interact with their environmentthrough terminals
There are manyelectrical, mechanical, hydraulic, thermal,civil engineering, pneumatic, ... connectionsthat can be viewed this way,exactly, literally.
For mechanical systems, think of interconnections asscrewing, gluing, welding, ...Hinges, hooks, etc. ought to be thought of as devices(modules).
The clearest example is anelectrical connection.A terminal = a single wire.
– p. 31/106
Interconnection architecture
– p. 32/106
Objective
Formalize mathematically interconnection of systems.
– p. 33/106
Graph with leaves
Architecture:
graph with leaves leaf
vertex
edge
vertices ; systems with terminalsedges ; connected terminalsleaves ; interaction with environment
terminals ; system variables– p. 34/106
Behavioral equations
1. Module equations for each vertex.Relation among the variables on the terminals.
2. Interconnection equations for each edge.Equating the variables on the terminals associatedwith the same edge.
3. Manifest variable assignmentSpecifies the variables of interest.
– p. 35/106
Behavioral equations
1. Module equations for each vertex.Relation among the variables on the terminals.
Behavioral equations stored as (parametrized) modulesin a data-base.
2. Interconnection equations for each edge.Equating the variables on the terminals associatedwith the same edge.
Interconnection laws stored in a data-base.Laws depend on terminal type:electrical / mechanical / hydraulic / etc.
3. Manifest variable assignmentSpecifies the variables of interest.
– p. 35/106
An example
– p. 36/106
RLC circuit
Model the port behavior of
��
RL
C
C
LRI
V−
+��
��
�� ��
��������
����
��
by tearing, zooming, and linking.
– p. 37/106
RLC circuit
Model the port behavior of
��
RL
C
C
LRI
V−
+��
��
d
f
b
c
h
��
1
4
6
3
5
2
a
e
g
��
��������
����
��
;
by tearing, zooming, and linking.
In each vertex there is a module; module equationseach terminal involves 2 variables (potential, current)in each edge there is an electrical interconnection;
interconnection equations– p. 37/106
Modules
1
3
2
22
11 1
11
2
322
������
������
������
������
connector1
capacitor connector2
inductorresistor1
resistor2– p. 38/106
Modules
1
3
2
22
11 1
11
2
322
������
������
������
������
connector1 n = 3
capacitor C connector2 n = 3
inductor Lresistor1 RC
resistor2 RL
– p. 38/106
Module equations
vertex 1 : Vconnector1,1 = Vconnector1,2 = Vconnector1,3
Iconnector1,1 + Iconnector1,2 + Iconnector1,3 = 0
vertex 2 : VRC,1−VRC,2 = RCIRC,1, IRC,1 + IRC,2 = 0
vertex 3 : L ddt IL,1 = VL,1−VL,2, IL,1+ IL,2 = 0
vertex 4 : C ddt
(
VC,1−VC,2)
= IC,1, IC,1 + IC,2 = 0
vertex 5 : VRL,1−VRL,2 = RLIRL,1
IRL,1 + IRL,2 = 0
vertex 6 : Vconnector2,1 = Vconnector2,2 = Vconnector2,3
Iconnector2,1 + Iconnector2,2 + Iconnector2,3 = 0
– p. 39/106
Module equations
Vconnector1,1 = Vconnector1,2 = Vconnector1,3
Iconnector1,1 + Iconnector1,2 + Iconnector1,3 = 0
VRC,1−VRC,2 = RCIRC,1, IRC,1 + IRC,2 = 0
L ddt IL,1 = VL,1−VL,2, IL,1 + IL,2 = 0
vertex 4: C ddt
(
VC,1 − VC,2
)
= IC,1 , IC,1 + IC,2 = 0
VRL,1−VRL,2 = RLIRL,1
IRL,1+ IRL,2 = 0
Vconnector2,1 = Vconnector2,2 = Vconnector2,3
Iconnector2,1 + Iconnector2,2 + Iconnector2,3 = 0
IC,1
IC,2
IV,1
VC,2
C
– p. 39/106
Interconnection
All interconnections are of electrical type
Ileft
Ileft
Iright
Iright
Vleft
Vleft
Vright
Vright
Interconnection equations:
potential left = potential right ; Vleft = Vright
current left + current right = 0 ; Ileft + Iright = 0
– p. 40/106
Interconnection equations
edge c: VRC,1 = Vconnector1,2 IRC,1 + Iconnector1,2 = 0
edge d: VL,1 = Vconnector1,3 IL,1 + Iconnector1,3 = 0
edge e: VRC,2 = VC,1 IRC,2 + IC,1 = 0
edge f: VL,2 = VRC,1 IL,2 + IRL,1 = 0
edge g: VC,2 = Vconnector2,1 IC,2 + Iconnector2,1 = 0
edge h: VRL,2 = Vconnector2,2 IRL,2 + Iconnector2,2 = 0
– p. 41/106
Interconnection equations
VRC,1 = Vconnector1,2 IRC,1 + Iconnector1,2 = 0
edge d: VL,1 = Vconnector1,3
IL,1 + Iconnector1,3 = 0
VRC,2 = VC,1 IRC,2 + IC,1 = 0
VL,2 = VRC,1 IL,2 + IRL,1 = 0
VC,2 = Vconnector2,1 IC,2 + Iconnector2,1 = 0
VRL,2 = Vconnector2,2 IRL,2 + Iconnector2,2 = 0
L
����connector1
Iconnector1,3
IL,1Vconnector1,3
VL,1
– p. 42/106
Manifest variable assignment
Vexternalport = Vconnector1,1−Vconnector2,3
Iexternalport = Iconnector1,1
−
��
+
����
��connector1
connector2
Iconnector1,1Vconnector1,1
Vconnector2,3
Iexternalport
Vexternalport
– p. 43/106
Complete model
vertex 1 : Vconnector1,1 = Vconnector1,2 = Vconnector1,3
Iconnector1,1 + Iconnector1,2 + Iconnector1,3 = 0
vertex 2 : VRC ,1−VRC ,2 = RCIRC ,1, IRC ,1 + IRC ,2 = 0
vertex 3 : L ddt IL,1 = VL,1−VL,2, IL,1 + IL,2 = 0
vertex 4 : C ddt
(
VC,1−VC,2)
= IC,1, IC,1 + IC,2 = 0
vertex 5 : VRL ,1−VRL ,2 = RLIRL,1
IRL,1 + IRL ,2 = 0
vertex 6 : Vconnector2,1 = Vconnector2,2 = Vconnector2,3
Iconnector2,1 + Iconnector2,2 + Iconnector2,3 = 0
edge c: VRC,1 = Vconnector1,2
IRC,1 + Iconnector1,2 = 0
edge d: VL1 = Vconnector1,3
IL1 + Iconnector1,3 = 0
edge e: VRC,2 = VC1
IRC,2 + IC1 = 0
edge f: VL2 = VRC,1
IL2 + IRL,1 = 0
edge g: VC2 = Vconnector2,1
IC2 + Iconnector2,1 = 0
edge h: VRL,2 = Vconnector2,2
IRL,2 + Iconnector2,2 = 0
Vexternalport = Vconnector,1,1−Vconnector2,3
Iexternalport = Iconnector1,1
– p. 44/106
Port behavior
B = { (Vexternalport, Iexternalport) : R → R2 |
∃ latent variables trajectories
(Vconnector1,1, Iconnector1,1, . . . , . . .) : R → R28
such that
Vconnector1,1 = Vconnector1,2 = Vconnector1,3, . . . ,
all 24 equations are satisfied}
– p. 45/106
Port behavior
B = { (Vexternalport, Iexternalport) : R → R2 |
∃ latent variables trajectories
(Vconnector1,1, Iconnector1,1, . . . , . . .) : R → R28
such that
Vconnector1,1 = Vconnector1,2 = Vconnector1,3, . . . ,
all 24 equations are satisfied}
Can we simplify this expression forB?
– p. 45/106
Port behavior
; the dynamical system with behaviorB specified by:
Case 1: CRC 6=L
RL
(
RCRL
+(
1+ RCRL
)
CRCddt +CRC
LRL
d2
dt2
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
; B = all solutions (V, I) : R → R2
– p. 46/106
Port behavior
; the dynamical system with behaviorB specified by:
Case 1: CRC 6=L
RL
(
RCRL
+(
1+ RCRL
)
CRCddt +CRC
LRL
d2
dt2
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RL
(
RCRL
+CRCddt
)
V =(
1+CRCddt
)
RCI
; B = all solutions (V, I) : R → R2
– p. 46/106
Port behavior
Thm: In LTIDSs latent variables can be eliminated !
; the dynamical system with behaviorB specified by:
Case 1: CRC 6=L
RL
(
RCRL
+(
1+ RCRL
)
CRCddt +CRC
LRL
d2
dt2
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RL
(
RCRL
+CRCddt
)
V =(
1+CRCddt
)
RCI
; B = all solutions (V, I) : R → R2
– p. 46/106
The complete model is a linear constant coefficient DAE
vertex 1 : Vconnector1,1 = Vconnector1,2 = Vconnector1,3
Iconnector1,1 + Iconnector1,2 + Iconnector1,3 = 0
vertex 2 : VRC ,1−VRC ,2 = RCIRC ,1, IRC ,1 + IRC ,2 = 0
vertex 3 : L ddt IL,1 = VL,1−VL,2 IL,1 + IL,2 = 0
vertex 4 : C ddt
(
VC,1−VC,2)
= IC,1 IC,1 + IC,2 = 0
vertex 5 : VRL ,1−VRL ,2 = RLIRL,1
IRL ,1 + IRL,2 = 0
vertex 6 : Vconnector2,1 = Vconnector2,2 = Vconnector2,3
Iconnector2,1 + Iconnector2,2 + Iconnector2,3 = 0
edge c: VRC,1 = Vconnector1,2
IRC,1 + Iconnector1,2 = 0
edge d: VL1 = Vconnector1,3
IL1 + Iconnector1,3 = 0
edge e: VRC,2 = VC1
IRC,2 + IC1 = 0
edge f: VL2 = VRC,1
IL2 + IRL,1 = 0
edge g: VC2 = Vconnector2,1
IC2 + Iconnector2,1 = 0
edge h: VRL,2 = Vconnector2,2
IRL,2 + Iconnector2,2 = 0
Vexternalport = Vconnector,1,1−Vconnector2,3
Iexternalport = Iconnector1,1
– p. 47/106
Canceling poles and zeros
– p. 48/106
Can poles and zeros be cancelled?
Case 1: CRC →L
RL
(
1+ LRL
ddt
)(
RCRL
+CRCddt
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RL
(
RCRL
+CRCddt
)
V =(
1+CRCddt
)
RCI
– p. 49/106
Can poles and zeros be cancelled?
Case 1: CRC →L
RL
(
1+ LRL
ddt
)(
RCRL
+CRCddt
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RL
(
RCRL
+CRCddt
)
V =(
1+CRCddt
)
RCI
Cancellation appears allowed.
– p. 49/106
Can poles and zeros be cancelled?
Case 1: CRC →L
RLand RC = RL
(
1+ LRL
ddt
)
(
1+CRCddt
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RLand RC = RL
(
1+CRCddt
)
V =(
1+CRCddt
)
RCI
– p. 50/106
Can poles and zeros be cancelled?
Case 1: CRC →L
RLand RC = RL
(
1+ LRL
ddt
)
(
1+CRCddt
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RLand RC = RL
(
1+CRCddt
)
V =(
1+CRCddt
)
RCI
One common factor can be cancelled, the other not.
Cancellation appearssometimes, but only sometimes allowed
– p. 50/106
Can poles and zeros be cancelled?
Case 1: CRC →L
RLand RC = RL
(
1+ LRL
ddt
)
(
1+CRCddt
)
V =(
1+ LRL
ddt
)
(
1+CRCddt
)
RCI
Case 2: CRC =L
RLand RC = RL
(
1+CRCddt
)
V =(
1+CRCddt
)
RCI
One common factor can be cancelled, the other not.
Cancellation appearssometimes, but only sometimes allowed
Important? Look at short circuit behavior V = 0.Incorrect cancellation gives spurious exponential responses!
– p. 50/106
Seshu graphs, trees, & admittance formula
��
RL
C
C
LRI
V−
+��
��
����
��
�� ��
�� ���� ��
��
��
��
�� ��
��
��
�� ��
��
�� ��
��
��
�� ��
������ ������ ��
����
���� ������ ��
– p. 51/106
Seshu graphs, trees, & admittance formula
��
RL
C
C
LRI
V−
+��
��
Graph 1: spanning trees:
CR ��
RL
C
L��
��
�� ��
LCR LC
LR
R
C
C
LR
L
RL
C
�� ���� ��R
C
��
��
��
�� ��
��
��
�� ��
��
�� ����
��
��
�� ��
������ ������ ��
����
���� ������ ��
– p. 51/106
Seshu graphs, trees, & admittance formula
��
RL
C
C
LRI
V−
+��
��
Graph 1: spanning trees:
CR ��
RL
C
L��
��
�� ��
LCR LC
LR
R
C
C
LR
L
RL
C
�� ���� ��R
C
��
��
��
�� ��
��
��
�� ��
��
�� ����
��
��
�� ��
Graph 2: spanning trees:
R
C RL
LC
������
LCR CR
RL
L
C C RL
������ ����
������ ��
���� ��
– p. 51/106
Seshu graphs, trees, & admittance formula
��
RL
C
C
LRI
V−
+��
��
Circuit admittance =
I(s)V (s)
=Σ
graph1Π
branchesbranch admittances
Σgraph2
Πbranches
branch admittances
Graph 1: spanning trees:
CR ��
RL
C
L��
��
�� ��
LCR LC
LR
R
C
C
LR
L
RL
C
�� ���� ��R
C
��
��
��
�� ��
��
��
�� ��
��
�� ����
��
��
�� ��
Graph 2: spanning trees:R
C RL
LC
������
LCR CR
RL
L
C C RL
������ ����
������ ��
���� ��
– p. 51/106
Seshu admittance formula
Seshu gives:
I(s)
V (s)=
RCRL
+(
1+ RCRL
)
CRCs+CRCL
RLs2
(
1+ LRL
s)
(1+CRCs)RC
Gives the correct admittance/impedance/transfer function.
– p. 52/106
Seshu admittance formula
Seshu gives:
I(s)
V (s)=
RCRL
+(
1+ RCRL
)
CRCs+CRCL
RLs2
(
1+ LRL
s)
(1+CRCs)RC
Gives the correct admittance/impedance/transfer function.
But, it does not give the correct behavior.It does not cope with common factors.
Same remarks for Mason’s formula, for series connection, ...
– p. 52/106
Seshu admittance formula
Seshu gives:
I(s)
V (s)=
RCRL
+(
1+ RCRL
)
CRCs+CRCL
RLs2
(
1+ LRL
s)
(1+CRCs)RC
Gives the correct admittance/impedance/transfer function.
But, it does not give the correct behavior.It does not cope with common factors.
Same remarks for Mason’s formula, for series connection, ...
Respect common factors
Respect the uncontrollable
Beware of transfer function thinking– p. 52/106
Other methodologies
– p. 53/106
Differential-algebraic equations (DAEs)
– p. 54/106
DAEs
Differential-algebraic equations:
ddt Ex = Ax+Bu, y = Cx+Du w =
[
uy
]
– p. 55/106
DAEs
Differential-algebraic equations:
ddt Ex = Ax+Bu, y = Cx+Du w =
[
uy
]
Is this a sensible first-principles-model alternative to theoverly structured
ddt
x = Ax+Bu, y = Cx+Du w =
[
uy
]
?
Where does the input/output partition come from?
– p. 55/106
DAEs
Differential-algebraic equations:
ddt Ex = Ax+Bu, y = Cx+Du w =
[
uy
]
Where does the input/output partition come from?
Often the additional assumption is made that the pencildeterminant(Eµ −Aξ ) is regular
; determinant(Eµ −Aξ ) 6= 0.
Where does this assumption come from?
Where does the fact thatE and A are regular come from?Why should they even be square?
– p. 55/106
vertex 1 : Vconnector1,1 = Vconnector1,2 = Vconnector1,3
Iconnector1,1 + Iconnector1,2 + Iconnector1,3 = 0
vertex 2 : VRC ,1−VRC ,2 = RCIRC ,1, IRC ,1 + IRC ,2 = 0
vertex 3 : L ddt IL,1 = VL,1−VL,2, IL,1 + IL,2 = 0
vertex 4 : C ddt
(
VC,1−VC,2)
= IC,1, IC,1 + IC,2 = 0
vertex 5 : VRL ,1−VRL ,2 = RLIRL,1
IRL,1 + IRL ,2 = 0
vertex 6 : Vconnector2,1 = Vconnector2,2 = Vconnector2,3
Iconnector2,1 + Iconnector2,2 + Iconnector2,3 = 0
edge c: VRC,1 = Vconnector12
IRC,1 + Iconnector1,2 = 0
edge d: VL1 = Vconnector13
IL1 + Iconnector13 = 0
edge e: VRC,2 = VC1
IRC,2 + IC1 = 0
edge f: VL2 = VRC,1
IL2 + IRL,1 = 0
edge g: VC2 = Vconnector21
IC2 + Iconnector21 = 0
edge h: VRL,2 = Vconnector22
IRL,2 + Iconnector22 = 0Vexternalport = Vconnector1,1−Vconnector2,3 Iexternalport = Iconnector11
Eddt
x = Ax+B Iexternalport Vexternalport = Cx+D Iexternalport
with x = the terminal variables (14 term’s, 28 variables),1 input (say,Iexternalport), 1 output (say,Vexternalport) and 24 eq’ns.
E,A ∈ R23×28
,B ∈ R23×1
,C ∈ R1×23
,D ∈ R
– p. 56/106
Signal flow graphs
– p. 57/106
input/output thinking
There are many many examples where output-to-inputconnection is eminently natural:
– p. 58/106
input/output thinking
There are many many examples where output-to-inputconnection is eminently natural:
fin
outf
– p. 58/106
input/output partition
terminal with 2 physical variables
Assume that one of these variables acts as input, the other asoutput.
– p. 59/106
input/output partition
input
output
Assume that one of these variables acts as input, the other asoutput.
– p. 59/106
Block diagram
variable 2
variable 1
◮ shows terminal variables separate
◮ suggests that inputs and outputs occur at differentphysical points
Pedagogically awkward, confusing.
– p. 60/106
input/output thinking
variable 2
variable 1
◮ allows impossible input-output connections
Does not respect the physics.– p. 61/106
input/output thinking
– p. 62/106
input/output thinking
variablesshared
– p. 62/106
input/output thinking
variablesshared
partitionsi/o
– p. 62/106
input/output thinking
variablesshared
partitionsi/o
?
?
– p. 62/106
input/output thinking
variablesshared
partitionsi/o
For physical systemsinput-to-input & output-to-output
assignment very prevalent:force to force; pressure to pressure; heat flow to heat flow;temperature to temperature; mass flow to mass flow; ...
Physical systems are not signal processors
– p. 62/106
The input/output approach as the primary and universalview of open systems is a historical misconception.
The sooner it is abandoned as a starting point, the better.
– p. 63/106
The input/output approach as the primary and universalview of open systems is a historical misconception.
◮ It fails in the most elementary examples.
◮ It does not deal adequately with interconnections.
◮ It breaks symmetries.
◮ It does not respect the physics.
◮ It is pedagogically ineffective.
The sooner it is abandoned as a starting point, the better.
– p. 63/106
“Block diagrams unsuitable for serious physical modeling
- the control/physics barrier”
“Behavior based (declarative) modeling is a good alternative”
Karl Astr om
from K.J. Astr om, Present Developments in Control Applications
IFAC 50-th Anniversary CelebrationHeidelberg, September 12, 2006.
– p. 64/106
Notes & arrows
My dear young man, don’t take it too hard.Your work is ingenious. It’s quality work.But there are simply too many notes that’s all ...
– p. 65/106
Notes & arrows
Ingenious. Quality work.But there are simply too many arrows , that’s all ...
– p. 65/106
Bond graphs
– p. 66/106
Bond graphs
variablesshared
– p. 67/106
Bond graphs
effortflow
Interconnection variables consist of
an effort and a flow effort × flow = power
Interconnection ⇔[efforts equal] & [flows sum to 0]
⇒ power equal
‘Power is the universal currency of physical systems’
– p. 67/106
Bond graphs
Interconnection variables:
◮ voltage & current
◮ force & velocity
◮ pressure & mass flow
◮ temperature & heat flow
temperature &heat flow
temperature◮ ...
– p. 68/106
Remarks
◮ Mechanical interconnections equate positions, notvelocities.
◮ Not all interconnections involve equating energy transfer.
◮ Terminals are for interconnection, ports for energytransfer.
– p. 69/106
Remarks
◮ Mechanical interconnections equate positions, notvelocities.
◮ Not all interconnections involve equating energy transfer.
◮ Terminals for interconnection, ports for energy transfer
This last point is illustrated for electrical interconnections.
– p. 69/106
Terminals versus ports
(potential, current)
Electricalcircuit
Terminal variables and behavior:
(V1, I1,V2, I2, . . . ,Vn, In) ; behavior B ⊆(
R2n)R
– p. 70/106
Terminals versus ports
Port 1
Port 2
Port k
Circuit
Port :⇔
sum currents = 0potentials + constant
⇒ potentials
– p. 71/106
Terminals versus ports
Port 1
Port 2
Port k
Circuit
Port :⇔
sum currents = 0potentials + constant
⇒ potentials
(
V1, I1 . . . ,Vp, Ip ,Vp+1, . . . , In)
∈ B,α : R → R
⇓
(
V1 +α , I1, . . . ,Vp +α , Ip ,Vp+1, . . . , In)
∈ B
I1 + · · ·+ Ip = 0
– p. 71/106
Terminals versus ports
Port 1
Port 2
Port k
Circuit
Port :⇔
sum currents = 0potentials + constant
⇒ potentials
The behavioral equations contain the variablesV1,V2 . . . ,Vp
only as the differences
Vi −Vj for i, j = 1, ...p
and contain the equation
I1 + I2 + · · ·+ Ip = 0
– p. 71/106
Terminals versus ports
(potential, current)
Electricalcircuit
All the terminals together form a port
(
V1, I1 . . . ,Vn, In)
∈ B,α : R → R
⇓(
V1 +α , I1, . . . ,Vn +α , In)
∈ B
I1 + · · ·+ In = 0
– p. 72/106
Terminals versus ports
(potential, current)
Electricalcircuit
All the terminals together form a port
(
V1, I1 . . . ,Vn, In)
∈ B,α : R → R
⇓(
V1 +α , I1, . . . ,Vn +α , In)
∈ B
I1 + · · ·+ In = 0
Viewed as universal ‘laws’ governing electrical circuits,thesemay be thought of as theKirchhoff laws, KVL & KCL
This property is closed under interconnection.– p. 72/106
Terminals versus ports
Circuit 1 Circuit 2
Circuit 3
Circuit 1 Circuit 2
Circuit 3
– p. 73/106
Terminals versus ports
Circuit 1 Circuit 2
Circuit 3
Circuit 1 Circuit 2
Circuit 3
Interconnection via terminals, energy transfer via ports.One cannot speak about
“the energy transferred from circuit 1 to circuit 2”
unless their interconnected terminals form a port.
– p. 73/106
Hierarchy
– p. 74/106
New modules from old ones
Tearing, zooming, linking is hierarchical :
leaf
vertex
edge
– p. 75/106
New modules from old ones
Tearing, zooming, linking is hierarchical :
leaf
vertex
edge
Embed modules in vertices, obtain behavioral equations forthe interconnected system, eliminate the latent variables,
– p. 75/106
New modules from old ones
Tearing, zooming, linking is hierarchical :
leaf
vertex
edge
Terminals
MODULE
Embed modules in vertices, obtain behavioral equations forthe interconnected system, eliminate the latent variables, anduse interconnected systemas a module with terminals in anew interconnection architecture.
– p. 75/106
Example
Model the behavior of the external terminal voltages andcurrents of the following circuit:
– p. 76/106
Example
Model the behavior of the external terminal voltages andcurrents of the following circuit:
One section:
;
– p. 76/106
Example
Model the behavior of the external terminal voltages andcurrents of the following circuit:
One section:
;
Hierarchical combination:
; ⇒
– p. 76/106
Circuit diagrams
– p. 77/106
Circuits and graphs
Classical circuit theory evolves around adigraph with2-terminal elements or external ports in the edges andconnections in the vertices.
vertex
edge
– p. 78/106
Circuits and graphs
Classical circuit theory evolves around adigraph with2-terminal elements or external ports in the edges andconnections in the vertices. For example,
��
RL
C
C
LRI
V−
+�� ��
��
��
;
��������
�� ��
��
– p. 78/106
Circuits and graphs
Classical circuit theory evolves around adigraph with2-terminal elements or external ports in the edges andconnections in the vertices.
vertex
edge
Associate a voltage drop and a current with each edge, and
embed an element (say,R, L, or C) in each ‘internal’ edge.
– p. 78/106
KVL & KCL
Basic laws:
Kirchhoff’s current law for each vertex:
∑edges adjacent to vertex
± currents in edges= 0
Kirchhoff’s voltage law for each cycle:
∑edges in the cycle
± voltage drops over edges= 0
Equivalently, the vertices have an electric potential.
– p. 79/106
KVL & KCL
Basic laws:
Kirchhoff’s current law for each vertex:
∑edges adjacent to vertex
± currents in edges= 0
Kirchhoff’s voltage law for each cycle:
∑edges in the cycle
± voltage drops over edges= 0
Equivalently, the vertices have an electric potential.
Combined with the constitutive laws of the elements in the‘internal’ edges, this yields equations for the behavior (say, ofthe voltages and currents of the external ports).
– p. 79/106
Limitations
This methodology is very limited:
◮ It can only deal with 2-terminal elements and 2-terminalexternal ports.
◮ It is purely port oriented. It does not articulate thatterminals, not ports make the interconnections.
◮ It is not hierarchicalAn already-modeled-circuit cannot be reused as asubsystem in a larger circuit diagram.
– p. 80/106
Embedding a circuit in a graph
edge
vertex
����
����
����
����
����
����
����
– p. 81/106
Embedding a circuit in a graph
edge
vertex
Perfect for 2-terminal one-ports
����
����
����
����
����
����
����
– p. 81/106
Embedding a circuit in a graph
edge
vertex
���
���
����
����
R
R
R
There is no way to embed a 3-terminal circuit in a circuitgraph,
����
����
����
����
– p. 81/106
Embedding a circuit in a graph
edge
vertex
���
���
����
����
R
R
R
There is no way to embed a 3-terminal circuit in a circuitgraph, unless we tear the blackbox into its components
����
���
���
����
R
RR ����
R/3
R/3R/3
– p. 81/106
Embedding a circuit in a graph
edge
vertex
If we imbed a 4-terminal circuit into a circuit graph, it has t obe a 2-port.
������
������
��������
��������
������
������
– p. 82/106
Embedding a circuit in a graph
edge
vertex
If we imbed a 4-terminal circuit into a circuit graph, it has t obe a 2-port.
������
������
��������
��������
������
������
R
R
R
R
not embeddable embeddable– p. 82/106
Vertices and edges
In circuit graphs,subsystems are in the edges ,connections are in the vertices
vertex
edge
– p. 83/106
Vertices and edges
In circuit graphs,subsystems are in the edges ,connections are in the vertices
vertex
edge
leaf
vertex
edge
Contrast with tearing, zooming, linking:subsystems are in the vertices , connections are in the edges
– p. 83/106
Various facets of control
– p. 84/106
Path planning
ddt
x = f (x,u)
Choose time-function u(·) : [0,T ] → U so as to achieve(optimal) state transfer.
‘open loop control’
1
x2X2
x
– p. 85/106
Decision making
��������
����
CONTROLLER
controlinputs
FEEDBACK
to−be−controlled outputsexogenous inputs
measuredoutputs
Actuators PLANT
CLOSED−LOOPSYSTEM
Sensors
Choose afeedback system that processes sensor outputs andgenerates actuator inputs so as to achieve good (optimal)performance.
‘feedback control’‘closed loop control’‘intelligent control’
– p. 86/106
Embedded systems control
ControllerPlant
Choose controller so as to achieve good (optimal)performance of the interconnected system
‘control as interconnection’‘integrated system design’
– p. 87/106
Example
suspension spring
road profile
axle mass
body mass
damper
tire tire
axle mass
body mass
mechanical impedance
road profile
– p. 88/106
Control as interconnection
– p. 89/106
Interconnecting a controller
Before interconnection:to−be−controlled
terminals
Plant terminals Controllerterminals
control
exogenous
After interconnection:to−be−controlled
terminals
Plantterminals
Controller
exogenous
Contrast with:
control outputsmeasured
inputsoutputs
to−be−controlled
Controller
Actuators
exogenous
Controlled system
SensorsPlant
inputs
– p. 90/106
Many controllers are not sensor-to-actuator
Controlling turbulence:
– p. 91/106
Many controllers are not sensor-to-actuator
Controlling turbulence:
– p. 91/106
Nagano 1998 Winter Olympics
– p. 92/106
Many controllers are not sensor-to-actuator
controlling drag:
– p. 93/106
Many stabilizers are not sensor-to-actuator
Stabilization:
– p. 94/106
Disturbance attenuation
tire
axle mass
body mass
mechanical impedance
road profile
suspension spring
road profile
axle mass
body mass
damper
tire
active damper
actuator
road profile
sensors
tire
control algorithm
body mass
axle mass
spring
– p. 95/106
Control as Interconnection
to−be−controlled
Controlled system
Plant Controller
controlterminals
terminals
◮ Are all interconnections ‘reasonable’?
◮ Which controlled behaviors can be achieved?
◮ Parametrize all stabilizing controllers
◮ ...
– p. 96/106
Implementability
to−be−controlled
controlterminals
terminals
w
c
B C
K
For simplicity, restrict attention to LTIDSs, L •.
Let B ∈ L w+c be the plant behavior,C ∈ L c be the controller behavior, and
K = {w : R → Rw | ∃ c ∈ C such that (w,c) ∈ B}
be thecontrolled behavior
– p. 97/106
Implementability
to−be−controlled
controlterminals
terminals
w
c
B C
K
For simplicity, restrict attention to LTIDSs, L •.
Let B ∈ L w+c be the plant behavior,C ∈ L c be the controller behavior, and
K = {w : R → Rw | ∃ c ∈ C such that (w,c) ∈ B}
be thecontrolled behavior
Elimination theorem ⇒ K ∈ L w
– p. 97/106
Implementability
(b)
to−be−controlled
controlterminals
terminals
w
c
B C
K
For a givenB ∈ L w+c, call K ∈ L w implementable if thereexistsC ∈ L c such thatK is the controlled behavior.
Which K ∈ L w are implementable ?
– p. 98/106
Every lecture must have at least one theorem
to−be−controlled
Hidden behavior
Plant
controlterminals
terminals
wc = 0
Define thehidden behavior
N := {w|(w,0) ∈ B}
– p. 99/106
Every lecture must have at least one theorem
to−be−controlled
Hidden behavior
Plant
controlterminals
terminals
wc = 0
Define thehidden behavior
N := {w|(w,0) ∈ B}
to−be−controlled
Uncontrolled plant behavior
Plant
controlterminals
terminals
wc = free
Define theuncontrolled plant behavior
P := {w|∃ c : (w,c) ∈ B}
– p. 99/106
Every lecture must have at least one theorem
to−be−controlled
Hidden behavior
Plant
controlterminals
terminals
wc = 0
Define thehidden behavior
N := {w|(w,0) ∈ B}
to−be−controlled
Uncontrolled plant behavior
Plant
controlterminals
terminals
wc = free
Define theuncontrolled plant behavior
P := {w|∃ c : (w,c) ∈ B}
Implementability theorem
K ∈ L w is implementable ⇔ N ⊆ K ⊆ P
– p. 99/106
Summary
– p. 100/106
Main points
◮ Interconnection = variable (terminal) sharing
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
◮ Hierarchical procedure
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
◮ Hierarchical procedure
◮ Importance of latent variables and theelimination theorem
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
◮ Hierarchical procedure
◮ Importance of latent variables and theelimination theorem
◮ Limitations of input/output thinking
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
◮ Hierarchical procedure
◮ Importance of latent variables and theelimination theorem
◮ Limitations of input/output thinking
◮ Control is interconnection, sensor output to actuatorinput feedback important special case
– p. 101/106
Main points
◮ Interconnection = variable (terminal) sharing
◮ Modeling by physical systems proceeds bytearing, zooming, and linking
◮ Hierarchical procedure
◮ Importance of latent variables and theelimination theorem
◮ Limitations of input/output thinking
◮ Control is interconnection, sensor output to actuatorinput feedback important special case
◮ Need generalization to distributed terminals, etc.
– p. 101/106
Overview
– p. 102/106
Behavioral systems
◮ Gets the physics right
– p. 103/106
Behavioral systems
◮ Gets the physics right
◮ Starts with first principles models
– p. 103/106
Behavioral systems
◮ Gets the physics right
◮ Starts with first principles models
◮ Latent variables with state as a special case
– p. 103/106
Behavioral systems
◮ Gets the physics right
◮ Starts with first principles models
◮ Latent variables with state as a special case
◮ Avoids universal use of signal flow graphs
– p. 103/106
Behavioral systems
◮ Gets the physics right
◮ Starts with first principles models
◮ Latent variables with state as a special case
◮ Avoids universal use of signal flow graphs
◮ i/o and i/s/o are important special cases
– p. 103/106
Behavioral systems
◮ Gets the physics right
◮ Starts with first principles models
◮ Latent variables with state as a special case
◮ Avoids universal use of signal flow graphs
◮ i/o and i/s/o are important special cases
◮ Extends seamlessly to PDEs
– p. 103/106
Behavioral systems
◮ Controllability becomes genuine system property
– p. 104/106
Behavioral systems
◮ Controllability becomes genuine system property
◮ Deals faithfully with interconnections: variable sharing
– p. 104/106
Behavioral systems
◮ Controllability becomes genuine system property
◮ Deals faithfully with interconnections: variable sharing
◮ Views control as interconnection
– p. 104/106
Behavioral systems
◮ Controllability becomes genuine system property
◮ Deals faithfully with interconnections: variable sharing
◮ Views control as interconnection
◮ Advantages in SYSID with the MPUM, etc.
– p. 104/106
Behavioral systems
◮ Controllability becomes genuine system property
◮ Deals faithfully with interconnections: variable sharing
◮ Views control as interconnection
◮ Advantages in SYSID with the MPUM, etc.
◮ Natural approach to dissipative systems
– p. 104/106
Behavioral systems
◮ Controllability becomes genuine system property
◮ Deals faithfully with interconnections: variable sharing
◮ Views control as interconnection
◮ Advantages in SYSID with the MPUM, etc.
◮ Natural approach to dissipative systems
◮ Far easier pedagogically
– p. 104/106
1. A dynamical system = a family of trajectories.
2. Interconnection = variable sharing
3. Control = interconnection
– p. 105/106
Want to read about it? SeeThe behavioral approach to open and interconnected systems,Control Systems Magazine, Volume 27, pages 46-99, 2007.
The lecture frames are available from/athttp://www.esat.kuleuven.be/∼jwillems
– p. 106/106
Want to read about it? SeeThe behavioral approach to open and interconnected systems,Control Systems Magazine, Volume 27, pages 46-99, 2007.
The lecture frames are available from/athttp://www.esat.kuleuven.be/∼jwillems
Thank youThank you
Thank youThank you
Thank you
Thank you– p. 106/106