Interconnection Protocols

Interconnection Protocols

Berk ÜSTÜNDAĞIstanbul Technical UniversityComputer Engineering [email protected] http://berk.tc

Contents1.Introduction

1.1 Goals of the lecture

1.2 OSI Reference Model

2. Wired communication techniques

2.1 Asynchronous Serial Communication

2.1.1 RS232

2.1.2 RS485 / RS422

2.2 Synchronous Serial Communication

2.2.1 I2C

2.2.2 Microwire

2.2.3 SPI

2.2.4 USB

2.2.5 IEEE1394 (Firewire)

3. NonWired communication techniques

3.1 Optical Communication

3.1.2 IRDA

3.1.2 Optical Fibers

3.1.3 Laser

3.2 Radio Frequency Communication

3.2.1 Frequency allocation (ETSI)

3.2.2 Radiomodems

3.2.3 Bluetooth

3.2.4 IEEE802.11

3.2.5 GPRS, 3G, UMTS

4. Mobile Data Transfer

4.1 Smart Cards

4.2 Contactless Smart Cards

4.3 Touch Memory

4.4 Magnetic Strips (Cards)

4.5 PCMCIA cards

5. Application Examples

5.1 GPS (NMEA protocol), vehicle tracking

5.2 Can Bus – automative applications

5.3 Virtual Money

5.4 Mobile officers, PDA

5.5 PC AT keyboard interface

5.6 Pay TV

5.7 Energy meter (PLC-Power line data collection)

1. Introduction

1.1 Goals of the lecture

Selection of digital communication environment

Designing the wired/nonwired interface

Interconnetion software

Application development

1.2 OSI Reference ModelAs a first step in standardization, the International Standards Organization (ISO) developed a seven-layer model known as the ISO Open Systems Interconnection (OSI) reference model.

1-Physical layer:

The lowest layer, the physical layer, is concerned with transmitting raw bits over a communication channel. It is concerned with insuring that when one side sends a ``1'' bit, the other side receives a ``1'' bit. The physical layer is usually the focus of an electrical engineer and deals with such questions as How many volts represents a ``1'', how many a ``0''? How to generate a ``1'' and a ``0''? How long does a bit time last? How many pins does the connector have How many wires does the transmission media have? Are pulses electrical or optical?

2-Data link layer:

The data link layer converts the raw transmission of bits into an error-free data communciation channel. It deals with communication between two machines sharing a common physical channel. It

Divides the bit stream of physical layer into frames, messages that contain data and control information.

Handles lost, damaged, and duplicated frames (Why would it be possible to duplate frame? - error control, timed out).

Handles slowing down a fast transmitter. The process is known as flow-control. (Why flow-control? - much like water flow control)

•Switches and bridges use MAC addressing to make networking decisions and therefore these types of equipment function on the data link layer.

•IEEE 802 Standards•The 802 Project defines 12-plus subcommittee standards groups. Some are as follows:

•802.1

•Internetworking/LAN Protocols

•Defines routing, bridging, and internetwork communications

•802.2

•Logical Link Control (LLC)

•Allows Network layer protocols to link to Physical layer and MAC sublayer protocols

•802.3

•Ethernet •The Ethernet standard; defines CSMA/CD

•802.5

•Token Ring •Defines logical ring topology, media, and interfaces

•802.12

•High-speed networks •Defines 100 Mbps technologies

3-Network layer:

The network layer controls operation of the subnet (communicaiton between hosts). It

Directs (routes) packets from source to destination host (but may not guarantee that all packets are delivered).

Worries about congestion - hosts sending data into the network faster than the network can handle.

Deals with addressing: how do we specify which machine data should be delivered to?

4-Transport layer:

The transport layer makes sure data gets delivered to a specific process on a specific machine. It: Is an end-to-end protocol because it deals with the ultimate endpoints of communications, the sending and receiving applications. Deals with retransmitting data if the network layer fails to deliver it. Deals with suppressing duplicates. If it retransmits messages, it may introduce a duplicate, if the retransmission was unnecessary. Also deals with addressing. Which process on a particular machine?

5- Session layer:

A session can be considered as a one-run of a particular applicaiton. The session layer Provides a cleaner interface to the transport layer. For example, one that is not operating system specific (e.g. sockets). Provides synchronization such as recovering from transport layer failure. For example, a file transfer may take two minutes, during which the network failed (power outage, for example). As long as the host is still running properly, the session layer should recover from this network failure without much intervention of the users. Similar case in a PC editing program such as Word, if a bad disk is encountered, one shouldn't have to start from scratch.

6-Presentation layer:

The presentation layer performs sevices that are requested often enough to warrant development of a general solution. For example, Encoding data in a standard format, so that ASCII systems can communicate with EBCDIC systems. Compressing data to reduce communication costs.

Encrypting data for privacy.

7- Applicaiton layer: The application layer refers to the user programs themselves.

2.1 Asynchronous Serial Communication

Electronic data communications between elements will generally fall into two broad categories: single-ended and differential. RS232 (single-ended) was introduced in 1962, and despite rumors for its early demise, has remained widely used through the industry.

2.1.1 RS232 Data Interface

•Independent channels are established for two-way (full-duplex) communications

• The RS232 signals are represented by voltage levels with respect to a system common (power / logic ground). The "idle" state (MARK) has the signal level negative with respect to common, and the "active" state (SPACE) has the signal level positive with respect to common.

• RS232 has numerous handshaking lines (primarily used with modems), and also specifies a communications protocol.

•The RS-232 interface presupposes a common ground between the DTE and DCE. This is a reasonable assumption when a short cable connects the DTE to the DCE, but with longer lines and connections between devices that may be on different electrical busses with different grounds, this may not be true.

RS232 data is bi-polar....

+3 TO +12 volts indicates an "ON or 0-state (SPACE) condition" while A -3 to -12 volts indicates an "OFF" 1-state (MARK) condition

Modern computer equipment ignores the negative level and accepts a zero voltage level as the "OFF" state. In fact, the "ON" state may be achieved with lesser positive potential. This means circuits powered by 5 VDC are capable of driving RS232 circuits directly, however, the overall range that the RS232 signal may be transmitted/received may be dramatically reduced.

The types of driver ICs used in serial ports can be divided into three general categories:

•Drivers which require plus (+) and minus (-) voltage power supplies such as the 1488 series of interface integrated circuits. (Most desktop and tower PCs use this type of driver.) •Low power drivers which require one +5 volt power supply. This type of driver has an internal charge pump for voltage conversion. (Many industrial microprocessor controls use this type of driver.) •Low voltage (3.3 v) and low power drivers which meet the EIA-562 Standard. (Used on notebooks and laptops.)

Glossary of Abbreviations etc.

CTS Clear To Send [DCE --> DTE]DCD Data Carrier Detected (Tone from a modem) [DCE --> DTE]DCE Data Communications Equipment eg. modemDSR Data Set Ready [DCE --> DTE]DSRS Data Signal Rate Selector [DCE --> DTE] (Not commonly used)DTE Data Terminal Equipment eg. computer, printerDTR Data Terminal Ready [DTE --> DCE]FG Frame Ground (screen or chassis)NC No ConnectionRCk Receiver (external) Clock inputRI Ring Indicator (ringing tone detected)RTS Ready To Send [DTE --> DCE]RxD Received Data [DCE --> DTE]SG Signal GroundSCTS Secondary Clear To Send [DCE --> DTE]SDCD Secondary Data Carrier Detected (Tone from a modem) [DCE --> DTE]SRTS Secondary Ready To Send [DTE --> DCE]SRxD Secondary Received Data [DCE --> DTE]STxD Secondary Transmitted Data [DTE --> DTE]TxD Transmitted Data [DTE --> DTE]

Is Your Interface a DTE or a DCE?Find out by following these steps: The point of reference for all signals is the terminal (or PC).

1 ) Measure the DC voltages between (DB25) pins 2 & 7 and between pins 3 & 7. Be sure the black lead is connected to pin 7 (Signal Ground) and the red lead to whichever pin you are measuring.2) If the voltage on pin 2 (TD) is more negative than -3 Volts, then it is a DTE, otherwise it should be near zero volts.3) If the voltage on pin 3 (RD) is more negative than -3 Volts, then it is a DCE.4) If both pins 2 & 3 have a voltage of at least 3 volts, then either you are measuring incorrectly, or your device is not a standard EIA-232 device. Call technical support.5) In general, a DTE provides a voltage on TD, RTS, & DTR, whereas a DCE provides voltage on RD, CTS, DSR, & CD.

PC Com Port - EIA-574

RS-232 pin out DB-9 pin used for Asynchronous Data

Description Signal 9-pin DTE 25-pin DCE Source DTE or DEC

Carrier Detect CD 1 8 from Modem

Receive Data RD 2 3 from Modem

Transmit Data TD 3 2 from Terminal/Computer

Data Terminal Ready DTR 4 20 from Terminal/Computer

Signal Ground SG 5 7 from Modem

Data Set Ready DSR 6 6 from Modem

Request to Send RTS 7 4 from Terminal/Computer

Clear to Send CTS 8 5 from Modem

Ring Indicator RI 9 22 from Modem

RS232 (25 pin) Tail Circuit CableNull Modem Cable for Async or Sync data

Cross Pinned cables for Async data.

Pin out for local Async Data transfer

Pin No.

Signal Description Abbr.DTE

DCE

1 DCE Ready, Ring IndicatorDSR/RI

2Received Line Signal Detector

DCD

3 DTE Ready DTR

4 Signal Ground SG

5 Received Data RxD

6 Transmitted Data TxD

7 Clear To Send CTS

8 Request To Send RTS

RS232D uses RJ45 type connectors (similar to telephone connectors)

RS-232 Specs.

SPECIFICATIONS RS232 RS423

Mode of OperationSINGLE-ENDED

SINGLE-ENDED

Total Number of Drivers and Receivers on One Line

1 DRIVER1 RECVR

1 DRIVER10 RECVRMaximum Cable Length 50 FT. 4000 FT.

Maximum Data Rate 20kb/s 100kb/sMaximum Driver Output Voltage +/-25V +/-6VDriver Output Signal Level (Loaded Min.)

Loaded+/-5V to +/-15V

+/-3.6VDriver Output Signal Level (Unloaded Max)

Unloaded +/-25V +/-6VDriver Load Impedance (Ohms) 3k to 7k >=450Max. Driver Current in High Z State

Power On

N/A N/AMax. Driver Current in High Z State

Power Off

+/-6mA @ +/-2v

+/-100uASlew Rate (Max.) 30V/uS

Adjustable

Receiver Input Voltage Range +/-15V +/-12VReceiver Input Sensitivity +/-3V +/-200mVReceiver Input Resistance (Ohms) 3k to 7k 4k min.

One byte of async data

•The RS-232 signal on a single cable is impossible to screen effectively for noise.

• By screening the entire cable we can reduce the influence of outside noise, but internally generated noise remains a problem. As the baud rate and line length increase, the effect of capacitance between the different lines introduces serious crosstalk (this especially true on synchronous data - because of the clock lines) until a point is reached where the data itself is unreadable.

• Signal Crosstalk can be reduced by using low capacitance cable and shielding each pair

How to Get power out of PC RS-232 port ...

Example: PC mouse and software protection dongle

Another choice is the same cable commonly used in the Twisted pair Ethernet cabling. This cable, commonly referred to as Category 5 cable, is defined by the ElA/TIA/ANSI 568 specification The extremely high volume of Category 5 cable used makes it widely available and very inexpensive, often less than half the price of specialty RS422/485 cabling. The cable has a maximum capacitance of 17 pF/ft (14.5 pF typical) and characteristic impedance of 100 ohms.

Category 5 cable is available as shielded twisted pair (STP) as well as unshielded twisted pair (UTP) and generally exceeds the recommendations making it an excellent choice for RS232 systems.

Interfacing Example - Analog Sampling Via the RS-232 Port

The above circuit when in a working state, will wait for a byte to be sent to it before it starts the analog conversion and sends data back to the computer using the 8N1 serial format at 9600 BPS. The circuit is based on a CDP6402C or equivalent UART. This, if you want to call it, is the brains of the operation and performs the conversion of Parallel data to a Serial format for transmission. The Analog to Digital Conversion is done by the ADC0804, while the MAX232 is used to convert TTL/CMOS voltage levels into RS-232 Voltage Levels. The 74HC4060 is a Oscillator/Divider which is used to generate the UART's Clock. The Analog to Digital Converter (ADC0804) starts it's conversion when the UART's Data Received line becomes active. Many people at this stage will say that this circuit cannot work! - The Data Received (DR) output is Active High, while the nWrite (WR) input to the ADC is a Active Low. This circuit is quite correct. If we look at the ADC's operation, on a high to low transition of the nWrite input the internal Successive Approximation and Shift Registers are reset. Provided the nWrite line remains in this state the ADC will remain reset. The conversion process will start when a low to high transition is made on the nWrite input. Therefore getting back to this circuit, the Data Received output will remain low while there is no data to be received, thus the ADC will remain in the reset mode. When data is received by the UART, a low to high transition will result on the Data Received line and thus on the connected nWrite pin of the ADC. This low to high transition will cause the ADC to spring to life and make a digital conversion of the analog voltage on it's pins. Once the conversion is finished, it's nINTR (Interrupt) line will become active low. This signal is then used to tell the UART to send the data residing on it's Transmitter Buffer Register inputs (TBR8:TBR1). nINTR is also connected to the UART's Data Received Reset so that the Data Received line will be reset. The circuit is then ready to repeat the entire process upon receiving the next byte.

ESD Considerations for RS-232 Drivers

For applications that suffer from the hazard of overvoltage due to lightning, ESD potential, or accidental transient voltage streeses, a bi-directional zener diode, such as a TranZorbTM, dissipates the external energy before it gets to the silicon chip. Additional series resistors limit the maximum current that the internal structures can withstand. Outputs usually have a low impedence and require less attention.

For maximum safety, the approach in Figure requires the least board space while protecting each individual terminal.

Circuit Diagram of Isolated RS232C Interface

1 2 C2,C1 470nF 2 2 C3,C4 100nF 3 2 D2,D1 1N4148 4 2 D4,D3 LED RED 3mm 5 1 K1 DB9 R/A PCB TYPE PLUG 6 1 K2 PCB TERMINAL BLOCK 4 WAY 7 1 R1 1K

8 1 R2 1K5 9 1 R3 100R 10 2 R4,R7 680R 11 2 R5,R8 4K7 12 1 R6 270R 13 1 U1 6N137 14 1 U2 CNY17-3, 4N37 15 1 U3 74HC14

In a daisy-chain configuration, the RS-232 signal enters through one receiver, is looped through to a transmitter, and then goes to the next unit. Cable breaks are a major problem for this technique. A break between slave 1 and slave 2, for instance, prevents all downstream units from transmitting or receiving data. Other multi-drop RS232 techniques involve pre-buffering or boosting the RS-232 output drive (enabling it to drive multiple 5k inputs in parallel) or switching out the input resistance.

Daisy-chain configuration

How And What Do We Attach To Messages

One simplest way is to use parity check. Add an extra bit so that the number of 1s in a message is even (or odd). Whether it is even or odd is pre-determined, known as even parity check, or odd parity check. For example, if we decide to use even parity check, the message being sent is 1001100 which is 7 bits. We would add an 1 to the end so that the number of 1s are even. The actual message being sent will be 10011001, last bit being a partiy check bit. This actually is a special case of a class of error-correcting code based on what is called Hamming distance.

1.What is CRC?CRC stands for Cyclic Redundancy Check. Which means that is based on cyclic algorithm that generates redundant information.The CRC performs a mathematical calculation on a block of data and returns information (number) about the contents and organization of that data. So the resultant number uniquely identifies that block of data. This unique number can be used to check the validity of data or to compare two blocks. So this approach is used in many communication and computer systems to ensure the validity of the transmitted or stored data.1.In general CRC codes are able to detect:

•All single- and double-bit errors. •All odd numbers of errors. •All burst errors less than or equal to the degree of the polynomial used. •Most burst errors greater than the degree of the polynomial used.

Check sum concept

One approach in of error checking is to append the sum value of all message bytes to the end of the message. This sum can identify the message and changes in its contents. On the other hand, if there is more than one change one that adds up a value and one subtracts one in a way that the sum remains the same, so it can not be used to detect errors. The same can happen if the check sum is changed with the same value as the message.

CRC idea

The main idea of CRC is to treat the message as binary numbers, and divide it by fixed binary number. The remainder from this division is considered the checksum. The recipient of the message performs the same division and compare the remainder with the "checksum" (transmitted remainder).

Theory of operation:The CRC is a simple binary division and subtraction. The only difference is that these operations are done on modulo arithmetic based on mod 2. For example the addition and subtraction are replaced with XOR operation that do the sum and subtraction without carry.

Polynomial conceptThe CRC algorithm uses the term polynomial to perform all of its calculations. This polynomial is the same concept as the traditional arithmetic polynomials. The divisor, dividend, quotient, and remainder that are represented by numbers are represented as polynomials with binary coefficients.For example the number 23 (10111b) can be represented in the polynomial form as:

1*x4 + 0*x3 + 1*x2 + 1*x1 + 1*x0

orx4 + x2 + x1 + x0

Note the binary representation of the number (10111).This representation simplifies the traditional arithmetic operations (addition, multiplication, etc…) that are all

done on normal algebraic polynomials.If we can assume that X is 2, then the operations are simplified more and some because some terms can be canceled. For example the term 3*x3 is represented as 24 in normal number representation and 24 = 16+8

which is x4+x3 in polynomial representation.

Generator polynomial:In order to do the CRC calculation; a divisor must be selected which can be any one. This divisor is called the generator polynomial. Even though, some polynomials became standard for many applications. Polynomial selection is behind the scope of this summary.One of the most used terms in CRC is the width of the polynomial. This width is represented by the order of the highest power in the polynomial. The width of the polynomial in the previous example is 4, which has 5 bits in its binary representation.Since CRC is used to detect errors, a suitable generator polynomial must be selected for each application. This is because each polynomial has different error detection capabilities.CRC algorithms are commonly called after the generator polynomial width, for example CRC-16 uses a generator polynomial of width 15 and 16-bit register and CRC-32 uses polynomial width of 31 and 32-bit register.

CRC Example Number 1

M=1010001101 (k=10) and,P=110101 (n+1=6)Then the FCS to be calculated by the transmitter will be n=5 bits in length. Lets assume that the transmitter has calculated the FCS to be:F=1110 (n=5)Then the transmitted frame will be:T=1010001101 1110

Following is a review of the CRC creation process:

1.Get the raw frame 2.Left shift the raw frame by n bits and the divide it by P. 3.The reminder of the last action is the FCS. 4.Append the FCS to the raw frame. The result is the frame to transmit

And a review of the CRC check process:1.Receive the frame. 2.Divide it by P. 3.Check the reminder. If not zero then there is an error in the frame.

The main idea behind the CRC algorithm is that the FCS is generated so that the reminder of T/P is zero. Its clear that(1) T= M * x^n + FThis is because by cascading F to M we have shifted T by n bits to the left and then added F to the result. We want the transmitted frame, T, to be exactly divisible by the pre-defined polynomial P, so we would have to find a suitable Frame Check Sequence (F) for every raw message (M). Suppose we divided only M*x^n by P, we would get:(2) M*x^n / P = Q + R/P There is a quotient and a reminder. We will use this reminder, R, as our FCS (F). Returning to Eq. 1: (3) T= M*x^n + RWe will now show that this selection of the FCS makes the transmitted frame (T) exactly divisible by P: (4) T/P = (M*x^n + R)/P = M*x^n / P +R/P = Q + R/P + R/P = Q + (R+R)/P but any binary number added to itself in a modulo 2 field yields zero so: (5) T/P = Q, With no reminder.

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Interconnection Protocols