Interface Engineering of Extremely Scaled Silicate Gate

2012 Master Thesis

Interface Engineering of Extremely

Scaled Silicate Gate Dielectrics

-EOT of 0.5 nm and beyond-

Daisuke Kitayama

Department of Electrical and Electronic Engineering

Tokyo Institute of Technology

Supervisor: Prof. Hiroshi Iwai

Interface Engineering of Extremely Scaled Silicate Gate Dielectrics

- 2 -

February, 2012 Abstract of Master Thesis


-EOT of 0.5 nm and beyond-

Supervisor: Prof. Hiroshi Iwai

Tokyo Institute of Technology

Department of Electrical and Electronic Engineering

10M36132 Daisuke Kitayama

High-k materials have been introduced as gate dielectrics to extend device

scaling which is hindered due to excess gate leakage current and short channel

effects. Rare-earth (RE) oxides such as La2O3 have an advantage to achieve ultimate

requirement for an EOT of 0.5 nm, since they can achieve direct contact on Si

substrate by forming RE-silicate at high-k/Si interface easily. One of the issues of

La2O3 dielectrics is the excess growth of the silicate layer post annealing, which

increases EOT. In addition, degradation in the mobility is a commonly observed

issue when the thickness of La2O3 or other high-k materials becomes thinner than a

certain value. Therefore, the suppression of EOT increase and mobility degradation

is of utmost important to achieve high performance MOSFETs. In this thesis, various

approaches are employed for interface engineering to overcome these critical issues.

Silicate layer formation is promoted by the presence of oxygen atoms. Thus, as

a novel method to control the silicate reaction, the influence of the thickness of W


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which is an oxygen-containing gate metal on the electrical characteristics has been

investigated. Almost no change in EOT from the as-deposited condition was

observed and an appropriate transistor operation at EOT of 0.5 nm has been

confirmed by short time annealing at high temperature. However, small effective

mobility indicates the existence of fixed charges induced by oxygen vacancies and

metal atoms diffusion from gate electrode. A thin layer of Si was deposited between

W and La2O3 to create an amorphous La-silicate layer at gate metal/La2O3 interface,

anticipating a reduction of the fixed charges enhanced by the grain boundaries within

high-k layer. As a result, net positive fixed charges were reduced and a large

improvement in mobility has been confirmed.

Moreover, the effect of annealing ambient gas during silicate formation on

device electrical characteristics has been investigated, suspecting the formation of

oxygen vacancies induced by annealing in reducing ambient. It has been confirmed

that the high-k dielectric oxygen vacancies can be prevented by separating the

annealing process for silicate formation and for dangling bond termination.

Consequently, La2O3-based MOSFETs with a high temperature annealing in N2

ambient for silicate formation, and a low temperature annealing in FG ambient for

dangling bond termination, achieve slightly higher mobility than record data with

Hf-based oxide. This is especially apparent at low electric field region. These

achievements provide a useful guidance for fabricating MOSFETs with high

performance and small EOT.


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Contents

Chapter 1. Introduction

1.1 Introduction of high-k materials as gate dielectrics.......................9

1.2 Issues in high-k gate dielectrics......................................................11

1.3 Reported Hf-based oxides with direct contact structure.............12

1.4 La2O3 as high-k gate dielectrics.....................................................13

1.5 Issues in RE-oxides

1.5.1 Increase in EOT by high temperature annealing…....................15

1.5.2 Mobility degradation by EOT scaling........................................18

1.6 Purpose of this study.......................................................................20

References..............................................................................................22

Chapter 2. Fabrication and Characterization

2.1 Fabrication procedure.....................................................................27

2.2 Experimental principle

2.2.1 SPM cleaning and HF treatment................................................28

2.2.2 RE-oxides deposition by MBE...................................................28

2.2.3 RF magnetron sputtering............................................................29

2.2.4 Dry etching by RIE.....................................................................30

2.2.5 PMA in F.G. ambient..................................................................31

2.2.6 Wet etching with HCl and BHF..................................................31

2.2.7 Vacuum evaporation for Al deposition.......................................31


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2.3 Characterization of MOS Device

2.3.1 Threshold voltage extraction…………………………………34

2.3.2 Subthreshold slope measurement……………………………...35

2.3.3 Mobility measurement method based on split C-V……………37

References……………………………………………………………..40

Chapter 3. Selection of High-k Dielectrics with

Annealing Process

3.1 Introduction……………………………………………………..42

3.2 Effect of annealing temperature and time……………………..44

3.3 CeOx insertion at Si substrate interface

3.3.1 Direct contact with Si substrate…………………………….....47

3.3.2 Comparison of La2O3 and La2O3/CeOx structure……………..51

3.3.3 Effect of annealing temperature and time with La2O3/CeOx

stacked gate dielectric………………………………………..54

3.4 MOSFET characteristics for La2O3/CeOx dielectric with EOT of

0.50 nm under different annealing conditions…………….……..58

3.5 Conclusion………………………………………………………..62

References……………………………………………………………..63


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Chapter 4. Selection of Metal Electrode for

Controlling Silicate Reaction

4.1 Introduction……………………………………………………..66

4.2 Control of silicate reaction by TiN/W gate electrode…………...69

4.3 Effect of W electrode thickness on electrical characteristic…....74

4.4 MOSFET characteristics with thin W film……………….……..81

4.5 Conclusion………………………………………………………..84

References……………………………………………………………..85

Chapter 5. Thin Si Insertion at Metal Gate/High-k

Interface

5.1 Introduction……………………………………………………..89

5.2 Electrical characteristics for MOS capacitors…………………..94

5.3 Electrical characteristics for MOS transistors……………….....97

5.4 Quantitative understanding for mobility improvement…….104

5.5 Conclusion………………………………………………………..108

References…………………………………………………………....109

Chapter 6. Influence of Annealing Ambient during

Siliicate Formation on Electrical Characteristics

6.1 Introduction………………………………………………………111

6.2 Electrical characteristics with capacitors……………………....115


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6.3 Results with transistors………………………………………….117

6.4 Conclusion………………………………………………………..123

References…………………………………………………………....124

Chapter 7. Conclusions............................................................126

Publications and Presentations...........................................131

Acknowledgements....................................................................135


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Chapter 1 Introduction

1.1 Introduction of high-k materials as gate dielectrics

1.2 Issues in high-k gate dielectrics

1.3 Reported Hf-based oxides with direct contact structure

1.4 La2O3 as high-k gate dielectrics


1.5.1 Increase in EOT by high temperature annealing

1.5.2 Mobility degradation by EOT scaling

1.6 Purpose of this study

References


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1.1 Introduction of high-k materials as gate dielectrics

Metal-oxide-semiconductor field effect transistor (MOSFET) is a requisite element

for very large scale integration (VLSI) technology, which is commonly used in

modern electronic equipments which are indispensable for our modern life. The

progress in VLSI technology thus improves the quality of life. The key to the

advancement of VLSI technology is the device scaling which means scaling down

the size of MOSFETs. Table 1.1 shows the scaling rules for various device and

circuit parameters. Scaling rules show speed up of circuit and reduction of power

consumption are obtained with the scaling of the device dimensions [1.1]. Therefore,

scaling leads to improvement of convenience for people and saving energy. However,

increase in the leakage current due to thinned physical thickness of SiO2, which have

been used as gate dielectrics, has been one of the problems [1.2]. Instead of SiO2,

materials with high dielectric constant (high-k) are required as gate dielectrics of

MOSFETs. High-k materials make it possible to thicken physical thickness with the

same equivalent oxide thickness (EOT), which means physical thickness can be

thickened with the same gate capacitance (Figure 1.1) [1.3]. The EOT can be written

as

oxkhigh

SiOtEOT

2 , (1.1)

where SiO2 and high-k are the permittivity of SiO2 and that of high-k materials,

respectively.

Therefore, study of high-k materials as gate dielectrics is important.


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1/sCircuit delay time (t)

1/sGate capacitance (Cox)

Multiplicative factor

Parameters

1/s2Device area (A)

1/s2Power consumption (P)

1/sChannel length (L)

sDoping concentration (N)

1/sGate oxide thickness (tox)

1/sChannel width (W)

1/sCircuit delay time (t)

1/sGate capacitance (Cox)

Multiplicative factor

Parameters

1/s2Device area (A)

1/s2Power consumption (P)

1/sChannel length (L)

sDoping concentration (N)

1/sGate oxide thickness (tox)

1/sChannel width (W)

Table 1.1 Constant-field scaling of MOSFET device and circuit

parameters. The scaling remains electrical field unchanged. Speed

up of circuit and reduction of power consumption is obtained with

the scaling

Gate

SiO2

S D

Si substrate

Gate

High-k

S D

Si substrate

Same EOT↓

Same gate capacitance

Figure 1.1 High-k dielectrics make it possible to get larger physical

thickness than SiO2 with same gate capacitance.


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1.2 Issues in high-k gate dielectrics

The high-k dielectrics have been studied for advanced MOSFETs mainly with

interfacial SiO2 layer to recover the degraded carrier mobility and enhance reliability

[1.4]. However, the thickness of SiO2 interfacial layer (IL) of small dielectric

constant would become a limit of EOT scaling [1.5]. Therefore, direct contact of

high-k/Si substrate (without SiO2-IL structure) is required for further scaling [1.6].

Nowadays, Hf-based oxides have been extensively studied as high-k gate dielectrics

and already in practical use. However, Hf-based oxides form SiO2-IL between high-k

dielectrics and Si substrate after annealing (Figure 1.2). In order to achieve a direct

contact of high-k/Si, the choice of high-k gate dielectrics is important.

Gate

Hf-basedoxides

Si substrate

Gate

Hf-basedoxides

Si substrate

SiO2

Anneal

Fig. 1.2 Cross sectional TEM image of HfO2 gate dielectrics after annealing.

Hf-based oxides form SiO2-IL easily after annealing.


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1.3 Reported Hf-based oxides with direct contact structure

Here are the examples of direct contact of HfO2/Si structure (Figure 1.3). In the

figures on the left hand side, SiO2-based IL was completely removed when TaN

electrode was alloyed with a scavenging element [1.7]. Then, capacitance-voltage

(C-V) characteristic shows dramatic EOT scaling with direct contact of high-k/Si.

In the figures on the right hand side, there is no SiO2-IL, where scavenging element

is doped in TiN electrode, resulting in achievement of small EOT of 0.54 nm with

direct contact structure [1.8]. In both cases, the direct contact of high-k/Si has been

achieved by selection of gate material to control the oxygen atoms.

K. Choi, et al., VLSI symp. Tech. p.138 (2009). T. Ando, et al., IEDM, Tech. p.423 (2009).

Fig. 1.3 Examples of the direct contact of HfO2/Si. In the case of Hf-based oxide,

the direct contact of high-k/Si has been achieved by controlling the oxygen atoms

[1.7, 1.8].


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1.4 La2O3 as high-k gate dielectrics

Besides process approaches shown in chapter 1.3, a direct contact of high-k/Si can

be achieved using rare-earth oxides (RE-oxides) such as La2O3 as gate dielectrics

[1.9-1.10]. A La2O3 can achieve a direct contact of high-k/Si structure by forming a

La-silicate layer of fairly high dielectric constant at the high-k/Si substrate interface.

Annealing of RE-oxides in oxygen containing atmospheres result in competing

reactions of interfacial SiO2 formation by oxygen diffusion through the high-k film

Gate

RE-oxides

Si substrate

Gate

RE-oxides

Si substrate

RE-silicate

Direct contactof high-k/Si

Anneal

Figure 1.4 RE-oxides can achieve direct contact of high-k/Si by forming silicate

easily. Cross sectional TEM image of La2O3/Si shows direct contact of high-k/Si by

forming La-silicate.


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and the RE-oxide to RE-silicate. In contrast to Hf-based oxides, RE-oxides have a

much greater driving force to form the silicate [1.11]. The k-value and bandgap of

each RE-oxides and its silicate is summarized in table 1.2 [1.12]. Fig. 1.4 shows a

cross sectional TEM image of MOS structure with La2O3 dielectric. Direct contact of

high-k/Si by forming La-silicate can be seen. In addition, a fairly good interfacial

property with a peak effective mobility of over 300 cm2 V-1 s-1 has been reported for

La2O3 gate dielectric [1.13]. Therefore, we select the La2O3 as gate dielectrics.

0 10 20 30 40 50 602

3

4

5

6

7

8

9

10

Ban

d G

ap [

eV]

dielectric constant,

0 10 20 30 40 50 602

3

4

5

6

7

8

9

10

Ban

d G

ap [

eV]

dielectric constant,

La2O3

J. Robertson, Solid-State Electronics 49 (2005) 283–293

6.5~10Pr-silicate

6.1~21Ce-silicate

6.4~9La-silicate

5.532Pr6O11

3.232CeO2

5.524La2O3

Eg (eV)Dielectric constant

Oxide

6.5~10Pr-silicate

6.1~21Ce-silicate

6.4~9La-silicate

5.532Pr6O11

3.232CeO2

5.524La2O3

Eg (eV)Dielectric constant

Oxide

Table 1.2 dielectric constant and bandgap of RE-oxides and its silicates [1.12].


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1.5.1 Increase in EOT by high temperature annealing

As described in chapter 1.1, EOT scaling is required for performance improvement

of MOSFETs. Figure 1.5 shows the EOT requirement as a function of year [1.14]. In

the near future, extremely small EOT of 0.5 nm is required for high-k gate dielectrics.

RE-oxides have an advantage to achieve EOT requirement, since it can achieve

direct contact of high-k/Si easily. However, one of the issues of RE-oxides is increase

of EOT by high temperature annealing [1.15]. Annealing temperature dependence of

EOT for La2O3 gate dielectric is shown in figure 1.6. The increase of EOT

accompanied with increase of annealing temperature can be confirmed.

0

0.2

0.4

0.6

0.8

1

1.2

2009 2014 2019 2024

ITRS 2009

Year

EO

T(n

m)

EOT=0.5 nm

bulk

MG

UTB FD

Effective oxide thickness

Figure 1.5 EOT requirements of ITRS 2009. An extremely small EOT of 0.5 nm is

required in the near future.


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0.0

0.4

0.8

1.2

1.6

2.0

As deposited200 400 600 800 1000

La2O3 (3nm)

Annealing time=30 min

Annealing temperature (oC)

EO

T (

nm

)

Figure 1.6 Annealing temperature dependence of EOT with La2O3 dielectric. An

EOT is increased by high temperature annealing.

0

0.05

0.1

0.15

0.2

0.25

1839184018411842184318441845

Si 1sAnnealed for 2 s

Inte

nsi

ty (

a.u

.)

Binding energy (eV)

Inte

nsi

ty (

a.u

.) La-richsilicate

As depo 700 oC

1000 oC

Si sub.SiO2

hν=7940 eVspring-8 BL46XU La-silicate

Figure 1.7 Si 1s photoelectron spectra arising from La2O3 deposited sample. A

positive correlation of the amount of La-silicate layer with annealing temperature is

observed..


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Figure 1.7 shows Si 1s photoelectron spectra arising from La2O3 deposited sample

measured by XPS as a function of annealing temperature. A positive correlation of

the amount of La-silicate layer with annealing temperature is observed. Therefore,

the increase of EOT accompanied with the increase of annealing temperature is

considered to be due to excess growth of silicate layer. To meet the requirement of

EOT scaling, excess silicate formation has to be prevented.


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1.5.2 Mobility degradation by EOT scaling

Figure 1.8 shows the peak effective electron mobility of La2O3 gated MOSFETs as a

function of EOT [1.13]. It is confirmed that the mobility degradation accompanied

with the EOT scaling is occurred. This mobility degradation is anticipated to reduce

effectiveness of scaling. Interfacial trap density and subthreshold slope of La2O3

gated MOSFETs as a function of EOT is shown in figure 1.9. Characteristics

degradation accompanied with the EOT scaling is observed as well as mobility

degradation.

W/La2O3/Si n-MOSFET

0

50

100

150

200

250

300

350

400

0 0.2 0.4 0.6 0.8 1.0

1.04nm1.37nm1.56nm1.74nmEOT

450

PMA500oC

Degrading

Eeff (MV/cm)

eff

(cm

2/ V

s)

J. A. Ng et al.: IEICE Electronics Express 3 (2006) 316

Figure 1.8 Peak effective electron mobility of La2O3 gated MOSFETs as a function of

EOT. The mobility degradation accompanied with the EOT scaling is observed

[1.13].


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EOT (nm)

1011

1012D

it(e

V-1

cm-2

)

507090

110130150170

S.S

(m

V/d

ec)

Vd=50mV

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

CP@1MHz

Figure 1.9 Interfacial trap density and subthreshold slope of La2O3 gated MOSFETs

as a function of EOT. Characteristics degradation accompanied with the EOT

scaling is observed as well as mobility degradation. [1.16]

It is reported that the metal atoms diffused from gate electrode to gate dielectrics

degrade the interfacial properties [1.16]. Moreover, mobility degradation

accompanied with EOT scaling by generation of fixed charges induced by oxygen

vacancies or metal atoms diffused from the gate electrode [1.17, 1.18]. In any case,

the fixed charges play an important role for the mobility degradation.


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1.6 Purpose of this study

As discussed in previous chapter, the suppression of the increase in EOT and that of

mobility degradation are important to achieve MOSFETs with high performance. In

this thesis, novel methods to overcome these issues are investigated by various

approaches.

In chapter 3, the effect of short time annealing at high temperature is examined to

suppress the EOT increase by high temperature annealing. Moreover, a gate stack

structure using CeOx which can form silicate layer with high permittivity is

investigated.

In chapter 4, as a method to control the amount of oxygen atoms supplied, the

influence of the thickness of an oxygen-containing gate metal on the electrical

characteristics is investigated to control the silicate reaction during high temperature

annealing.

In chapter 5, a thin amorphous La-silicate layer formed by Si deposition at the

interface of W and La2O3 is examined, anticipating formation of the amorphous

La-silicate layer at the metal gate/La2O3 interface eliminate the grain boundaries. As

a result, diffusion of metal atoms thorough grain boundaries and oxygen vacancies

segregated at grain boundaries might be reduced. Then, its effect on the electrical

characteristics at scaled EOT has been observed.

In chapter 6, the effect of annealing ambient during silicate formation on electrical

characteristics is examined, being anxious about formation of oxygen vacancies

induced by annealing in reducing ambient. The fabricated samples are subjected to

annealing in F.G. or N2 ambient.

Finally, chapter 7 summarizes this study.


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As described above, chapter 1 summarizes the background and the purpose of this

study. Figure 1.10 shows the contents of this thesis. This thesis is consisted of 7

parts.

Chapter 1Introduction

Chapter 2Fabrication and Characterization

Chapter 3Selection of High-k Dielectrics

with Annealing Process

Chapter 4Selection of Metal Electrode

for Controlling Silicate Reaction

Chapter 5Thin Si Insertion

at Metal Gate/High-k Interface

Chapter 6Influence of Annealing Ambient

during Silicate FormationOn Electrical Characteristics

Chapter 7Conclusion

Figure 1.10 Contents of this thesis


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References

[1.1] Y. Taur, T. H. Ning: “Fundamentals of MODERN VLSI DEVICES”,

Cambridge University Press, (1998) p.165,

[1.2] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M.

Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance

and low-power logic transistor applications”, IEEE Trans. Nanotechnol., 4 (2005) p.

153.

[1.3] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M.

Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R.

Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly,

P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B.

McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M.

Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D.

Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams,

and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors,

Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100%

Pb-free Packaging”, IEDM Tech. Dig., 2007, p. 247.


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[1.4] S. Saito, K. Torii, Y. Shimamoto, O. Tonomura, D. Hisamoto, T. Onai, M.

Hiratani, S. Kimura, Y. Manabe, M. Caymax, and J. W. Maes,

“Remote-charge-scattering limited mobility in field-effect transistors with SiO2 and

Al2O3/SiO2 gate stacks”, J. Appl. Phys. 98 (2005) p. 113706.

[1.5] M. Takahashi, A. Ogawa, A. Hirano, Y. Kamimuta, Y. Watanabe, K. Iwamoto, S.

Migita, N. Yasuda, H. Ota, T. Nabatame, and A. Toriumi, “Gate-First Processed

FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm –Interfacial Layer Formation by

Cycle-by-Cycle Deposition and Annealing-”, IEDM Tech. Dig., 2007, p. 523.

[1.6] K. Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M.

Wang, E. Cartier, S. Zafar, J. Bruley, A. Kerber, B. Linder, A. Callegari, Q. Yang, S.

Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan: VLSI Symp. Tech.

Dig., 2009, p. 138.

[1.7] K. Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M.

Wang, E. Cartier, S. Zafar, J. Bruley, A. Kerber, B. Linder, A. Callegari, Q. Yang, S.

Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan, “Extremely Scaled

Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial

Layer Scavenging Techniques for 22nm Technology Node and Beyond”, VLSI Symp.

Tech. Dig., 2009, p. 138.


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[1.8] T. Ando, M. M. Frank, K. Choi, C. Choi, J. Bruley, M. Hopstaken, M. Copel, E.

Cartier, A. Kerber, A. Callegari, D. Lacey, S. Brown, Q. Yang, and V. Narayanan,

“Understanding Mobility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm)

Using Remote Interfacial Layer Scavenging Technique and Vt-tuning Dipoles with

Gate-First Process“, IEDM Tech. Dig., 2009, p.423.

[1.9] S. J. Jo, J. S. Ha, N. K. Park, D. K. Kang, and B. H. Kim, “5 nm thick

lanthanum oxide thin films grown on Si(100) by atomic layer deposition: The effect

of post-annealing on the electrical properties”, Thin Solid Films, 513 (2006) p. 253.

[1.10] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T.

Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, and H. Iwai, “Advantage of

La2O3 Gate Dielectric over HfO2 for Direct Contact and Mobility Improvement”,

Proc. ESSDERC, 2008, p. 126.

[1.11] S. Stemmer, “Thermodynamic considerations in the stability of binary oxides

for alternative gate dielectrics in complementary metal-oxide-semiconductors”, J.

Vac. Sci. Technol. B, 22 (2004) p. 791.

[1.12] J. Robertson, “Interface and defects of high-k oxides on silicon”, Solid-State

Electron., 49 (2005) p.283.


- 25 -

[1.13] J. A. Ng, N. Sugii, K. Kakushima, P. Ahmet, K. Tsutsui, T. Hattori, and H.

Iwai, “Effective mobility and interface-state density of La2O3 nMISFETs after post

deposition annealing”, IEICE Electron. Express, 3 (2006) p. 316.

[1.14] International Technology Roadmap for Semiconductors (ITRS) 2009 roadmap.

[1.15] Y. Kim, K. Miyauchi, S. Ohmi, K. Tsutsui, and H. Iwai, “Electrical properties

of vacuum annealed La2O3 thin films grown by E-beam evaporation”, Microelectron.

J. 36 (2005) p. 41.

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Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, and H. Iwai, “Interface and

electrical properties of La-silicate for direct contact of high-k with silicon”,

Solid-State Electron., 54 (2010) p. 715.

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T. Hattori, and H. Iwai, “Characterization of flatband voltage roll-off and roll-up

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metal impurities”, Phys. Rev. B, 41 (1990) p. 5075.


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Chapter 2 Fabrication and Characterization

2.1 Fabrication procedure


2.2.1 SPM cleaning and HF treatment

2.2.2 RE-oxides deposition by MBE

2.2.3 RF magnetron sputtering

2.2.4 Dry etching by RIE

2.2.5 PMA in F.G. ambient

2.2.6 Wet etching with HCl and BHF

2.2.7 Vacuum evaporation for Al deposition


2.3.1 Threshold voltage extraction

2.3.2 Subthreshold slope measurement

2.3.3 Mobility measurement method based on split C-V

References


- 27 -

2.1 Fabrication procedure

Fig. 2.1 shows the fabrication flow of capacitors and transistors. MOS capacitors

and transistors were fabricated on HF-last n-type Si (100) substrates. Thin films of

RE-oxides (La2O3, CeOx, and Pr6O11) were successively deposited by MBE. A

tungsten film was in situ deposited by magnetron sputtering to avoid any moisture or

carbon-related contamination. The gate electrodes were patterned by reactive-ion

etching (RIE) with SF6. The samples were subjected to RTA at different annealing

conditions. In order to contact with source and drain of transistor, RE-oxides and

SiO2 were etched by HCl and buffered HF (BHF). Al contact layers on the front and

backside of the substrate were deposited by thermal evaporation.

Metal deposition by RF-sputtering

Source/Drainpre-formed Substrate

(3×1016 cm-3)

High-k e-beam evaporation@ 300oC under ~10-6 Pa

Metal dry etching

SPM, HF-last treatment

Backside contact formation (Al)

Post metallization annealing (PMA)

Contact hole formation

Al wiring for S/D

n-Si Substrate(3×1015 cm-3)

capacitor transistor

[Chapter 2.2.3]

[Chapter 2.2.2]

[Chapter 2.2.4]

[Chapter 2.2.1]

[Chapter 2.2.7]

[Chapter 2.2.5]

[Chapter 2.2.6]

[Chapter 2.2.7]

Figure 2.1 Experimental procedure of capacitor and transistor


- 28 -


2.2.1 SPM cleaning and HF treatment

Particles and organic substance at the surface of Si substrate become a cause of false

operation. Therefore, it is important to clean the surface of Si substrate. SPM

cleaning is one of the effective cleaning methods. The cleaning liquid is made from

H2O2 and H2SO4 (H2O2:H2SO4 = 1:4). Because of its oxidizability, particles and

organic substance are oxidized and separated from the surface of Si substrate.

However, the surface of Si substrate is oxidized and SiO2 is formed during SPM

cleaning. 1% HF is used to eliminate the SiO2.

2.2.2 RE-oxides deposition by MBE

Molecular beam epitaxy (MBE) is one of the deposition methods for crystalline

growth, which is classified into vacuum evaporation. A source material of RE-oxide

is heated by electron beam (E-beam) and emits the molecules. The deposition is done

in ultra high vacuum (~10-6 Pa), so that the molecule of RE-oxide doesn’t absorb the

scattering of other molecules and be deposited on substrates. The physical thickness

of deposited film is measured by crystal oscillator. Fig. 2.2 shows a schematic

illustration of MBE.


- 29 -

ultra high vacuum (~10-6 Pa)

shutter

sourceE-beam

molecule beam

substrate

crystal oscillator

Pr6O11 La2O3

CeOx

Figure 2.2 Schematic illustration of MBE.

2.2.3 RF magnetron sputtering

Tungsten which is used as gate electrode in this study is deposited by radio

frequency (RF) magnetron sputtering with Ar gas. An RF with 13.56 MHz at a power

of 150 W is applied between substrate side and target (W) side. Because of the

difference of mass, Ar ions and electrons are separated. A magnet is set underneath

the target, so that the plasma damage is minimized. Electrons run through the circuit

from substrate side to target side, because substrate side is subjected to be conductive

and target side is subjected to be insulated. Then, target side is negatively biased and

Ar ions hit the target.


- 30 -

shutter

W

substrate

PlasmaAr+Ar+

W

WWW

Figure 2.3 Schematic illustration of RF magnetron sputtering.

2.2.4 Dry etching by RIE

Reactive ion etching (RIE) is one of the patterning methods. Etching gas becomes

the plasma in a similar way in the case of RF sputtering. However, RIE is not only

physical but also chemical reaction. For etching of tungsten, SF6 chemistry is used as

etching gas in this study. The tungsten which is uncovered with resist reacts with F-

and becomes WF6 which is gas at room temperature. When the resist is eliminated,

O2 is used as etching gas and this process is called ashing.


- 31 -

2.2.5 PMA in F.G. ambient

Post metallization annealing (PMA) is effective to recover the defects in the

dielectric film, which is made during fabrication process such as sputtering. In

addition, PMA is done in forming gas (F.G.) (N2:H2=97:3), so that the effect of

terminating the dangling bonds with H+ at the interface of high-k/Si substrate is

obtained. Dangling bonds are become a causes of interfacial trap. Therefore, PMA is

a very important factor to achieve high quality MOS devices. In this study, different

annealing conditions such as annealing time and annealing temperature are

examined.

2.2.6 Wet etching with HCl and BHF

HCl and buffered HF (BHF) are used for wet etching process. When the RE-oxides

uncovered with resist are etched, HCl is used as etching liquid which is called

etchant. When the SiO2 is etched, BHF is used as etchant.

2.2.7 Vacuum evaporation for Al deposition

Al for wiring and backside contact is deposited by vacuum evaporation. Al source is

set on W boat and heated up to boiling point of Al by joule heating. However,

melting point of W is higher than boiling point of Al, W boat doesn’t melt. The base

pressure in the chamber is maintained to be 10-3 Pa (Fig. 2.4).


- 32 -

quartz thickness monitor

W boat

Al source

~10-3 Pa

Figure 2.4 Schematic illustration of vacuum evaporation.


- 33 -

A schematic illustration of MOSFET fabrication process is put together in Fig 2.5.

Particles

n+ n+

p-Si

SiO2 SiO2

n+ n+

p-Si

Chemical oxide

n+ n+

p-Si

n+ n+

p-Si

Gate dielectric (RE-oxide)

n+ n+

p-Si

W

n+ n+

p-Si

W

Resist

n+ n+

p-Si

W

n+ n+

p-Si

W

n+ n+

p-Si

W

Resist

n+ n+

p-Si

W

n+ n+

p-Si

W

Al

n+ n+

p-Si

W

n+ n+

p-Si

W

Al

SPM cleaning

HF treatment

Gate dielectric deposition by MBE

Gate electrode deposition by

sputtering

Photolithography

Dry etching with SF6

Wet etching with HCl and BHF

Photolithography

ashing

Eliminate resist (Lift off)

Al deposition by vacuum

evaporation

Al deposition by vacuum evaporation

Figure 2.5 Schematic illustration of MOSFET process.


- 34 -


2.3.1 Threshold voltage extraction

Threshold voltage (Vth) is an important MOSFET parameter. However, Vth is a

voltage that is not uniquely defined [2.1]. The existent of nonlinear curve at

subthreshold region on the Id-Vg plot make it difficult to have a universal definition.

One of the most common threshold voltage measurement techniques is the “linear

extrapolation method” with the drain current measured as a function of gate voltage

at a low drain voltage of 50-100 mV to ensure operation in the linear MOSFET

region [2.1]. The drain current is not zero below threshold and approaches zero only

asymptotically. Hence the Id versus Vg curve is extrapolated to Id=0, and the

threshold voltage is determined from the extrapolation or intercept gate voltage Vg by

2d

Gsth

VVV (2.1)

where VGs is the intercepted Vg value at Id=0 and Vd is the drain voltage used during

the measurement (50 mV in this study).

The Id-Vg curve deviates from the straight line at low gate voltage below threshold

voltage due to subthreshold currents and above threshold voltage due to series

resistance and mobility degradation effects. Thus, in order to determine the threshold

voltage accurately, it is a common practice to find the point of maximum slope on the

Id-Vg curve by maximum in the transconductance (gm), fit a straight line to the Id-Vg

curve at the point and extrapolate to Id=0, as illustrated in figure 2.6 [2.1].


- 35 -

Figure 2.6 Threshold voltage determination by the linear extrapolation technique.

2.3.2 Subthreshold slope measurement

Depending on the gate and source-drain voltages, a MOSFET device can be biased

in one of the three following regions; subthreshold, linear or saturation. In the

subthreshold region where Vg < Vth, the drain on the linear scale appears to approach

zero immediately below the threshold voltage. However, on a logarithmic scale, the

descending drain current remains at nonnegligible levels for several tenths of a volt

below threshold voltage [2.2]. This is because the inversion charge density does not

drop to zero abruptly. Rather, it follows an exponential dependence on gate voltage.

Subthreshold behavior is of particular important in modern ULSI application because

it describes haw a MOSFET device switches off (or turns on).


- 36 -

The subthreshold current is independent of the drain voltage once drain voltage is

larger than a few kT/q, as would be expected for diffusion-dominated current

transport. The dependence on gate voltage, on the other hand, is exponential with an

inverse subthreshold slope [2.2].

ox

dm

g

ds

C

C

q

kT

dV

IdSS 13.2

)(log..

1

10 (2.2)

Subthreshold slope, which is that gate voltage necessary to change the drain current

by one decade, is typically 70-100 mV/decade in modern MOSFET device [2.2].

Figure 2.7 illustrates the determination technique of subthreshold slope from log Id

versus linear Vg plot.

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

-0.5 0.0 0.5 1.0 1.5

10-9

10-8

10-7

10-6

10-5

10-4

I ds

(A)

Vg (V)

S.S.

Figure 2.7 Determination technique of subthreshold slope.

If the oxide/Si interface trap density is high, the subthreshold slope will be more

graded since the capacitance associated with the interface is in parallel with the


- 37 -

depletion capacitance Cdm. Hence eq. (2.2) can be rewritten as

ox

itdm

ox

dm

C

CC

q

kT

C

C

q

kTSS 13.213.2.. (2.3)

where Cit is the interface trap capacitance. The direct relationship between S.S. and

Cit, as shown in eq. (2.3) can be used as an index of quality of interfacial property.

2.3.3 Mobility measurement method based on split C-V

The MOSFET drain current is due to drift and diffusion of the mobile carriers in the

inverted Si channel. Let consider an n-channel device of gate length L and gate width

W for the derivation. The derivation for p-channel device is similar to n-channel

device with minor changes. The drain current Id can be written as

dx

dQ

q

kTW

L

VQWI inv

effdsinveff

d

(2.4)

Where Qinv is the carrier channel charge density and eff is the effective mobility. The

effective mobility is measured at low drain voltage under 100 mV. At low Vds, one

can assume that channel charge to be fairly distribute and uniform from the source to

drain, allowing the diffusive second term in eq. (2.4) to be dropped. Solving eq. (2.4)

then gives,

inv

deff WQ

Lg (2.5)

where the drain conductance gd is defined as

tconsVds

dd

fV

Ig

tan

(2.6)

To accurately determine the Qinv, direct measurement of Qinv from 100 kHz high


- 38 -

frequency capacitance measurement, with mobile channel density or inverted charge

density determined from the gate-to-channel capacitance/unit area (Cgc) according to

the following equation

g

V

V gcinv dVCQg

fb (2.7)

where Vfb and Vg are the flatband voltage and gate voltage, respectively. The Cgc is

measured by using the connection of figure 2.8 (a). The capacitance meter is

connected between the gate and the source-drain connected together with substrate

grounded. Setup in figure 2.8 (b) is used to measure the gate-to-substrate

capacitance/unit area (Cgb). The connected source-drain is grounded during Cgb

measurement. Cgb is used to calculated bulk charge density (Qb) according to the

following equation

g

V

V gbb dVCQg

fb (2.8)

Both Qinv and Qb are then used to calculate the effective vertical electric field (Eeff)

according to

Si

invbeff

QQE

(2.9)

where is the inversion layer charge accounts for averaging of the electric field over

the electron distribution in the inversion layer. The parameter =1/2 for the electron

mobility and =1/3 for the hole mobility. The Siis the Si permittivity [2.3-2.5]. In

this study, Cgc is measured at 100 kHz. The eff and gd are extracted from the area of

Cgc-Vg characteristic and the slope of the Ids-Vds characteristic, respectively as shown

in figure 2.9 (a) and (b).


- 39 -

Figure 2.8 Configuration for (a) gate-to-channel, (b) gate-to-substrate capacitance

measurement for split C-V measurement. [2.4]

Vg

Qinv

Figure 2.9 (a) Qinv is obtained from Cgc-Vg characteristic. (b) gd is obtained from

Ids-Vds characteristic .


- 40 -

References

[2.1] D. K. Schroder, “Semiconductor material and device characterization”, John

Willey & Sons, 3rd Edition, 2006, pp. 222-230.

[2.2] Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge

Press, 1998, pp. 125-129.

[2.3] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility

in thin dielectric MOS transistors”, Solid-State electron., 25 (1982) p. 833.

[2.4] D. K. Schroder, “Semiconductor material and device characterization”, John

willey & Son, 3rd Edition, 2006, pp. 489-500.

[2.5] S. Takagi, M. Iwase, and A. Toriumi, “On universality of inversion-layer

mobility in n- and p-channel MOSFETs”, IEDM Tech. Dig., 1988, p. 398.

Chapter 3. Selection of High-k Dielectrics with Annealing Process

- 41 -

Chapter 3 Selection of High-k Dielectrics with

Annealing Process

3.1 Introduction

3.2 Effect of annealing temperature and time


3.3.1 Direct contact with Si substrate

3.3.2 Comparison of La2O3 and La2O3/CeOx structure


stacked gate dielectric


0.50 nm under different annealing conditions

3.5 Conclusion

References


- 42 -

3.1 Introduction

Electrical characteristics of MOS devices are strongly affected by annealing

conditions such as annealing time and temperature. Figure 3.1 shows charge

pumping current as a function of pulse frequency [3.1]. Small charge pumping

current corresponds to the small interfacial trap density (Dit). The smaller Dit is

observed as an annealing temperature becomes high.

Figure 3.1 Annealing temperature dependence of charge-pumping current for La2O3

gated nMOSFET. Smaller Dit is obtained with higher temperature annealing. [3.1]

The annealing temperature dependence of the effective electron mobility is shown in

figure 3.2 [3.1]. All the nMOSFETs compared in figure 3.2 are same EOT of 1.3 nm.

Higher effective electron mobility is obtained with higher temperature annealing. In

particular, effective electron mobility is largely improved at low effective electric


- 43 -

field (Eeff) region. It can be considered that the improvement of mobility is occurred

by suppression of Coulomb scattering induced by interfacial trapped charges and

fixed oxide charges [3.2].

Figure 3.2 Annealing temperature dependence of effective electron mobility for

La2O3 gated nMOSFET. Mobility improvement is confirmed with high temperature

annealing. [3.1]

We can see from the above that high temperature annealing is necessary to fabricate

MOS devices with good electrical characteristics. However, as is shown in figure 1.6,

high temperature annealing leads to excess silicate formation, which increases the

EOT. In this chapter, therefore, the effect of short time annealing at high temperature

is examined. Moreover, a gate stack structure using CeOx which can form silicate

layer with high permittivity is investigated.


- 44 -

3.2 Effect of annealing temperature and time

Annealing temperature dependence on EOT for W(60 nm)/La2O3(3 nm)/n-Si

capacitors with annealing duration of 30 min or 2 s is shown in figure 3.3. From this

result, it is confirmed that the increase in EOT after annealing can be effectively

suppressed by shortening the annealing time.

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

400 500 600 700 800 900 1000

W/La2O3(3 nm)/n-Si

EO

T(n

m)

Annealing temperature(oC)

PMA 2 s

PMA 30 min

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

400 500 600 700 800 900 1000

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

400 500 600 700 800 900 1000

W/La2O3(3 nm)/n-Si

EO

T(n

m)


PMA 2 s

PMA 30 min

Figure 3.3 Annealing temperature dependence of EOT with La2O3 gated capacitors

with different annealing time. Increase in EOT is suppressed by shortening the

annealing time.

To examine the effect of annealing conditions, leakage current analysis of two

capacitors for the same EOT of 1 nm, namely one annealed at 850 oC for 2 s and

another at 600 oC for 30 min, are compared. Figure 3.4 shows Leakage current

density-electric field (Jleak-E) plot of two samples which are same EOT of 1 nm.


- 45 -

From Schottky plot, thermionic emission is dominant at the region where electric

field is lower than 4 MV/cm. On the other hand, at the region where electric field is

higher than 4 MV/cm, Poole-Frenkel (PF) emission is confirmed from PF plot [3.3].

Comparing the Jleak at the electric field where thermionic emission is dominant,

smaller leakage current is obtained with capacitor annealed at 850 oC for 2 s. It can

be considered that the conduction band offset at the interface facing to Si substrate is

higher with annealing at high temperature due to formation of Si-rich silicate at Si

substrate interface (Figure 3.5). In addition to leakage current, the effect of annealing

temperature and time on the amount of fixed charges and interfacial property are

discussed with other gate dielectric material in chapter 3..

10-1

100

10-2

101

102

103

104

0 1 2 3 4 5 6 7

Electric field (MV/cm)

10-3

J le

ak(A

/cm

2)

600 oC30 min

850 oC2 s

Thermionic emission

Poole-Frenkelemission

-3

-2

-1

0

1

2

3

4

0 500 1000 1500 2000 2500 3000

E1/2

log

(J)

Linear

Schottky plot

cmV( )

-8

-7

-6

-5

-4

-3

-2

0 500 1000 1500 2000 2500 3000

E1/2

log

(J/E

)

Linear

Poole-Frenkel plot

cmV( )

(a)

(b)

(c)600 oC30 min

850 oC2 s

600 oC30 min

850 oC2 s

log

(J)

(lo

g(A

/cm

2 ))

log

(J/E

)(l

og

(A/V

cm))

Figure 3.4 Jleak-E plots of two samples which are same EOT of 1 nm. Smaller

thermionic emission is confirmed for a capacitor annealed at 850 oC for 2 s.


- 46 -

φLa-rich

Metal

DielectricSi-substrate

Thermionic emission

φSi-rich

Metal

DielectricSi-substrate

Thermionic emission

Capacitor with low temperature annealing

Capacitor with high temperature annealing

φLa-rich φSi-rich＜

Ec Ec

Ef Ef

Si-richLa-rich

Figure 3.5 Band diagram of La2O3 gated capacitors with different annealing

conditions. Si-rich silicate whose barrier height is higher than that of La-rich silicate

might be formed with high temperature annealing.


- 47 -


3.3.1 Direct contact with Si substrate

As is shown in table 1.2, Ce-silicate has high dielectric constant and wide bandgap.

Therefore, a capacitor using CeOx as a gate dielectric is fabricated. Figure 3.6 shows

cross sectional TEM image of CeOx on Si after annealing at 500 oC for 30 min. A

formation of an SiO2 interfacial layer is confirmed. To achieve an EOT of ~0.5 nm, a

formation of gate stack structure with no SiO2 interfacial layer is required. Then,

La2O3 which can easily form silicate layer with Si is deposited on the CeOx, and a

La2O3/CeOx gated capacitor is fabricated.

2nm2nm metal

CeOx

SiO2

Ce-silicate(~0.5nm)(~0.6nm)

500oC 30minEOT=1.2nm

Figure 3.6 Cross sectional TEM image of CeOx on Si after annealing. A formation of

SiO2 interfacial layer is confirmed.


- 48 -

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-1.5 -1.0 -0.5 0.0 0.5 1.0

Voltage(V)

Cap

acit

ance

(μF

/cm

2)

As depoEOT=0.90 nm

PMA 800 oC, 2 sEOT=0.73 nm

100 kHz

La2O3/CeOx

Figure 3.7 C-V characteristics of as-deposited La2O3/CeOx dielectric capacitor and

that annealed at 800 oC for 2 s. Smaller EOT is obtained for annealed capacitor.

An EOT of as-deposited La2O3/CeOx dielectric capacitor, extracted from

capacitance-voltage (C-V) characteristics, is 0.90 nm, whereas that of the capacitor

annealed at 800 oC for 2 s is 0.73 nm (Figure 3.7). This result indicates that SiO2-IL

changes to silicate layer, whose dielectric constant is higher than that of SiO2, by

annealing. Figure 3.8 shows cross sectional TEM image of La2O3/CeOx on Si after

annealing. A direct contact of high-k/Si structure without SiO2-IL is confirmed. A

uniform contrast indicates a compositional uniformity of amorphous LaCe-silicate.

Figure 3.9 shows the observed photoelectron intensity ratio I(Ce)/I(La) as a function


- 49 -

metal

LaCe-silicate

2nm2nm

Direct high-k/Siinterface

800oC 2secEOT=0.58nm

kav=17.4EOT=0.64nm

Figure 3.8 Cross sectional TEM image of La2O3/CeOx dielectric capacitor after

annealing at 800 oC for 2 s. A direct high-k/Si structure is confirmed. A uniform

contrast indicates a compositional uniformity.

I(C

e)/I(

La)

90

Take off angle (deg.)300 60

0.0

0.1

0.2I(Ce):Ce3d5/2

I(La):La3d5/2

300oC

600oC

diffusion of Ce atoms to

surface

La atom downwarddiffusion

Figure 3.9 Intensity ratio of Ce 3d5/2 to La3d5/2 by angle-resolved XPS analysis

confirms the silicate layer and intermixing of Ce and La atoms, especially when

annealed at high temperature. [3.4]


- 50 -

of photoelectron take-off angle. Here, I(Ce) and I(La) are the intensity of Ce 3d5/2

and La 3d5/2 spectra arising from W/La2O3/CeOx/Si structure [3.4]. This result

indicates that the diffusion of Ce and La atoms occurs at La2O3/CeOx interface,

especially when annealed at high temperature. Thus, it is considered that direct

contact of LaCe-silicate/Si is achieved by La atoms, which can easily form silicate

layer, diffusion to Si substrate interface.


- 51 -

3.3.2 Comparison of La2O3 and La2O3/CeOx structure

Figure 3.10 shows the Annealing temperature dependence of EOT for W(60

nm)/La2O3(3 nm)/n-Si and W(60 nm)/La2O3(2 nm)/CeOx(1 nm)/n-Si capacitors with

different annealing time. A suppression of EOT increase after annealing at both 800

oC for 2 s and 500 oC for 30 min are confirmed with CeOx insertion at Si substrate

interface. As discussed in chapter 3.3.1, this result is due to formation of silicate

layer with high dielectric constant.

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

400 500 600 700 800 900 1000

W/La2O3(3 nm)/n-Si

EO

T(n

m)


PMA 2 s

PMA 30 min

W/La2O3(2 nm)/CeOx(1 nm)/n-Si

Figure 3.10 Annealing temperature dependence of EOT for W(60 nm)/La2O3(3

nm)/n-Si and W(60 nm)/La2O3(2 nm)/CeOx(1 nm)/n-Si capacitors with different

annealing time. Increase in EOT is suppressed by CeOx insertion.


- 52 -

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-1.5 -1.0 -0.5 0.0 0.5 1.0

Cap

acit

anc

e(μ

F/c

m2)

Voltage(V)

La2O3(2 nm)/CeOx(1 nm)EOT=0.66 nm

La2O3(3 nm)EOT=0.90 nm

PMA 500 oC, 30 min

Figure 3.11 C-V characteristics of W(60 nm)/La2O3(3 nm)/n-Si and W(60

nm)/La2O3(2 nm)/CeOx(1 nm)/n-Si capacitors annealed at 500 oC for 30 min. Lower

Dit and Smaller EOT are obtained with Si insertion.

C-V characteristics of W(60 nm)/La2O3(3 nm)/n-Si and W(60 nm)/La2O3(2

nm)/CeOx(1 nm)/n-Si capacitors annealed at 500 oC for 30 min are shown in figure

3.11. It is observed that the hump shapes of C-V curve, which is due to interfacial

traps, is smaller with CeOx inserted capacitor, as well as an EOT. Figure 3.12 shows

X-ray photoelectron spectroscopy (XPS) of each RE-silicate after annealing at 500

oC for 30 min. The Si 1s spectra arising from the La, Ce, and Pr-silicate gated

samples reveal compositional differences in the layer. Relatively SiO2-rich silicate is

formed with Ce-silicate, resulting in fairy nice interfacial property of CeOx inserted

capacitor. (Fig. 3.12) [3.5].


- 53 -

W W

La2O3La2O3

Ce-silicate

n-Si substraten-Si substrate

La-silicate

La-rich silicate SiO2-rich silicate

Fairy nice interfacial property

Interfacial trap

1845 1843 1841 1839

Binding energy (eV)

Inte

nsity

(a.u

.)

La-silicate

Ce-silicate

Pr-silicateSi sub.

SiO 2-rich

PrO 1.5-rich

LaO 1.5-rich

h =7940eV, Si 1s, TOA=80o

W(8nm)/RE-oxide/Re-silicate/sub.

1845 1843 1841 1839

Binding energy (eV)

Inte

nsity

(a.u

.)

La-silicate

Ce-silicate

Pr-silicateSi sub.

SiO 2-rich

PrO 1.5-rich

LaO 1.5-rich



1845 1843 1841 1839

Binding energy (eV)

Inte

nsity

(a.u

.)

La-silicate

Ce-silicate

Pr-silicateSi sub.

SiO 2-rich

PrO 1.5-rich

LaO 1.5-rich



1845 1843 1841 1839

Binding energy (eV)

Inte

nsity

(a.u

.)

La-silicate

Ce-silicate

Pr-silicateSi sub.

SiO 2-rich

PrO 1.5-rich

LaO 1.5-rich



hν=7940eV, Si 1s, TOA=80o

W(8nm)/RE-oxide/RE-silicate/sub.

Inte

nsity

(a.

u.)

Figure 3.12 Synchrotron XPS measurement through gate metal reveals difference in

composition of RE-silicates. Relatively SiO2-rich silicate is formed with Ce-silicate,

resulting in fairy nice interfacial property of CeOx inserted capacitor.


- 54 -


stacked gate dielectric

Figure 3.13 shows the C-V characteristics of W(60 nm)/La2O3(1.5-2.5 nm)/CeOx(1

nm)/n-Si capacitors with different annealing conditions. Comparing the capacitors

annealed at 800 oC for 2 s with those annealed at 500 oC for 30 min, smaller EOT is

achieved for all samples. Moreover, lower Dit are confirmed for capacitors annealed

at 800 oC for 2 s. It can be considered that the profile of mutual diffusion of atoms

such as Ce, La and Si is changed by annealing time and temperature. As shown in

0.0

1.0

2.0

3.0

4.0La2O3(1.5nm)/CeOX(1nm)

800oC 2s

500oC 30min

-1.5 -1.0 -0.5 0.0 0.5Voltage (V)C

apac

itan

ce (μ

F/c

m2 )

0.0

1.0

2.0

3.0La2O3(2nm)/CeOX(1nm)

-1.5 -1.0 -0.5 0.0 0.5Voltage (V)C

apac

itan

ce (μ

F/c

m2) 4.0

0.0

1.0

2.0

3.0La2O3(2.5nm)/CeOX(1nm)

-1.5 -1.0 -0.5 0.0 0.5Voltage (V)C

apa

cita

nce

(μ

F/c

m2) 4.0

W(60nm)

La2O3(2nm)

CeOx(1nm)

n-Si substrate

W(60nm)

La2O3(1.5nm)

CeOx(1nm)

W(60nm)

La2O3(2.5nm)

CeOx(1nm)

(a) (a)(b) (c)

(b) (c)

Figure 3.13 C-V characteristics of W(60 nm)/La2O3(1.5-2.5 nm)/CeOx(1 nm)/n-Si

capacitors with different annealing conditions. From hump shapes of C-V curves,

lower Dit are confirmed with capacitors annealed at 800 oC for 2 s.


- 55 -

figure 3.5, Si-richer interface might be formed by higher temperature annealing,

resulting in lower interfacial trap density for capacitors annealed at 800 oC for 2 s.

Fig. 3.14 shows a flat-band voltage (Vfb)-EOT plot of W(60 nm)/La2O3(1.5-2.5

nm)/CeOx(1 nm)/n-Si capacitors with different annealing conditions. The fixed

charge density (Nfix) in gate insulator can be calculated from the slope of Vfb-EOT

plot by using eq. 3.1

msSiO

fixfb EOT

qNV

2

. (3.1)

Nfix=2.4×1013/cm2 with capacitors annealed at 500 oC for 30 min and Nfix=9.1×

1012/cm2 with those annealed at 800 oC for 2 s are calculated from figure 3.14 [3.6].

Then, small fixed charge density is achieved with annealing at 800 oC for 2 s. A

reduction of the fixed charges by high temperature annealing even for short time is

confirmed.

-0.6

-0.5

-0.4

-0.3

0.5 0.6 0.7 0.8

EOT (nm)

Vfb

(V)

800oC 2s

500oC 30min

Effective fixedcharge density

Figure 3.14 Vfb-EOT plot of W(60 nm)/La2O3(1.5-2.5 nm)/CeOx(1 nm)/n-Si

capacitors with different annealing conditions. A calculated fixed charge density

from the slopes of plots is smaller for capacitors annealed at 800 oC for 2 s.


- 56 -

Figure 3.15 shows the EOT dependence of leakage current density of W(60

nm)/La2O3(1.5-2.5 nm)/CeOx(1 nm)/n-Si capacitors annealed under different

conditions. The Jleak of capacitors annealed at 500 oC for 30 min and those annealed

at 800 oC for 2 s are meet the requirements of gate leakage current in a roadmap of

ITRS 2009 [3.7]. Comparing the Jleak of the capacitors annealed at 800 oC for 2 s

with those annealed at 500 oC for 30 min in each EOT, smaller leakage current is

obtained with short time annealing at high temperature. As described above, higher

temperature annealing forms Si-richer silicate layer with wide bandgap and a gate

dielectric with smaller fixed charges even by short time annealing. Thus, thermionic

emission current is considered to be small. Moreover, PF emission current which

0.5 0.6 0.7 0.8

800oC 2s

500oC 30min

Requirements in the ITRS roadmap.

104

103

102

101

100

EOT (nm)

Lea

kag

e cu

rren

td

ensi

ty (

A/c

m2 )

Vg=1.0V

Figure 3.15 Jleak-EOT relationt of W(60 nm)/La2O3(1.5-2.5 nm)/CeOx(1 nm)/n-Si

capacitors with different annealing conditions. All samples meet the requirements in

the ITRS roadmap and smaller leakage current is obtained by high temperature

annealing.


- 57 -

flows thorough traps in the dielectric is also considered to be small. As a result,

observed gate leakage current is suppressed by high temperature annealing for 2 s.

Because of the good results on CeOx inserted capacitors with high temperature

annealing for 2 s, the MOSFETs with La2O3/CeOx gate dielectric annealed at 800 oC

for 2 s are fabricated and be compared with that annealed at 500 oC for 30 min in the

following chapter.


- 58 -


0.50 nm under different annealing conditions

Fig. 3.16 shows gate to channel capacitance (Cgc)-gate voltage (Vg) characteristic of

the nMOSFET with W (60 nm)/La2O3 (1.5 nm)/CeOx (1 nm) gate stack annealed at

800 oC for 2 s. A hysteresis is observed for Cgc-Vg curve. A measurement error due to

excess gate leakage current increases rapidly at the region of Vg > 0.5 V. It is

confirmed that the EOT of W (60 nm)/La2O3 (1.5 nm)/CeOx (1 nm) gate stacked

MOSFET annealed at 800oC for 2s is 0.50 nm from Cgc-Vg curve.

0.0

1.0

2.0

3.0

-0.5 0.0 0.5 1.0

Cg

c(μ

F/c

m2)

Vg (V)

Measurement error due to excess gate leakage current

Figure 3.16 Cgc-Vg curve of W(60 nm)/La2O3(1.5 nm)/CeOx(1 nm) gate stacked

MOSFET with EOT of 0.50 nm. A measurement error due to gate leakage current

and hysteresis are observed.


- 59 -

Drain-to-source current (Ids)-Vg and Ids-drain voltage (Vd) characteristics of W(60

nm)/La2O3(1.5 nm)/CeOx(1 nm) gate stacked MOSFET annealed at 800oC for 2s are

shown in figure 3.17. Operation of EOT=0.50 nm MOSFET is achieved. A relatively

large subthreshold voltage swing (SS) values over 130 mV/dec. indicates the

presence of large Dit and should be improved by further process optimization

including the selection of metal gate materials. The effect of metal gate materials is

investigated in chapter 4.

Vd=50mV

Vd=1V

-0.4 0 0.4Vg(V)

I ds

(A)

10-3

10-4

10-5

10-6

10-7

10-8

10-9

W/L=10/2.5μmEOT=0.50nm

Vth=-0.08VSS=136mV/dec.

Vd=1V

Vd=50mV

(a)

1.00 0.5

Vd (V)

I ds

(mA

)

0.3

0.2

0.1

0.0

Vg= -0.4~0.6V(step 0.2V)

(b)

Figure 3.17 (a) Ids-Vg and (b) Ids-Vd characteristics of W(60 nm)/La2O3(1.5

nm)/CeOx(1 nm) gate stacked MOSFET with EOT of 0.50 nm. Operation of

EOT=0.50 nm MOSFET is achieved.


- 60 -

Fig. 3.18 shows effective electron mobility of W(60 nm)/La2O3(1.5 nm)/CeOx(1 nm)

gate stacked MOSFET annealed at 800oC for 2s. Annealing at 500oC for 30min is

shown as a reference. The eff of the MOSFET annealed at 800oC for 2s revealed a

peak value of 120 cm2/Vs and 100 cm2/Vs at an effective field of 1 MV/cm.

Relatively-high eff for 800 oC annealing compared with that for 500 oC annealing is

considered to be due to smaller fixed charges and interfacial traps as shown in figure

3.13 and 3.15.

0

50

100

150

200

0 0.2 0.4 0.6 0.8 1.0Effective field (MV/cm)

Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

EOT=0.50nm

EOT=0.51nm500oC, 30min

800oC, 2s

Nsub=3×1016 cm-3

Figure 3.18 Effective electron mobility of MOSFET annealed at 800 oC for 2 s and

that annealed at 500 oC for 30 min. Relatively higher effective mobility is observed

with high temperature annealing for 2 s.

Fig. 3.19 shows the eff obtained with annealing at 800oC for 2s at 1 MV/cm together

with reported MOSFETs with Hf-based oxides [3.8-3.10]. Our result with RE-oxides

marks slightly smaller value than others, however, further process optimization

including shorter time annealing with higher temperature may recover the eff.


- 61 -

50

100

150

200

0.4 0.5 0.6 0.7 0.8 0.9 1.0Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

EOT (nm)

[11]

[10] [9] [9] [9]

This study

@1MV/cm

[3.8][3.8][3.8][3.9]

[3.10]

Figure 3.19 Effective electron mobility on EOT trend at 1 MV/cm with reported

direct contact structure data.


- 62 -

3.5 Conclusion

In order to achieve a direct contact of high-k/Si substrate, La2O3/CeOx structure as

gate dielectric has been investigated. A formation of SiO2-IL is confirmed with CeOx

dielectric. However, It is revealed that SiO2-IL changes to LaCe-silicate layer, whose

dielectric constant is higher than that of SiO2, by depositing La2O3 on CeOx.

Suppression of an increase of EOT and fairy nice interfacial property are confirmed

with CeOx insertion.

Second, capacitors annealed at 800 oC for 2 s and those annealed at 500 oC for 30

min are compared. It is confirmed that annealing at 800 oC for 2 s is suitable to

obtain better electrical property of MOSFETs in terms of EOT, interfacial trap

density, fixed charge, and gate leakage current.

And finally, an operation of the MOSFET with an EOT of 0.50 nm has been

successfully demonstrated even if RE-oxide is used as gate dielectric. The relatively

large S. S. and slightly degraded μeff compared should be improved by further

process optimization including the selection of metal gate materials and annealing

method.


- 63 -

References

[3.1] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.

Sugii, K. Natori, T. Hattori, and H. Iwai, “EOT of 0.62 nm and High Electron

Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing

Metal-Inserted Poly-Si Stacks and Annealing at High Temperature”, IEEE Trans. on

Electron Devices, 59 (2012) p. 269.


Cambridge University Press, (1998) p.82.

[3.3] S. M. Sze, and K. K. Ng, “Physics of Semiconductor Devices”, John Wiley &

Sons Inc., 2007, p. 227

[3.4] H. Nohira, Y. Kon, K. Kitamura, M. Kouda, K. Kakushima, and H. Iwai,

“Annealing-temperature Dependence of Compositional Depth Profiles and Chemical

Bonding States of CeOx/LaOx/Si and LaOx/CeOx/Si Structure”, ECS Trans., 25 (6),

2009, p. 321

[3.5] K. Kakushima, K. Okamoto, T. Koyanagi, M. Kouda, K. Tachi, T. Kawanago, J.

Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, and H. Iwai, “Selection of rare earth

silicates for highly scaled gate dielectrics”, Microelectron. Eng., 87 (2010) p. 1868.


- 64 -

[3.6] S. C. Song, C. S. Park, J. Price, C. Burham, R. Choi, H. C. Wen, K. Choi, H. H.

Tseng, B. H. Lee, and R. Jammy, “Mechanism of Vfb roll-off with High Work

function Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS

Band Edge Work function”, IEDM Tech. Dig., 2007, p. 337

[3.7] International Technology Roadmap for Semiconductors (ITRS) 2009 roadmap.

[3.8] J. Huang, D. Heh, P. Sivasubramani, P. D. Kirch, G. Bersuker, D. C. Gilmer, M.

A. Quevedo-Lopez, M. M. Hussain, P. Lysaght, H. Park, N. Goel, C. Young, C. S.

Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. Tseng, and R. Jammy, “Gate First

High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for

16nm Application”, VLSI Tech. Dig., 2009, p. 34

[3.9] K.Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M.

Wang, E. Cartier, S. Zafar, J. Bruler, A. Kerber, B. Linder, A. Callegari, Q. Yang, S.

Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan, “Extremely Scaled

Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial

Layer Scavenging Techniques for 22nm Technology Node and Beyond”, VLSI Tech.

Dig., 2009, p. 138

[3.10] M. Takahashi, A. Ogawa, A. Hirano, Y. Kamimuta, Y. Watanabe, K. Iwamoto,

S. Migita, N. Yasuda, H. Ota, T. Nabatame, and A. Toriumi, “Gate-First Processed

FUSI/HfO2/HfSiOx/Si MOSFETs with EOT=0.5 nm –Interfacial Layer Formation by

Cycle-by-Cycle Deposition and Annealing-“, IEDM Tech. Dig., 2007, p. 523.

Chapter 4. Selection of Metal Electrode for Controlling Silicate Reaction

- 65 -

Chapter 4

Selection of Metal Electrode for

Controlling Silicate Reaction

4.1 Introduction

4.2 Control of silicate reaction by TiN/W gate electrode

4.3 Effect of W electrode thickness on electrical characteristics

4.4 MOSFET characteristics with thin W film

4.5 Conclusion

References


- 66 -

4.1 Introduction

As described in chapter 1, one of the issues of La2O3 dielectrics is the excess growth

of the silicate layer after annealing, which increases EOT. In chapter 3, annealing

time and gate dielectric material is investigated for highly scaled MOSFETs. Next,

the effect of gate metal on electrical characteristics including EOT is examined.

Silicate layer formation is promoted by the presence of oxygen atoms as shown in

following chemical reaction of

La2O3+Si+nO2→La2SiO5, La10(SiO4)6O3

La9.33Si6O26, La2Si2O7 (4.1)

Thus, an excess supply of oxygen atoms results in the excess silicate layer formation.

On the other hand, an insufficient oxygen atom supply leads to the formation of

oxygen vacancies, which results in mobility degradation [4.1]. Hence, controlling the

amount of oxygen atoms is important for achieving MOSFETs with an EOT of 0.5

nm without degrading electrical characteristics. It is known that W, Mo, and column

VA metals such as Ta contain oxygen atoms depending on the free energy of oxygen

[4.2-4.4]. Secondary ion-microprobe mass spectrometry (SIMS) analysis revealed

oxygen concentration of ~1022 atoms/cm3 for W electrode used in this study (Figure

4.1). In this chapter, as a method to control the amount of oxygen atoms supplied, the

influence of the thickness of an oxygen-containing gate metal on the electrical

characteristics is investigated. A schematic concept of the oxygen supply control

method is illustrated in figure 4.2.


- 67 -

Figure 4.1 Oxygen profile of the W electrode layer obtained by SIMS analysis.

Oxygen concentration of ~1022 atoms/cm3 is revealed.

La-silicate

Metal

La2O3

n-Si

OO

O

OO

O

OO

O

La-silicate

Metal

La2O3

n-Si

O

O

OO

Amount of oxygendiffused to dielectric

Large Small

Figure 4.2 Schematic illustration of oxygen supply control method. Silicate reaction

is controlled by the thickness of oxygen-containing metal.

1.E+21

1.E+22

1.E+23

0 50 100 150 200 250

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

Depth (nm)

Sec

on

dar

y io

nin

ten

sit

y (a

rb.

un

it)

O c

on

cen

tra

tio

n (

ato

ms

/cm

3)

1021

1022

1023

Oxygen

Si

W

SiW


- 68 -

Figure 4.3 shows fabrication process of MOS devices used in this chapter. The

oxygen-containing metal s of various thickness such as W, Mo and Ta layers were

in-situ deposited by RF sputtering. A 40-nm-thick TiN layer was also deposited on

some samples. Wafers were subjected to postmetallization annealing (PMA) in FG

ambient under different annealing temperatures for 2 s.


La2O3 e-beam evaporation @ 300oC under ~10-6 Pa

Metal dry etching



Post metallization annealing (PMA)


Al wiring for S/D

n-Si Substrate


W, Mo or Ta deposition by RF-sputtering

in-situ

TiN deposition by RF-sputtering

Figure 4.3 Process flow of MOS capacitors and transistors fabricated in this

chapter.


- 69 -

4.2 Control of silicate reaction by TiN/W gate electrode

Figures 4.4 (a)-(c) show the C-V characteristics of Mo, Ta, and W/La2O3(3.5

nm)/n-Si gate stack capacitors annealed at 800 oC for 2 s. From these C-V

characteristics, it is confirmed that a smaller EOT is obtained using thinner gate

metal capacitors. These results indicate that changing the thickness of an

oxygen-containing metal is effective for controlling the amount of oxygen supplied

to gate dielectrics. Moreover, the smaller hump shapes of C-V curves are observed

for thinner oxygen-containing metal. About a relation of thickness of

oxygen-containing meal and hump shapes of C-V curves are discussed later. Having

confirmed the oxygen concentration of the W electrode by SIMS (~1022 atoms/cm3),

W thickness was used as the parameter to control amount of oxygen supplied.

The C-V characteristics of TiN(40 nm)/W(6 nm)/La2O3(3.5 nm)/n-Si gate stack

capacitors annealed at 800 oC for 2 s are shown in Fig. 4. Filled circles represent the

C-V curve of the capacitor annealed before TiN deposition and open circles represent

those annealed after TiN deposition. The reduction of EOT from 0.86 to 0.53 nm is

observed with TiN capping. It is reported that oxygen diffusion from the gate

dielectric to the TiN electrode is induced by annealing and suppressing EOT increase

[4.5]. Then oxygen in the W layer diffuse to TiN electrode, resulting in reduction of

amount of oxygen atoms supplied to gate dielectric, which could be the reason for

the EOT behavior observed in Fig. 4.4.


- 70 -

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-2.0 -1.5 -1.0 -0.5 0.0 0.5

Cap

acit

ance

(F

/cm

2 )

Voltage (V)

Mo(60 nm)EOT=0.84 nm

Mo(20 nm)EOT=0.77 nm

100 kHz

Mo/La2O3(3.5 nm)/n-Si800 oC/2 s

(a)

0.0

0.5

1.0

1.5

2.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5

Ta(60 nm)EOT=1.57 nm

Ta(20 nm)EOT=1.48 nm

Cap

aci

tan

ce (F

/cm

2)

Voltage (V)

100 kHz

Ta/La2O3(3.5 nm)/n-Si800 oC/2 s

(b)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-2.0 -1.5 -1.0 -0.5 0.0 0.5

W(60 nm)EOT=1.18 nm

W(6 nm)EOT=0.87 nm

Voltage (V)

100 kHz

W/La2O3(3.5 nm)/n-Si800 oC/2 s

(c)Cap

aci

tan

ce (F

/cm

2)

Figure 4.4 C-V characteristics of La2O3(3.5 nm)/n-Si gate stack capacitors using (a)

Mo, (b) Ta, and (c) W electrodes annealed at 800 oC for 2 s. EOTs positively

correlate with the thickness of the metal.


- 71 -

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

-1.5 -1.0 -0.5 0.0 0.5 1.0Voltage (V)

Annealed before TiN depositionEOT=0.86 nm

Annealed after TiN deposition EOT=0.53 nm

100 kHz

TiN/W(6 nm)/La2O3(3.5 nm)/n-Si

800 oC/2 s

Cap

acit

ance

(F

/cm

2 )

Figure 4.5 C-V characteristics of TiN(40 nm)/W(6 nm)La2O3(3.5 nm)/n-Si capacitors

annealed at 800 oC for 2 s. Closed dots represent the capacitor annealed before TiN

deposition and open dots represent that annealed after TiN deposition.

Figure 4.6 shows EOT dependence on annealing temperature for TiN(40 nm)/W(6 or

12 nm)/La2O3(3.5 nm)/n-Si and W(60 nm)/La2O3(3.5 nm)/n-Si gate stack capacitors

annealed for 2 s. The increase in EOT after annealing is well suppressed as the W

layer becomes thin and the controllability such as range of EOT from 0.51 to 1.2 nm

at 800 oC annealing is confirmed. Moreover, almost no change in EOT from the

as-deposited condition occurs with thin W and TiN capping. To ensure the effect of

W film thickness on silicate reaction, the dependence of the amount of La-silicate

layer on W film thickness is measured by XPS for TiN(10 nm)/W(0-10 nm)/La2O3(3

nm)/n-Si structures. Figure 4.7 shows the Si 1s spectra of the samples with and


- 72 -

without post metallization annealing at 800 oC for 2 s measured at a photoelectron

take-off angle of 80o. Here, Si 1s spectral intensities arising from the Si substrate are

adjusted to be equal to each other in order to indicate the changes in the La2O3/Si

interface. The as-deposited sample of the TiN/W (0 nm) electrode shows nearly no

silicate reaction. On the other hand, the increase in the number of La-O-Si bonds

with the thickness of the W film indicates that silicate reaction could be controlled by

changing the thickness of the W film [4.6, 4.7].


- 73 -

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

600 700 800 900 1000As depo

～～Annealing temperature (oC)

EO

T (

nm

)

Annealed for 2 sLa2O3(3.5 nm)

W(60 nm)

TiN/W(12 nm)

TiN/W(6 nm)

Figure 4.6 EOT dependence on annealing temperature for TiN(40 nm)/W(6 or 12

nm)/La2O3(3.5 nm)/n-Si and W(60 nm)/La2O3(3.5 nm)/n-Si capacitors annealed for 2

s. An increase in EOT after annealing is effectively suppressed by thinning the W

thickness.

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

1839184018411842184318441845

Si 1s

Binding energy (eV)

Increase in La-silicate

TiN/W(x nm)/La2O3(3 nm)/n-SiPMA 800 oC 2 s

W(3 nm)

W(10 nm)

W(0 nm) as-depo

W(0 nm)

Inte

nsi

ty (

a.u

.)

Figure 4.7 Si 1s photoelectron spectra arising from TiN(10 nm)/W(0, 3 and 10

nm)/La2O3(3.5 nm)/n-Si structure annealed at 800 oC for 2 s.


- 74 -

4.3 Effect of W electrode thickness on electrical characteristics

C-V characteristics of TiN(40 nm)/W(6 or 12 nm)La2O3(3.5 nm)/n-Si capacitors

annealed at 800 oC for 2 s is shown in figure 4.8. A larger right-handed hysteresis

window is observed for thinner W electrode capacitor. The hysteresis of C-V curve

suggests the existence of traps in the gate dielectric. The windows of the hysteresis in

the C-V curves for TiN(40 nm)/W(6 or 12 nm)/La2O3(3.5 nm)/n-Si and W(60

nm)/La2O3(3.5 nm)/n-Si gate stack capacitors annealed for 2 s are summarized in

Figure 4.9. It is confirmed that thinner W layer capacitors represent a larger

right-handed hysteresis and need further higher-temperature annealing to reduce the

hysteresis.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-1.0 -0.5 0.0 0.5

Cap

acit

ance

(μF

/cm

2 )

Voltage(V)

800 oC, 2 s

100 kHz

TiN(40 nm)/W(12 nm)

TiN(40 nm)/W(6 nm)

Figure 4.8 C-V characteristics of TiN(40 nm)/W(6 or 12 nm)La2O3(3.5 nm)/n-Si

capacitors annealed at 800 oC for 2 s. A larger hysteresis window is observed with

capacitor of thinner W film.


- 75 -

0

10

20

30

40

50

60

700 800 900 1000


Wid

th o

f h

yste

res

is (

mV

)

W(60 nm)

TiN/W(12 nm)

TiN/W(6 nm)

Annealed for 2 sLa2O3(3.5 nm)Ramp rate=0.25 V/s

Figure 4.9 Hysteresis window dependence on annealing temperature for TiN(40

nm)/W(6 or 12 nm)La2O3(3.5 nm)/n-Si and W(60 nm)/La2O3(3.5 nm)/n-Si capacitors

annealed for 2 s. A ramp rate of measurement is 0.25 V/s. Hysteresis window

becomes large when the W film is thin.

As described in chapter 3.3.3, high temperature annealing reduces the traps in the

dielectric, which induce the generation of hysteresis. Moreover, this relationship

indicates that electron traps are formed near the La2O3/La-silicate interface and in

La2O3 [4.8, 4.9], where the distance from the Si substrate has a positive correlation

with the amount of oxygen supplied. This implies that C-V characteristics with a

small EOT as well as a small hysteresis can be obtained by optimization of annealing


- 76 -

temperature and W film thickness. A TEM image of a TiN(45 nm)/W(3

nm)/La2O3(2.5 nm)/n-Si gate stack capacitor annealed at 800 oC for 2 s reveals that

the direct contact of high-k material to the Si structure is obtained (Figure 4.10). An

extremely small EOT of 0.43 nm with an average dielectric constant (kav) of 22.7 is

obtained.

1 nm

La-silicate

W

TiN

PMA 800 oC, 2 s

EOT=0.43 nmTphy=2.5 nm

k =22 7

(3 nm)

La2O3 &La-silicate

Tphy=2.5 nm EOT=0.43 nmKav=22.7

Figure 4.10 Cross-sectional TEM image of TiN (40 nm)/W(3 nm)/La2O3(2.5 nm)/n-Si

capacitor annealed at 800 oC for 2 s. A direct contact structure of high-k/Si is

confirmed.


- 77 -

The Vfb-EOT plot measured for TiN(40 nm)/W(6 or 12 nm)/La2O3/n-Si and W(60

nm)/La2O3/n-Si gate stack capacitors annealed at 800 oC for 2 s is shown in Fig. 4.10.

The slopes in the Vfb-EOT relation show nearly the same trend for all W film

thicknesses. However, a negative parallel shift in Vfb, depending on the thickness of

the W film, is observed. Given the result shown in figure 4.7, it can be anticipated

that the formation of the La-silicate layer induces the formation of oxygen vacancies

or positive fixed charges. Actually, the formation of positive fixed charges in the

La-silicate layer due to the metal diffusing from the gate electrode is reported [4.10,

4.11].

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.3 0.5 0.7 0.9 1.1

Vfb

(V)

EOT (nm)

Annealed at 800 oC for 2 s

W(60 nm)

TiN/W(12 nm)

TiN/W(6 nm)

Vfb shiftaccompanied with silicate formation

Figure 4.11 Vfb-EOT plot of TiN(40 nm)/W(6 or 12 nm)/La2O3(3.5 nm)/n-Si and

W(60 nm)/La2O3(3.5 nm)/n-Si capacitors annealed at 800 oC for 2 s. A parallel Vfb

shift accompanied with the silicate formation is observed, indicating the formation of

positive fixed charges.


- 78 -

Figure 4.11 shows the C-V characteristics of TiN(40 nm)/W(6 or 12 nm)/La2O3(3.5

nm)/n-Si and W(60 nm)/La2O3(3.5 nm)/n-Si gate stack capacitors annealed at 800 oC

for 2 s. A correlation between the hump shapes at the weak inversion region, which

are caused by interfacial trap density [4.12], and the amount of the La-silicate layer is

revealed. There is a possibility that electron traps in the La-silicate layer contribute to

the hump shapes and cause the degradation of Dit.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-1.5 -1.0 -0.5 0.0 0.5

Cap

acit

ance

(F

/cm

2)

Voltage (V)

W(60 nm) TiN/W(12 nm) TiN/W(6 nm)

cvc simulation

800 oC/2 s100 kHz

Figure 4.12 C-V characteristics of TiN(40 nm)/W(6 or 12 nm)/La2O3(3.5 nm)/n-Si

and W(60 nm)/La2O3(3.5 nm)/n-Si capacitors annealed at 800 oC for 2 s (inset:

scale-up hump shapes at weak inversion region). Smaller hump is obtained for

thinner W film capacitor.


- 79 -

To explain the origin of hysteresis, Vfb shift and hump shapes observed in figure 4.9,

4.11, and 4.12, a model is proposed as is shown in figure 4.13. In the study of

Hf-based oxides, difference of oxygen vacancy energy level between HfO2 and

Hf-silicate is reported [4.13, 4.14]. In the band diagrams shown in figure 4.13,

assuming oxygen vacancy level in La2O3 is different from that of La-silicate as an

analogy from Hf-based oxide, oxygen vacancy levels at flat-band condition in La2O3

are located at a higher energy than Fermi-level (Ef) and those in La-silicate are

aligned lower than Ef. When a positive voltage is applied to the gate to accumulation,

electrons are trapped in the oxygen vacancy level in La2O3 or La2O3/La-silicate

interface. The trapped electrons generate negative charges which results in

right-handed hysteresis, where the hysteresis window degrades as oxygen supply

becomes deficient. When a negative voltage is applied to the gate to depletion,

electrons at oxygen vacancy levels near Ef in La-silicate respond to AC signal. As a

result, a capacitance connected in parallel to depletion capacitance increases and the

hump shapes at the weak inversion region is observed.


- 80 -

La-silicateLa2O3

Si-substrateMetal

Trap due to Vo2+

Ef

++ +++

Metal induced defects(origin of Vfb shift)

++ +++

Trap

Origin of hysteresis

Flat-band condition

Accumulation condition

Depletion condition

++ +++

Origin of humps

Electrons respondto AC signal

Figure 4.13 Conceivable band diagram model of flat-band, accumulation and

depletion conditions.


- 81 -

4.4 MOSFET characteristics with thin W film

Figures 4.14 show the Cgc-Vg characteristics of TiN(40 nm)/W(3 or 12 nm)/La2O3(3

nm)/n-MOSFETs. For a W(3 nm) FET, a small EOT of 0.50 nm is extracted from Cgc.

A Cgc of W(12 nm) FET reveals an EOT of 0.71 nm. In the case of the MOSFET

fabrication process, it is confirmed that oxygen supply control by changing the

thickness of the oxygen-containing metal is also effective. In addition, the threshold

voltage (Vth) relation with W film thickness coincides with the result of capacitors

shown in figure 4.11.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

-1.0 -0.5 0.0 0.5 1.0

Voltage (V)

Cg

c(

F/c

m2)

W(3 nm)EOT=0.50 nm

W(12 nm)EOT=0.71 nm

800 oC/2 s TiN/W/La2O3(3nm)

100 kHz(a)

Figure 4.14 Cgc-Vg characteristics of TiN(40 nm)/W(3 or 12 nm)/La2O3(3

nm)/nMOSFETs. EOT and Vth relations with W film thickness coincide with the

results of capacitors.


- 82 -

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

-0.6 -0.1 0.4 0.9 1.4

10-4

10-5

10-6

10-7

10-8

10-9

Vg (V)

I ds

(A)

86 mV/dec.

101 mV/dec.

Vds=50 mV

(b)

W(3 nm)L/W=10/10mEOT=0.50 nm

W(12 nm)L/W=20/20mEOT=0.71 nm

Figure 4.15 Ids-Vg characteristics of TiN(40 nm)/W(3 or 12 nm)/La2O3(3

nm)/nMOSFETs. The relationship of SS value corresponding to hump shapes of

capacitors is obtained.

0

20

40

60

80

100

120

0.0 0.5 1.0 1.5 2.0

Eff

ecti

ve M

ob

ilit

y (c

m2/V

s)

Effective field (MV/cm)

W(3 nm)L/W=10/10mEOT=0.50 nm

W(12 nm)L/W=20/20mEOT=0.71 nm

800 oC/2 s TiN/W/La2O3(3nm)

Figure 4.16 eff of TiN(40 nm)/W(3 or 12 nm)/La2O3(3 nm)/nMOSFETs..


- 83 -

Figure 4.15 shows Ids-Vg characteristics of TiN(40 nm)/W(3 or 12 nm)/La2O3(3

nm)/nMOSFETs. The relationship of subthreshold slope (SS) corresponding to hump

shapes of C-V curves (figure 4.12) is confirmed. An appropriate transistor operation

at an EOT of 0.5 nm is confirmed for W(3 nm) nMOSFET annealed at 800 oC for 2 s,

as shown in figure 4.16. However, degradation due to EOT scaling is observed for

the thinned W film. The lower eff of thinner W MOSFET where amount of oxygen

supplied is small indicates that defects caused by oxygen vacancies in La2O3 degrade

eff. Thus, reduction of oxygen vacancies is important to improve mobility, which is

discussed in chapter 5 and 6.


- 84 -

4.5 Conclusion

To achieve an EOT of 0.5 nm using La2O3 gate dielectric, a control method for

silicate reaction has been proposed. The amount of supplied oxygen atoms, which

trigger the formation of the silicate layer, is controlled by changing the thickness of

an oxygen-containing metal such as W. Almost no change in EOT from the

as-deposited condition was observed for the TiN/W(6 nm)/La2O3(3.5 nm)/n-Si

capacitor annealed for 2 s, and an EOT of 0.51 nm is achieved with 800 oC annealing.

The relationships between the amount of formed silicate and the hysteresis window

of the C-V curve, the humps at the weak inversion region, and Vfb shift have been

explained by the defect energy levels in the silicates and La2O3 and at the

La2O3/La-silicate interface. An appropriate transistor operation at an EOT of 0.5 nm

has been confirmed for TiN(40 nm)/W(3 nm)/La2O3(3 nm)/nMOSFETs annealed at

800 oC for 2 s.


- 85 -

References

[4.1] H. Kim, P. C. Mclntyre, C. O. Chui, K. C. Saraswat, and S. Stemmer,

“Engineering chemically abrupt high-k metal oxide/silicon interfaces using an

oxygen-gettering metal overlayer”, J. Appl. Phys. 96 (2004) p. 3467.

[4.2] E. J. Preisler, S. Guha, M. Copel, N. A. Bojarczuk, M. C. Reuter, and E. Gusev:,

“Interfacial oxide formation from intrinsic oxygen in W-HfO2 gated silicon

field-effect transistors”, Appl. Phys. Lett. 85 (2004) p. 6230.

[4.3] J. D. Fast, “Interactions of Metals and Gases”, Academic Press, New York,

1965, vol. 1, p. 70.

[4.4] J. D. Fast, “Interactions of Metals and Gases”, Academic Press, New York,

1965, vol. 1, p. 210.

[4.5] L. Wu, H. Y. Yu, X. Li, K. L. Pey, J. S. Pan, J. W. Chai, Y. S. Chiu, C. T. Lin, J.

H. Xu, H. J. Wann, X. F. Yu, D. Y. Lee, K. Y. Hsu, and H. J. Tao, “Thermal stability

of TiN metal gate prepared by atomic layer deposition or physical vapor deposition

on HfO2 high-k dielectric”, Appl. Phys. Lett. 96 (2010) p.113510.


- 86 -

[4.6] H. Nohira, T. Matsuda, K. Tachi, Y. Shino, J. Song, Y. Kuroki, J. A. Ng, P.

Ahmet, K. Kakushima, K. Tsutsui, E. Ikenaga, K. Kobayashi, H. Iwai, and T. Hattori,

“Effect of Deposition Temperature on Chemical Structure of Lanthanum Oxide/Si

Interface Structure”, ECS Trans., 3 (2006) p. 169.

[4.7] H. Nohira, “Study on Chemical Bonding States of High-k Gate Stacks for

Advanced CMOS”, ECS Trans., 28 (2010) p. 129.

[4.8] N. Umezawa, and K. Shiraishi, “Origin of high solubility of silicon in La2O3: A

first-principles study”, Appl. Phys. Lett. 97 (2010) p. 202906.

[4.9] H. Castan, S. Duenas, H. Garcia, A. Gomez, L. Bailon, M. Toledano-Luque, A.

Del Prado, I. Martil, and G. Gonzalez-Diaz, “Effect of interlayer trapping and

detrapping on the determination of interface state densities on high-k dielectric

stacks”, J. Appl. Phys. 107 (2010) p. 114104.

[4.10] K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii,

T. Hattori, and H. Iwai, “Characterization of flatband voltage roll-off and roll-up





- 87 -

[4.12] B. Raeissi, J. Piscator, O. Engstrom, S. Hall, O. Buiu, M. C. Lemme, H. D. B.

Gottlob, P. K. Hurley, K. Cherkaoui, and H. J. Osten, “High-k-oxide/silicon

interfaces characterized by capacitance frequency spectroscopy”, Solid-State

Electron., 52 (2008) p. 1274.

[4.13] K. Xiong, Y. Du, K. Tse, and J. Robertson, “Defect states in the

high-dielectric-constant gate oxide HfSiO4”, J. Appl. Phys., 101 (2007) p. 024101.

[4.14] G. Lucovsky, D. M. Fleetwood, S. Lee, H. Seo, R. D. Schrimpf, J. A. Felix, J.

Luning, L. B. Fleming, M. Ulrich, and D. E. Aspnes, “Differences Between Charge

Trapping States in Irradiated Nano-Crystalline HfO2 and Non-Crystalline Hf

Silicates”, IEEE Trans. Nucl. Sci., 53 (2006) p. 3644.

Chapter 5. Thin Si Insertion at Metal Gate/High-k Interface

- 88 -

Chapter 5

Thin Si Insertion at Metal Gate/High-k

Interface

5.1 Introduction

5.2 Electrical characteristics for MOS capacitors

5.3 Electrical characteristics for MOS transistors

5.4 Quantitative understanding for mobility improvement

5.5 Conclusion

References


- 89 -

5.1 Introduction

At a region of EOT>1.5 nm, A fairly nice interfacial property with a peak effective

mobility of over 300 cm2/Vs has been reported with La2O3 dielectrics. Also, La2O3

gated MOSFETs with EOT of ~0.5 nm were achieved by using W electrode as a

source of oxygen atoms supply as described in chapter 4. However, degradations in

the mobility have been observed when the thickness of La2O3 is thinned down.

Figure 5.1 shows the peak eff of La2O3 gated MOSFETs as a function of EOT. The

mobility degradation accompanied with EOT scaling can be confirmed, especially at

EOT below 1.3 nm.

EOT (nm)

eff

(cm

2 /V

s)

150

200

250

300

350

0.5 1.0 1.5 2.0

PMA 500oCpeak

La2O3 dielectric

T. Koyanagi, et. al., ECS 2009

Figure 5.1 Peak eff of La2O3 gated MOSFETs as a function of EOT. The mobility

degradation accompanied with the EOT scaling is observed.


- 90 -

The negative shifts in Vth as well as Vfb are also observed as the EOT below

approximately 1.3 nm as shown in figure 5.2. Thus, the cause of mobility

degradation is considered to be fixed charges (Qfix) in gate dielectric. However, the

origin of fixed charges generation in gate dielectric is still under discussion. For

example, formation of positive fixed charges in the dielectrics caused by diffused

metal from the gate electrode is proposed [5.1]. In addition, the defect segregation

and enhanced diffusion of oxygen vacancies induced by grain boundaries, which

result in generation of positive fixed charges, are also reported (Figure 5.3) [5.2, 5.3].

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0

0.2

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Vth

, V

fb(V

)

Electrical properties ofW/La2O3/Si n-MOSFET

EOT (nm)

Because ofFixed charges

PMA500oC

Figure 5.2 Vfb and Vth trend of W/La2O3 gated MOSFETs as a function of EOT,

showing negative shift below EOT of ~1.3 nm.


- 91 -

K. McKenna, et. al., Appl. Phys. Lett. 95 (2009) 222111

K. Kakushima, et. al., Solid-State Electron. 54 (2010) 720

Fixed charges induced by gate metal

Grain boundaries with oxygen vacancies

Gate metal

Dielectric

Si sub.

Gate metal

Dielectric

Si sub.

Vo VoVoVo

Possible models for Qfix generation

Figure 5.3 Reported models for fixed charge generation. The oxygen vacancies

segregated at grain boundaries and metal atoms diffusion from gate metal are taken

into account as an origin of fixed charges in this chapter.


- 92 -

Inte

nsity

[a.u

.]

14121086420Distance [nm]

Si

O

La

N

W

TiT

iN W

La

-sil

ica

te

Si

su

b.

Figure 5.4 Depth direction profile of W atoms for TiN/W/La2O3/Si structure annealed

at 800 oC measured by EELS. W atoms diffusion to La2O3 dielectric is confirmed.

Actually, the diffusion of W atoms from gate metal to gate dielectric is confirmed by

electron energy loss spectroscopy (EELS) measurement as shown in figure 5.4. In

any case, the fixed charges play an important role for the mobility degradation. In

this study, a thin amorphous La-silicate layer formed by Si insertion at the interface

of W and La2O3 has been conducted, anticipating formation of the amorphous

La-silicate layer at the metal-gate/La2O3 interface eliminate the grain boundaries.

Then, its effect on the electrical characteristics at scaled EOT has been observed.


- 93 -

Figure 5.5 shows the fabrication process of MOS devices discussed in this chapter. Si

was in situ deposited with a rate of ~0.2 nm/min on some samples by RF sputtering

to form a thin La-silicate layer at the top of La2O3 dielectrics. A 12-nm-thick W layer

was also deposited by RF sputtering. The wafers were not exposed to air until W

layer was formed.

Si deposition by RF-sputtering



Metal dry etching



Post metallization annealing (PMA)with F. G. for 2 s


Al wiring for S/D

n-Si Substrate


W deposition by RF-sputteringin-situ

TiN deposition by RF-sputtering

La-silicate

La-silicate

W

La2O3

Si

TiN

La-silicate

La2O3

Si

La-silicate

La-silicate

La2O3

Si

Si deposition

Metal deposition

Figure 5.5 Fabrication process of La2O3 gated MOS devices used in this chapter.


- 94 -

5.2 Electrical characteristics for MOS capacitors

Figure 5.6 shows C-V characteristics of TiN/W/Si(0 or 0.3 nm)/La2O3(3 nm) gate

stack capacitors annealed at 800 oC for 2 s. A small EOT of 0.62 nm was obtained

with the Si inserted capacitor while the EOT of that without Si insertion was 0.71 nm.

Moreover, a positive shift in Vfb was observed with Si insertion. The EOT

dependence on the annealing temperature is summarized in figure 5.7. An increase of

the EOT accompanied with annealing temperature is suppressed for Si inserted

capacitors annealed at from 700 to 900 oC for 2 s.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-1.5 -1.0 -0.5 0.0 0.5 1.0

Voltage (V)

Cap

acit

ance

(F

/cm

2)

TiN/W/Si(0 or 0.3 nm)/La2O3(3 nm)

w/ SiEOT=0.62 nm

w/o SiEOT=0.71 nm

800 oC, 2 s100 kHz

Figure 5.6 C-V characteristics of TiN/W/Si(0 or 0.3 nm)/La2O3(3 nm)/n-Si capacitors

annealed at 800 oC for 2 s. La2O3 of 3 nm dielectrics with and without Si insertion

are deposited at once. Smaller EOT is obtained for Si inserted capacitor.


- 95 -

0.5

0.6

0.7

0.8

0.9

600 700 800 900


EO

T (

nm

)

as depo


w/o Si

w/ Si

Annealed for 2 s

Figure 5.7 EOT dependence on annealing temperature for TiN/W/Si(0 or 0.3

nm)/La2O3(3 nm)/n-Si capacitors annealed for 2 s. La2O3 of 3 nm dielectrics with

and without Si insertion are deposited at once.

It can be considered that formation of amorphous La-silicate layer at the interface of

W/La2O3 inhibits the diffusion of oxygen atoms thorough grain boundaries and

formation of La-silicate layer at the La2O3/Si substrate interface is suppressed.

Vfb-EOT plot measured for TiN/W/Si(0.3 nm)/La2O3(2.5-3.1 nm) and

TiN/W/La2O3(2.7-3.3 nm) gate stack capacitors annealed at 800 oC for 2 s is shown

in figure 5.8. A positive Vfb shift by ~150 mV is obtained for Si inserted capacitors,

indicating the suppression of positive fixed charges generation. A formation of

positive fixed charges in the dielectrics caused by diffused metal from the gate


- 96 -

electrode and the defect segregation and enhanced diffusion of oxygen vacancies

induced by grain boundaries, which result in generation of positive fixed charges, are

reported [5.3-5.6]. The formation of the amorphous La-silicate layer at the

metal-gate/La2O3 interface might eliminate the grain boundaries. As a result, the

amount of diffused metal in dielectrics or oxygen vacancies segregated at the grain

boundaries are reduced, resulting in the suppression of positive fixed charge

generation.

EOT (nm)

Vfb

(V)

-0.6

-0.5

-0.4

-0.3

-0.2

0.55 0.65 0.75 0.85

w/o SiLa2O3 (2.7-3.3 nm)

w/ SiLa2O3 (2.5-3.1 nm)

TiN/W/Si(0 or 0.3 nm)/La2O3

800 oC, 2 s

Figure 5.8 Vfb-EOT plot of TiN/W/Si(0 or 0.3 nm)/La2O3/n-Si capacitors annealed at

800 oC for 2 s. A negative Vfb shift is suppressed by Si insertion.


- 97 -

5.3 Electrical characteristics for MOS transistors

Next, Si insertion effect on the electrical properties of FETs was performed. Figure

5.9 shows the gate-to-channel capacitance (Cgc) of TiN/W/Si(0 or 0.3 nm)/La2O3(3

nm) gate stack nFETs annealed at 800 oC for 2 s. Compared to EOT of 0.68 nm for

nFET without Si insertion, a smaller EOT of 0.58 nm is obtained for Si inserted

nFET, consistent with the capacitor experiment. A positive shift in the threshold

voltage is also observed for Si inserted nFET.

0.0

1.0

2.0

3.0

4.0

-1.0 -0.5 0.0 0.5

Voltage (V)

Cg

c(

F/c

m2 )


w/ SiEOT=0.58 nm

w/o SiEOT=0.68 nm

800 oC, 2 s100 kHz

Figure 5.9 Cgc–Vg characteristics of TiN/W/Si(0 or 0.3 nm)/La2O3(3 nm) gate stack

nMOSFETs annealed at 800 oC for 2 s. EOT relation with existence or non-existence

of Si insertion coincides with result of capacitors.


- 98 -

Figure 5.10 shows EOT dependence of Vth measured for TiN/W/Si(0.3

nm)/La2O3(2.5-3. nm) and TiN/W/La2O3(2.7-3.3 nm) gate stack nFETs annealed at

800 oC for 2 s. The positive Vth shift by ~150 mV is confirmed for Si inserted nFETs

as well as the positive Vfb shift of capacitor (fig. 5.8), implying the reduction of

positive fixed charges.

-0.4

-0.3

-0.2

-0.1

0.5 0.6 0.7 0.8

EOT (nm)

Vth

(V)

w/o SiLa2O3 (2.7-3.3 nm)

w/ SiLa2O3 (2.5-3.0 nm)

TiN/W/Si(0 or 0.3 nm)/La2O3800 oC, 2 s

Figure 5.10 Vth dependence on EOT of TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack

nMOSFETs annealed at 800 oC for 2 s. Vth relation with existence or non-existence of

Si insertion coincides with Vfb of capacitors.


- 99 -

0

20

40

60

80

100

120

140

0.0 0.5 1.0 1.5 2.0

w/ SiEOT=0.58 nm

w/o SiEOT=0.66 nm


800 oC, 2 s

eff

(cm

2 /V

s)


(a)

L/W=20/20m

Figure 5.11 eff of TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack nMOSFETs annealed at

800 oC for 2 s as a function of Eeff. Higher eff is achieved with Si inserted FET at all

Eeff region.

Effective mobility of TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack nMOSFETs annealed

at 800 oC for 2 s as a function of Eeff is shown in figure 5.11. It can be seen that even

EOT of Si inserted nMOSFET is smaller than that of nMOSFET without Si insertion,

higher eff is achieved with Si inserted FET at all Eeff region. Figure 5.12 shows eff

at peak value around Eeff of 0.3 MV/cm for TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack

nMOSFETs annealed at 800 oC for 2 s as a function of EOT. The same degradation

trend in the eff caused by EOT scaling is observed for nFETs with and without Si

insertion. However, when compared at the same EOT, a large improvement can be


- 100 -

100

110

120

130

140

0.5 0.55 0.6 0.65 0.7 0.75

EOT (nm)

Pea

k e

ff(c

m2 /

Vs) w/ Si

La2O3 (2.5-3.0 nm)

w/o SiLa2O3 (2.7-3.3 nm)


800 oC, 2 s(b)

Figure 5.12 eff at peak value around Eeff of 0.3 MV/cm for TiN/W/Si(0 or 0.3

nm)/La2O3 gate stack nMOSFETs annealed at 800 oC for 2 s as a function of EOT. A

large improvement of peak eff is confirmed by Si insertion.

90

100

110

120

130

0.5 0.55 0.6 0.65 0.7 0.75

EOT (nm)

eff

(cm

2 /V

s) (

Ee

ff=

1 M

V/c

m)

w/ SiLa2O3 (2.5-3.0 nm)

w/o SiLa2O3 (2.7-3.3 nm)


800 oC, 2 s

Eeff=1 MV

(c)

Figure 5.13 eff at Eeff of 1 MV/cm for TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack

nMOSFETs annealed at 800 oC for 2 s as a function of EOT. A large improvement of

eff at Eeff of 1 MV is confirmed by Si insertion.


- 101 -

confirmed for eff at peak value with Si inserted nFETs. Considering the reduction of

positive fixed charges with Si insertion as is seen in figure 5.8 and 5.10, the

improvement of peak eff can be explained by the suppression of remote charge

scattering (RCS) which is dominant in low Eeff region [5.7]. Then, figure 5.13 shows

eff at Eeff of 1 MV/cm for TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack nMOSFETs

annealed at 800 oC for 2 s as a function of EOT. An improvement can be also

confirmed for eff at Eeff of 1 MV/cm with Si inserted nFETs. The improvement in

the high Eeff region is considered to be due to the suppression of surface roughness

scattering which is dominant at high Eeff. La-silicate has various compositions as

stable phase, including La2SiO5, La9.33Si6O26 and La2Si2O7 [5.8], and its dielectric

constant changes as its composition varies. As shown in figure 5.7 and 5.9, the

formation of amorphous La-silicate layer at the metal gate/La2O3 interface might

suppress the diffusion of oxygen atoms, resulting in the formation of La-rich silicate

with higher k-value at the surface of Si substrate. Consequently, electrical roughness

sensed by carriers might become small with Si inserted nFETs. Figure 5.14

summarizes the Si insertion effect.

Figure 5.15 shows gate leakage current density-EOT plot for TiN/W/Si(0 or 0.3

nm)/La2O3 gate stack nFETs annealed at 800 oC for 2 s. A fairly nice Jg of 3.3 A/cm2

at Vg=1 V, which is ~103 times smaller with respect to the requirement in the ITRS

2009 roadmap, is achieved. Approximately same value of Jg even the EOT of Si

inserted nMOSFET is smaller can be explained by suppression of PF current which

flow through the traps in the dielectric as discussed in chapter 3.2.


- 102 -

W

La2O3

Si sub.

La rich-silicate

TiN

La-silicatex x

O

S D

W

La2O3

Si sub.

TiN

Si rich-silicate

O

O O

O

OO

S D

Higher k-valuew/ Si

w/o Si

W

La2O3

Si sub.

La-silicate

TiN

S D

W

La2O3

Si sub.

Vo VoVoVo

TiN

La-silicate

S D

Oxygen diffusion fromW electrode

W atoms diffusion fromW electrode

Oxygen vacancies segregatedat grain boundaries

Figure 5.14 Reduction of fixed charges which cause RCS and formation of La-rich

silicate at Si substrate interface by formation of amorphous silicate layer at metal

gate/high-k interface.


- 103 -

0.1

1

10

100

1000

10000

0.5 0.6 0.7 0.8

EOT (nm)

w/o SiLa2O3 (2.7-3.3 nm)

w/ SiLa2O3 (2.5-3.0 nm)

Requirements in the ITRS 2009 roadmap

104

103

102

101

100

10-1

J g(A

/cm

2)

(Vg=

1 V

)

Vg=1 V

Figure 5.15 Jg at Vg of 1 V for TiN/W/Si(0 or 0.3 nm)/La2O3 gate stack nMOSFETs

annealed at 800 oC for 2 s as a function of EOT. Jg of approximately 103 times

smaller with respect to the requirement in the ITRS 2009 roadmap, is achieved.


- 104 -

5.4 Quantitative understanding for mobility improvement

As described in previous chapter, RCS induced by fixed charges in the dielectric is

suppressed by Si insertion and improvement in mobility at low electric field region is

observed. However, Vfb and Vth behavior, parallel shift of ~150 mV by Si insertion,

and mobility improvement by suppression of RCS is explained only qualitatively.

Then, Vfb and Vth behavior and mobility improvement by suppression of RCS is

quantitatively studied. For simplicity, fixed charge in the dielectric is assumed to be

sheet charge. The influence of RCS depends on the distance from fixed charge to Si

substrate and fixed charge density (Nfix). In this chapter, difference of RCS effect for

FETs with and without Si insertion is expressed as distance of fixed charges and Si

substrate, conforming the value of Nfix of FETs with Si insertion to that without Si

insertion.

metal

dielectric

＋＋＋＋＋＋＋EOTchargeNfix

substrate

Figure 5.16 Schematic illustration of parameters used in this chapter.


- 105 -

Following Matthiessen’s rule, different contributions to the mobility is given by

...1111

321

(5.1)

where 1,2 and 3 correspond to the limited components of mobility such as the

lattice and impurity scattering 5.9. Then eq. 5.1 can be rewritten to

RCSwithoutRCS 111

(5.2)

where withoutRCS is limited components of mobility without RCS and RCS is the

mobility component limited by RCS. The reported mobility at low electric field

region with La2O3 gate dielectric is saturated at ~300 cm2/Vs for EOT>1.5 nm. Thus

withoutRCS can be considered to be 300 cm2/Vs for La2O3 gated MOSFET. The value

of Vfb and Vth shift is

ox

echfixg

EOTqNV

arg (5.3)

where q and ox denote the electronic charge and permittivity of SiO2 respectively.

EOTcharge corresponds to the EOT between gate electrode and fixed charges.

Considering the Vfb and Vth shift of 150 mV observed in figure 5.8 and 5.10, eq. (5.3)

gives

ox

Siwechfix

ox

oSiwechfixSiwgoSiwg

EOTqNEOTqNVV

/_arg/_arg

/_/_

=0.15 [V] (5.4)

where EOTcharge_w/oSi and EOTcharge_w/Si are the electrical distance between gate

electrode and fixed charges of FET without and with Si insertion, respectively. Then,

the eq. (5.2) can be calculated by using the equation of RCS reported in reference

[5.10], adjusting the parameters to satisfy the eq. (5.4). The calculated parameters

and mobility are shown in figure 5.17. The EOTcharge for Si inserted nFETs is

revealed to be smaller than that for nFETs without Si insertion. It can be


- 106 -

100

110

120

130

140

150

0.5 0.6 0.7 0.8

Eff

ecti

ve e

lect

ron

mo

bili

ty (

cm2/V

s)

EOT (nm)

w/ SiLa2O3 (2.5-3.0 nm)

w/o SiLa2O3 (2.7-3.3 nm)

Eeff=0.3 MV/cm

RCS1

300

11

W

La-silicate

＋＋＋＋＋＋＋

W

La-silicate＋＋＋＋＋＋＋

ΔVw/oSi-ΔVw/Si=150 mVNfix=~8×1013 /cm2

1 nm1.3 nm

w/ Si w/o Si

Figure 5.17 Calculated result of mobility. The lines correspond to calculated mobility.

Effective diffusion length of gate metal atoms is suppressed by Si insertion.

understood that effective diffusion length of gate metal atoms is suppressed by Si

insertion. Thus, the model for suppression of fixed charges ingression is proposed.

However, detailed analysis and experiment are necessary for future works.


- 107 -

5.5 Conclusion

A thin amorphous La-silicate layer formed by Si deposition at the W/La2O3 interface

is conducted and its effect on the electrical characteristics of MOS capacitors and

transistors is examined. A suppression of increase in EOT indicates the diffusion of

oxygen atoms thorough grain boundaries are inhibited by the formation of an

amorphous La-silicate at the W/La2O3 interface, resulting in reduction of La-silicate

layer at the La2O3/Si substrate interface. In addition, positive shifts in Vfb and Vth

with Si insertion implies the formation of amorphous La-silicate layer at the

W/La2O3 interface reduces positive fixed charges induced by diffused metal atoms or

oxygen vacancies segregated at grain boundaries. Consequently, a large improvement

in mobility has been confirmed for both at peak value and at high Eeff of 1 MV/cm

with Si inserted nFETs. Although a degradation trend on EOT scaling has been

observed, the insertion of thin Si layer is effective in pushing the scaling limit and

might be applicable for other metal /high-k gate stack such as Hf-based dielectrics.


- 108 -

References

[5.1] K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T.

Hattori, and H. Iwai, “Characterization of flatband voltage roll-off and roll-up




[5.3] K. McKenna, and A. Shluger, “The interaction of oxygen vacancies with grain

boundaries in monoclinic HfO2”, Appl. Phys. Lett., 95 (2009) p. 222111.

[5.4] L. V. Goncharova, M. Dalponte, D. G. Starodub, T. Gustafsson, E. Garfunkel, P.

S. Lysaght, B. Foran, J. Barnett, and G. Bersuker, “Oxygen diffusion and reactions in

Hf-based dielectrics”, Appl. Phys. Lett., 89 (2006) p. 044108.

[5.5] X. Li, C. H. Tung, and K. L. Pey, “The nature of dielectric breakdown”, Appl.

Phys. Lett., 93 (2008) p. 072903.

[5.6] G. Lucovsky, and J. Lüning, “Intrinsic limitations for CMOS with high-k gate

dielectrics: electrically-active grain boundary and oxygen atom defect states”, Proc.

ESSDERC, 2005, p. 439.


- 109 -

[5.7] S. Saito, K. Torii, M. Hiratani, and T. Onai, “Improved theory for

remote-charge-scattering-limited mobility in metal-oxide-semiconductor transistors”,

Appl. Phys. Lett., 81 (2002) p. 2391.

[5.8] G. Tzvetkov, and N. Minkova, “Mechanochemically induced formation of

La2SiO5”, J. Mater. Sci., 35 (2000) p. 2435.


Cambridge University Press, (1998) p. 20.


Hiratani, and S. Kimura, “Remoto-charge-scattering limited mobility in field-effect

transistors with SiO2 and Al2O3/SiO2 gate stack”, J. Appl. Phys., 98 (2005) p.

113706.

Chapter 6. Influence of Annealing Ambient during Silicate Formation

- 110 -

Chapter 6

Influence of Annealing Ambient during

Silicate Formation on Electrical

Characteristics

6.1 Introduction

6.2 Electrical characteristics with capacitors

6.3 Results with transistors

6.4 Conclusion

References


- 111 -

6.1 Introduction

Thus far, all samples are subjected to post-metallization annealing in F.G. ambient to

form high-quality silicate layer with various temperature and time. However it can be

considered that an annealing ambient also has a profound effect on electrical

characteristics of MOS devices. Therefore, examining the influence of the annealing

ambient on electrical characteristics is important to achieve high performance MOS

devices. Figure 6.1 shows C-V characteristics of a capacitor with HfO2-based gate

dielectric [6.1]. The capacitors are annealed in F.G. ambient which is reducing

condition and in oxidizing condition. The Vfb is shifted positive and negative

direction in sequence by simply switching the annealing ambient from reducing to

oxidizing and

Figure 6.1 C-V characteristics of MOS devices with HfO2-based gate dielectric. The

reversibility of the Vfb shift by reducing and oxidizing ambient is confirmed. [6.1]


- 112 -

vice versa. This Vfb behavior can be understood by the change of amount of oxygen

vacancies in gate dielectric. Whereas the annealing in oxidizing condition reduces

oxygen vacancies and Vfb shifts positive, the annealing in F.G., reducing condition,

forms oxygen vacancies and Vfb shifts negative.

Figure 6.2 C-V characteristics of MOS devices with La2O3 gate dielectric. The

no-reversibility of the Vfb shift by reducing and oxidizing ambient is confirmed. [6.2]

On the other hand, C-V characteristics of La2O3 gated capacitors annealed in the

oxidizing and reducing ambient is shown in figure 6.2 [6.2]. In the case of La-silicate,

negative shift of Vfb by annealing in reducing condition doesn’t occur, whereas

positive Vfb shift by oxidizing condition is observed. A different behavior of Vfb

between HfO2-based and La-silicate dielectric can be explained by existence of


- 113 -



Metal dry etching



Post metallization annealing (PMA)in F.G. or N2 ambient


Al wiring for S/D

n-Si Substrate


W deposition by RF-sputtering

in-situ

TaN deposition by RF-sputtering

Annealing at 420 oC in F.G. ambient

Figure 6.3 Fabrication process of La2O3 gated MOS devices used in this chapter.

Until the end of silicate formation annealing, samples are not exposed to the air.

covalent bond in La-silicate. The electrical instability of HfO2 for annealing ambient

is due to material nature associated with ionic bond. On the other hand, in La-silicate

layer, oxygen atoms are covalently-bonded with silicon atoms, resulting in

no-reversibility of the Vfb shift by reducing and oxidizing ambient. However, oxygen

atoms in La2O3, which a lot exists soon after deposition, are ionically-bonded.

Therefore, in the case of annealing in F.G. ambient during silicate formation, it is

anticipated that oxygen vacancy is formed in gate dielectric. In this chapter,

fabricated samples are subjected to annealing in F.G. or N2 ambient, investigating the


- 114 -

effect of annealing ambient on electrical characteristics. Figure 6.3 shows fabrication

process of La2O3 gated MOS devices used in this chapter. After the deposition of gate

electrode, samples are in-situ annealed in F.G. or N2 ambient. Until the end of silicate

formation annealing, samples are not exposed to the air.


- 115 -

6.2 Electrical characteristics with capacitors

C-V characteristics of TaN/W/La2O3/n-Si capacitors annealed at 900 oC for 30 min

in F.G. and N2 ambient are shown in figure 6.4. The EOTs of the two capacitors are

aligned to same value of 1nm. Although the hysteresis and hump shapes of C-V

curves are same, a difference in Vfb is observed.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-1.0 -0.5 0.0 0.5 1.0

Cap

acit

ance

(F

/cm

2 )

Voltage (V)

EOT=1 nm100 kHz

PMA 900 oC, 2 s

F.G.N2

Figure 6.4 C-V characteristics of TaN/W/La2O3/n-Si capacitors annealed in F.G. and

N2 ambient with an EOT of 1 nm. A difference of Vfb is observed.

Figure 6.5 shows Vfb-EOT plot of TaN/W/La2O3/n-Si capacitors annealed at 900 oC

for 30 min in F.G. and N2 ambient. The positive Vfb shift of ~200 mV is observed for

capacitors annealed in N2 ambient. These results indicate that the positive fixed

charges in gate dielectric are reduced by annealing in N2 ambient. As described in

chapter 6.1, the annealing in F.G. ambient, which is reducing condition, is anticipated


- 116 -

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

0.8 0.9 1 1.1 1.2

EOT (nm)

Vfb

(V)

PMA 900 oC, 30 min

N2

F.G.

Figure 6.5 Vfb-EOT plot of TaN/W/La2O3/n-Si capacitors annealed in F.G. and N2

ambient. A suppression of negative Vfb shift is observed for N2 annealing, indicating

the reduction of oxygen vacancies.

to form the oxygen vacancies, positive fixed charges, in La2O3 including ionic bonds.

Then, there is a possibility that mobility is improved by annealing in N2 ambient due

to suppression of RCS [6.3]. Next, electrical characteristics of transistors are

discussed to examine the influence of RCS.


- 117 -

6.3 Results with transistors

Effective mobility of TaN/W/La2O3 gate stack transistors annealed in F.G. and N2

ambient with the EOT of 0.72 nm as a function of Eeff is shown in figure 6.6. It can

be confirmed that higher eff is achieved for FET annealed in N2 ambient at all Eeff

region. Figure 6.7 shows the effective electron mobility at (a) Eeff of 0.3 MV/cm and

(b) Eeff of 0.8 MV/cm for TaN/W/La2O3 gate stack transistors annealed at 900 oC for

30 min in F.G. and N2 ambient as a function of EOT. The same degradation trend in

the eff caused by EOT scaling is observed for both annealing ambient.

0

20

40

60

80

100

120

140

160

180

200

0.0 0.2 0.4 0.6 0.8 1.0

EOT=0.72 nmL/W=10/10 m

eff

(cm

2 /V

s)


EOT=0.72 nmL/W=10/10 m

PMA 900 oC, 30 min

N2

F.G.

Figure 6.6eff-Eeff characteristic of TaN/W/La2O3 gate stack transistors annealed in

F.G. and N2 ambient. Mobility improvement is observed for transistor annealed in N2

ambient, especially at low electric region.


- 118 -

(a)

(b)EOT (nm)

Eff

ecti

ve m

ob

ility

(c

m2 /

Vs)

100

110

120

130

140

150

160

170

0.5 0.6 0.7 0.8 0.9 1

Eeff=0.3 MV/cmEeff=0.3 MV/cm

N2

F.G.

100

110

120

130

140

150

160

170

0.5 0.6 0.7 0.8 0.9 1

Eeff=0.8 MV/cm

EOT (nm)

Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

Eeff=0.8 MV/cm

N2

F.G.

Figure 6.7 eff at (a) Eeff of 0.3 MV/cm and (b) 0.8 MV/cm, respectively as a function

of the EOT. The mobility improvement is observed for N2 annealing, especially at low

electric field region, indicating suppression of RCS.


- 119 -

However, when compared at the same EOT, a large improvement can be confirmed

for eff, notably at low electric field of 0.3 MV/cm. Considering the reduction of

positive fixed charges with annealing in N2 ambient as shown in figure 6.7, the

improvement of eff at low Eeff can be explained by the suppression of RCS which is

dominant in low Eeff region.

For a quantitative understanding, the effect of RCS on the mobility is examined with

the similar approach as shown in chapter 5.4. For simplicity, fixed charge in the

dielectric is assumed to be sheet charge. Here, the effective length between the gate

electrode and fixed charges are supposed to be 1 nm for both annealing in F.G. and

N2 ambient. Considering the Vfb shift of 200 mV observed in figure 6.5, eq. (5.3)

gives

ox

echNfix

ox

echFGfixNgFGg

EOTqNEOTqNVV

arg2_arg_

2__

=0.2 [V] (6.1)

where Nfix_FG and Nfix_N2 correspond to the fixed charge density of FET annealed in

F.G. and N2 ambient, respectively. Then, the eq. (5.2) can be calculated by using the

equation of RCS reported in reference [6.4], adjusting the parameters to satisfy the eq.

(6.1). The calculated parameters and mobility are shown in figure 6.8. The Nfix in

FET with N2 annealing and that with F.G. annealing are revealed to be 3.8×1013 cm2

and 6.1×1013 cm2.

Thus, it is confirmed that the annealing in reducing ambient during silicate formation

forms oxygen vacancies in gate dielectric due to ionic bonds of La2O3, resulting in

degradation of mobility at low Eeff region. This mobility degradation can be

prevented by splitting the annealing process in annealing for silicate formation and


- 120 -

that for dangling bond termination. The annealing for silicate formation shouldn’t be

taken place in reducing ambient and that for dangling bond termination should be

taken place in F.G. ambient.

W

La-silicate

＋＋＋＋

ΔVFG-ΔVN2=200 mV

1 nm

N2

W

La-silicate

＋＋＋＋＋＋＋1 nm

F.G

NfixN2=3.8×1013 /cm2

NfixFG=6.1×1013 /cm2

100

110

120

130

140

150

160

170

0.5 0.6 0.7 0.8 0.9 1

Eeff=0.3 MV/cm

EOT (nm)

Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

Eeff=0.3 MV/cm

N2

F.G.

RCS1

300

11

Figure 6.8 C-V characteristics of TaN/W/La2O3/n-Si capacitors annealed in F.G. and

N2 ambient with an EOT of 1 nm.


- 121 -

(a)

(b)

0

50

100

150

200

250

300

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

EOT (nm)

Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

Eeff=0.5 MV/cm

This work

Hf-based oxide[IEDM]

0

50

100

150

200

250

300

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

EOT (nm)

Eff

ecti

ve m

ob

ility

(cm

2 /V

s)

Eeff=1 MV/cm

This work

Hf-based oxide[IEDM]

Figure 6.9 Benchmark of this work for effective electron mobility at (a) Eeff of 0.5

MV/cm and (b) 1 MV/cm respectively. A slightly higher mobility is achieved,

especially at low electric region.


- 122 -

Figure 6.9 shows the benchmark of effective electron mobility at (a) Eeff of 0.5

MV/cm and (b) Eeff of 1 MV/cm. The results of Hf-oxides reported in IEDM might

be record mobility with scaled EOT at the time of writing [6.5]. The La2O3 gated

FETs with annealing at 900 oC for 30 min in N2 ambient fabricated in this chapter

achieve slightly higher mobility than that of Hf-based oxide, especially at low

electric field region. This indicates the potentiality of amorphous La-silicate

dielectric fabricated with appropriate process.


- 123 -

6.4 Conclusion

In this chapter, fabricated samples are subjected to annealing in F.G. or N2 ambient,

investigating the effect of annealing ambient during silicate formation on electrical

characteristics. It is confirmed that the annealing in reducing ambient during silicate

formation forms oxygen vacancies in gate dielectric due to ionic bonds of La2O3,

resulting in degradation of mobility at low Eeff region. This mobility degradation can

be prevented by splitting the annealing process in annealing for silicate formation

and that for dangling bond termination. The annealing for silicate formation

shouldn’t be taken place in reducing ambient and that for dangling bond termination

should be taken place in F.G. ambient. The La2O3 gated FETs with annealing at 900

oC for 30 min in N2 ambient achieve slightly higher mobility than that of record data,

especially at low electric field region. This indicates the potentiality of amorphous

La-silicate dielectric fabricated with appropriate process.


- 124 -

References

[6.1] E. Cartier, F. R. McFeely, V. Narayanan, P. Jamison, B. P. Linder, M. Copel, V.

K. Paruchuri, V. S. Basker, R. Haight, D. Lim, R. Carruthers, T. Shaw, M. Steen, J.

Sleight, J. Rubino, H. Deligianni, S. Guha, R. Jammy, and G. Shahidi, “Role of

Oxygen Vacancies in VFB/Vt stability of pFET metals on HfO2” VLSI Tech. Dig.,

2005, p.230.

[6.2] T. Kawanago, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.

Natori, T. Hattori, and H. Iwai, “Covalent Nature in La-Silicate Gate Dielectrics for

Oxygen Vacancy Removal”, to be published in IEEE Electron Device Lett..

[6.3] S. Saito, K. Torii, M. Hiratani, and T. Onai, “Improved theory for

remote-charge-scattering-limited mobility in metal-oxide-semiconductor transistors”,

Appl. Phys. Lett., 81 (2002) p. 2391.


Hiratani, and S. Kimura, “Remoto-charge-scattering limited mobility in field-effect

transistors with SiO2 and Al2O3/SiO2 gate stack”, J. Appl. Phys., 98 (2005) p.

113706.


- 125 -

[6.5] T. Ando, M. M. Frank, K. Choi, C. Choi, J. Bruley, M. Hopstaken, M. Copel, E.

Cartier, A. Kerber, A. Callegari, D. Lacey, S. Brown, Q. Yang, and V. Narayanan,

“Understanding Mobility Mechanisms in Extremely Scaled HfO2 (EOT 0.42 nm)

Using Remote Interfacial Layer Scavenging Technique and Vt-tuning Dipoles with

Gate-First Process“, IEDM Tech. Dig., 2009, p.423.

Chapter 7. Conclusions

- 126 -

Chapter 7

Conclusions


- 127 -

In this thesis, the ways to fabricate the MOSFET with extremely small EOT of 0.5

nm and to prevent the effective mobility degradation accompanied with EOT scaling

is proposed for the scaling of MOS devices. In this chapter, the studies are

summarized below.

a) Selection of High-k Gate Dielectrics with Annealing Process (Chapter 3)

In order to suppress the increase in EOT after annealing, using CeOx which forms

silicate with high dielectric constant as a gate dielectric and short time annealing are

investigated. It is revealed that SiO2-IL changes to LaCe-silicate layer, whose

dielectric constant is higher than that of SiO2, by depositing La2O3 on CeOx, although

the formation of SiO2-IL is confirmed with CeOx dielectric. Suppression of an

increase in EOT and fairy nice interfacial property are confirmed with CeOx insertion.

Moreover, it is confirmed that short time annealing at high temperature is suitable to

obtain better electrical property of MOSFETs in terms of EOT, interfacial trap

density, fixed charge, and gate leakage current.

b) Selection of Metal Gate Electrode for Controlling Amount of Oxygen Atom

Supply (Chapter 4)

A novel control method for silicate reaction is proposed to achieve an EOT of 0.5 nm

using La2O3 gate dielectric. The amount of supplied oxygen atoms, which trigger the


- 128 -

formation of the silicate layer, is controlled by changing the thickness of an

oxygen-containing metal such as W. Almost no change in EOT from the as-deposited

condition was observed for the thin W electrode capacitor annealed for 2 s, and an

EOT of 0.51 nm is achieved with 800 oC annealing. In addition, the reduction of

EOT is observed with TiN capping due to oxygen diffusion from the gate dielectric

to the TiN electrode. On the other hand, larger hysteresis is observed for thin W film

capacitor, needing high temperature annealing to reduce the hysteresis. These imply

that C-V characteristics with a small EOT as well as a small hysteresis can be

obtained by optimization of annealing temperature and W film thickness. Moreover,

the hysteresis of the C-V curve, the humps at the weak inversion region, and Vfb shift

can be explained by the defect energy levels in the dielectric and La2O3/La-silicate

interface. Then, an appropriate transistor operation at an EOT of 0.5 nm is confirmed

for nMOSFETs with W of 3 nm annealed at 800 oC for 2 s.

c) Thin Si Insertion at Metal Gate/High-k Interface (Chapter 5)

A novel structure for eliminating grain boundaries at the top of La2O3 is proposed. A

thin amorphous La-silicate layer formed by Si deposition at the W/La2O3 interface is

conducted and its effect on the electrical characteristics of MOS devices is examined.

A suppression of increase in EOT indicates that the diffusion of oxygen atoms

thorough grain boundaries are inhibited by the formation of an amorphous La-silicate

at the W/La2O3 interface, resulting in reduction of La-silicate layer at the La2O3/Si

substrate interface. In addition, positive shifts in Vfb and Vth with Si insertion implies


- 129 -

the amorphous La-silicate layer at the W/La2O3 interface reduces diffused metal

atoms or oxygen vacancies induced by grain boundaries. Consequently, a large

improvement in mobility is confirmed for both at peak value and at high Eeff of 1

MV/cm with Si inserted nFETs. The Si insertion technique proposed in this study is

effective in pushing the scaling limit.

d) Influence of Annealing Ambient during Silicate Formation (Chapter 6)

The effect of annealing ambient during silicate formation on electrical characteristics

is investigated. It is confirmed that the annealing in reducing ambient during silicate

formation forms oxygen vacancies in gate dielectric, resulting in degradation of

mobility at low Eeff region. This mobility degradation can be prevented by splitting

the annealing process in annealing for silicate formation and that for dangling bond

termination. The annealing for silicate formation shouldn’t be taken place in reducing

ambient and that for dangling bond termination should be taken place in F.G. ambient.

According to the annealing guideline above, the La2O3 gated FETs is fabricated and

achieve slightly higher mobility than that of record data with Hf-based oxide,

especially at low electric field region. This indicates the potentiality of amorphous

La-silicate dielectric fabricated with appropriate process.


- 130 -

Finally, I would like to propose the fabrication process obtained from studies noted

above to achieve the MOSFET with high performance and small EOT (Figure 7.1).

Si substrateS D

Si substrateS D

CeOx

SiO2

CeOx deposition for good interfacial property

and small EOT

Si substrateS D

CeOx

SiO2

La2O3 depositionfor direct contact of high-k/Si

La2O3

Si substrateS D

CeOx

SiO2

Si depositionfor eliminating fixed charges induced by grain boundaries

La2O3

La-silicate

Si substrateS D

CeOx

SiO2

Oxygen-containing metal depositionfor formation of high quality silicate

La2O3

La-silicate

W

Si substrateS D

CeOx

SiO2

TiN depositionfor small EOT

La2O3

La-silicate

W

TiN

Si substrateS D

LaCe-silicate

La-silicate

W

TiN

Annealing at high temperature in N2and

Annealing at low temperature in F.G.

Figure 7.1 Guideline obtained from this thesis for MOSFET with high performance

and small EOT.

Publications and Presentations

- 131 -


[Publications]

[1] D. Kitayama, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nighiyama, N.

Sugii, K. Natori, T. Hattori, and H. Iwai, “High Temperature Rapid Thermal

Annealing of Rare-Earth Oxides Dielectrics for Highly Scaled Gate Stack of

EOT=0.5nm”, IEICE Technical Report, 110 [90] (2010) 43.


Sugii, K. Natori, T. Hattori, and H. Iwai, “TiN Capping Effect on High

Temperature Annealed RE-Oxide MOS Capacitors for Scaled EOT”, ECS Trans.,

33 [3] (2010) 527.

[3] D. Kitayama, T. Kubota, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A.

Nighiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, “Silicate Reaction

Control at Lanthanum Oxide and Silicon Interface for Equivalent Oxide

Thickness of 0.5 nm: Adjustment of Amount of Residual Oxygen Atoms in Metal

Layer”, Jpn. J. Appl. Phys., 50 (2011) 10PA05.


Sugii, K. Natori, T. Hattori, and H. Iwai, “Effect of thin Si insertion at metal

gate/high-k interface on electrical characteristics of MOS device with La2O3”,

Microelectron. Engineering, 88 (2011) 1330.


- 132 -

[Invited Talk]


Sugii, K. Natori, T. Hattori, and H. Iwai, “High Temperature Rapid Thermal

Annealing of Rare-Earth Oxides Dielectrics for Highly Scaled Gate Stack of

EOT=0.5nm”, SDM 2010, The University of Tokyo, Tokyo, June, 2010.

[International Presentations]



Temperature Annealed RE-Oxide MOS Capacitors for Scaled EOT”, 218th ECS

Meeting, Las Vegas, October, 2010.


Sugii, K. Natori, T. Hattori, and H. Iwai, “Influences of W Electrodes Thickness

on Electrical Properties of High Temperature Annealed La2O3 MOS Devices for

EOT of 0.5 nm”, IWDTF-11, Tokyo Institute of Technology, Tokyo, January,

2011.


Sugii, K. Natori, T. Hattori, and H. Iwai, “Effect of thin Si insertion at metal

gate/high-k interface on electrical characteristics of MOS device with La2O3”,

INFOS 2011, Minatec, Grenoble, June, 2011.


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Sugii, K. Natori, T. Hattori, and H. Iwai, “Effect of Silicate Formation at Metal

Gate/High-k Interface on Electrical Characteristics of La2O3 gated MOS Device”,

IS-AHND 2011, Tokyo Institute of Technology, Tokyo, October, 2011.

[Domestic Presentations]


Sugii, K. Natori, T. Hattori, and H. Iwai, “Electrical Characterization of High

Temperature Annealed La2O3 Gated MOS Capacitor”, 70th Japan Society of

Applied Physics (JSAP) Autumn Meeting, University of Toyama, Japan,

September, 2009.


Sugii, K. Natori, T. Hattori, and H. Iwai, “High Temperature Annealing of

La2O3/CeOx Dielectrics for Highly Scaled Gate Stack”, 15th Gate-Stack Meeting,

Japan, January, 2010.


Sugii, K. Natori, T. Hattori, and H. Iwai, “Study on TaSi2/La2O3/CeOx Gate Stack

toward EOT=0.5 nm”, 57th Japan Society of Applied Physics (JSAP) Spring

Meeting, Tokai University, Japan, March, 2010.


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Temperature Annealed RE-Oxide Capacitors for Scaled EOT”, 71th Japan Society

of Applied Physics (JSAP) Autumn Meeting, Nagasaki University, Japan,

September, 2010.


Sugii, K. Natori, T. Hattori, and H. Iwai, “Effect of La-silicate Formation at

W/La2O3 Interface on Electrical Characteristics of MOS Capacitor”, 58th Japan

Society of Applied Physics (JSAP) Spring Meeting, Kanagawa Institute of

Technology, Japan, March, 2011.

[6] D. Kitayama, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nighiyama, N. Sugii, K.

Tsutsui, K. Natori, T. Hattori, and H. Iwai, “Influence of Annealing Ambient

during Silicate Formation on MOS Characteristics”, 59th Japan Society of

Applied Physics (JSAP) Spring Meeting, Waseda University, Japan, March, 2012.

Acknowledgments

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Acknowledgments

First of all, I would like to express my gratitude to my supervisor Prof. Hiroshi

Iwai for his continuous encouragement and advices for my study. He also gave me

many chances to attend conferences. The experiences are precious for my present

and future life.

I deeply thank to Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Nobuyuki Sugii,

Prof, Akira Nishiyama, Prof. Kazuo Tsutsui, Prof. Yoshinori Kataoka, Associate Prof.

Parhat Ahmet, and Associate Prof. Kuniyuki Kakushima for useful advice and great

help whenever I met difficult problem.

I also thank research colleagues of Iwai Lab. for their friendship, active many

discussions and many of encouraging words.

I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms.

Matsumoto.

I would like to thank Mr. Koyanagi who is lonely man and Mr. Shigemory who is

thai for their passion.

I also express the appreciation to Mr. Monkichi, Ms. Koume, Ms. Jiko, and Ms.

Makie for giving me much healing.

Finally, I would like to thank my parents Mikio and Kumiko and my sister Nanami

for their endless support and encouragement.

Daisuke Kitayama

February, 2012

Documents

Interface Engineering of Extremely Scaled Silicate Gate