BYProf. Y. P. JadhavPhysics Department Smt. CHM college, Ulhasnagar - 3 YPJ*

Tri-state DevicesMicrocomputer contains at least one microprocessor and large number of interfacing devices (Peripheral or ICs or Chips). These devices are connected to microprocessor through a bus oriented system. The microprocessor can access (communicate with) only one (IO or memory) device at a time; hence all other devices (chips) must be disconnected. But all the devices cannot be disconnected within very short duration (1 sec) physically. Hence tri-state logic is used to disconnect unwanted chips or devices from the bus electrically, but not physically. YPJ*

Tri-state logic devices Three states logic 1, logic 0 and high impedance state (logic z). It has third input line called Enable, enabled - device works in its normal way. disabled - the logic device goes in to high impedance state-as if it is disconnected from the system.Tri-state logic is used to make devices compatible with bus oriented system.

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Truth tables:

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EI/PO/P0XLogic z101110

I/PO/P1XLogic z001010

Bufferthe logic device which amplifies the current or power. It has one input and one output line.non inverting or inverting output tri-state devices to facilitate their uses in bus oriented system. Use - primarily to increase the driving capability of a logic circuit (compared to logic gate) therefore also knows as driver. Two types:UnidirectionalBidirectional YPJ*

Unidirectional buffer:IC 74LS 224 - an octal tri-state non inverting unidirectional buffer. also known as line driver or line receiver. used as a driver for the address bus to improve driving capability of address lines. two groups of four buffers with tri-state output and controlled by two active low enable lines. Each buffer is capable of sinking 24 mA and sourcing 15 mA of current.

74 LS 240 is another example of tri-state buffer with inverted output.YPJ*

74LS244 is Octal Buffer and Line Driverdesigned to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. Hysteresis at Inputs - to Improve Noise Margins 3-State Outputs - to drive Bus Lines or Buffer Memory Address Registers Input Clamp Diodes - to limit High-Speed Termination EffectsYPJ*

Bidirectional buffer:The data bus of microprocessor is bidirectional therefore it requires a buffer that allows data to flow in both directions. bidirectional buffer 74LS 245. also called octal bus transceiver.

The direction of data flow is controlled by the pin DIR.

Another example - Intel 8286 high capability than 74LS245.These two buffers are not pin compatible. YPJ*

Enable DIROperationLLHLHXB data to A busA data to B busIsolation

Bidirectional buffer 74LS 245YPJ*

FUNCTIONAL DESCRIPTION OF OCTAL BUS TRANSCEIVER

The SN54/74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses.Direction Input (DIR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input can be used to isolate the buses.Hysteresis Inputs to Improve Noise Immunity2-Way Asynchronous Data Bus CommunicationInput Diodes Limit High-Speed Termination EffectsYPJ*

DecoderA decoder is a circuit that changes a code into a set of signals.used to convert one form of binary code into another form. it is a multi-input multi-output combinational logic device. For a particular input combination only one output line is activated. is a logic device that identifies each combination of the input signal and decodes it into a proper output line. decoder having n input lines will decode maximum m = lines types - 2-4, 3-8, 4-16, 4 -10 (BCD) etc.YPJ*

uses:interfacing I/O peripherals and memory. built internal to a memory chip to identify individual memory register (location). as an 8-output demultiplexer.YPJ*

74LS138 and Intel 8205 are examples of 3-to-8 decoder with active low output lines. YPJ*

FUNCTIONAL DESCRIPTION

The 74LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky barrier diode process.

The decoder accepts three binary weighted inputs (A2, A1, A0) and provides eight mutually exclusive active LOW Outputs (O0O7 or Y0Y7).

The LS138 features three Enable inputs, two active LOW (E1, E2) and one active HIGH (E3).

All outputs will be HIGH unless G2A and G2B are LOW and G1 is HIGH.

The 74 LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state.YPJ*

YPJ*Multiple enable inputs also allows easy parallel expansion of the decoder device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter (as shown in figure).

74LS138 Function TableYPJ*

InputsOutputsEnableSelectG1G2CBAY0Y1Y2Y3Y4Y5Y6Y7XHXXXHHHHHHHHLXXXXHHHHHHHHHLLLLLHHHHHHHHLLLHHLHHHHHHHLLHLHHLHHHHHHLLHHHHHLHHHHHLHLLHHHHLHHHHLHLHHHHHHLHHHLHHLHHHHHHLHHLHHHHHHHHHHL

EncoderAn encoder is a circuit that changes a set of signals into a code.The encoder is the logic circuit that provides the appropriate code as output for each input signal.74LS148:an 8 to 3 priority encoder.Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. data inputs and outputs are active at the low logic level. All inputs are buffered

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Encoders are commonly used- To interface input devices in n-Bit Encoding circuits in Code Converters and Generators

Priority encoder - in priority interrupts in computers and microprocessors. Function Table of 74LS 148YPJ*

InputsOutputsE101234567A2A1A0GSE0HXXXXXXXXHHHHHLHHHHHHHHHHHHLLXXXXXXXLLLLLHLXXXXXXLHLLHLHLXXXXXLHHLHLLHLXXXXLHHHLHHLHLXXXLHHHHHLLLHLXXLHHHHHHLHLHLXLHHHHHHHHLLHLLHHHHHHHHHHLH

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LatchIn its simplest from, a latch is a data flip-flop YPJ*

A latch is commonly used to interface output devices. Example: 74LS373 - a transparent latchIt includes eight D latches with tri-state buffers two input signals, Enable (G) and Output Control ( )

The Enable is the active high input connected to clock input of the flip-flops. The Output Control is active low, and it enables the tri-state buffers to output data

This latch can be viewed as register in a memory chip.YPJ*

Function table of 74LS373 YPJ*

OutputControlEnableGDataDOutputQLLLHHHLXHLXXHLQ0Logic Z

What is a Multiplexer (MUX)?A MUX is a digital switch that has multiple inputs (sources) and a single output (destination).The select lines determine which input is connected to the output.MUX Types 2-to-1 (1 select line) 4-to-1 (2 select lines) 8-to-1 (3 select lines) 16-to-1 (4 select lines)

*Multiplexer Block Diagram

Typical Application of a MUX*MUXY

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MULTIPLEXER (DATA SELECTOR)

A multiplexer is a logic circuit that accepts inputs from several different channels and feeds all of them into a single output channel in a sequential orderIt is a circuit that gates one of several inputs to a single output. It is multi-input single output combinational logic circuit. The input selected is controlled by a set of select (control) lines. MUX has n input lines and one output line. For selecting one input out of n inputs, a set of m select lines are required, where2 m = n. Normally, a active low strobe (enable) input (G) is incorporated. YPJ*

Block Diagram:YPJ*

4-to-1 Multiplexer (MUX)*

BAY00D001D110D211D3

4:1 Multiplexer:Logic equation :Truth table:YPJ*

Enable inputGSelect inputsoutputYS1S0000I0001I1010I2011I31XX0

Standard ICs are available for 2:1, 4:1, 8:1 and 16:1 multiplexers.Application of MUX:Sequence generator.Parallel to serial data converter .Combinational logic device.As a Multiplexer . YPJ*

IC No.DescriptionOutput7415774158741537435274151A7415274150Quad 2:1 Multiplexer.Quad 2:1 Multiplexer.Dual 4:1 Multiplexer.Dual 4:1 Multiplexer.8:1 Multiplexer.8:1 Multiplexer.16:1 Multiplexer.Same as inputInverted input.Same as inputInverted input.Inverted input.Inverted input.Inverted input.

8-to-1 MUX

Medium Scale Integration MUX4-to-1 MUX8-to-1 MUX16-to-1 MUX*InputsSelectEnableOutput (Y)(and inverted output)

Multiplexer Tree:8:1 MUX using two 4 :1 MUX YPJ*

InputsOutputCBAY000D0001D1010D2011D3100D4101D5110D6111D7

Alternative method:YPJ*

Implementation table for sumImplementation table for CarryFull adder using multiplexer:Truth table:YPJ*

InputsOutputsA BCinCarrySum0000000101010010111010001101101101011111

D0D1D2D30110A1001AA

D0D1D2D30001A01110AA1

Implementation of full adder using 4:1 MUX:YPJ*

Implementation of 4-variable logic equationusing 8:1 MUX. Solution:

Write the truth table for the logic equationConnect inputs A, B and C to S2, S1, S0 select inputs respectively.Observe the relation between D and Y and prepared the reduction table.Implement this truth table using 8:1 MUX.YPJ*

Truth tableTruth table after reduction logicYPJ*

InputsOutputABCDY00000000100010100110010010101001101011111000010011101011011111001110101110011111

InputsOutputABCY00000010100111100D1011110111D

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ABCD0011D

20300415116071D

8091D

100110012113111401500

What is a Demultiplexer (DEMUX)?A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).The select lines determine which output the input is connected to.DEMUX Types 1-to-2 (1 select line) 1-to-4 (2 select lines) 1-to-8 (3 select lines) 1-to-16 (4 select lines)

*Demultiplexer Block Diagram

Typical Application of a DEMUX*

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DEMULTIPLEXERSDemultiplexer is a logic circuit with one input and many outputs. By applying proper control signal, we can steer (transfer) the input signal to one of the output lines. Fig shows block diagram of DEMUX. The circuit has - one input line n output lines and m select (control) lines. Where n = 2 m YPJ*

1-to-4 De-Multiplexer (DEMUX)*

BAD0D1D2D300X000010X001000X011000X

1:4 (2-line to 4-line) Demultiplexer:Block diagramLogic diagramYPJ*

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IC No.DescriptionOutput74139

---------------------74155

---------------------74156

---------------------74138 --------------------- 74154

---------------------74159Dual 1:4 Demultiplexer (2-line to 4-line decoder)-----------------------------------do

-----------------------------------do

---------------------------------1: 8 Demultiplexer (3-line to 8-line decoder)---------------------------------1:16 Demultiplexer (4-line to 16-line decoder)-----------------------------------do--Inverted input.

---------------------------------1Y Inverted input.2Y Same as input ---------------------------------Open collector.1Y Inverted input.2Y Same as input ---------------------------------Inverted input.

---------------------------------Same as input.

----------------------------------Same as input.Open collector.

Medium Scale Integration DEMUX1-to-4 DEMUX1-to-8 DEMUX16-to-1 MUX*SelectInput(inverted)Outputs(inverted)Note : Most Medium Scale Integrated (MSI) DEMUXs , like the three shown, have outputs that are inverted. This is done because it requires few logic gates to implement DEMUXs with inverted outputs rather than no-inverted outputs.

Applications of DEMUX:Data Distributor.DecoderTo implement multi-output combinational logic expression.

Multiplexer and Demultiplexer in combination areused in Data transmission systems. YPJ*

Demultiplexer tree:YPJ*

Implementation of 1:8 DEMUX using two 1 : 4 DEMUXYPJ*

The multi-output combinational circuit using DEMUX and some additional logic gates

Example: Implement the following multi-output combinational circuit using 4 to 16 lines DEMUX. F1 = m (0, 3, 5, 10) F2 = m (0, 2, 4, 10) F3 = m (2, 4, 11, 15)

standard SOP form

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F1 = m (0, 3, 5, 10)F2 = m (0, 2, 4, 10)F3 = m (2, 4, 11, 15)YPJ*

Mux / Demux applications:All these six (mux, Demux, encoder, decoder, serial to parallel and || to serial convertors) devices are used in digital processing, telecommunications, instrumentation and computer architecture etc. And in a particular complete system they appear in pairs, like complex conjugates in maths. Frequency division, time division, wavelength division etc.

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*in which the same bus lines are shared by several devices (components).Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*This slide shows a typical application of a multiplexer (in this case a 4-to-1 MUX). Have the students share other common applications of MUXs.

http://images.tigerdirect.ca/skuimages/large/Logitech-X-540-L23-7250-mai.jpgMultiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*SSI logic diagram, block diagram, and truth table for a 4-to-1 MUXMultiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*Block diagrams for 4-to-1, 8-to-1, and 16-to-1 MSI Multiplexers.Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*This slide explains the function of a demultiplexer.Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*This slide shows a typical application of a demultiplexer (in this case a 1-to-4 DEMUX). Ask students to share other common applications of DEMUXs.Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*SSI logic diagram, block diagram, and truth table for a 1-to-4 De-MUX

Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*Block diagrams for 1-to-4, 1-to-8, and 1-to-16 MSI Demultiplexers.

Multiplexers & DemultiplexersDigital Electronics Lesson 2.4 Specific Combo Circuits & Misc TopicsProject Lead The Way, Inc.Copyright 2009*