Intro to IEEE 1149.1

Boundary-Scan (JTAG)

David Lavo

lavo@soe.ucsc.edu

UC Santa Cruz

January 27, 2005

© David Lavo Intro To Boundary-Scan 2

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

© David Lavo Intro To Boundary-Scan 3

IEEE 1149.1 Boundary-Scan

• Facilitates board testing

• Provides an on-chip means of

controlling and testing pads

• Boundary-scan components can also be

used for other test purposes:

– Logic and RAM BIST control

– Scan chain control

– Scan wrapper config., test modes, etc.

© David Lavo Intro To Boundary-Scan 4

Board Test

© David Lavo Intro To Boundary-Scan 5

Pad & Parametric Test

• 1149.1 can be used to control and

exercise pads independent of the chip

core

• Leakage on tri-state outputs

• Measure voltage and current for output

pads driving 0 or 1

• Test logic levels captured by input pads

at various voltages

© David Lavo Intro To Boundary-Scan 6

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

© David Lavo Intro To Boundary-Scan 7

1149.1 Hardware

• Test Access Port: 5 pins

• TAP Controller

– Finite State Machine

– Internal registers (Bypass, Instruction, etc.)

– Test control logic

• Boundary-Scan Register Chain

• Internal Data Registers (Optional)

© David Lavo Intro To Boundary-Scan 8

Boundary-Scan Components

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

I

O

© David Lavo Intro To Boundary-Scan 9

TAP Controller Components

TDI

TMS

TCK

TRST_N

TDO

Various TAP

Outputs:

UpdateDR,

CaptureDR,

TriState,

Etc.

Finite

State

Machine

Instruction Register

Bypass Reg.

Instruction

Decode

SO SI

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 11

BYPASS Instruction

• A mandatory instruction

• The default instruction for TAPs with no

IDCODE register

• Short scan path: 1 bit between TDI and

TDO

• Usually loaded in chips that are idle

while other chips on the board are being

tested

© David Lavo Intro To Boundary-Scan 12

BYPASS Data Path

TDI

TMS

TCK

TRST_N

TDO

Finite

State

Machine

Instruction Register

Instruction

Decode

SO SI

Bypass Reg.

© David Lavo Intro To Boundary-Scan 13

EXTEST & SAMPLE/PRELOAD

• EXTEST is the “workhorse” JTAG instruction

– Sample (“Capture”) & Drive (“Update”) output

signals

– Sample & optionally drive input signals

• Data is first loaded into boundary register

chain with SAMPLE/PRELOAD instruction

– Samples inputs and outputs, pass-through

– Loads boundary register with data

© David Lavo Intro To Boundary-Scan 14

SAMPLE/

PRELOAD

SAMPLE/PRELOAD: Start

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

BYPASS

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 16

Instruction Register Data Path

TDI

TMS

TCK

TRST_N

TDO

Finite

State

Machine

Instruction

Decode

SO SI

Bypass Reg.

Instruction Register

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

Exit2-IR

Update-IR

© David Lavo Intro To Boundary-Scan 18

SAMPLE/

PRELOAD

SAMPLE/PRELOAD:

UpdateIR

Chip

Core

TAP

Controller

TDI

TMS

TC

K TDO

TRST_N

BYPASS SMP/PRLD

DATA

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

Update-IR

© David Lavo Intro To Boundary-Scan 20

SAMPLE/PRELOAD: CaptureDR

Chip

Core

TAP

Controller

TDI

TMS

TC

K TDO

TRST_N

SMP/PRLD

DATA

Mode=0

Capture (sample)

0 1 0 1

0 1 0 1

0

1

0

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 22

SAMPLE/PRELOAD: ShiftDR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

SMP/PRLD

DATA

0 1 0 1 1 0 1 0

0 1 0 1

1

0

0

0 1 0 1 1

0

1

0

0

1

1

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 24

SAMPLE/PRELOAD:

UpdateDR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

SMP/PRLD

1 0 1 0

0 1 0 1

0

1

1

Mode=0

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

Update-DR

© David Lavo Intro To Boundary-Scan 26

EXTEST: UpdateIR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

1 0 1 0

0 1 0 1

0

1

1

EXTEST

EXTEST

Mode=1

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

Update-IR

© David Lavo Intro To Boundary-Scan 28

DATA

EXTEST: CaptureDR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

1 0 1 0

0 1 0 1

0

1

1

EXTEST

1

1

1

1 1 1 1

Capture (sample)

1 1 1 1

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 30

DATA

EXTEST: ShiftDR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

EXTEST

1 1 1 1 0 0 0 0

1

1

1

0

0

0

1 1 1 1 0 0 0 0 1

1

1

1

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0 1 0 1

© David Lavo Intro To Boundary-Scan 32

EXTEST: UpdateDR

Chip

Core

TAP

Controller

TDI

TMS

TCK

TDO

TRST_N

DATA

0 0 0 0

0 0 0 0

0

0

0

EXTEST

Mode=1

© David Lavo Intro To Boundary-Scan 33

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

© David Lavo Intro To Boundary-Scan 34

Boundary-Scan Documentation

• IEEE Standard:

– IEEE Std 1149.1-1990 & 1149.1a-1993:

“IEEE Standard Test Access Port and

Boundary-Scan Architecture”

– IEEE Std 1149.1b-1994:

“Supplement to IEEE Std 1149.1-1990 ….”

(BDSL)

– IEEE Std 1149.1-2001

• “The Boundary-Scan Handbook”,

Second Edition (1998), by Ken Parker

© David Lavo Intro To Boundary-Scan 35

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

© David Lavo Intro To Boundary-Scan 36

Why JTAG is Cool

• Adds a lot of test functionality with a

small amount of effort

– Board test

– Pad/parametric test

– Enhanced debug and diagnosis

– Control of TAP-based tests (BIST, clocks)

• Functionally simple

• Ultra low performance: 5 to 10 MHz!

© David Lavo Intro To Boundary-Scan 37

Lots of Uses Besides Board

Test • On-chip access to BIST, programmable

logic & EEPROMs, system and circuit test

• System configuration & maintenance:

© David Lavo Intro To Boundary-Scan 38

Why JTAG is a Pain

• Messes with chip timing!

• Complicates placement and routing

• Obtuse rules, motivations, language

and documentation

• Requires some manual data entry or

massaging

• No automated debugging tools

© David Lavo Intro To Boundary-Scan 39

1149.1 Timing Impact

• JTAG adds a mux, and sometimes a

gate, into the data path

– Insert JTAG early in design process!

• The impact can be reduced to just a

load by using a “read-only” cell

– Intended only for clocks and other sensitive

inputs

– Some test capability is lost

© David Lavo Intro To Boundary-Scan 40

JTAG Input Cell/Macro

Data Path

Capture Path

Scan Path

Update Path

© David Lavo Intro To Boundary-Scan 41

JTAG Read-Only Input

Cell/Macro

Data Path

Capture Path

Scan Path

Update Path

© David Lavo Intro To Boundary-Scan 42

JTAG Output Cell/Macro

Data Path

Capture Path

Scan Path

Update Path

© David Lavo Intro To Boundary-Scan 43

JTAG Output-Enable

Cell/Macro

Data Path

Capture Path

Scan Path

Update Path

© David Lavo Intro To Boundary-Scan 44

1149.1 Place & Route Impact

• Boundary-scan register cells should be

placed near associated pads

– Best location is routing track next to pads

– Avoid long wires from registers to pads

• TAP signals can cause routing congestion

– From 3 to 5 global signals from TAP to each

boundary-register cell (all around chip)

– Need to budget for this early

© David Lavo Intro To Boundary-Scan 45

Placement of Boundary

Registers

Core

Bad

Good

© David Lavo Intro To Boundary-Scan 46

Global Routing Congestion

© David Lavo Intro To Boundary-Scan 47

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

© David Lavo Intro To Boundary-Scan 48

Beyond Board-Test:

Extending the TAP Controller

• The TAP Controller runs the show for

boundary-scan and other TAP-based tests

• Some TAP-based test functions have

become increasingly complex & specialized

– Test signal control

– BIST control and capture

– Scan shifting

• Most functions are based on TAP registers

© David Lavo Intro To Boundary-Scan 49

Static Register: IDCODE

• 32 Bits predefined in

internal register:

– Version (4 bits)

– Part Number (16 bits)

– Manufacturer (11 bits)

– LSB is set to 1

• Scan out through

TDO during IDCODE

instruction

0

TDI

TDO

V P M 1

Instruction:

1

0

1

0

BYPASS IDCODE

1

0

1

0

0

V

P

M

1

X

X

X

X

© David Lavo Intro To Boundary-Scan 50

Update-Only: User Register

• General-purpose bits

• User defines and

connects signals

• Scan in a value

(through TDI) to set

• Used for test modes,

configurable logic,

etc.

• No capture capability

TDI

TDO

0 0 0 0

Instruction: SELUSER

0

0

0

0

TAP State: UpdateDR

1 0 1 1

1

0

1

1

0

0

0

0

1

0

1

1

© David Lavo Intro To Boundary-Scan 51

1 1 1 1

Capture/Update Register:

RAMBIST • Capture and update

capability

• User-defined signals:

– Drive RAMBIST enable

– Read RAMBIST results

• Scan in a value

(through TDI) to set

• Scan out results

through TDO

TDI

TDO

Instruction:

SELRAMBIST

TAP State:

1 1 1 0 1 0 1 X

R0

R1

R2

R3 X

4

ScanDR UpdateDR RUNRAMBIST

R1

R2

R3

RunTest

R1

R2

R3 1

0

1

X

1

1

1

0

CaptureDR ScanDR