Confidential

Introduce ARM &

Programmer’s model

June 4, 2008

SW2G-SW4team Roy, Kang

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Contents

Introduce ARM

Programmer’s model

Reference

Q/A

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Introduce ARM – Why ?

32bit RISC processor from …

Advanced RISC Machines Ltd.

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Introduce ARM – Architecture VS Processor

Architecture : 명령어, register 구조, 처리되는 데이터의 크기 등기본 구성 및 동작 원리

Processor : Core에 cache, MMU, write buffer, TCM 등과 같은 주변회로를 포함하는 독립된 형체

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Architecture Processor

V4 ARM7TDMI, ARM720T, ARM940T, ARM920T, ARM922T

v5TE ARM946E-S, ARM926E-S, Xscale

v5TEJ ARM926EJ-S

V6 ARM1136JF-S

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Introduce ARM – Postfix

ARM {x} {y} {z} {T} {D} {M} {I} {E} {J} {F} {-S}

– x : Family

– y : MMU / MPU

– z : Cache

– T : 16bit Thumb instruction set decoder

– D : JTAG debugger

– M : 32bit multiplier function

– I : Embedded ICE macrocell (for break and watch point)

– E : Extended DSP instruction set

– J : Jazelle

– F : Floating point processor

– -S : Synthesizable version

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Introduce ARM – Core

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Introduce ARM – Pipeline

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Programmer’s model – Data types & Access

ARM processors support the following data types:

– Byte : 8bits

– Halfword : 16bits (must be aligned to two-byte boundaries)

• 0x0, 0x2, 0x4, 0x6, 0x8, … (bit 0 is must 0)

– Word : 32bits (must be aligned to four-byte boundaries)

• 0x0, 0x4, 0x8, 0xC, 0x10, … (bit 0, 1 is must 0)

If access un-aligned memory (0x1, 0x3, …)

– Generated Abort exception by memory system

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Programmer’s model – Memory (Big-endian)

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Programmer’s model – Memory (Little-endian)

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Programmer’s model – Processor mode

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Programmer’s model – Register

The ARM processor has a total 37 registers

– 31 general-purpose registers (including SP_<mode>, LR_<mode>, PC)

• SP : Stack pointer of current processor mode

• LR : Link register has two special functions in the architecture

– Hold subroutine return address

– Set to the exception return address

• PC : Program counter (execution address)

– 6 status registers (1 CPSR, 5 SPSR)

Unbanked VS banked registers

– Unbanked : r0 – r7 (same all processor mode)

– Banked : r8 – r14 (depends on current processor mode, refer next page)

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Programmer’s model – Register organization

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Programmer’s model – Status register

Flag bits

– Negative, Zero, Carry, oVerflow

– saturation (Q, 27, v5TE/J)

– Jazelle (J, 24, upper v5TEJ)

Control bits

– IRQ (I), FIQ (F) mask

– ARM / Thumb (T) mode

– operation Mode (5bits)

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Programmer’s model – Exception

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Programmer’s model – Exception handling

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Exception

Copy CPSR to SPSR_<mode>

Modify CPSR bit

Change processor mode

Change to ARM mode

Disable interrupt (optional)

Copy PC to LR_<mode>

Change PC to vectorException handling vector

Exception handler

Return

Revert CPSR

Revert PC

Context

Processed by ARM (H/W)Processed by USER (S/W)

Atomic instruction!!

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Programmer’s model – Return to user context

There two types:

– Using SUB”S” or MOV”S” instruction

– Using stack

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handler

<handler code>

…

SUBS pc, r14, #4 or

MOVS pc, r14

; Postfix “S” and op1 PC mean : copy SPSR_<mode> to CPSR

handler

SUB r14, r14, #4

STMFD r13!, {r0-r3, r14}

…

<handler code>

…

LDMFD r13!, {r0-r3, pc}^

;^ mean : copy SPSR_<mode> to CPSR

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Programmer’s model – Return address

Type Exception Return address

- Reset -

Fault Data Abort LR – 8

Trap FIQ LR – 4

Trap IRQ LR – 4

Trap Prefetch Abort LR – 4

Abort SWI LR

Abort Undefined Instruction LR

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Programmer’s model – Reset exception

ARM processor immediately stops execution of the current instruction,

following actions are performed:

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Programmer’s model – Undefined Instruction exception

Two ways of exception occurs

– No coprocessor responds

– Attempt is made to execute an instruction that is UNDEFINED

Following actions are performed:

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Programmer’s model – SWI exception

Request a particular supervisor (operating system) function, the

following actions are performed:

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Programmer’s model – Prefetch Abort exception

Call to “instruction fetch memory abort”, it signaled by the memory

system (MMU / MPU / other memory controller)

Processor tries to execute the invalid (don’t has permission for access

address) instruction. If not executed, no Prefetch Abort occurs.

The following actions are performed:

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Programmer’s model – Data Abort exception

Call to “data access memory abort”, it signaled by the memory system

(MMU / MPU / other memory controller)

Processor tries to R/W on invalid address, the following actions are

performed:

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Programmer’s model – IRQ exception

The IRQ exception is generated externally by asserting the IRQ input

on the processor, the following actions are performed:

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Programmer’s model – FIQ exception

The FIQ exception is generated externally by asserting the FIQ input

on the processor, the following actions are performed:

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Reference

ARM Architecture Reference Manual – ARM

ARM System Developer’s Guide – SciTech, Andrew M. Sloss, …

ARM으로 배우는 Embedded system – 한빛미디어, 안효복

ARM processor – MDS technology

ARM Core 강좌 - 박길성

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Q/A

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