Introduction to ANSYS SIwave - bbs.hwrf.com.cnbbs.hwrf.com.cn/downpcbe/WS08_siwave_dc-944.pdf · February 23, 2009 Inventory #002593 WS8-3 © 2013 ANSYS, Inc. June 14, 2013 Release

14.5 Release

Introduction to ANSYS SIwave

Workshop 8: DC

February 23, 2009

Inventory #002593 © 2013 ANSYS, Inc. WS8-2 Release 14.5 June 14, 2013

• DC Voltage (DCIR) Drop Across a PWB – This DCIR example is intended to show you how to simulate the voltage drop across a power plane between the

voltage regulator module (VRM) and an ASIC controller.

– Due to the larger number of plane cut outs, non-ideal current paths, vias and signals on a PWB the power distribution

network (PDN) suffers dramatically. This example will show you to verify a PDN for I2R losses.

– For this example, we will define a voltage source and current sink on a PWB to analyze the voltage drop as the current

approaches the ASIC controller.

SIwave DC Analysis

February 23, 2009


• Ansoft SIwave Design Environment – The following features of the Ansoft SIwave Design Environment are used to simulate the voltage drop.

• Verification of board import

– Check stack up

– Check nets

– Check circuit elements

• Generate sources and sinks

– Voltage sources

– Current sinks

• Meshing

– Bondwire meshing

– Via meshing

– Adaptive mesh refinement

– Defining earth ground

• Plotting and analyzing results

– Current plots

– Voltage plots

– Element data

Example – DC Voltage Drop Across a PWB

February 23, 2009


• Starting SIwave – To launch SIwave program, click the Microsoft Start Button, select All Programs, select ANSYS Electromagnetics,

SIwave with Alinks 7.0, Windows XX-bit. Select the executable SIwave 7.0 (xx-bit).

• Open a SIwave Project – Select the menu item File > Open

• Browse for file:

SIwave DC Analysis.siw

• Click the Open button


February 23, 2009


• Verification of Board Importation – After importing the layout into SIwave verify the import was performed correctly by checking the following: board

geometry, stack up, nets, and circuit elements

– To check the stack up select the menu item Edit > Layer Stack (Crtl+L). This will open the Layer stack

window.


February 23, 2009


• Verification of Board Importation • To check the circuit elements select the menu item Edit > Circuit Element Parameters. This displays the circuit

elements.


To check the nets click on the Nets Tab

in the dockable window. This displays

the netlist.

February 23, 2009


• Generation of Sources and Sinks – To perform a DCIR drop simulation, voltage sources and current sinks must be defined. Generally, these will be defined

at the VRM and at the ICs, however it may be valuable to place these sources and sinks in other locations such as

connectors. In this example we will define the sinks with a wizard and the source manually.

• Set layer display in the Layers dockable window, to display SURFACE layer only.

• To Select the IC device that we will place sources on, click the following:

– Select the menu item Circuit Elements > Generate on Components…


February 23, 2009


• Generation of Sources and Sinks – For the Positive Terminal Component

• Change Part Name to SQFP28X28_208

• Reference Designator: U2

– For the Reference Terminal Component

• Change Part Name to SQFP28X28_208

• Reference Designator: U2

– Circuit Element Positive Terminal: VCC

– Circuit Element Reference Terminal: GND

• Use Nearest Pin as reference pin

– Circuit Element Type: Current Source

– Click the Create button


February 23, 2009


• Generation of Sources and Sinks – Generation of current sinks

• Several options exist: frequency independent and dependent sources may be used.

• This example will focus on the frequency independent setup.

• Generally, the parallel resistance of a current source is high. We will use the default value of 5E+007 ohms for this

example.

– In the Set Current Source Properties box:

• Select Frequency Independent

– Magnitude: 1 Amps

– Parasitic Resistance: 5e+07

– Phase: 0 degrees

– Click the OK button


February 23, 2009


• Generation of Sources and Sinks – Generation of current sinks

• Notice that a sink was generated for each VCC pin for this IC.

• Verify the Current sources were properly created and click OK.

• Note: Default naming convention was the following: $NETNAME_$REFDES_$POSTERMINAL


February 23, 2009


• Generation of Sources and Sinks – Generation of voltage source

• To visually locate the VRM, change the net color

– Select Nets Tab > VCC > RMB click >

Change Net Color > Red

• To visually locate the nearest ground, change

the net color.

– Select Nets Tab > GND > RMB click >

Change Net Color > Green


February 23, 2009


• Generation of Sources and Sinks – Select the menu item View > Top-Down View

– Set the Units to mils

– Select the menu item Circuit Elements > Voltage Source

• For the Positive Terminal Select x = 2800 mils, y = -1950 mils

– Hit Enter

• For the Negative Terminal Select x = 2800 mils, y = -2150 mils

– Hit Enter

• For the Positive Terminal Layer Select Surface

• For the Negative Terminal Layer Select Surface

• Click the OK button


February 23, 2009


• Generation of Sources and Sinks – For the voltage source the Parasitic Resistance refers to series resistance. In this example we want it to be a minimum

– In the Set Voltage Source Properties box

• Select Frequency Independent

• Magnitude: 1.8 Volts

• Parasitic Resistance: 1e-08

• Phase: 0 degrees

• Click the OK button


February 23, 2009


• Generation of Sources and Sinks – Select the menu item Edit > Circuit Element Parameters to view the setup of the Current Sources, and the Voltage

Sources

– When finished press the OK button.


February 23, 2009


• Simulation and Meshing – Change units to mils (from Units pull-down menu)

– Select the menu item Simulation > SIwave > Compute DC Current/Voltage.

• The Compute DC Current and Voltage Distribution box is used to define the mesh.

• Place check mark next to Mesh Via

• Check Perform Adaptive Mesh Refinement.

– We will use a minimum of 1 and maximum of 5 to reduce the meshing time. Generally a minimum of 3 and

maximum of 8 – 10 provides accurate answers. You may modify how quickly the mesh may change to

improve its accuracy (Local %) and the convergence criteria (Global Error).

• Define earth ground at the VRM negative terminal by changing V1; Node to Ground to Negative.


February 23, 2009


• Simulation and Meshing – Put a check mark next to Export Power Dissipation to Ansys Icepak

• Min Thermal Cell Size: 118.11 mils

• Min Power Loss Per Cell: 0.05 milliwatts

• Click OK.

– When the solution is finished, the output files (.OUT) that Icepak reads will be located in the project directory:

• \01_7_DC_voltage_drop.siwaveresults\0000\dcthermal


February 23, 2009


• Results and Analysis – Click Results > SIwave > DC IR DROP > DC IR SIM 1 > Currents/Voltages

– The DC IR Drop Simulation Results box appears. When both current and voltage are checked you do not have a scale.

However, by looking at the voltage and current independently a scale will be present.

– Plot just the voltage (V) on the VCC layer by un-checking all other boxes


February 23, 2009


• Results and Analysis – Change the voltage color scale by clicking on it and selecting User Defined. Change the maximum to 1.8 V and the

minimum to 1.77 V then click OK.

– Hovering the mouse over the board gives real time voltage readout at the location of the cursor.


February 23, 2009


• Results and Analysis – In the DC IR Drop Simulation Results box, select Current Density (J) for the Vcc layer and unselect the Voltage.

– Change the scale to Logarithmic

• Click OK.

– Hovering the mouse over the board give real time current density (A/m2).


February 23, 2009


• Results and Analysis – Select Results > SIwave > DC IR DROP > DC IR SIM 1 > Element Data

• This shows the parallel current and voltage at each current sink and voltage source along with the current,

resistance, and voltage drop at each via. It shows pass or fail at each via based upon the default current limits or

user supplied current limits.

– Pass/Fail criteria is used to determine whether reliability issues will arise due to electromigration.


Documents

Introduction to ANSYS SIwave - bbs.hwrf.com.cnbbs.hwrf.com.cn/downpcbe/WS08_siwave_dc-944.pdf · February 23, 2009 Inventory #002593 WS8-3 © 2013 ANSYS, Inc. June 14, 2013 Release