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Introduction toCMOS VLSI
Design
Lecture 4: DC & Transient Response
Greco/Cin-UFPE
(Material taken/adapted from Harris’ lecture notes)
CMOS VLSI Design4: DC and Transient Response Slide 2
Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation
CMOS VLSI Design4: DC and Transient Response Slide 3
Activity1) If the width of a transistor increases, the current will
increase decrease not change 2) If the length of a transistor increases, the current will
increase decrease not change3) If the supply voltage of a chip increases, the maximum
transistor current willincrease decrease not change
4) If the width of a transistor increases, its gate capacitance willincrease decrease not change
5) If the length of a transistor increases, its gate capacitance willincrease decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
CMOS VLSI Design4: DC and Transient Response Slide 4
Activity1) If the width of a transistor increases, the current will
increase decrease not change 2) If the length of a transistor increases, the current will
increase decrease not change3) If the supply voltage of a chip increases, the maximum
transistor current willincrease decrease not change
4) If the width of a transistor increases, its gate capacitance willincrease decrease not change
5) If the length of a transistor increases, its gate capacitance willincrease decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
CMOS VLSI Design4: DC and Transient Response Slide 5
DC Response DC Response: Vout vs. Vin for a gate
Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
– In between, Vout depends on
transistor size and current– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations– But graphical solution gives more insight
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 6
Transistor Operation Current depends on region of transistor behavior For what Vin and Vout are nMOS and pMOS in
– Cutoff?– Linear?– Saturation?
CMOS VLSI Design4: DC and Transient Response Slide 7
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn >
Vdsn <
Vgsn >
Vdsn >
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 8
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 9
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
CMOS VLSI Design4: DC and Transient Response Slide 10
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
CMOS VLSI Design4: DC and Transient Response Slide 11
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp <
Vdsp >
Vgsp <
Vdsp <
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 12
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 13
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
CMOS VLSI Design4: DC and Transient Response Slide 14
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
CMOS VLSI Design4: DC and Transient Response Slide 15
I-V Characteristics Make pMOS is wider than nMOS such that n = p
Vgsn5
Vgsn4
Vgsn3
Vgsn2Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
CMOS VLSI Design4: DC and Transient Response Slide 16
Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
CMOS VLSI Design4: DC and Transient Response Slide 17
Load Line Analysis
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn
Idsp Vout
VDD
Vin
CMOS VLSI Design4: DC and Transient Response Slide 18
Load Line Analysis
Vin0
Vin0
Idsn, |Idsp|
VoutVDD
Vin = 0
CMOS VLSI Design4: DC and Transient Response Slide 19
Load Line Analysis
Vin1
Vin1Idsn, |Idsp|
VoutVDD
Vin = 0.2VDD
CMOS VLSI Design4: DC and Transient Response Slide 20
Load Line Analysis
Vin2
Vin2
Idsn, |Idsp|
VoutVDD
Vin = 0.4VDD
CMOS VLSI Design4: DC and Transient Response Slide 21
Load Line Analysis
Vin3
Vin3
Idsn, |Idsp|
VoutVDD
Vin = 0.6VDD
CMOS VLSI Design4: DC and Transient Response Slide 22
Load Line Analysis
Vin4
Vin4
Idsn, |Idsp|
VoutVDD
Vin = 0.8VDD
CMOS VLSI Design4: DC and Transient Response Slide 23
Load Line Analysis
Vin5Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Vin = VDD
CMOS VLSI Design4: DC and Transient Response Slide 24
Load Line Summary
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
CMOS VLSI Design4: DC and Transient Response Slide 25
DC Transfer Curve Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
CMOS VLSI Design4: DC and Transient Response Slide 26
Operating Regions Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region nMOS pMOS
A
B
C
D
E
CMOS VLSI Design4: DC and Transient Response Slide 27
Operating Regions Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
CMOS VLSI Design4: DC and Transient Response Slide 28
Beta Ratio If p / n 1, switching point will move from VDD/2
Called skewed gate Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.51
2
10p
n
0.1p
n
CMOS VLSI Design4: DC and Transient Response Slide 29
Noise Margins How much noise can a gate input see before it does
not recognize the input?
IndeterminateRegion
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical HighInput Range
Logical LowInput Range
Logical HighOutput Range
Logical LowOutput Range
CMOS VLSI Design
By definition, VIH and VIL are the operational points of the inverter where
4: DC and Transient Response Slide 30
VDD
Vin
Vout
VOH
VDD
VOL
VIL VIHVtn
Unity Gain PointsSlope = -1
VDD-|Vtp|
p/n > 1
Vin Vout
0
A high gain (g) is desirable
CMOS VLSI Design4: DC and Transient Response Slide 31
Logic Levels To maximize noise margins, select logic levels at
VDD
Vin
Vout
VDD
p/n > 1
Vin Vout
0
CMOS VLSI Design4: DC and Transient Response Slide 32
Logic Levels To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL VIHVtn
Unity Gain PointsSlope = -1
VDD-|Vtp|
p/n > 1
Vin Vout
0
CMOS VLSI Design4: DC and Transient Response Slide 33
Transient Response DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
CMOS VLSI Design4: DC and Transient Response Slide 34
Inverter Step Response Ex: find step response of inverter driving load cap
0( )
(
)
)
(o
i
ut
n
out
V t t
t
V
t
V
d
d
t
Vin(t) Vout(t)Cload
Idsn(t)
CMOS VLSI Design4: DC and Transient Response Slide 35
Inverter Step Response Ex: find step response of inverter driving load cap
0
0
( )
( )
( )
( )
ou
DDin
t
out
u t t V
d
d
t
t t
V t
V
V
t
Vin(t) Vout(t)Cload
Idsn(t)
CMOS VLSI Design4: DC and Transient Response Slide 36
Inverter Step Response Ex: find step response of inverter driving load cap
0
0(
( ))
(
(
)
)
DD
Do
i
D
o t
n
ut
u
V t
u t t V
V
d
d
t
t
V
V
t
t
Vin(t) Vout(t)Cload
Idsn(t)
CMOS VLSI Design4: DC and Transient Response Slide 37
Inverter Step Response Ex: find step response of inverter driving load cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
( ) DD tout
ou
ds
t DD t
nI t V V
VV V
V
t t
Vin(t) Vout(t)Cload
Idsn(t)
CMOS VLSI Design4: DC and Transient Response Slide 38
Inverter Step Response Ex: find step response of inverter driving load cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
2
2
0
2)
)
( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
t
V t V t
Vin(t) Vout(t)Cload
Idsn(t)
CMOS VLSI Design4: DC and Transient Response Slide 39
Inverter Step Response Ex: find step response of inverter driving load cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
2
2
0
2)
)
( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
t
V t V t
Vout(t)
Vin(t)
t0t
Vin(t) Vout(t)Cload
Idsn(t)
nMOS – “1” transfer is bad
CMOS VLSI Design4: DC and Transient Response Slide 40
Delay Definitions tpdr: rising propagation delay
– From input to rising output crossing VDD/2 (upper bound)
tpdf: falling propagation delay
– From input to falling output crossing VDD/2 (upper bound)
tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
tr: rise time
– time required for a node to charge from the 10% point to 90% ( 0.1 VDD to 0.9 VDD )
tf: fall time
– time required for a node to discharge from 90% to 10% point (0.9 VDD to 0.1 VDD )
CMOS VLSI Design4: DC and Transient Response Slide 41
Tpdr = TpHL Tcdf = TpHL
tr tf
Delay Definitions
CMOS Inverter Switching Characteristics Define:
– Falling delay tdf = delay time with output falling
– Rising delay tdr = delay time with output rising
43
Trajectory of a n-transistor operating point
a. Transistor is Cut offb. Capacitance CL is loaded with VDD
a. Applying a Vgs=VDD
b. Vout -> 0,9 to (VDD-Tth)
a. VDD-Tth -> to 0.1V
Slide 44
Fall-time equivalent circuit
Rise-time equivalent circuitThe fall-time is faster than the rise time, tf=tr/2primarily due to different carrier mobilities associated with the p and n- devices: µn = 2 µp It is true considering equally sized n and p transistors βn = 2 βp
CMOS VLSI Design
If the designer wants to have both n an p transistor with the same rise and fall time:
βn / βp = 1
This implies that channel width for the p-device must be increased to approximately two to three times of the n-device:
wp = 2 – 3 wn
4: DC and Transient Response Slide 45
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.90)
polysilicongate
Trajectory of a n-transistor operating point
CMOS VLSI Design4: DC and Transient Response Slide 46
Delay Estimation We would like to be able to easily estimate delay
– Not as accurate as simulation– But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay– C = total capacitance on output node– Use effective resistance R– So that tpd = RC
Characterize transistors by finding their effective R– Depends on average current as gate switches
CMOS VLSI Design4: DC and Transient Response Slide 47
RC Delay Models Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kCR/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
Capacitance proportional to width
Resistance inversely proportional to width
nMOS pMOS
CMOS VLSI Design4: DC and Transient Response Slide 48
Resistance of a uniform slab:– R = (l/A) = (/t) (L/W) where is the
resistivity in ohm-cm, t is the thickness in cm, L is the length, W is the width, and A is the cross-sectional area
– Using the concept of sheet resistance, R = Rs (L/W) where Rs is called the sheet resistance and given in ohms per square
• Rs = / t Gate Capacitance
- Cg = oxWL/tox = oxA/tox
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.90)
polysilicongate
RC Delay Models
CMOS VLSI Design
MOS device capacitances MOS Device capacitances
– Cgs, Cgd = gate-to-channel capacitances, which are lumped at the source and the drain regions.
– Csb, Cdb = source and drain-duiffusion capacitances to bulk (or substrate)
– Cgb = gate –to-bulk capacitance
4: DC and Transient Response Slide 49
CMOS VLSI Design4: DC and Transient Response Slide 50
1. Off region, where Vgs < Vt. There is no channel Cgs, Cgd = 0.2. Non-saturated region, where Vgs - Vt. > Vds. Cgb = 03. Saturated region, where Vgs <-Vt. < Vds. Channel is heavely inverted. The drain is pinched off causing Cgd = 0.
MOS device capacitances
CMOS VLSI Design
RC Delay Models
4: DC and Transient Response Slide 51
pMOS capacitance = 2x nMOS capacitance
CMOS VLSI Design4: DC and Transient Response Slide 52
Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a unit inverter (R).
CMOS VLSI Design4: DC and Transient Response Slide 53
Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a unit inverter (R).
CMOS VLSI Design4: DC and Transient Response Slide 54
Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a unit inverter (R).
3
3
222
3
CMOS VLSI Design4: DC and Transient Response Slide 55
3-input NAND Caps Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3
CMOS VLSI Design4: DC and Transient Response Slide 56
3-input NAND Caps
Annotate the 3-input NAND gate with gate and diffusion capacitance.
2 2 2
3
3
33C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
Resultant capacitance per gate = 2C+3C = 5C
Parallel capacitances 3x2C+3C = 9C
CMOS VLSI Design4: DC and Transient Response Slide 57
3-input NAND Caps Annotate the 3-input NAND gate with gate and
diffusion capacitance.
9C
3C
3C3
3
3
222
5C
5C
5C
CMOS VLSI Design4: DC and Transient Response Slide 58
Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder
R1 R2 R3 RN
C1 C2 C3 CN
nodes
1 1 1 2 2 1 2... ...
pd i to source ii
N N
t R C
RC R R C R R R C
CMOS VLSI Design4: DC and Transient Response Slide 59
Example: 2-input NAND Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
2
2
22
B
Ax
Y
CMOS VLSI Design4: DC and Transient Response Slide 60
Example: 2-input NAND Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
CMOS VLSI Design4: DC and Transient Response Slide 61
Example: 2-input NAND Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
Parallel capacitances 2C+2C+2C= 6C
CMOS VLSI Design4: DC and Transient Response
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
CMOS VLSI Design4: DC and Transient Response Slide 63
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CY
pdrt
CMOS VLSI Design4: DC and Transient Response Slide 64
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CY 6 4pdrt h RC
Rising time: nMOS - “off” pMOS - “on”
CMOS VLSI Design4: DC and Transient Response Slide 65
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
CMOS VLSI Design4: DC and Transient Response Slide 66
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
pdft (6+4h)C2CR/2
R/2x Y
Consider that the nMOS resistance = (pMOS resistance)/2 = R/2
CMOS VLSI Design4: DC and Transient Response Slide 67
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
2 2 22 6 4
7 4
R R Rpdft C h C
h RC
(6+4h)C2CR/2
R/2x Y
CMOS VLSI Design4: DC and Transient Response Slide 68
Delay Components Delay has two parts
– Parasitic delay• 6 or 7 RC• Independent of load
– Effort delay• 4h RC• Proportional to load capacitance
CMOS VLSI Design4: DC and Transient Response Slide 69
Contamination Delay Best-case (contamination) delay can be substantially
less than propagation delay. Ex: If both inputs fall simultaneously
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CYR
3 2cdrt h RC
CMOS VLSI Design4: DC and Transient Response Slide 70
7C
3C
3C3
3
3
222
3C
2C2C
3C3C
IsolatedContactedDiffusionMerged
UncontactedDiffusion
SharedContactedDiffusion
Diffusion Capacitance we assumed contacted diffusion on every source/drain Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C– Merged uncontacted diffusion might help too
Capacitance = 2C+2C+3C = 7C
CMOS VLSI Design4: DC and Transient Response Slide 71
Layout Comparison Which layout is better?
AVDD
GND
B
Y
AVDD
GND
B
Y