Introduction to DSP with the ARM Cortex-M4 Microcontroller - Feb 2012.pdf

7/25/2019 Introduction to DSP with the ARM Cortex-M4 Microcontroller - Feb 2012.pdf

1/26

TM

- -

, , , , , , , ,

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. 2011 Freescale Semiconductor, Inc.


2/26

Cortex-A

servers netbooks mobile applicationsset top boxes

Cortex-Rdisk drives digital cameras mobile baseband

Cortex-M

appliances motors audio

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore

and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet,Flexis, Kinetis, MXC, Platform in a

Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks ofFreescale Semiconductor, Inc.

All other product or service names are the property of their respective owners. 2011 Freescale Semiconductor, Inc.

2


3/26

Cortex-M4Ease of useC Programming

Harvard architectureSingle cycle MAC

Interrupt handlingUltra low power

Barrel shifter

TM





3


4/26

ARMv7ME Architecture - , .

Integrated NVIC and optional MPU

Low cost debug and trace

Single cycle MAC (Up to 32 x 32 + 64 -> 64)

Optional single precision FPU

Microarchitecture

3-stage pipeline x - e us n er aces

Configurable for ultra low power eep eep o e, a eup n errup on ro er

Power down features for Floating Point Unit

Configurable NVIC and Debug & Trace. Optional MPU,WIC and FPU.

TM





4


5/26

TM





5


6/26

Cyclecounts

CLASS INSTRUCTION ARM9E

S CORTEX

M3 Cortex

M4Arithmetic ALUoperation(notPC) 1 2 1 1

ALUo erationtoPC 3 4 3 3

CLZ 1 1 1

QADD,QDADD,QSUB,QDSUB 1 2 n/a 1

QADD8,QADD16,QSUB8,QSUB16 n/a n/a 1

QDADD,QDSUB n/a n/a 1

, , ,

SHASX,

SHSAX,

UHASX,

UHSAX n/a n/a 1SADD8,SADD16,SSUB8,SSUB16 n/a n/a 1

SHADD8,SHADD16,SHSUB8,SHSUB16 n/a n/a 1

UQADD8,UQADD16,UQSUB8,UQSUB16 n/a n/a 1

, , , n a n a

UADD8,UADD16,USUB8,USUB16 n/a n/a 1

UQASX,UQSAX,USAX,UASX n/a n/a 1

UXTAB,UXTAB16,UXTAH n/a n/a 1

USAD8,USADA8 n/a n/a 1

Multiplication MUL,MLA 2 3 1 2 1

MULS,MLAS 4 1 2 1

SMULL,UMULL,SMLAL,UMLAL 3 4 5 7 1

SMULBB,SMULBT,SMULTB,SMULTT 1 2 n/a 1

SMLABB,SMLBT,SMLATB,SMLATT 1 2 n/a 1

SMULWB,SMULWT,SMLAWB,SMLAWT 1 2 n/a 1

SMLALBB,

SMLALBT,

SMLALTB,

SMLALTT 2

3 n/a 1SMLAD,SMLADX,SMLALD,SMLALDX n/a n/a 1

SMLSD,SMLSDX n/a n/a 1

ng e

cycleMAC

,

SMMLA,SMMLAR,SMMLS,SMMLSR n/a n/a 1

SMMUL,SMMULR n/a n/a 1

SMUAD,SMUADX,SMUSD,SMUSDX n/a n/a 1

UMAAL n/a n/a 1

TM





6

v s on , n a


7/26

OPERATION INSTRUCTIONS , , ,

16x16+32=32 SMLABB,SMLABT,SMLATB,SMLATT

16x16+64=64 SMLALBB,SMLALBT,SMLALTB,SMLALTT

16x32=32 SMULWB,SMULWT

(16

x

32)

+

32

=

32 SMLAWB,

SMLAWT(16x16) (16x16)=32 SMUAD,SMUADX,SMUSD,SMUSDX

(16x16) (16x16)+32=32 SMLAD,SMLADX,SMLSD,SMLSDX

x x + = , , ,

32x32=32 MUL

32 32x32 =32 MLA MLS

32x32=64 SMULL,UMULL

(32x32)+64=64 SMLAL,UMLAL

(32x32)+32+32=64 UMAAL

32

(32

x

32)

=

32

(upper) SMMLA,

SMMLAR,

SMMLS,

SMMLSR(32x32)=32(upper) SMMUL,SMMULR

All the above operations are single cycle on the Cortex-M4 processor

TM





7


8/26

Sin le recision floatin oint unit

IEEE 754 standard compliant

-Add, subtract, multiply, divide, MAC and square root

use g er prec s on

OPERATION CYCLE

COUNT

Add/Subtract 1

Divide 14

Multi l 1

Multiply

Accumulate

(MAC) 3FusedMAC 3

S uareRoot 14

TM





8


9/26

Sum = Sum + A x C + B x D

32-bit 32-bit

64-bit64-bit

SIMD techniques operate with packed data

TM





9


10/26

S Q SH U UQ UHPrefixSigned Signed

Saturating

Signed

Halving

Unsigned Unsigned

Saturating

Unsigned

HalvingInstr

SUB8 SSUB8 QSUB8 SHSUB8 USUB8 UQSUB8 UHSUB8

ADD16 SADD16 QADD16 SHADD16 UADD16 UQADD16 UHADD16

SUB16 SSUB16 QSUB16 SHSUB16 USUB16 UQSUB16 UHSUB16

ASX SASX QASX SHASX UASX UQASX UHASX

SAX SSAX QSAX SHSAX USAX UQSAX UHSAX

USAD8 UnsignedSumofAbsoluteDifference(8bits)

USADA8 Uns gne Sumo A so uteD erencean Accumu ate 8 ts

ASX1. Exchanges halfwords of the second operand register

SAX1. Exchanges halfwords of the second operand register

. .

TM





10


11/26

Harvard architecture

High performance MAC

Saturatin math

SIMD instructions for parallel computation

Floating point hardware

rcu ar an -reverse a ress ng

Zero overhead loops

Load and store operations in parallel with math operations

Text in bold indicates DSP processor advantage over Cortex-M4

TM





11


12/26

Circular addressing alternatives

Loop unrolling

Caching of intermediate variables

Extensive use of SIMD and intrinsics

TM





12


13/26

DSP assembly code = 1 cycle

Cortex-M4 standard C code takes 12 cycles

Using circular addressing alternative = 8 cycles

er oop unro ng < cyc es

After using SIMD instructions < 2.5 cycles [note: 16-bit data]

After caching intermediate values ~ 1.6 cycles

Cortex-M4 C code now comparable in performance

TM





13


14/26

(CMSIS)(CMSIS)

Cortex Microcontroller Software Interface Standard

Abstraction layer for all Cortex-M processor based devices

Developed in conjunction with silicon, tools and middleware

partners

ene s o e em e e eve oper

Consistent software interfaces for silicon and middleware vendors

Simplifies re-use across Cortex-M processor-based devices

Reduces software development cost and time-to-market

Reduces learning curve for new Cortex microcontroller developers

TM





14


15/26

Basic math vector mathematics Fast math sin, cos, sqrt, etc.

Interpolation linear, bilinear

Complex math

Statistics max, min, RMS, etc.

Filtering IIR, FIR, LMS, etc.

, , .

Matrix functions

,

Support functions copy/fill arrays, data type conversions, etc

Available at http://www.onARM.com

Variants for functions across q7,q15,q31 and f32 data types

TM





15


16/26

General Purpose MCUsMCU1

MCU2

Discrete DSPsDSP1

DSP2

Cortex-M4 estimated

0 5 10 15 20 25 30

DSP2

MHz required for MP3 decode, smaller is better

TM





16


17/26

Audio Input:

Kinetis

SDIOor

USBFlash

MP3 files

emory

CodecAnalog

Outputs

File decode

Output: * Could also use K40, K50, K60, or K70





17TM


18/26

TM

- -, , , , , , , ,he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. 2011 Freescale Semiconductor, Inc.


19/26

Backwards compatible with ARM Cortex-M3 New features

DSP extensions

Single precision floating point unit

Available on-chip cache for instructions and dataenhanced performance reaching zero wait states

Crossbar switch for concurrent multi-master/slaveaccessing improves system throughput

MPU with multi-master protection enhances systemsafety and security

- - -power operation

Architected for digital signal processing

Motor Control advanced al orithms lon er

Dotted boxes denote optional blocks

lifespan, power efficiency

Automation high calculation and algorithmbandwidth at a low cost

ower anagemen es gne or ow a ery-powered systems

Audio and Video 5x performance improvementover software, helping batteries last longer

http://www.freescale.com/kinetis

TM





19


20/26

32-bit CPU for

application andconnectivity control

USBconnectivity

Display controller foruser interface

K30, K40: Segment LCDK70: Gra hics QVGA/SVGA

Ethernet for network

connectivity(K60, K70)

32-chDMA

DisplayController

Up to 150MHzARM Cortex-M4 Core

DSP & FPU*1.25DMIPs/MHz

Clock Module:

NANDFlash SDIO

EthernetMAC

HS* + FSUSB

H/D/OTG

SDIO for memorycards and wireless

connectivity

CrossBar Switch (XBS)

Controller

Memory Protection Unit

DSP unit foraudio

processingNAND flash controller

for large media file

Up to 1M FlashMemory

FlexBus

Peripheral Bus Controllers (x2)

DRAMController

Crossbar switch for

s orage

Up to 128KBSRAM

AnalogTimersunications

cluding

to2x*I2S

Crypto

Tamper Detect

Touch Sense

-data movement

up to 16KB EEPROM

or 512KBFlashComI

up Interface

GPIO

protection

I2S modules to interfaceto audio codecs

for low system cost and

power consumption

Touch sense foruser interface

TM





20

NOTE Fl ti i t it d NAND fl h t l l l


21/26

tect

ly)

erly)

tect

NOTE: Floating point unit and NAND flash control ler are onlyoffered on 120/150MHz K10/20/60/70 devices.

Controller

APBG

Aonly)

areTamperD

AN

areE

ncryption

et(IE

EE1588

ngPo

intUnit

Hz/150MHzo

FlashControll

Hz/150MHzo

ent/G

raphics)

TG(

FS&H

S

iceChargerDe

144pin now , 80-121pin now,


22/26

Freescale MQX RTOSFreescale Tower System Freescale CodeWarrior IDE

Connectivity

.

reesca e

RTOS &Middleware

BPS &

USB FileSystem

Modular, expandable, open-source

h/ware development platform for

Eclipse environment

Includes Processor Expert

Full-featured, scalable, proven RTOS

with TCP/IP, USB, Graphics, Security

Drivers

- s s Rapid evaluation and prototyping

with maximum h/ware reuse Supported by a growing range of

co e genera on w zar Creates MQX-aware drivers Build, debug and flash tools Software analysis

an e ys ems p ug- ns Makes application code more stable,

more maintainable and easier toupgrade reduces time-to-market!

peripheral plug-in boards (WiFi,

Sensing, Graphics LCD, Audio,...) www.freescale.com/tower

Kernel-aware debug

Special Edition $0 up to 128KB www.freescale.com/codewarrior

Compatible with CodeWarrior, IAR,

Keil & Green Hills IDEs www.freescale.com/mqx

un e or,

hardware platform

generation wizard for $0!

One-stop-shop for silicon, IDE & RTOSOne Stop Shop for Silicon, IDE & RTOS

TM


and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a



22


23/26

www. reesca e.com owerwww. reesca e.com ower www. owergee s orgwww. owergee s org

MCU Families PriceSupported

(SRP)

K30/40

TWR-K40X256 TWR-K40X256 (144MGA), TWRPI-SLCD $69

TWR-K40X256 144MBGA , TWRPI-SLCD- -

TWR-SER, TWR-ELEV

K50

TWR-K53N512 TWR-K53N512 (144MBGA), TWRPI-SLCD $109

TWR-K53N512 144MBGA TWRPI-SLCD- -

TWR-SER, TWR-ELEV

TWR-K60N512 TWR-K60N512 (144MBGA) $69

TWR-K60N512 144MBGA TWR-SER

TWR-SENSOR-

PAK

K10/20/60

- -TWR-ELEV

TWR-K60N512-IAR TWR-K60N512-KIT (144MBGA),TWR-PROTO, Segger J-Link Lite Debug $239

ro e, eva . vers on

TWR-K60N512-KEIL TWR-K60N512-KIT (144MBGA),UNLINK-ME Debug Probe,

KEIL MDK IDE eval. version$199

TWR-LCD

IDEs: FSL CodeWarrior, IAR Embedded Workbench, Keil MDK, ... Freescale MQX RTOS

TM


and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a



23

e ug c rcu ry program e ug w ca e Low power touch sensing & plug-in socket for expansion: Sensors, Radio, etc Fully compatible with all Tower peripheral modules

TWR-WIFI-RS2101


24/26

S/W MP3 decoding and playback under MQX with touch screen LCD using Kinetis K60 MCU

Decompression Task

State Machine

TM





24


25/26

Main features: basic control features (play, stop, pause, play next, play previous) as c song n orma on sp ay e, ar s , a um, year, name o e plotting of both channels samples in a time domain display of actual time and current position of song current osition chan e ossible usin slide bar movin

volume and balance control

Spectrum Analyser: w u u ~ z - z v usub-bands display 16 frequency sub-band lines with 10 pixel resolution

spectrum analyser is based on sub-bands data hidden in every mp3frame each of sub-band line includes average value of both channels in aspecific frequency band

Other: equalizer setting select from playlist

TM





25


26/26

TM

Documents

Introduction to DSP with the ARM Cortex-M4 Microcontroller - Feb 2012.pdf