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Introduction to VLSI Circuits and Systems, NCUT 2007
Chapter 07Electronic Analysis of CMOS Logic
Gates
Introduction to VLSI Circuits and Systems積體電路概論
賴秉樑Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
The Inverter Circuit
The CMOS inverter gives the basic for calculating the electrical characteristic of logic gates
» The conduction states of Mn and Mp is determined by input voltage Vin
» Two types of calculations: DC analysis and transient analysis
DC analysis» Provide a direct mapping of the input to the output, su
ch that to determine Vout
Transient analysis» The input voltage is an explicit function of time Vin(t)
corresponding to a changing logic value
Figure 7.1 The CMOS inverter circuit
Introduction to VLSI Circuits and Systems, NCUT 2007
DC Analysis of Inverter
The DC characteristics of the inverter are portrayed in the voltage transfer characteristic (VTC), which is a plot of Vout as a function of Vin
» Simply, the output high voltage of the circuits as
» The output low voltage
» The logic swing at the output is
Since this is equal to the full value of the power supply, this is called a full-rail output
DDOH VV
VVOL 0
DDOLOHL VVVV
Figure 7.2 VOH and VOL for the inverter
(a) Low input voltage
(b) High input voltage
(7.1)
(7.2)
(7.3) (full-rail output)
(Vin = 0)
(Vin = VDD)
Introduction to VLSI Circuits and Systems, NCUT 2007
VTC of the Inverter
Starting with an input voltage of Vin = 0V and then increasing it up to a value of Vin = VDD
» Mp goes into cutoff when
» The logic 0 and 1 voltage ranges are defined by the changing slope of the VTC
A logic 0 input voltage (input low voltage)
A logic 1 input voltage (input high voltage)
» The voltage noise margins give a quantitative measure of how stable the inputs are with respect to coupled electromagnetic signal interface, there are
inGSn VV
inDDSGp VVV
TpDDin VVV
ILin VV 0
DDinIH VVV
IHOHH VVVNM
OLILL VVVNM (7.8)
(7.4)
(7.5)
(7.6)
(7.7)
Figure 7.3 Voltage transfer curve for the NOT
gate
Introduction to VLSI Circuits and Systems, NCUT 2007
Definition of Noise Margins
"1"
"0"
VOH
VIH
VIL
VOL
UndefinedRegion
"1"
"0"
VOH
VIH
VIL
VOL
UndefinedRegion
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
Noise Margin High
Noise Margin Low
IHOHH VVVNM
OLILL VVVNM (7.8)
V(x)
V(y)
VOH
VOL
VIHV
IL
Slope = -1
Slope = -1
Introduction to VLSI Circuits and Systems, NCUT 2007
Midpoint Voltage VM
Figure 7.4 Inverter voltage for VM calculation
DpDn II
TnMTnGSnsat VVVVV
TnMsatDSn VVVV
22 )(2
)(2 TpMDD
pTnM
n VVVVV
p
n
Tnp
nTpDD
M
VVV
V
1
pp
nn
p
n
L
WL
W
'
'
32'
'to
p
n
p
n
p
n
'
'
DDM VV2
1
2
2
12
1
TnDD
TpDD
p
n
VV
VV
pn
(7.9)
(7.10)
(7.11)
(7.12)
(7.13)
(7.14)
(7.15)
(7.16)
(7.17)
(7.18)
(7.19)
(7.20)
(Let Vin = Vout = VM)
TpMDDTnMp
n VVVVV )(
Symmetrical inverter principle
Introduction to VLSI Circuits and Systems, NCUT 2007
VTC Variation
Figure 7.5 Comparison of the layouts
Figure 7.6 Dependence of VM on the device ratio
(a) Large pFET design (b) Equal aspect ratios
In Figure 7.5(a), the pFET has a width of about Wp≒2Wn
» VM = (VDD/2)
In Figure 7.5(b), the pFET has a width of about Wp≒Wn
» VM < (VDD/2)
At the physical level, the relative device sizes contained in the ratio (βn/βp) determine the switching points
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
Switching Characteristic
High-speed digital system design requires that logic gates introduce a minimum amount of time delay when the inputs change
» The output 1-to-0 transition introduces a fall time delay of tf
» The output 0-to-1 transition introduces a rise time delay of tr
The rise time and fall time can be calculated by analyzing the electronic transitions of the circuits
» parasitic resistance» parasitic capacitances of the transistors
Figure 7.7 General switching waveforms
Introduction to VLSI Circuits and Systems, NCUT 2007
RC Model of Inverter
Both FETs can be replaced by their switch equivalents, which results in the simplified RC model
» Given the aspect ratios and
» Finding the capacitance CDn and CDp at the output node
It is significant that increasing the channel width of a FET increases the parasitic capacitance values
nL
W
pL
W
)(
1
TnDDnn VV
R
)(
1
TpDDp
pVV
R
(7.28)
njswnnjnoxDBnGSnDn PCACWLCCCCn
'2
1
pjswpppjpoxDBpGSpDp PCACWLCCCCp
'2
1 (7.29)
Figure 7.8 RC switch model equivalent for the CMOS
inverter
(a) FET circuit
(b) RC switch model equivalent
Introduction to VLSI Circuits and Systems, NCUT 2007
Fan-out (FO)
The fan-out gates act as a load to the driving circuit because of their input capacitance Cin
» Therefore, the total input capacitance is (Figure 7.9(a))
» In Figure 7.9(b), the external load capacitance CL is
In Figure 7.10 where the total output capacitance is defined as
GnGpin CCC
inL CC 3
LFETout CCC
DpDnFET CCC
Figure 7.9 Input capacitance and load effects
Figure 7.10 Evolution of the inverter switching model
(a) Single stage(b) Loading due to fan-
out
(a) External load (b) Complete switch model
(7.30)
(7.31)
(7.32)
(7.33)
Introduction to VLSI Circuits and Systems, NCUT 2007
Fall Time Calculation
9ln
9.0ln
1.0ln
n
DD
DDn
DD
DDn
xyf
V
V
V
V
ttt
Initially, Vout(0) = VDD, and Vin = 0 V and is switched to Vin = VDD at time t = 0; we time shift this event to occur at t = 0
» The current leaving the capacitor is
» The differential equation for the discharge events
(7.42)
outnn
t
DDout CRwhereeVtV n
,)(
n
outoutout R
V
dt
dVCi
(7.43, 44)
out
DDn V
Vt ln
nft 2.2 )( fHL tt
(7.45)
(7.46)
(7.48, 49)
Figure 7.12 Discharge circuit for the fall time
calculation
(a) Discharge circuit
(b) Output waveform
Introduction to VLSI Circuits and Systems, NCUT 2007
The Rise Time
Initially, Vout(0) = 0 V, and Vin = VDD and is switched to Vin = 0 V at t = 0; we time shift this event to occur at t = 0
» The charge current is given by
» The differential equation for the charge events
fmax is the largest frequency that can be applied to the gate and still allow the output to settle to a definable state
p
outDDoutout R
VV
dt
dVCi
outpp
t
DDout CRwhereeVtV p
,1)(
uvr ttt
pprt 2.29ln
frLHHL ttttf
11
max
(7.50)
(7.51, 52)
(7.53)
(7.54)
(7.55)
Figure 7.13 Rise time calculation
(a) Charge circuit
(b) Output waveform
Introduction to VLSI Circuits and Systems, NCUT 2007
Propagation Delay (1/2)
The propagation delay time tp is often used to estimate the “reaction” delay time from input to output
» tpf is the output fall time from the maximum level to the “50%” voltage line, i.e., from VDD to (VDD/2)
» tpr is the propagation rise time from 0 V to (VDD/2)
Commonly used in basic logic simulation programs because does not provide detailed information on the rise and fall times as individual quantities
2
prpfp
ttt
npft 2ln
pprt 2ln
(7.64)
(7.65)
(7.65)
(7.66)Figure 7.14 Propagation time
definitions
pnpt 35.0
Introduction to VLSI Circuits and Systems, NCUT 2007
Propagation Delay (2/2)
Figure 7.15 General behavior of the rise and
fall time
LFETout CCC
FETprr CRtt 2.20
FETnff CRtt 2.20
)(
2.22.2
TpDDp
ppVV
R
)(
2.22.2
TnDDnnn VV
R
ppp L
W
'
nnn L
W
'
(7.67)
)(2.2 LFETpr CCRt
)(2.2 LFETnf CCRt (7.68)
(7.69)Lprr Ctt 0
Lnff Ctt 0
(7.70)
(7.71)
(7.72)
(7.73)
The rise and fall time equations provide the basic for high-speed CMOS design
Case I: When CL = 0,
Case II: When CL ≠ 0,
Introduction to VLSI Circuits and Systems, NCUT 2007
Delay Definitions
tpHL tpLH
t
t
Vin
Vout
50%
50%
tr
10%
90%
tf
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
Power Dissipation (1/2)
The current IDD flowing from the power supply to ground gives a dissipated power of
» Since VDD is assumed to be a constant
» DC contribution
Leakage current is very small, therefore, the value of PDC is thus quite small
» However, leakage power on today is critical for low-power Design
(7.85)
(7.86)Where PDC is the DC term and Pdyn is due to dynamic switching events
DDDDIVP
dynDC PPP
DDQDDDC IVP (7.87)
Where IDDQ is leakage current
Figure 7.17 DC current flow
Figure 7.16 Origin of power dissipation calculation
(a) VTC (b) DC current
Introduction to VLSI Circuits and Systems, NCUT 2007
Power Dissipation (2/2)
Dynamic power dissipation Pdyn
» Pdyn arises from the observation that a complete cycle effectively creates a path for current to flow from the power supply to ground
» The average power dissipation over a single cycle with a period T is
Tf
1
DDoute VCQ
T
QVIVP e
DDDDDDav
fVCIVP DDoutDDQDD2
Figure 7.18 Circuit for finding the transient power
dissipation
(a) Input voltage
(b) Charge (c) Discharge
(7.88)
(7.89)
(7.90)
(7.91)
(7.92)
DC termdynamic power term
fVCP DDoutsw2
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Analysis (1/2)
Figure 7.22 Simplification of the series-connected nFETs
(a) Separate transistors(b) Single equivalent FET
Figure 7.21 Layout of NAND2 for VM calculation
Figure 7.19 NAND2 logic circuit
Figure 7.20 NAND 2 VTC analysis
(a) Transition table (b) VTC family
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Analysis (2/2)
Find VM for the case of simultaneous switching, where the nFET and pFET transconductance are (βn/2) and 2βp
Figure 7.23 Simplification of the series-connected nFETs
(a) Separate transistors(b) Single equivalent FET
Figure 7.24 Simplified VM circuit for the NAND2 gate
22
2
2
2
2/TpMDD
pTnM
n VVVVV
p
n
Tnp
nTpDD
M
VVV
V
2
11
2
1
p
n
Tnp
nTpDD
M
N
VN
VV
V
11
1
(7.93)
(7.94)
(7.95)
Introduction to VLSI Circuits and Systems, NCUT 2007
NOR Analysis
Figure 7.27 NOR23 VM calculationFigure 7.25 NOR2 circuit
Figure 7.26 NOR 2 VTC analysis
(a) Transition table (b) VTC family
22
2
2/
2
2TpMDD
pTnM
n VVVVV
p
n
Tnp
nTpDD
M
VVV
V
21
2
p
n
Tnp
nTpDD
M
N
VNVV
V
1
DDQDDDC IVP
gateDDoutsw fVCP 2
(7.96)
(7.97)
(7.98)
(7.99)
(7.100)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Switching Times (1/2)
Figure 7.28
Figure 7.29 (a)
Figure 7.28 NAND2 circuit for transient calculations
LFETout CCC
]1[)( / ptDDout eVtV
outpp CRwhere
prt 2.2
Lr Ctt 00
FETpCRt 2.20
pR2.20 Figure 7.29 NAND2 subcircuits for
estimating rise and fall times
(a) Charge circuit
(b) Discharge circuit
(7. 101)
(7. 102)
(7. 104)
(7. 105)
(7. 106)
(7. 107)
(7. 103)
(7. 108)
(7. 109)
DpDnFET CCC 2
TnDDnn
TpDDp
P VVR
VVR
1
,(
1
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND Switching Times (2/2)
(b) Discharge circuit
ntDDout eVtV /)(
nXnnoutn RCRRC )(
21 nnn
)(1 nnoutn RRCwhere
nXn RC2
nft 2.2
])2)([(2.2 nXnLFETf RCRCCt
Lf Ctt 11
)2(2.21 XFETn CCRt
nR4.41
)2( Xoutnn CCR
Xouteff CCC 2
nXnoutn RCRC )2(
(7. 110)
(7. 111)
(7. 112)
(7. 113)
(7. 114)
(7. 115)
(7. 116)
(7. 117)
(7. 118)
(7. 119)
(7. 120 from 7.111)
(7. 122)
(7. 121)
Introduction to VLSI Circuits and Systems, NCUT 2007
NOR Switching Times (1/2)
Figure 7.30 NOR2 circuit for switch time calculations
Figure 7.31 Subcircuits for the NOR2 transient calculations
(a) Discharge circuit
(b) Charge circuit
LFETout CCC
DpDnFET CCC 2
ntDDout eVtV /)(
outnn CR
nft 2.2
Lf Ctt 11
FETnCRt 2.21
nR2.21
Figure 7.30
Figure 7.31 (a)
(7. 123)
(7. 125)
(7. 126)
(7. 127)
(7. 128)
(7. 129)
(7. 130)
(7. 124)
Introduction to VLSI Circuits and Systems, NCUT 2007
NOR Switching Times (2/2)
Figure 7.31 (b)
]1[)( / ptDDout eVtV
)(1 ppout RRC
py RC2
pypout
p
RCRC
)2(
21
prt 2.2
Lr Ctt 00
)2(2.20 yFETp CCRtwhere
pR4.40
(b) Charge circuit
(7. 131)
(7. 133)
(7. 134)
(7. 135)
(7. 136)
(7. 137)
(7. 138)
(7. 132)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
Analysis of Complex Logic Gates
Figure 7.32 Complex logic gate circuit
)( zyxf
nznynx L
W
L
W
L
W
LFETout CCC
outnnnn CRCR 2
L
LFETnn
nf
Ct
CCCR
t
11
)](2[2.2
2.2
)2(2.21 FETnn CCRtwhere
nR2.21
pzpypx L
W
L
W
L
W
outpppp CRCR 2
Lr Ctt 00
)2(2.20 FETpp CCRt
pR2.20
(7. 141)
(7. 142)
(7. 143)
(7. 144)
(7. 145)
(7. 149)
(7. 150)
(7. 146)
(7. 147)
(7. 148)
(7. 151)
(7. 152)
Introduction to VLSI Circuits and Systems, NCUT 2007
Power Dissipation
Power dissipation in a simple inverter
We introduce the activity coefficient a that represents the probability that an output 0 1 transition takes place during one period
Figure 7.33 Truth tables for determining activity
coefficients
fVCIVP DDoutDDQDD2
fVaCP DDoutdyn2
N
iDDiiidyn fVVCaP
1
10 ppa
16
3
4
1
4
32
NORa
16
3
4
1
4
32
NANDa
33 64
7NANDNOR aa
22 4
1XORXNOR aa
(7. 154)
(7. 155)
(7. 156)
(7. 158)
(7. 159)
(7. 160)
(7. 153)
(7. 157)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
Gate Design for Transient Performance (1/2)
Figure 7.34 Relative FET sizing
(a) Inverter
(b) NAND2 (c) NOR2
L
Wk '
)(
1,
)(
1
TnDDnn
TpDDp
p VVR
VVR
pn
np L
Wr
L
W
'
'
p
n
k
krwhere
pP
Nn RRR 2
)(
2
)(
1
TnDDNTnDDn VVVV
nN 2
nN L
W
L
W
2
nN
)(
2
)(
1
TpDDPTpDDp VVVV
pP 2
pP L
W
L
W
2
(Inverter reference starting)
(NAND2 vs Inverter)
NN RRR
)(
1
TnDDNN VV
Rwhere
(NOR2 vs Inverter)
Introduction to VLSI Circuits and Systems, NCUT 2007
Gate Design for Transient Performance (2/2)
Figure 7.35 Sizing for 3-input gates
(a) NAND3 (b) NOR3
Extend to large chains as Figure 7.35
Figure 7.36
pPnN ,3
pPnN L
W
L
W
L
W
L
W
,3
pPnN 3,
pPnN L
W
L
W
L
W
L
W
3,
Figure 7.36 Sizing of a complex logic gate
xdcbaf )(
13 NnN
pP 2
pP 1
PPP 21
(7. 177)
(7. 178)
(7. 179)
(7. 180)
(7. 181)
(7. 182)
(7. 183)
(7. 184)
(7. 185)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
DC Characteristic of the CMOS Inverter Inverter Switching Characteristic Power Dissipation DC Characteristic: NAND and NOR Gates NAND and NOR Transient Response Analysis of Complex Logic Gates Gate Design for Transient Performance Transmission Gates and Pass Transistors
Introduction to VLSI Circuits and Systems, NCUT 2007
Transmission Gates
Large ratio of (W/L) decrease the resistance, but a large W implies large capacitances
Figure 7.37 Transmission gate modeling
(a) Circuit
(b) RC model
),max( pnTG RRR
pDnSin CCC ,,
(7. 186)
(7. 187)
Introduction to VLSI Circuits and Systems, NCUT 2007
Pass Transistor
Pass FETs can be used in place of transmission gates in most circuits
» Less area and wiring, but cannot pass the entire voltage range
Figure 7.38 nFET pass transistor
Figure 7.39 Voltage waveforms for a nFET pass transistor
n
nout t
tVtV
2/1
2/)( max
TnDD VVVwhere max
max)(lim VtVoutt
nrt 18
)/(
)/(
max1
2)(
n
n
t
t
oute
eVtV
0)(lim
tVoutt
nnft 94.2)19ln( (7. 188)
(7. 189)
(7. 190)
(7. 191)
(7. 193)
(7. 194)
(7. 195)
(7. 196)
(7. 197)
(7. 192)
(7. 198)
fr tt 6
prt 94.2
outpp CRwhere
TpVV min
pft 18
outnn CR
(7. 199)
(7. 200)