Embed Size (px)
Citation preview
Inverter Domino Chain
Analog input
Analog output
Readout Shift RegisterClock 40MHz
Speed Control (V) 2 – 4 GHz
SRIN SRCLK
Domino Wave
Rotating sampling wave
Impulse
1024 cells
SRCLK SRRES
SROUT
Synchr
Domino Wave
Domino Ring Sampler (DRS)
DRS2 Mezzanine
DRS2
PLL CLK
TRIGGER
PULSAR CONNECTOR
RECEIVER BOARD CONNECTOR
POWER SUPPLY
40 MHz ADC (AD9235 12 – bit)
SERIAL P.I.
ADC/DAC
Input Stage High BW
Differential Amplifier
T SENSOR
2 PLLs (in BOTTOM side)
SINGLE ENDED
DIFFERENTIAL
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
BUSY
PULSAR
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
D I G I TAL
PULSAR
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
CPUVME
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
1 5 6
VME CRATE 1
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
0
M E Z
Z
M E Z
Z
M E Z
Z
M E Z
Z
S V T I N
S V T O U T
L 1 I N
L 1 O U T
ANALOG
PULSAR
127
VME CRATE 2
TRIGGER DISTRIBUTION BOARD TRIGGER DISTRIBUTION BOARD
CLOCK DISTRIBUTION BOARDCLOCK DISTRIBUTION BOARD
RECEIVER BOARDS: 1039 CAMERA SIGNALS
0 1 10 11 25 26 5251
From TRIGGER SYSTEM
1
25
24
2
51
52
ABORTBUSY
DIGITAL DATA DIGITAL DATA DIGITAL DATABUSY
ABORT
2 DRS2 cards
DATA BLOCK
DATA
DATA
SUPER SEQUENCER
SE_WORD EE_WORD
TRIGGER
32
DATAEN
WRENDATA
CEN
DRS
CONTROL
SRAM CONTROL
FPGA
LFFUWE32
UDATA
P3
HOLA
ADCx2
Mezzanines
HardwareFILAR
PC
CLK40MHz
CLK40MHz
SRRES
SRCLK
SRIN
ADCx2
RAM
DATA BLOCK
DATA
DATA
SUPER SEQUENCER
SRAM CONTROLLER
DATA
CH_WORD
32
ADDR
17
DRS
CONTROL
CTRL SIGNALS
SRAM CONTROL
FPGA
ANALOG DATAIO FPGA
LFFUWE
32
UDATA
VME
SIGNALS
LFFUWE32
UDATA
P3
HOLA
ADCx2
Mezzanines
HardwareFILAR
PC
CLK40MHz
CLK40MHz
CLK40MHz
CLK40MHz
ADCx2
RAM
VME
INTERFACE
VME SIGNALS
24
24
ST_DRS CH_ADDSRCKEN ADCCKENST_RD
4
HOLA
FILAR
SVT IN
HOLD
TRIG CELL-TRIG NUMB
SVT IN CABLE
BUSY
SstartSend
Sstart
Send
PULSer And RecorderPULSer And Recorder
ANALOG PULSARRead-Out System, Data Format
Trigger Cell and Trigger Number propagation via SVT cable
Region-of-Interest: 100 samples
DRS Mezzanine
DIGITAL PULSAR
DRS Mezzanine
Trigger Number, Digital Data
Trigger Cell
Read-out system of Read-out system of 1200 channels1200 channels: : 1 Digital + 15 Analog PULSARs1 Digital + 15 Analog PULSARs
1024 samples/ch1024 samples/ch ~2,4 GBytes/s~2,4 GBytes/s @ 1 kHz max @ 1 kHz max4 h Acquisition Time ~34 TBytes4 h Acquisition Time ~34 TBytes
With Region of Interest (RoI):With Region of Interest (RoI):100 samples/ch100 samples/ch 240 MBytes/s240 MBytes/s @ 1 kHz max@ 1 kHz max4 h Acquisition Time4 h Acquisition Time ~~3,4 TBytes3,4 TBytes
100 cells wide
fc = 2.5 GHz
1 Domino cell = 0.4 ns
250 cells wide
Latency
Trigger
RoI
Data Acquisition SystemData Acquisition System
Daisy- chained
distribution of trigger
number and trigger cell
Consistence Tests and verify
