Investigation of Alternative Power Architectures for CPU ... · Investigation of Alternative Power Architectures for CPU Voltage Regulators Julu Sun Dissertation submitted to the

Investigation of Alternative Power Architectures for CPU

Voltage Regulators

Julu Sun

Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy in

Electrical Engineering

Fred C. Lee, Chairman Dusan Boroyevich

Ming Xu William T. Baumann Carlos T.A. Suchicital

Elaine P. Scott

November 22nd, 2008 Blacksburg, Virginia

Keywords: two-stage, voltage regulator, high power density, high efficiency

Investigation of Alternative Power Architectures for CPU

Voltage Regulators

Abstract

Since future microprocessors will have higher current in accordance with Moore’s law,

there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only

for easy thermal management, but also for saving on electricity costs for data centers, or battery

life extension for laptop computers. At the same time, high power density is required due to the

increased power of the microprocessors. This is especially true for data centers, since more

microprocessors are required within a given space (per rack). High power density is also required

for laptop computers to reduce the size and the weight.

To improve power density, a high frequency is required to shrink the size of the output

inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the

output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz.

Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to

ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high

switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power

density is very low.

To attain high efficiency and high power density at the same time, two-stage power

architecture was proposed. The concept is “Divide and Conquer”. A single-stage VR is split into

two stages to get better performance. The second stage has about 5V-6V input voltage; thus the

duty cycle can be extended and the switching losses are greatly reduced compared with a single-

stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high

frequencies.

The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High

efficiency is required for the first stage since it is in series with the second stage. Previous first

stage which is a buck converter has good efficiency but bulky size due to low frequency

operation. Another problem with using a buck converter is that light-load efficiency of the first

stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since

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the first stage does not require voltage regulation, the sweet point for the voltage divider can be

determined and high efficiency can be achieved. At the same time, since there are no magnetic

components for the switched-capacitor voltage divider, high power density can be achieved. By

very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can

be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can

be as high as 99% by reducing the switching frequency at light load.

As for the second stage, different low-voltage devices are evaluated, and the best device

combinations are found for high-frequency operation. It has been demonstrated that 91%

efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a

1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-

linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage

respectively.

Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also

be applied to other systems. In this dissertation, the two-stage power architecture is applied to

two different applications: laptop computers and high-end server microprocessors. The common

characteristics of the two applications are their thermal design power (TDP) requirement. Thus

the first stage can be designed with much lower power than the maximum system power. It has

been demonstrated that the two-stage power architecture can achieve either higher efficiency or

higher power density and a lower cost when compared with the single-stage VR.

To get higher efficiency, a parallel two-stage power architecture, named sigma architecture,

is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency,

fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the

output power, while using a low-power buck converter to achieve voltage regulation. Both the

DCX converter and the buck converter can achieve around 90% efficiency when used in the

sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma

VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can

also be applied to low-power point of load (POL) applications to reduce the magnetic component

size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly

compared.

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To my family:

My parents: Songtai Sun and Xiuhua Zhao My wife: Juan Liu

My daughters: Stella Sun and Isabella Liu

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ACKNOWLEDGEMENTS

With sincere appreciation in my heart, I would like to thank my advisor, Dr. Fred C. Lee

for his guidance, encouragement, and support. There are many things I learned from him, and

one of the most important one is to “think hard before doing something” since I used to do things

without careful thought. I believe everything I’ve learned from Dr. Lee will benefit my future

career.

I am also grateful to the other five members of my advisory committee, Dr. Dushan

Boroyevich, Dr. Ming Xu, Dr. William T. Baumann, Dr. Carlos T.A. Suchicital, and Dr. Elaine

P. Scott, for their support, suggestions and encouragement.

I am especially indebted to my colleagues in the PMC group (including VRM and power

architecture sub-groups). I would like to specially thank Dr. Ming Xu, who is the VRM group

leader and also my best friend at CPES. He inspired me and helped me a lot with my research,

and I learned a tremendous amount from him. I would also like to thank two other friends: Dr.

Jinghai Zhou and Dr. Yuancheng Ren. They encouraged me during my first year of study at

CPES. Thanks also to all the other team members: Dr. Kaiwei Yao, Dr. Jia Wei, Dr. Yang Qiu,

Dr. Juanjuan Sun, Mr. Yu Meng, Dr. Shuo Wang, Dr. Kisun Lee, Dr. Bing Lu, Mr. Chuanyun

Wang, Mr. Dianbo Fu, Ms. Yan Jiang, Mr. Doug Sterk, Mr. David Reusch, Dr. Xu Yang, Dr.

Yan Xing, Dr. Yugang Yang, Dr. Ke Jin, Mr. Andrew Schmit, Mr. Authur Ball, Dr. Ching-Shan

Leu, Mr. Yan Dong, Mr. Jian Li, Mr. Bin Huang, Mr. Ya Liu, Mr. Yi Sun, Mr. Pengju Kong, Mr.

Yucheng Ying, Mr. Qiang Li, Mr. Pengjie Lai, Mr. Zijian Wang, Mr. Daocheng Huang, Mr.

Qian Li and Mr. Zheng Luo. It was a pleasure to work with such a talented and creative group. I

would also like to thank all of the other students I have met in CPES during my five-year study,

especially to Dr. Lingyin Zhao, Dr. Wenduo Liu, Dr. Qian Liu, Ms. Yan Liang, Ms. Jing Xu, Ms.

Michele Lim, Mr. Rixing Lai, Mr. Honggang Sheng, Mr. Di Zhang and Mr. Puqi Ning. It has

been a great pleasure, and I’ve had fun with them.

I would also like to thank the wonderful members of the CPES staff who were always

willing to help me out, Ms. Teresa Shaw, Ms. Linda Gallagher, Ms. Teresa Rose, Ms. Ann Craig,

Ms. Marianne Hawthorne, Ms. Elizabeth Tranter, Ms. Michelle Czamanske, Ms. Linda Long,

Mr. Steve Chen, Mr. Robert Martin, Mr. Jamie Evans, Mr. Dan Huff, and Mr. David Fuller.

Specially, I would like to thank Ms. Keara Axelrod for her editing of this dissertation.

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With much love, I would like to thank my parents, my wife and my twin daughters. My

parents pray for me every day as I am staying in a different country. My wife encourages me

every time I feel frustrated. My twin daughters have brought me a lot of fun during their first two

years.

This work was supported primarily by Analog Devices, C&D Technologies, CRANE,

Delta Electronics, HIPRO Electronics, Infineon, International Rectifier, Intersil, FSP-Group,

Linear Technology, LiteOn Tech, Primarion, NXP, Renesas, National Semiconductor, Richtek,

Texas Instruments. Also, this work made use of ERC shared facilities supported by the National

Science Foundation under Award Number EEC-9731677.

Table of Contents

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Table of Contents

Chapter 1. Introduction ...................................................................................... 1

1.1. Evolution of Microprocessors ...........................................................................................1

1.2. High Efficiency and High Power Density Requirement for Voltage Regulators .........3

1.3. Limitations of Single-Stage Multi-phase Buck Voltage Regulators for High

Efficiency and High Power Density ................................................................................16

1.4. Two-Stage Voltage Regulator Architectures – “Divide and Conquer” Concept .......20

1.5. Dissertation Outline .........................................................................................................22

Chapter 2. High Power Density Non-Isolated Bus Converters .................... 24

2.1. Background ......................................................................................................................24

2.2. Review of Previous 12V Two-Stage VR Research ........................................................26

2.2.1. Two-Stage VR for Desktop Computers .......................................................................26

2.2.2. Two-Stage VR for Laptop Computers .........................................................................28

2.3. Possible Improvement for Two-Stage VR .....................................................................30

2.4. Proposed Switched-capacitor Voltage Divider as the First Stage ...............................31

2.4.1. Basic Switched-Capacitor Circuits ..............................................................................31

2.4.2. Proposed Switched-Capacitor Voltage Divider ...........................................................34

2.4.3. Challenges for the proposed voltage divider ...............................................................37

2.4.4. Minimizing Power Losses by Circuit Analysis and Design ........................................38

2.4.5. Design of C1, C2 and C3 ...............................................................................................42

2.4.6. Light-Load Efficiency and Gate-Driving Method .......................................................45

2.4.7. Prototype ......................................................................................................................47

2.4.8. Effect of Parasitic Inductors for High Frequency Operation .......................................50

2.5. Transient Analysis of the Proposed Voltage Divider ....................................................58

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2.5.1. Output Impedance ........................................................................................................58

2.5.2. Stability of Two-Stage VR with Voltage Divider as the First Stage ...........................60

2.5.3. Interaction between VRs ..............................................................................................61

2.6. Startup and Protection of the Proposed Voltage Divider .............................................64

2.6.1. Proposed Soft-Start Method for Switched-Capacitor Voltage Divider .......................64

2.6.2. Short Circuit and Over Current Protection ..................................................................67

2.7. Other Related Topologies ................................................................................................69

2.7.1. Controllability: Achieving Output Voltage Regulation ...............................................69

2.7.2. ZVS Voltage Divider ...................................................................................................72

Chapter 3. Two-Stage Architecture with Improved Second-Stage

Efficiency 74

3.1. Low Voltage Rating Devices for Second Stage ..............................................................74

3.1.1. Introduction of New Device FOM Proposed by CPES ...............................................74

3.1.2. Efficiency Improvement by Great Wall LDMOS for Top Switch ..............................79

3.1.3. Efficiency Improvement by Ciclon Lateral-Trench MOSFET ....................................80

3.1.4. Applying Ciclon 12V Lateral-MOSFET to Top Switch using an Improved Loss

Model ...........................................................................................................................82

3.2. Proposed System Level Two-Stage VR for Laptop and Server Computers ...............87

3.2.1. New Situations for Two-stage VR ...............................................................................87

3.2.2. Proposed System Level Two-Stage Power Architecture for Laptop Computers ........87

3.2.3. Evaluation of Two-Stage VR for Laptop .....................................................................93

3.2.4. System Level Two-Stage Power Architecture for High-End Servers .........................97

3.2.5. Evaluation of Two-Stage Architecture for High-End Servers .....................................99

3.3. Light Load Efficiency Improvement ............................................................................101

Table of Contents

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3.3.1. Introduction ................................................................................................................101

3.3.2. Proposed Adaptive On-time Control to Improve Buck CCM Efficiency ..................104

3.3.3. Improve DCM Efficiency with Non-linear Inductor .................................................114

Chapter 4. High Efficiency Quasi-Parallel Two-Stage Architecture –

Sigma Voltage Regulators .............................................................................. 125

4.1. Introduction ....................................................................................................................125

4.2. Proposed Sigma VR Structure ......................................................................................126

4.3. Design Sigma VR with Scalability ................................................................................129

4.3.1. Buck Converter Design in Sigma VR ........................................................................129

4.3.2. DCX Design in Sigma VR .........................................................................................129

4.3.3. Sigma Cell Concept for Scalability ............................................................................134

4.4. Modeling and Transient Analysis of Sigma VR ..........................................................138

4.5. Startup and Light Load Efficiency Improvement of Sigma VR................................146

4.6. Comparison between Sigma VR and Two-Stage VR ..................................................152

4.7. Three Other Implementations of Sigma VR ...............................................................153

4.8. Other Applications for Sigma Architecture ................................................................154

4.8.1. Sigma Architecture for Low Current POL Converters ..............................................154

4.8.2. Sigma Architecture for Server and Telecom Applications ........................................157

Chapter 5. Conclusions and Future Work ................................................... 159

5.1. Improvements of Series Two-Stage Power Architecture ...........................................159

5.2. Analysis and Design on Proposed Sigma Power Architecture...................................160

5.3. Future Work ...................................................................................................................161

References ............................................................................................................. 163

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List of Figures

Figure 1.1 The number of transistors integrated on the die for Intel microprocessors ................... 1

Figure 1.2 The speed of Intel microprocessors [2] ......................................................................... 2

Figure 1.3 Intel microprocessors’ power road map [5] ................................................................... 3

Figure 1.4 A four-phase interleaved voltage regulator ................................................................... 3

Figure 1.5 Load-line specifications from Intel VRD 11.0 .............................................................. 4

Figure 1.6 The relationship between the load-line specifications and time domain waveforms .... 5

Figure 1.7 A typical power delivery path for today’s processors ................................................... 5

Figure 1.8 A lumped circuit model of the power delivery path of today’s microprocessor ........... 6

Figure 1.9 Constant output impedance looking from the CPU die ................................................. 7

Figure 1.10 Impedance requirement from the CPU socket (VR sensing point) ............................. 8

Figure 1.11 Bulk capacitance and cost vs. VR bandwidth ............................................................. 9

Figure 1.12 Data center installed base and spending [11] ............................................................ 10

Figure 1.13 Power flow example in one server system [13] ......................................................... 10

Figure 1.14 Light-load efficiency target for laptop voltage regulators ......................................... 11

Figure 1.15 Rack drawing more power [11] ................................................................................. 12

Figure 1.16 One example of a server motherboard with VR highlighted ..................................... 13

Figure 1.17 Power delivery from 12V VR to high-end server microprocessors .......................... 13

Figure 1.18 CPES proposed solution to minimize the interconnection effect .............................. 14

Figure 1.19 ZVRM proposed by Intel [16] ................................................................................... 15

Figure 1.20 5V input CPU voltage regulators .............................................................................. 16

Figure 1.21 12V input VR ............................................................................................................ 16

Figure 1.22 Effciency of 12V and 5V VRs (fs = 1MHz, top switch: Si7112, bottom switch: two

Si7112) .................................................................................................................................. 17

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Figure 1.23 State-of-the-art VR efficiency at 300kHz, 600kHz and 1MHz ................................. 17

Figure 1.24 Loss breakdown of a six-phase buck converter running at 300kHz, 600kHz and

1MHz (120A) ........................................................................................................................ 18

Figure 1.25 FOM vs. breakdown voltage ..................................................................................... 19

Figure 1.26 Efficiency of 5V input VR with low voltage rating devices (fs = 1MHz, GWS15N15

+ IRF6691) ............................................................................................................................ 19

Figure 1.27 Two-stage VR Solution ............................................................................................. 20

Figure 1.28 Two-stage VR with buck as the first stage [22] ........................................................ 21

Figure 1.29 Another parallel type of two-stage voltage regulators – sigma VR .......................... 22

Figure 2.1 Two-stage architecture for the isolated application [26] ............................................. 24

Figure 2.2 Factorized power architecture by Vicor [27] ............................................................... 25

Figure 2.3 Efficiency of FPA ........................................................................................................ 25

Figure 2.4 Another two-stage architecture with isolation ............................................................. 26

Figure 2.5 350kHz bandwidth can eliminate output capacitors [22] ............................................ 26

Figure 2.6 Two-stage VR with buck as the first stage [22] .......................................................... 27

Figure 2.7 Overall efficiency comparison between single-stage and two-stage VRs [22] ........... 27

Figure 2.8 Cost comparison between single stage and two-stage VRs [22] ................................. 28

Figure 2.9 The two-stage architecture in laptop computer application with wide input range [23]

............................................................................................................................................... 28

Figure 2.10 The CPU power consumption and the bus voltage following ABVP control strategy

[23] ........................................................................................................................................ 29

Figure 2.11 The transient waveforms of output current, output voltage and bus voltage [22] ..... 29

Figure 2.12 The efficiency improvement by ABVP control strategy [23] ................................... 29

Figure 2.13 First stage in two-Stage VR ....................................................................................... 30

Figure 2.14 The experimental efficiency of the 1st stage. ............................................................ 31

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Figure 2.15 Overall efficiency comparison between single stage and two-stage @ 1MHz [22] . 31

Figure 2.16 A typical switched capacitor converter for low power application ........................... 32

Figure 2.17 Another switched-capacitor converter with current sink ........................................... 33

Figure 2.18 Equivalent circuit for two capacitors in parallel ........................................................ 34

Figure 2.19 Proposed switched-capacitor voltage divider ............................................................ 35

Figure 2.20 Switched-capacitor converters for high power application [31] ............................... 36

Figure 2.21 Prototype of the four-level switched-capacitor DC/DC converter and tested

efficiency [31] ....................................................................................................................... 37

Figure 2.22 Switching performance of switched-capacitor voltage divider ................................. 38

Figure 2.23 The equivalent circuit of the voltage divider ............................................................ 39

Figure 2.24 Peak current on MOSFET vs. C2 (R = 6mΩ, fs = 375kHz, Io = 12A) ...................... 43

Figure 2.25 C2 RMS current vs. kN and τN ................................................................................. 43

Figure 2.26 C2 RMS current vs. kN for different C2 (each curve corresponds to one C2 value) . 44

Figure 2.27 Output ripple and input AC current vs. C1 and C3 .................................................. 45

Figure 2.28 Light-load efficiency improvement for proposed VD ............................................. 47

Figure 2.29 Proposed gate driving for VD .................................................................................. 47

Figure 2.30 Prototype and efficiency of 70W voltage divider for laptop ................................... 48

Figure 2.31 Prototype and efficiency of 150W voltage divider for server ................................. 49

Figure 2.32 The influence from the parasitic inductors ................................................................ 51

Figure 2.33 Loss breakdown of voltage divider (Vin = 12V, Po = 70W, Lp = 3nH) ..................... 51

Figure 2.34 The equivalent circuit of the voltage divider with parasitic inductance ................... 52

Figure 2.35 Inductor current with different C2 for half of the switching period .......................... 54

Figure 2.36 Total power loss vs. C2 for a given switching frequency ......................................... 55

Figure 2.37 Total power loss vs. C2 for different switching frequencies .................................... 55

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Figure 2.38 Optimal C2 and minimum power loss vs. frequency ( Lp = 3nH, R = 6mΩ, Vin =

12V, Io = 12A, driving loss included) ................................................................................... 56

Figure 2.39 Power loss vs. C2 for different parasitic .................................................................... 57

Figure 2.40 650kHz, 70W voltage divider prototype and tested efficiency curve ....................... 57

Figure 2.41 Equivalent circuit to derive output impedance .......................................................... 59

Figure 2.42 Output impedance of the voltage divider (R=10mohm, Ro=1mohm, Co=88µF) ...... 60

Figure 2.43 An example of Zo1 and Zin2 ........................................................................................ 60

Figure 2.44 Experiment setup and test results .............................................................................. 61

Figure 2.45 Two VRs share the same voltage divider .................................................................. 61

Figure 2.46 No interaction between different VRs due to low output impedance of voltage

divider ................................................................................................................................... 63

Figure 2.47 Comparison of transfer function from io1 to vo2 for voltage divider first stage and

buck first stage ...................................................................................................................... 64

Figure 2.48 Startup waveforms without soft-start (Vin=3V) ......................................................... 64

Figure 2.49 Device startup trajectory with Vgs = 5V (Device: HAT2165) ................................... 65

Figure 2.50 Proposed soft-start method for voltage divider ......................................................... 66

Figure 2.51 Simulation result of the proposed soft-start method .................................................. 66

Figure 2.52 Device junction temperature at startup ...................................................................... 67

Figure 2.53 Experimental result at startup with the proposed method (Vin=12V) ....................... 67

Figure 2.54 Test result of Vin/2-Vo vs. Io ( Vin = 12V ) ................................................................ 68

Figure 2.55 Simulation result at short circuit and over current .................................................... 68

Figure 2.56 Protection of voltage divider based on the voltage difference between Vin/2 and Vo 69

Figure 2.57 Three-level resonant buck (fs = fo) ............................................................................ 70

Figure 2.58 Efficiency comparison between 3-level resonant buck and voltage divider ( C2 =

50µF, Lo = 25nH, fs = 160kHz for 3-level resonant Buck .................................................... 71

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Figure 2.59 Two control methods to regulate output voltage ....................................................... 71

Figure 2.60 Low power density 48V bus converters .................................................................... 72

Figure 2.61 Proposed high power density 48V-12V bus converter .............................................. 72

Figure 2.62 Proposed ZVS voltage divider ................................................................................... 73

Figure 2.63 Simulated waveforms for ZVS voltage divider ......................................................... 73

Figure 3.1 Three basic structures for low-voltage application ................................................... 74

Figure 3.2 One example of lateral-trench MOSFET Structure ................................................... 75

Figure 3.3 The definition of Qgd, Qgs2 and Qg ............................................................................. 75

Figure 3.4 Figure of merit vs. breakdown voltage for different MOSFET structures ( All

devices are for VRM applications) ....................................................................................... 76

Figure 3.5 New figure of merit vs. breakdown voltage for different MOSFET structures (All

devices are for VRM applications) ....................................................................................... 77

Figure 3.6 Test efficiency with Si7106 and RJK0303 as top switch .......................................... 78

Figure 3.7 Efficiency improvement from Great Wall 15V devices ............................................ 79

Figure 3.8 Compare Ciclon devices with the best bottom switch ............................................... 80

Figure 3.9 Comparison of Ciclon devices with the best top switch ............................................ 81

Figure 3.10 A new device loss model which includes parasitic inductance and non-linear

capacitors .............................................................................................................................. 82

Figure 3.11 Comparison between loss model and physical model ............................................. 83

Figure 3.12 Piece-wise linear model for calculation of the turn-off loss in [51] ......................... 84

Figure 3.13 A new piece-wise linear model for calculation of turn-off loss ............................... 84

Figure 3.14 Breakdown of the improved model shows more accuracy ...................................... 85

Figure 3.15 Sweep die size of 12V device technology for top switch ........................................ 86

Figure 3.16 Final efficiency achievement ................................................................................... 86

Figure 3.17 Cost difference between 2004 and 2008 for desktop VR .......................................... 87

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Figure 3.18 Intel’s Narrow VDC power architecture .................................................................. 88

Figure 3.19 One possible two-stage solution for laptop VRs ....................................................... 88

Figure 3.20 Proposed system level two-stage power architecture for laptop ............................... 89

Figure 3.21 Two-stage system for Narrow VDC power architecture ........................................... 90

Figure 3.22 Inductance determines the transient performance for non-linear control .................. 91

Figure 3.23 Number of bulk capacitors vs. inductance for CPU VR ........................................... 92

Figure 3.24 Minimum switching frequency to meet the output ripple requirement ( Vin = 6V, Vo

= 1.2V, three phases, Io = 0.1A, constant on-time control) .................................................. 93

Figure 3.25 Evaluation board for two-stage solution .................................................................... 93

Figure 3.26 Two different two-stage designs ............................................................................... 94

Figure 3.27 CPU VR Efficiency comparison between single-stage and two-stage Design #1 .... 95

Figure 3.28 CPU VR Efficiency comparison between single-stage and two-stage Design #2 .... 95

Figure 3.29 Transient response of CPU VR ................................................................................. 96

Figure 3.30 Footprint comparison for CPU VR ............................................................................ 96

Figure 3.31 DDR VR efficiency comparison ............................................................................... 97

Figure 3.32 ZVRM proposed by Intel........................................................................................... 97

Figure 3.33 Proposed two-stage power architecture for future server microprocessors ............... 98

Figure 3.34 1MHz two-stage VR prototype and efficiency (No bulk capacitors) ...................... 100

Figure 3.35 Control bandwidth and transient waveforms ........................................................... 100

Figure 3.36 A typical power consumption breakdown in laptop .............................................. 101

Figure 3.37 Inductor current waveforms for constant on-time control with different loads .... 102

Figure 3.38 Improved light load efficiency with constant on-time control ............................... 103

Figure 3.39 Synchronous buck converter ................................................................................... 104

Figure 3.40 Output voltage ripple vs. on-time ............................................................................ 104

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Figure 3.41 Maximum on-time vs. load current to meet inductor requirement .......................... 106

Figure 3.42 Maximum on-time vs. load current after considering both ripple and inductor

requirement ......................................................................................................................... 106

Figure 3.43 Power losses vs. Ton at CCM for one-phase of a three-phase buck ....................... 108

Figure 3.44 Tested power loss vs. on-time with different load currents ..................................... 110

Figure 3.45 Proposed adaptive on-time control to improve CCM efficiency- Case 1 ............... 111

Figure 3.46 Proposed adaptive on-time control to improve CCM efficiency – Case 2 .............. 112

Figure 3.47 Transient performance comparison between constant on-time control and adaptive

on-time control .................................................................................................................... 113

Figure 3.48 Loss breakdown at DCM Vin = 12V,Vo = 0.9V, Io = 2A, Ton = 0.5µs, fs = 200kHz 114

Figure 3.49 Inductor current with increased on-time ( Dashed line is with larger on-time ) ..... 114

Figure 3.50 Output current ripple increases under DCM operation, which increase the voltage

ripple. .................................................................................................................................. 115

Figure 3.51 Conflict between efficiency and voltage ripple at DCM ......................................... 116

Figure 3.52 Switching frequency is reduced by increasing output inductance at during DCM . 116

Figure 3.53 Preferred output inductance to improve light-load efficiency ................................. 117

Figure 3.54 Proposed saturable core to achieve desired inductance ........................................... 118

Figure 3.55 Increased on-time for DCM operation with the proposed non-linear inductor ....... 119

Figure 3.56 Calculated switching frequency with proposed control with non-linear inductor .. 120

Figure 3.57 Core loss estimation (Material: 3F3) ....................................................................... 120

Figure 3.58 Large inductance can be seen at CCM if Isat is large ............................................... 121

Figure 3.59 Trade-off design for LL ............................................................................................ 122

Figure 3.60 Experimental results with the non-linear inductor (Vin = 12V, Vo = 1.05V) ........ 124

Figure 3.61 2nd stage of two-stage VR efficiency with non-linear inductor ............................... 124

Figure 4.1 Parallel power architecture proposed by MIT ........................................................... 126

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Figure 4.2 Proposed sigma VR architecture ............................................................................... 127

Figure 4.3 Voltage regulation of sigma VR ................................................................................ 128

Figure 4.4 Buck converter in sigma VR ..................................................................................... 129

Figure 4.5 DCX example 1: ZVS quasi-resonant converter proposed by CPES ........................ 130

Figure 4.6 DCX example 2: LLC resonant converter working at fixed frequency .................... 131

Figure 4.7 Autotransformer is required to reduce output voltage ripple for ZVS-QR DCX ...... 132

Figure 4.8 Efficiency comparison between ZVS-QR DCX and LLC DCX (fs = 600kHz) ........ 133

Figure 4.9 Loss break down of ZVS-QR DCX and LLC DCX @ 80A ..................................... 133

Figure 4.10 Comparing 60A sigma cell with 3-phase buck ........................................................ 134

Figure 4.11 Scalable VR with sigma Cell ................................................................................... 135

Figure 4.12 Current of DCX can be shared by controlling buck duty cycle ............................. 135

Figure 4.13 One design example: 120A VR for VR11 ............................................................... 136

Figure 4.14 Tested efficiency for sigma VR ............................................................................... 137

Figure 4.15 30A sigma VR cell .................................................................................................. 137

Figure 4.16 30A sigma VR cell design ....................................................................................... 138

Figure 4.17 Small-signal model for the power stage .................................................................. 139

Figure 4.18 Current injection control to achieve AVP from Intel .............................................. 140

Figure 4.19 Control diagram and desired impedance by sensing buck current only .................. 141

Figure 4.20 Small single block diagram of the sigma VR .......................................................... 142

Figure 4.21 Output impedance when the current loop closed (Zoi) ........................................... 142

Figure 4.22 Reduced T2 bandwidth of sigma VR - with the same output capacitance with buck

............................................................................................................................................. 143

Figure 4.23 Reduced output capacitance of sigma VR - with the same T2 bandwidth with buck

............................................................................................................................................. 143

Figure 4.24, Loop gain and closed-loop impedance ................................................................... 144

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Figure 4.25 Transient waveforms (Vo initial spike can be ignored) .......................................... 144

Figure 4.26 Bulk capacitors are required with large Lout and Rout .............................................. 145

Figure 4.27 Transient performance of sigma VR ....................................................................... 146

Figure 4.28 VR startup with no-load condition .......................................................................... 146

Figure 4.29 Huge current observed if there is input and output voltage difference for DCX .... 147

Figure 4.30 Proposed start-up method for sigma VR ................................................................. 148

Figure 4.31 Experimental result for soft-start method ................................................................ 148

Figure 4.32 Light load efficiency comparison ............................................................................ 149

Figure 4.33 Loss break at light load for sigma VR ..................................................................... 149

Figure 4.34 Shut-down DCX at light load to improve light load efficiency .............................. 150

Figure 4.35 Activate DCX at heavy load for sigma VR ............................................................. 151

Figure 4.36 Light-load efficiency comparison by shutting down DCX at light load ................. 151

Figure 4.37 Wide input voltage range for buck converter if the input voltage range is wide .... 152

Figure 4.38 Implementation #2 of sigma concept ...................................................................... 153



Figure 4.41 Inductor size is too large for POL converters .......................................................... 155

Figure 4.42 Implementation #2 is selected for POL converters ................................................. 155

Figure 4.43 Detailed circuit diagram for POL application ......................................................... 156

Figure 4.44 Inductor size comparison of sigma POL and buck POL converters ....................... 156

Figure 4.45 Efficiency comparison ............................................................................................. 157

Figure 4.46 Sigma architecture for server and telecom applications .......................................... 158

xix

List of Tables

Table 2.1 Parameters in the 70W Voltage Divider prototype…………………………………...48

Table 2.2 Parameters in the 150W Voltage Divider prototype....................................................49

Table 3.1 Comparison between Si7106 and RJK0303……………………………………...….. 77

Table 3.2 Comparison between GWS15N15 and RJK0303……………………………….…… 79

Table 3.3 Comparison between CSD13301 and IRF6691……………………………………… 80

Table 3.4 Comparison between CSD16402 and GWS15N15………………………………….. 81

Table 3.5 Comparison between two two-stage designs for laptop……….………………….….97

Table 4.1 Circuit parameters for sigma VR and 6-phase buck VR…………………………….136

Table 4.2 An example of 10A buck design…………………………………………………….138

Chapter 1. Introduction

1


1.1. Evolution of Microprocessors

The microprocessor, which is also known as the central processing unit or CPU, is widely

used in many applications such as computer systems and handheld devices. To achieve better

performance, more transistors are being integrated into the microprocessor. Since 1971, when the

first microprocessor, Intel’s 4-bit 4004 chipset, was released, more and more transistors have

been integrated into the microprocessor, following Moore’s Law, which states that the number of

components on an integrated circuit doubles roughly every two years. Figure 1.1 shows the

historical data of the number of transistors integrated into Intel’s microprocessor [1]. The dual-

core processor, which was released in 2006, has more than one billion transistors in it.

Figure 1.1 The number of transistors integrated on the die for Intel microprocessors

With more transistors integrated into the microprocessor, better performance is achieved.

Figure 1.2 shows the speed of Intel microprocessors [2]. Millions of instructions per second

(MIPS) is a measure of a computer’s processing speed. Intel targets to build a microprocessor

with ten trillion instruction per second (TIPS) by 2015, which is about ten billion times faster

than the first 4004 microprocessor.


2

Figure 1.2 The speed of Intel microprocessors [2]

These advances in microprocessor technology challenge the power supplies of these

devices. With a single microprocessor, a device’s power consumption is roughly proportional to

the clock frequency, the total lumped capacitance C of the transistors, and the square of the core

voltage [3], [4]. In order to get a higher operating speed, the clock frequency must be higher and

the power consumption must increase accordingly. Moreover, the scaling of microprocessors

will increase capacitance C, and the power consumption increases. This power consumption

eventually results in greater heat dissipation, which is a huge challenge for the thermal

management of the microprocessors.

Starting in 2005, Intel changed the microprocessor structure from the single core to core

multi-processor (CMP); this product uses multiple cores on the die, and includes dual-core and

quad-core processors [2]. Assuming the maximum performance of the single core is 1.00x with a

power consumption of 1.00x, in order to increase the performance to 1.13x, the clock frequency

must be increased by 20% and the supply voltage (VCC) should be increased proportionally. The

power consumption is increased as 1.73x (≈ 1.23). Meanwhile, if the clock frequency is reduced

by 20%, the supply voltage can be reduced by 20% and the power consumption becomes 0.51x

(≈ 0.83) with 0.87x performance. The dual-core processor uses two under-clocked cores, which

increases the performance to 1.73x, with almost the same power consumption. Since the supply

voltage is reduced, the processors demand more current. With more cores, the supply voltage is

further reduced, and the current becomes higher. Figure 1.3 shows the power road map of Intel’s

microprocessors, which were surveyed in [5]. In the near future, the voltage will be under 1V

and the current demand will be larger than 150A.


3

Figure 1.3 Intel microprocessors’ power road map [5]

1.2. High Efficiency and High Power Density Requirement for Voltage

Regulators

A. Multi-phase Buck Voltage Regulators

In order to supply power to the microprocessor with high current and low voltage demand,

the dedicated power supply voltage regulator (VR) is used. In low-end computer systems, since

there is no isolation requirement, synchronous buck converters are widely used for VRs because

of their simple structure, low cost and low conduction loss. An improvement on the synchronous

buck converter is the adoption of the multiphase interleaved technique [6] (illustrated in Figure

1.4). By paralleling several synchronous buck converters and phase shifting their drive signals,

the interleaving approach can reduce both the input and output current ripples, improve the

transient response, and distribute power and heat.

Figure 1.4 A four-phase interleaved voltage regulator

140

120

100

80

60

40

20

0

Icc(A

)

Icc

CPU Core Voltage and Current2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.81999 2000 2001 2002 2003

Vcc(V

)

Vcc

2004 2005 2006 2007 2008 2009 2010

Co RLV in

Q 1

Q 3

L

L

Q 5

Q 7

L

L

Q 2

Q 4

Q 6

Q 8

Q 4

Q 2

Q 6

Q 8


4

B. Transient Requirement for Voltage Regulators

Today’s VR faces the stringent challenge of not only high current but also a strict transient

response requirement. In the Intel VRD 11.0 specification, the maximum current slew rate is

1.9A/ns at the CPU socket [7]. Figure 1.5 shows the VR output load line from the Intel VRD

11.0 specification. The vertical axis is the VR output voltage deviation from the voltage

identification (or VID, which is a code supplied by the processor that determines the reference

output voltage), and the horizontal axis is the CPU current (ICC). The maximum, typical and

minimum load lines are defined by (1-1):

CCLL IRVIDV ⋅−=max

TOBIRVIDV CCLLtyp −⋅−=

TOBIRVIDV CCLL ⋅−⋅−= 2min

(1-1)

where RLL is the load-line impedance and TOB is the tolerance band. The VR output voltage

should be within this load line band for both static and transient operation.

Figure 1.5 Load-line specifications from Intel VRD 11.0

Figure 1.6 shows the relationship between the load-line specifications and the time domain

waveforms [7]. When the CPU current (IO=ICC) is low, the VR output voltage should be high,

and when the CPU current is high, the VR output voltage should be low. This is achieved by the

VR controller, which is known as the adaptive voltage positioning control (AVP). The VR output

voltage must also follow the load line during the transient, with one exception. During the load

‐0.18

‐0.16

‐0.14

‐0.12

‐0.1

‐0.08

‐0.06

‐0.04

‐0.02

0

0 20 40 60 80 100 120 140

Vmax LL

Vtyp LL

Vmin LL

Icc (A)

ΔV (V

)


5

step-down transient, the VR output voltage can be over Vmax load line for 25µs. This overshoot

should not exceed the overshoot relief, which is VID+50mV in the VRD 11.0 specification.

Figure 1.6 The relationship between the load-line specifications and time domain waveforms

The voltage overshoots, which cannot meet this specification, will cause higher processor

operating temperature, and this may result in damage or a reduced processor life span. The

processor temperature rise from higher functional voltages may lead to operation at low power

states, which directly reduces processor performance. The voltage undershoots may cause system

lock-up, “blue screening,” or data corruption.

The above concerns clarify why output filter capacitors are so important for a processor to

operate properly. Figure 1.7 shows a typical power delivery path for today’s processors [9], [10].

In order to supply sufficient energy to the processor, sufficient energy storage components must

be placed in different locations.

Figure 1.7 A typical power delivery path for today’s processors

Vmax LL

Vmax LL

Vmin LL

Vmin LL

Min Load SS WindowMin Load

SS WindowMin Load

SS Window

Volta

geVID

Current Icc max

Volta

geVID

Current

Volta

geVID

Current Icc max

Max Load SS Window

Max Load SS Window

Max Load SS Window

VO

Overshoot releif (VID + 50mV)< 25 us

IO

Socket

Processor Die

OLGA

OsconOscon

For 478-pin socket

Cavity Cap

Packaging CapBulk Cap


6

The capacitors closest to the VR are so-called ‘bulk’ capacitors. In most of today’s designs,

a special type of electrolytic capacitor ⎯ the Oscon capacitor ⎯ is widely used as the bulk

capacitor. It has relatively low ESR and ESL values compared to the general-purpose electrolytic

capacitor, while still having a large capacitance; for example: C=560µF, ESR=6-10mΩ,

ESL=3nH. Since Oscon capacitors have relatively high profile, it cannot be used in applications

in which low profile is required, e.g. laptop computers. Another high-density capacitor called

specify polymer capacitor (SPCAP) is now widely used as bulk capacitors in laptop or server

computers due to its low profile. SPCAP has even better performance than Oscon capacitors; for

example: C=390µF, ESR=7mΩ, ESL=2nH. Following the bulk capacitors in the power path,

multi-layer ceramic capacitors (MLCCs) are used as the decoupling capacitors. The MLCC has

even lower ESR and ESL values than the Oscon capacitors, but the capacitance is small. A

typical value would be: C=22µF, ESR=4mΩ, ESL=1nH. Because of their small package sizes,

these MLCCs are usually located in the socket cavity. So sometimes it is referred as ‘cavity’

capacitors. The packaging capacitors are those included in the CPU package. They are also

ceramic capacitors with extremely low ESL. There is also one on-die capacitor to help the

transient performance at high current slew-rate.

Figure 1.8 shows a lumped circuit model of the power delivery path of today’s

microprocessor [9], [10]. The selection of different types of capacitors is an attempt to achieve

constant output impedance for best transient performance.

Figure 1.8 A lumped circuit model of the power delivery path of today’s microprocessor

Figure 1.9 explains this using the constant output impedance concept [9]. Each type of

capacitor has a different resonant frequency, so that they can cover a certain range of the

Cavity capBulk cap

VID

Lvr Rvr Lskt Rskt Lvia Rvia

Lblk

RblkCblk

LMB

RMBCMB

Lpkg

RpkgCpkg

RdieCdie

Idie

CPUSocketVR

Sensing point


7

frequency to make the overall output impedance lower than the desired impedance, as shown in

Figure 1.9(a). The overall output impedance is shown in Figure 1.9(b), and it can achieve

constant or lower output impedance than the desired impedance with very wide frequency range.

Since packaging capacitors and on-die capacitors are beyond the circuit designer’s control,

Intel defines only the socket load line impedance requirement [7], as shown in Figure 1.10. The

impedance includes VR, bulk capacitors and cavity capacitors. Since the number of cavity

capacitors is limited by the CPU socket, the maximum number is eighteen 22µF ceramic

capacitors with 1206 footprint. As a result, it can only cover the frequency range from around

390kHz to 2MHz. Below 390kHz, bulk capacitors must work with VR to get the desired

impedance.

(a) Impedances for different decoupling capacitors

(b) Overall output impedance from die side

Figure 1.9 Constant output impedance looking from the CPU die

Desired

VR Close‐loop

Cavity Cap(MLCC)

Packaging cap(MLCC)

Die Cap

f

|Z|

Bulk Cap(Oscon)

fc

Desired

f

|Z|


8

Figure 1.10 Impedance requirement from the CPU socket (VR sensing point)

For example, assume VR control bandwidth is 50kHz, which means the impedance below

50kHz can be taken care by VR close loop. Therefore, there is a gap between the VR control

bandwidth and the cavity capacitors from 50kHz to 390kHz. As a result, ten 560µF Oscon

capacitors must be added to fill the gap. If VR control bandwidth can be pushed to 390kHz, there

is no gap between VR impedance and cavity capacitance impedance, which indicates that there

are no bulk capacitors required. With different VR control bandwidth, different number of the

bulk capacitors should be used, as shown in Figure 1.11. The capacitor parameters are: Oscon

capacitor: C=560µF, ESR=6mΩ, ESL=3.3nH, price: $0.15/piece; ceramic capacitor: C=100µF,

ESR=1.4mΩ, ESL=1nH, price: $0.25/piece. A very interesting phenomenon is that within 50kHz

and 390kHz control bandwidth, capacitance does not change for Oscon capacitors but gradually

changed for ceramic capacitors. The reason is that larger ESL of Oscon capacitors limits the

number of the capacitors. From Figure 1.11(b), it can be observed that with 150kHz VR

bandwidth, it is better to switch from the Oscon capacitor to the ceramic capacitor to reduce the

footprint while keeping the same cost.

f

|Z|

2MHz390kHzfc

RLL

VR Close‐loop

Cavity Cap(MLCC)

Bulk Cap


9

(a)Capacitance vs. VR bandwidth

(b)Capacitor cost vs. VR bandwidth

Figure 1.11 Bulk capacitance and cost vs. VR bandwidth

C. High Efficiency Requirement for Voltage Regulators

As described in Figure 1.3, the current of the CPU will continue to increase. Because of

this, the thermal management of the power system will become more and more challenging. This

problem is even severe in a data center, where many CPUs are used for high performance.

Figure 1.12 shows the increase of data center installed bases for the worldwide server market

[11]. It can be seen that the cost for powering and cooling the data center increases much faster

than new server spending due to the high current requirement for CPUs.

10

100

1000

10000

100000

1.E+04 1.E+05 1.E+06

Cap

acita

nce

(µF)

fc (Hz)

OsconCap

Ceramic Cap

0.1

1

10

1.E+04 1.E+05 1.E+06

Cap

acito

r cos

t ($)

fc (Hz)

OsconCap

Ceramic Cap


10

Figure 1.12 Data center installed base and spending [11]

Figure 1.13 shows an example of the power flow of one server system [12], [13]. The load

power is normalized to be 100W. The total input power can be as high as 285W - 405W, which

is three or four times higher than the load power. If we exclude the cooling power, due to low

efficiency of power supplies the power efficiency of the whole system is only 50%, which means

power supplies consume an amount of power similar to the final load.

(a) Power delivery for server systems

(b) Efficiency breakdown for each stage

Figure 1.13 Power flow example in one server system [13]


11

As a result, it is required to improve the efficiency of each stage of the power delivery

system in the server. Web giant Google™ proposed to improve their entire server power

system’s efficiency to 90% [14]. They estimate that if this is deployed in 100 million PCs

running for an average of eight hours per day, this new standard would save 40 billion kilowatt-

hours over three years, or more than $5 billion at California’s energy rates. However, this

efficiency target is not that realistic, so they decreased the target to 85%. Assuming the PSU can

achieve 95% efficiency, the VR must provide at least 90% efficiency!

A similar efficiency requirement is proposed by IBM [15] and Intel [12]. Some efforts have

already been made, so VR efficiency has increased from 75% to 85% - 86% [13]. However,

there is still a 3% - 4% gap between the state-of-the-art VR efficiency and the target VR

efficiency.

Efficiency as discussed above refers to full-load efficiency. Light-load efficiency of the VR

is also very important, since the CPU goes into sleep states very frequently to save power. When

the computer is in hibernate mode, or when there is no software running, the operating system

(OS) sends a signal through the advanced configuration and power interface (ACPI), and the

system goes into sleep mode. When the CPU goes into sleep mode, the clock frequency and the

supply voltage are reduced. The light-load efficiency is particularly important for laptop voltage

regulators, since the laptop VR goes to sleep about 80% of the time, and light-load efficiency is

very important for battery life extension.

Figure 1.14 Light-load efficiency target for laptop voltage regulators

70%

75%

80%

85%

90%

95%

0.1 1 10 100Io(A)

Efficien

cy


12

Figure 1.14 shows an example of the light-load efficiency expectation from Intel. The

expected efficiency is 90% for the active state (9A to 45A), 80% at 1A, and 75% at 300mA for

the sleep states. Since the fixed power loss, which consists of gate driving losses, core losses,

etc., becomes dominant at light load, it is very challenging to meet the efficiency requirement.

D. High Power Density Requirement for Voltage Regulators

At the same time, data center power density is increasing by approximately 15% annually.

Figure 1.15 shows the rack power increasing year by year. The power could go as high as 25kW

in 2009 [11]. The servers per rack increase dramatically. In 1996, there was an average of seven

servers per rack. This number increased to ten servers per rack in 2002 and 14 in 2005. It is

projected to increase to 20 servers per rack by 2010!

Figure 1.15 Rack drawing more power [11]

More servers per rack mean more CPUs, which indicates that the CPU voltage regulators

increase correspondingly. Figure 1.16 shows an example of a server motherboard with two CPUs

and two VRs. It can be calculated that the VR occupies more than 13% of the total motherboard

footprint. To reduce the server size, it is necessary to reduce the VR size. If we perform further

calculation, it can be seen that the passive components of the VR, which are the output inductors

and output capacitors, are about 60% of the total VR size. So if we want to achieve a high-

power-density VR, the passive component size must be reduced. In the future, since CPU current

will continue to increase, more VR phases should be designed to power higher current. With


13

more VR phases, the size of the VR will be further increased. As a result, reducing the passive

component size is very important for server voltage regulators.

Figure 1.16 One example of a server motherboard with VR highlighted

The above VR is mainly for Xeon processors. For Itanium processors which are widely

used in high-end servers, the power delivery is very different, as shown in [16], [17], [18]. The

VR delivers power from one side of the OLGA board through the power connector. There are

three kinds of decoupling capacitors: bulk capacitors on the VR board, die-side capacitors (DSC)

on the OLGA, and a pin-side capacitor (PSC) underneath the microprocessor.

Figure 1.17 Power delivery from 12V VR to high-end server microprocessors

VR

Socket

Processor

OLGA

Inductor Bulk capsVR

motherboard

Power connectorDSC

(die side cap)PSC

(pin side cap)


14

In the future, server microprocessors will have more and more power consumption and

transient requirements. Based on Intel’s information, the expected next-generation Itanium CPU

current is around 170A and the load-line resistance is 0.8mΩ at the CPU packaging point. The

main limitation of the current power delivery approach for the future VR specification is the

interconnection effect. The parasitic resistance of the interconnection is 0.6mΩ which causes a

huge distribution loss of about 17.3W at 170A load current. The large ESL of the interconnection

(400pH) will introduce a huge voltage spike with a fast load transient, which is hard to reduce

with VR control. Many capacitors must be added to meet the transient requirement. Based on the

design methodology introduced in [10], to meet the future VR transient requirements it can be

predicted that the die-side capacitor number should be sixteen times as many as the current

solution, and the pin-side capacitor number should be eleven times as many as the current

solution. Due to the limited footprint of the OLGA, it is impractical to include so many

capacitors.

To solve this problem, CPES proposed the new power delivery structure where the VR is

put on the OLGA to minimize the interconnection effect [19]. The concept is shown in Figure

1.18, where the VR is put on the OLGA and delivers power from four sides of the

microprocessor. The power delivery path is much shorter than in the previous architecture.

Therefore, efficiency and transient response are improved. Simulations show that the parasitic

resistance from the VR to the die-side capacitor is about 0.11mΩ, which reduces the distribution

loss by 82%. The parasitic inductance is about 6pH, which results in a 75% die-side capacitor

reduction.

Figure 1.18 CPES proposed solution to minimize the interconnection effect

Socket

ProcessorOLGA

motherboard

DSC (die side cap)

PSC(pin side cap)

VRVR

VR

VR VR

VR


15

This concept is also used in industry. For example, Intel and other companies are now

considering the Z-Axis VRM (ZVRM) structure, as shown in Figure 3.32 [16]. There is a small

difference between the ZVRM and CPES’ proposed structure; the ZVRM is plugged into the

OLGA instead of putting it on the OLGA. The reason for this is that ZVRM failure does not

cause CPU failure. Nevertheless, the concept is still to put VR as close as the microprocessor to

minimize the power delivery path, like CPES’ proposed structure.

(a)

(b)

Figure 1.19 ZVRM proposed by Intel [16]

(a) Original Drawing (b) Concept redrawing

In this arrangement, the VR must be very small to put it on (or around) the OLGA. As we

know, the bulky elements of the VR are the output inductors and output capacitors. Based on the

information from Intel, VR switching frequency must be pushed to about 800kHz to fit the size

to the space around CPU.

A similar requirement exists for the laptop VR, since the laptop demands smaller size and

lighter weight.

Socket

Processor

OLGA

motherboard

DSC PSCDSC

(die side cap)Inductor Bulk cap InductorBulk capZVRM ZVRM

Socket

Processor

OLGA

motherboard

DSC PSCDSC

(die side cap)Inductor Bulk cap InductorBulk capZVRM ZVRM


16

1.3. Limitations of Single-Stage Multi-phase Buck Voltage Regulators for

High Efficiency and High Power Density

A. Low Efficiency due to High Input Voltage

At the very beginning of the use of voltage regulators, since the output current was only

about 15A, a 5V input from a silver box was widely used. The efficiency of this type of VR is

about 90% [6].

Figure 1.20 5V input CPU voltage regulators

However, as the current of the CPU keeps getting higher and higher, the input current from

5V is also higher, which gives much more burden to the silver box. Furthermore, a high input

current can cause high distribution loss since the distance between the silver box and the VRM is

very long.

To meet the higher current VR requirements, the VR input changed from 5V to 12V. As a

result, the input current is low, so both of the above problems are solved. However, the

efficiency drops to about 80%.

Figure 1.21 12V input VR

ACSilver Box

VRMVRM12V Pentium Processor

0.8~1.6VACSilver Box


0.8~1.6V

5V

2V/15A

ACSilver Box


0.8~1.6VACSilver Box


0.8~1.6V


17

Nowadays, the device performance is better so the efficiency gap between 12V VR and 5V

VR is reduced. Nevertheless, there is still 4% efficiency difference in an example shown in

Figure 1.22.

Figure 1.22 Effciency of 12V and 5V VRs (fs = 1MHz, top switch: Si7112, bottom switch: two Si7112)

Figure 1.23 shows the tested efficiency curves for six-phase voltage regulators with 12V

input and 1.2V output and the best available devices. Each phase contains one top switch, the

RJK0305, one bottom switch, the RJK0301, and one output inductor. It clearly shows that the

VR efficiency drops a good deal at 600kHz and 1MHz, which indicates the switching losses

becomes dominant for high-frequency operation, since conduction losses are not related to the

switching frequency.

Figure 1.23 State-of-the-art VR efficiency at 300kHz, 600kHz and 1MHz

70%72%74%76%78%80%82%84%86%88%90%

2 6 10 14 18

Effic

ienc

y

Io (A)

Vin=5VVin=12V

70%

75%

80%

85%

90%

95%

0 20 40 60 80 100 120 140

300kHz600kHz1MHz

Io(A)


18

Figure 1.24 shows the loss breakdown of the above voltage regulator at full load [21]. It

clearly shows two dominant losses: the top switch turn-off loss and the bottom switch conduction

loss. Since the turn-off loss is roughly proportional to the input voltage and the commutation

time, a high input voltage (12V) is a major reason for high turn-off loss. As for the bottom

switch, since it conducts current for most of the time due to a small duty cycle (0.1 for 12V input

1.2V out), the conduction loss is also very high.

Figure 1.24 Loss breakdown of a six-phase buck converter running at 300kHz, 600kHz and 1MHz (120A)

B. Device Limitation of Multi-Phase Buck

For low-voltage applications, there are three basic types of device technology widely used

in industry: the vertical diffusion MOS (VDMOS), the trench MOS [45] and the lateral diffusion

MOS (LDMOS) [46]. Among these structures, the trench MOSFET has the lowest on-resistance,

while the lateral MOSFET has the fastest switching speed due to low Cgd. For sub-30V

applications, the trench MOS and lateral MOS are widely used.

Recently, the lateral-trench MOSFET structure was developed to obtain the benefits of

both the lateral MOSFET and the trench MOSFET. Both Cgs and Cgd can be reduced comparing

with trench MOSFET, and on resistance is lower than lateral MOSFET.

The traditional device figure of merit (FOM = Qgd * Rdson) [20] is shown in Figure 1.25. A

lower FOM means the device can achieve lower power loss. For 12V voltage regulators, a 30V

MOSFET should be used for both top and bottom switches due to the device’s hard-switching.

Unfortunately, most of lateral MOSFET and lateral-trench MOSFDET are low voltage rating

02468

10121416

300kHz600kHz1MHz

Power Lo

ss (W

)


19

devices with sub-20V breakdown voltage. Figure 1.25 shows that a 30V device’s FOM is much

larger than the FOM of sub-20V devices. Although companies put a lot of effort into improving

device performance at 30V, e.g. the improvement of the Renesas D8 to D9 and the Infineon

OptiMOS 2 to OptiMOS 3, the lowest FOM for 30V devices is still higher than the FOM of most

sub-20V devices with lateral or lateral-trench structure. As a result, the power losses on both the

top switch and bottom switch are larger. The MOSFET used in Figure 1.23 is the best available

30V MOSFET, a Renesas D9 generation, but the efficiency is not that exciting even at 300kHz

switching frequency.

Figure 1.25 FOM vs. breakdown voltage

Figure 1.26 shows the efficiency of 5V VR with low voltage rating devices. It can be seen

that the efficiency can be improve about 9% comparing with 12V VR with 30V devices.

Figure 1.26 Efficiency of 5V input VR with low voltage rating devices (fs = 1MHz, GWS15N15 + IRF6691)

0510152025303540

5 10 15 20 25 30 35Vds (V)

FOM=Q

gd*R

ds

Infineon ‐ Trench 3

Vishay ‐ Trench

Renesas ‐ Trench D8

Ciclon ‐ Lateral‐TrenchGreatwall ‐ Lateral



IRDirectFET

70%72%74%76%78%80%82%84%86%88%90%

2 6 10 14 18

Effic

iency

Io (A)

Vin=5V with low voltage devicesVin=5V with 30V deviceVin=12V dwith 30V devices


20

C. Low Power Density Due to Low Frequency

As explained above, the frequency of the 12V VR is relatively low due to efficiency

requirement. The frequency is about 200kHz~300kHz for laptop VR. For server VR the

frequency range varies from 300kHz to 600kHz. Assuming the VR bandwidth is about one sixth

of the frequency, the bandwidth of server VR is only 50kHz to 100kHz, which means at least 10

Oscon capacitors should be used. Low frequency also results in bulky inductor size. These are

the reasons why we see so many capacitors and so large output inductors in Figure 1.16.

1.4. Two-Stage Voltage Regulator Architectures – “Divide and Conquer”

Concept

In order to achieve high efficiency and high power density at the same time, this

dissertation proposes using two-stage power architectures. The concept is “Divide and Conquer”.

A single-stage VR is split to a two-stage VR and both of the two-stage can achieve high

efficiency. There are two types of two-stage VR connection: series two-stage and parallel two-

stage.

A. Series Two-Stage Solution: CPES Proposed Two-Stage Solution [22], [23]

To avoid the problems of the 5V input and to take advantage of the high efficiency of a 5V

VR, a two-stage VR solution was proposed, as shown in Figure 1.27. By adding a high-

efficiency first stage, both the silver box and the VR can be satisfied. Thus the first stage works

like a buffer. The second stage is to conquer the high current requirement with low input voltage

and low voltage rating devices and the first stage just needs to step down the 12V input to 5V.

Figure 1.27 Two-stage VR Solution

AC Silver Box


0.8~1.6VAC Silver Box

2nd Stage

5V

Pentium Processor

0.8~1.6V

1st Stage


21

Figure 1.28 shows one possible implementation of two-stage concept. The first stage is

buck converter which converts 12V input to 5V. Since it does not require fast transient response,

low switching frequency is desired for high efficiency. With 300kHz switching frequency, the

first stage efficiency is more than 97%. The second stage is multi-phase buck converter with 5V

input. It can achieve higher switching frequency with similar efficiency as 12V VR.

Figure 1.28 Two-stage VR with buck as the first stage [22]

B. Parallel Two-Stage Solution: Proposed Sigma Voltage Regulators [25]

The previous two-stage structure is in series; thus each stage should be able to handle the

full power. A more efficient way to deliver power is that two stages deliver power to the load in

parallel, and use a high-efficiency unregulated converter to handle most of the power. A parallel-

type two-stage approach is proposed, as shown in Figure 1.29. The input-side of the two

converters is in series instead of in parallel. It is named as quasi-parallel architecture, or sigma

architecture. The DC/DC Transformer (DCX) delivers most of the power, so high efficiency is

expected. The low-power buck converter only needs to take care of the output voltage regulation

and transient performance. Another benefit of this architecture is that low-voltage-rating devices

can be used in both the DCX and buck converter.

Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…

Multi-Phase Buck 2nd Stage

CbusQ12Q11

300~500KHz

Voltage step-down converter

Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…


Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…


CbusQ12Q11

300~500KHz


CbusQ12Q11

300~500KHz


CbusQ12Q11

300~500KHz



22

Figure 1.29 Another parallel type of two-stage voltage regulators – sigma VR

1.5. Dissertation Outline

From the above discussion, the CPES proposed series two-stage and quasi-parallel power

architectures are good candidates for the voltage regulators. In this dissertation, I will focus on

the investigation of these two power architectures.

This dissertation consists of five chapters organized as follows:

Chapter 1 gives an introduction of the research background. It highlighted the main

challenges of VR design which are high efficiency and high power density requirement. The

limitations of the current single-stage solution are illustrated in very detail.

Chapter 2 and Chapter 3 outline the improvement of the CPES proposed two-stage

architecture.

Chapter 2 proposes a new first stage with very high power density and high efficiency. The

first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is

required for the first stage since it is in series with the second stage. Previous first stage which is

a buck converter has good efficiency but bulky size due to low frequency operation. Another

problem with using a buck converter is that light-load efficiency of the first stage is poor. To

solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does

not require voltage regulation, the sweet point for the voltage divider can be determined and high

efficiency can be achieved. At the same time, since there are no magnetic components for the

Vin

Io

+

-

+

-

Vin1

Vin2

1* *

nDCX

Buck

isolation


23

switched-capacitor voltage divider, high power density can be achieved. The detailed analysis of

the switched-capacitor voltage divider will be provided in Chapter 2.

Chapter 3 focuses on how to improve the second stage’s efficiency with the help of low-

voltage-rating devices, and how to improve the light-load efficiency. The different low-voltage

devices will be evaluated, and the best device combinations are found for high-frequency

operation. Moreover, adaptive on-time control method and a non-linear inductor structure are

proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the

two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other

systems. Two different applications will be studied for two-stage architecture: laptop computers

and high-end server microprocessors. It will be demonstrated that the two-stage power

architecture can achieve either higher efficiency or higher power density and a lower cost when

compared with the single-stage VR.

In Chapter 4, a high efficiency parallel two-stage power architecture (Sigma VR) is

proposed, and the design is illustrated in detail. The proposed sigma VR takes advantage of the

high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver

most of the output power, while using a low-power buck converter to achieve voltage regulation.

Both the DCX converter and the buck converter can achieve around 90% efficiency when used

in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the

sigma VR will be studied to achieve adaptive voltage positioning (AVP). The sigma power

architecture can also be applied to low-power point of load (POL) applications to reduce the

magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma

VR are briefly compared.

Chapter 5 provides a summary of the dissertation.

Chapter 2. High Power Density Non-Isolated Bus Converters

24


2.1. Background

Two-stage power architecture is originally used for the isolated DC/DC converter

applications [26], as shown in Figure 2.1. The voltage regulation is achieved by the first stage

which is a buck converter. The second stage is totally unregulated. The major benefit is to

achieve self driven for the synchronous rectifier for the second stage. Also the secondary side

gate driving loss can be partially recovered, which is very important for high frequency

operation.

Figure 2.1 Two-stage architecture for the isolated application [26]

Vicor applies the above two-stage architecture to 48V VRM application, which is called as

factorized power architecture (FPA) [27]. A FPA is shown in Figure 2.2. We can see that the first

stage is regulated, while the second stage is totally unregulated. The difference of FPA

comparing with the architecture proposed in [26] is that the first stage is a buck-boost type

converter which can achieve ZVS for all switches; the second stage is a LLC resonant converter

running at resonant frequency. It is indicated that the unregulated resonant converter can achieve

much higher efficiency than the regulated one since it can work with an optimal point. As a

result, the second stage can achieve very high efficiency with high frequency. In addition, the

second stage can use low-voltage-rating devices to improve the performance.

* *


25

Figure 2.2 Factorized power architecture by Vicor [27]

Figure 2.3 shows the efficiency of the FPA structure for 48V application. The overall

efficiency can be as high as 88% with a switching frequency greater than 1MHz.

Figure 2.3 Efficiency of FPA

However, since the second stage is unregulated, the transient performance is not easy to

achieve. Another problem with the FPA is that since the second stage is unregulated, the stages

cannot be in parallel to increase the current capability. As a result, this structure has a problem

with scalability.

To get better transient performance and achieve more scalability, another two-stage

architecture was proposed for 48V applications [22], as shown in Figure 2.4. The first stage is

isolated and unregulated, and the second stage just uses a simple buck converter, which can

achieve very good transient performance. It is also well known that buck converter can achieve

scalability very easily by using multi-phase interleaving structure. Nowadays, this structure is

widely used in telecom industry and it is called as intermediate bus architecture (IBA).

Pre‐regulated Module Voltage Transformation Module

Voltage regulation

η=97%fs =1MHz

η=91% @ 1.5V/100A, fs=1.3MHz×

Vbus = 48V

PRM36~75V input

VTM1.5V/100A


26

The above two-stage structure is used for isolated applications. For 12V VR, since no

isolation is required, is the two-stage architecture still a valid approach? The following section

will review some research done for 12V two-stage VR.

Figure 2.4 Another two-stage architecture with isolation

2.2. Review of Previous 12V Two-Stage VR Research

2.2.1. Two-Stage VR for Desktop Computers

For desktop VRs, cost is the greatest concern. In reference [22], it is proven that with

around 350kHz control bandwidth, the output bulk capacitors can be eliminated, as shown in

Figure 2.5.

**Primary-SidePower Circuit

Secondary-SidePower Circuit

VoltageRegulator

Output Voltage

Control Path

Isolation

Fixed Duty-Cycle

First Stage Second Stage

(a)Measure loop gain (b)Transient response without bulk capacitors

Figure 2.5 350kHz bandwidth can eliminate output capacitors [22]

1 .103 1 .104 1 .105 1 .106 1 .10740

20

0

20

40

60

fc=320kHz

1 .103 1 .104 1 .105 1 .106 1 .10740

20

0

20

40

60

fc=320kHz

1 .103 1 .104 1 .105 1 .106 1 .107400

300

200

100

09

6

0

80º

1 .103 1 .104 1 .105 1 .106 1 .107400

300

200

100

09

6

0

80º 100mV

100A

Vo

Io

100mV

100A

Vo

Io


27

To achieve 350kHz control bandwidth, a 2MHz VR is required, assuming the bandwidth is

one-sixth of the switching frequency. The efficiency of a 2MHz single-stage VR is only about

75%, so it is not applicable. Figure 2.6 shows the two-stage architecture. The first stage

efficiency is about 97%, and the second stage efficiency is as high as 89% with 2MHz switching

frequency due to the low input voltage (5V). Figure 2.7 shows that a 2MHz two-stage VR can

achieve even higher efficiency than a 1MHz single-stage VR.

Figure 2.6 Two-stage VR with buck as the first stage [22]

Figure 2.7 Overall efficiency comparison between single-stage and two-stage VRs [22]

Figure 2.8 shows the cost comparison between the single-stage VR and the two-stage VR.

The two-stage VR can save about 5% of the cost when compared with the single-stage VR. We

can thus conclude that the two-stage approach is a more cost-effective solution and a promising

candidate for desktop voltage regulators.

Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…


CbusQ12Q11

300~500KHz


Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…


Co RLQ2Q1 io1

Q4Q3 io2

Q6Q5 io3

io

…


CbusQ12Q11

300~500KHz


CbusQ12Q11

300~500KHz


CbusQ12Q11

300~500KHz


System Efficiency Comparison

76

78

80

82

84

86

88

90

0 20 40 60 80 100 120

Io (A)

Effic

ienc

y (%

)

Single stage @ 1MHz Two stage @ 2MHz and Vbus=5V


28

Figure 2.8 Cost comparison between single stage and two-stage VRs [22]

2.2.2. Two-Stage VR for Laptop Computers

The requirement for laptop VRs is different from the requirement for desktop VRs. Since

the laptop VR is used in portable devices, the size and the weight are very important, which

implies that VR should run at a high switching frequency. At the same time, since the laptop VR

is powered by batteries on the road, the efficiency is very important to extend the battery life.

However, the laptop VR has a very wide input voltage range (8.7V-19V) to cover both the

adapter voltage and battery voltage, which makes it even more challenging than the desktop VR

with the input voltage range of 12V±10%. From both power density and efficiency points of

view, a single-stage VR is not a good solution for laptop VRs.

To achieve both high efficiency and high power density with a wide input voltage range,

the two-stage VR is proposed for laptop applications [23], with the configuration shown in

Figure 2.9. Compared with the two-stage approach in desktop applications, the only difference is

the wide input voltage range. Since the laptop computer has a much wider input range, it is more

desirable to regulate the bus voltage, which makes the second stage easier and more efficient.

Figure 2.9 The two-stage architecture in laptop computer application with wide input range [23]

$0.00

$0.50$1.00

$1.50$2.00

$2.50$3.00

$3.50

Controll

er

Top F

ET

bot F

ET

Cer Cin

Driver

Lout Lin

Os-con (

560uF

/10m)

Decoupli

ng ca

p

First s

tage

S ingle s tageTwo s tage VR

C busVin Q12Q11

Co RLQ2Q1

Q4Q3

Q6Q5

L

L

LRegulated, low fs 1st stage

High fs2nd stage

~5V

8.7~19V


29

One more benefit from the two-stage VR is that the bus voltage (input voltage for the

second stage) can be optimized to get higher light-load efficiency. Reference [22], [23] proposed

an ABVP concept to improve the two-stage efficiency under light load conditions. The basic idea

is to reduce the bus voltage under light load conditions to reduce the switching-related losses of

the second stage. The analysis shows a trend that when the load is lighter, the optimal bus

voltage is lower. As discussed previously, the optimal bus voltage is around 5-6V under heavy

load; under light load, the optimal bus voltage gradually decreases. Based on this, the control

strategy is illustrated in Figure 2.10.

Figure 2.10 The CPU power consumption and the bus voltage following ABVP control strategy [23]

Figure 2.11 The transient waveforms of output

current, output voltage and bus voltage [22]

Figure 2.12 The efficiency improvement by ABVP

control strategy [23]

Time

CPUPower

C0 C0

Time

Vbus

C1C2C3C1C2C3

C1C2C3C1C2C3

C1C2C3C1C2C3

Vbus

Vo

Io

1V

20mV

20ATwo-stage With ABVPTwo-stage With ABVP

Vbus=3V Vbus=6V

1MHz Two-Stage VR Efficiency

10 20 30 40 50Output Current (A)

50%

60%

70%

80%

90%

0

Effic

ienc

y

(With Gate Drive Loss)

Two-stage w/o ABVP

Single stage

1MHz Two-Stage VR Efficiency

10 20 30 40 50Output Current (A)

50%

60%

70%

80%

90%

0

Effic

ienc

y

(With Gate Drive Loss)

Two-stage w/o ABVP

Single stage

Vbus=3V


30

A prototype has been built to verify the feasibility of this concept [22]. The input voltage is

12V. The output voltage transitions from 1.28 to 1.3V as the load jumps from 0 to 20A. The bus

voltage varies from 4.2 to 5.3V as the load changes from 20A to 0A. The inductance of the first

stage is 10uH. The inductance of the second stage is 300-nH for each phase. The first-stage

switching frequency is 200kHz and that of the second stage is 1MHz. The bus capacitance is

1mF and the output capacitance is 1mF. Figure 2.11 shows the experimental waveforms. It can

be seen that the bus voltage jumps from 4V to 5V as the output current transitions from 0A to

20A. Both ABVP and AVP functions are realized. The experimental efficiency in Figure 2.12

indicates that the ABVP concept is able to improve the efficiency throughout the whole load

range. The improvement is more significant at lighter loads.

2.3. Possible Improvement for Two-Stage VR

In the previous two-stage research, a buck converter was proposed for the first stage, as

shown in Figure 2.6 and Figure 2.9. It is configured to run at a low switching frequency, e.g. a

couple hundred kHz, to attain high efficiency. However, this low switching frequency is the first

stage to a large size, and counteracts the space savings of the high-frequency second stage. As

we know, high power density is very important for server and laptop applications. Figure 2.13

shows two different VR designs in the two-stage approach. One is the version for a desktop or

laptop, the other is the VRM version for a server. It can be clearly seen that the first stage has a

size similar to the second stage. Detailed analysis reveals that the two-stage approach with a

buck converter as the first stage cannot cause too much size reduction.

(a) 120W two-stage VR for desktop (b) 130W two-stage VRM for server

Figure 2.13 First stage in two-Stage VR

500KHz 1st Stage

Industry Design for 1U VRM

Both sides are used for 1st stage


31

Another problem of using a buck converter in the first stage is its poor light-load efficiency

[22], as shown in Figure 2.14. Even with pulse-skipping control [28] to improve light-load

efficiency, the light-load efficiency is still not that high. Since the first stage is in series with the

second stage, the low light-load efficiency of the first stage causes low light-load efficiency in

the overall system directly. Figure 2.15 shows that due to the low light-load efficiency of the first

stage, the two-stage overall efficiency at light load is even lower than the single stage approach.

This is not acceptable since light-load efficiency becomes more and more efficient. As a result,

this chapter explores more candidates for the first stage.

Figure 2.14 The experimental efficiency of the 1st stage.

Solid line: constant frequency

Dash line: Pulse-skipping @ DCM

Figure 2.15 Overall efficiency comparison between

single stage and two-stage @ 1MHz [22]

As for the second stage, since the input voltage is about 5V-6V, low-voltage-rating devices

(20V or lower) can be used. References [22]and [23] do not pay too much attention to low-

voltage-rating devices since such devices were not popular at that time. In Chapter 3, a number

of low-voltage-rating devices are evaluated and the efficiency benefits are proven by

experimental tests. Moreover, some methods are proposed to improve the light-load efficiency of

the second stage, which are also discussed in Chapter 3.

2.4. Proposed Switched-capacitor Voltage Divider as the First Stage

2.4.1. Basic Switched-Capacitor Circuits

As stated above, using a buck converter in the first stage is too bulky due to the large

output inductors. To get a high power density, it is better to have no inductors in the circuit. Thus

we looked into a switched-capacitor technology where capacitors are used as the energy transfer.

92

93

94

95

96

97

98

0 5 10 15 20 25 30

Output Current (A)

Effic

ienc

y

92

93

94

95

96

97

98

0 5 10 15 20 25 30

Output Current (A)

Effic

ienc

y

System Efficiency Comparison

828384858687888990

0 20 40 60 80 100 120

Io (A)

Effic

ienc

y (%

)

Single stage @ 1MHz Two stage @ 1MHz and Vbus=5V


32

Figure 2.16 shows a typical switched-capacitor converter [29]. When S1 and S2 are on, the

input voltage source charges C2 while Co provides the energy to the load. Assuming that the R

and C2 time constant is much smaller than half of the switching period, C2 is charged to Vin.

When S3 and S4 are on, C2 charges both Co and the load. Finally, C2 is discharged to Vo. Since

the output voltage is regulated, there should be some voltage difference between Vin and Vo. At

the moment when S3 and S4 turn on, the voltage difference between C1 and Co is (Vin-Vo).

Therefore a large R is required to limit the current and protect the devices. The output voltage is

controlled by controlling the power loss in the devices. Larger losses lead to lower output

voltage. Since R must be high enough to serve as the buffer between two voltage sources, the

current cannot be very high. The efficiency of this converter can be simply calculated by Vo/Vin,

and Vo is always lower than Vin. A larger voltage difference between Vin and Vo leads to lower

efficiency. This is why it can only be used in low-power applications.

Figure 2.16 A typical switched capacitor converter for low power application

Another type of switched-capacitor converter is shown in Figure 2.17 [30]. When Q1 and

Q3 are on, Q1 is controlled as a current sink to limit the current. So if we look at the equivalent

circuit, it is like a current-fed circuit during this period. When Q2 and Q4 are on, since there is a

voltage difference between C2 and Co, a large R must be presented to limit the current. The

output voltage can be simply expressed as:

Vin

‐Vo

S1

S2

S4

S3

C2

Co RL

RLVinC2

S1,S2 on, S3, S4 off

+_ +

_

RLVin

C2

S3,S4 on, S1, S2 off

+_

+_

R R

Co Co


33

Lono RDIV 2= (2-1)

where D is the duty cycle of Q1 and Q3. The efficiency of this circuit is 2Vo/Vin [30]. Again, if Vo

is much less than Vin/2, the efficiency is very low.

Figure 2.17 Another switched-capacitor converter with current sink

From the above two examples, a basic concept of switched-capacitor technology can be

generalized. Figure 2.18 shows the case of two capacitors in parallel with a switch. As we know,

two capacitors cannot be in parallel directly if there is a voltage difference between them.

Therefore, there should be some mechanism to limit the current. As shown in Figure 2.18, there

are at least three cases when two capacitors can be in parallel without a high surge current:

(1) Resistance R is large to limit the current when the voltage difference is large;

(2) S1 serves as a current sink to limit the current when the voltage difference is large;

(3) Resistance R can be small if the voltage difference between C1 and C2 is small.

It can be seen that the first two cases have higher power loss but they can achieve voltage

regulation. The power loss of the third case is small but it cannot achieve voltage regulation.

‐

+

Q1

Q2

Q3

Q4

Vin

Vo

C2

Co RL

RLVin

C2

Q1,Q3 on, Q2, Q4 off

RLVin

C2

Ion R

Co

+ ‐+‐


Co


34

(a) (b) (c)

Figure 2.18 Equivalent circuit for two capacitors in parallel

2.4.2. Proposed Switched-Capacitor Voltage Divider

For the two-stage power architecture, since the second stage can achieve voltage

regulation, the first stage can be unregulated as long as it can lower the input voltage from 12V

to the 5V-6V range. This converter can be treated as a non-isolated bus converter. As a result, it

is possible for us to use a switched-capacitor circuit with the concept shown in Figure 2.18(c) to

get lower power loss. Figure 2.19(a) shows the concept of the proposed voltage divider. The key

is that Q1-Q4 have very low on-resistance and the output voltage is unregulated. By careful

design, the voltage on capacitors C2 and Co are almost half of the input voltage, so there is a very

small voltage difference between their capacitances. A 50% duty cycle for all switches is

applied. An improved version is shown in Figure 2.19(b), where Co is split into C1 and C3. The

output ripples are the same as long as Co is equal to the sum of C1 and C3. However, C1 also

serves as the input decoupling capacitor. Since C1 provides the AC current path, the real

decoupling capacitor for the Vin can be reduced. Also the voltage rating of C1 is only half of the

input voltage, which can decrease the converter size.

+‐

V1

+‐

Large R

V2

Ion

+‐

V1+‐V2

V1‐V2 is large V1‐V2 is large

+‐

V1

+‐

Small R

V1‐V2 is small

V2


35

(a) Concept of the proposed voltage divider

(b) Improved version of voltage divider

Figure 2.19 Proposed switched-capacitor voltage divider

Recently, another switched-capacitor circuit with a similar concept has been proposed [31]

for high-output power automotive applications. As shown in Figure 2.20, since there are both a

42V battery and 14V battery in the system, a bi-directional DC/DC converter is required to

power both the 42V loads and 14V loads. It can be seen that there are no voltage regulation

function required for the system.

‐

+

Q1

Q2

Q3

Q4

Vin

Vo

C2

Co RL

Vgs 50%Duty Cycle

Q1 & Q3

Q2 & Q4

t0 t1 t2 t3 t4 t5

Vgs 50%Duty Cycle

Q1 & Q3

Q2 & Q4

t0 t1 t2 t3 t4 t5

RLVin

C2


RLVin

C2Co

+ ‐+‐


Co

Small R Small R

‐

+

Q1

Q2

Q3

Q4

Vin

Vo

C2

C3 RL

C1


36

(a) Four-level DC/DC converters with switched-capacitor technology

(b) Equivalent circuit for each stage

Figure 2.20 Switched-capacitor converters for high power application [31]

Figure 2.20(b) shows the equivalent circuit for each stage, where R1 is the total resistance

in the loop. To deliver more current, R1 and R2 must be very small. To limit the current, the

voltage difference between C1 and Vo must be very small. This can be controlled by selecting

large C1 and C2. C1 is almost the same as Vo, while C2 is almost 2Vo. Finally, the ratio between

Vin and Vo is about 3:1. There is small voltage difference which depends on the load current.

The problem with this circuit design is that the switching frequency is too low (5kHz) since

the author does not analyze the switching performance of this circuit very carefully. As a result,


37

there are too many capacitors needed to limit the current in the circuit which counteracts the size

saving by eliminating the magnetic components, as shown in the prototype in Figure 2.21.

Figure 2.21 Prototype of the four-level switched-capacitor DC/DC converter and tested efficiency [31]

(fs = 5kHz, C1: 10*3300µF/7m electrolytic capacitors and C2: 10*2200µF/12m electrolytic)

2.4.3. Challenges for the proposed voltage divider

(A) Minimize the power losses and achieve highest efficiency

Previously, some methods are used to analyze and design the switched-capacitor circuits.

For example, the state-space averaging method is used in [30] and the time-domain analysis

method is applied in [32]. However, there are some limitations for the previous methods.

• Since most of them are designed for the regulated converters, the efficiency is well

determined by the ratio between the output voltage and the input voltage. As a result,

they did not pay attention to the power loss analysis for the switched-capacitor circuit.

• Most of the methods neglected the switching losses in the circuit.

• All of the methods neglected the influence from the parasitic inductors.

As we know, high efficiency must be achieved for the first stage of two-stage VR, so the

power losses must be analyzed for the proposed voltage divider. Moreover, switching losses can

be very high without very careful design due to the parasitic inductors. All of the above issues

are solved with the detailed analysis in the following sections.

(B) System design consideration with voltage divider as the first stage

Since the voltage divider is used as the first stage and it can be followed by several

different second stages, two important concerns emerge. The first is the stability of the whole


38

system. The second concern is how the bus voltage, which is the output voltage of the voltage

divider, responds to the VR load transient. If the bus voltage changes a lot with one VR load

transient, it may cause undesirable voltage noise with other VRs.

(C) Start-up and protection of the voltage divider

As mentioned above, at steady state, since Vc2,Vc1 and Vc3 are very close, the current on

devices is relatively small. However, at startup and fault operation, the voltage difference

between capacitors is very large, which causes a huge surge current on the devices. So some

actions must be taken for start-up and protection.

2.4.4. Minimizing Power Losses by Circuit Analysis and Design

To simplify the design, the parasitic inductors in the circuit are firstly ignored. The power

loss model with parasitic inductors will be introduced later.

(A) Switching loss analysis

Compared to the buck DC/DC converter, the proposed circuit has the following advantages

in terms of the switching performance:

• All switches can be turned off in a zero voltage condition (ZVS)

Figure 2.22 (a) shows the turn-off of Q1 and Q3. Since there is no current charging the

junction capacitor of Q3, the Vds stays at zero after it turns off. The Q1 voltage also stays at

zero. This means Q1 and Q3 turn off with zero voltage. There is no turn-off loss for the

switches. The same conclusion applies for Q2 and Q4.

(a) Turn-off of Q1 and Q3 (b) Turn-on of Q2 and Q4

Figure 2.22 Switching performance of switched-capacitor voltage divider

Vin

Q1

Q2

Q3

Q4

C4

C2

Vin

Q1

Q2

Q3

Q4

I O

C2

C4

IC2

Vin

Q1

Q2

Q3

Q4

I O

C2

C4VinVin

Q1

Q2

Q3

Q4

I OI O

C2

C4

IC2


39

• All switches can be turned on in a zero current condition (ZCS)

Figure 2.22(b) shows the turn-on for Q2 and Q4. Since the voltage difference between C2

and C4 is very small, the current on Q2 and Q4 is almost zero before their on-resistance drops to

a very small value. This means Q2 and Q4 turn on with zero current. However, there is

capacitive turn-on loss for the switches. The total turn-on losses of the four switches are:

sineqonturn fVCP 2_ = (2-2)

where Ceq is the energy equivalent capacitance of each MOSFET with half of the input voltage.

• There are no body diode conduction losses.

Because there is no inductor and its current is freewheeling, the body diode of the device

will not conduct during the dead time, which is normally reserved in the gate driver to avoid the

short-through among the switches in the totem-pole structure.

(B) Conduction Loss Analysis

To simplify the deviation for the conduction, the parasitic inductors and the ESR of the

capacitors are ignored. The resulting equivalent circuit is shown in Figure 2.23, where RDSon is

the on-resistance of each MOSFET. Since the switching loss of the voltage divider is

minimized, now we would like to know how to calculate the conduction loss of the circuit.

Figure 2.23 The equivalent circuit of the voltage divider

C3

iC2

R=2RDSon

Io

C1C2

+vc2_

+vc1_+

Vin

_ C3

iC2

R=2RDSon

Io

C1

C2

+vc2_

+vc1_

+

Vin

_

0~Ts/2 Ts/2~Ts

C3

iC2

R=2RDSon

Io

C1C2

+vc2_

+vc1_+

Vin

_ C3

iC2

R=2RDSon

Io

C1C2

+vc2_

+vc1_+

Vin

_ C3

iC2

R=2RDSon

Io

C1

C2

+vc2_

+vc1_

+

Vin

_

0~Ts/2 Ts/2~Ts


40

To derive the RMS current on C2, the voltage on C2 must be solved first. Since the circuit is

symmetric during the 0-Ts/2 period and the Ts/2-Ts period, the solution during 0-Ts/2 is provided

as the example.

The voltage on C2 during 0-Ts/2 can be easily solved as:

2/

12 )( ktBektv tc +⋅+= − τ

(2-3)

where k1 and k2 are variables which are to be determined, and B and τ are:

321 CCCIB o

++=

321

231 )(CCCCCCR

+++

⋅=τ

(2-4)

Due to the charge balance, the average absolute current on C2 is Io. Then:

2

2/

02

2222 2

)(2/)0()2/(CITdtti

CTvTvV os

T

Cs

cscc

s

∫ ==−=Δ (2-5)

During 0-Ts/2:

ocinc viRVv −⋅−= 22 (2-6)

During Ts/2-Ts:

22 coc iRvv ⋅−= (2-7)

Then:

∫ ∫∫ ∫

∫ ∫∫

+−=+−+=

⋅−+−⋅−==

2/

0 2/

2/

0 2/)(2

2/

0 2/22

02)(2

22

])()([11

s s

s

s s

s

s s

s

s

T T

Too

inT T

Tooavgc

in

T T

Tcoocin

s

T

cs

avgc

dtvdtvVdtvdtvIV

dtiRvdtviRVT

dtvT

V

(2-8)

Due to the symmetry of the circuit:

∫∫ ==s

s

s T

To

s

T

os

oavg dtvT

dtvT

V2/

2/

0 2/1

2/1 2

(2-9)

Then:


41

2)(2in

avgcVV =

(2-10)

From (2-5) and (2-10), two boundary conditions for vc2 can be derived (For the curve as

(2-3), the average voltage is in the middle of the peak-to-peak voltage):

2

22 42

)0(CITVv oin

c −= 2

22 42

)2/(CITVTv oin

sc +=

(2-11)

From (2-3) and (2-11), k1 and k2 can be derived as:

ACITV

kAk oin −−==2

221 42

,

(2-12)

where

1)(22

)2/(3212

−++

−=

− τsT

soso

eCCC

TICTI

A

(2-13)

Finally, the current on C2 during 0-Ts/2 period can be expressed as:

)()( /22 BeACti t

c +−= − τ

τ (2-14)

The RMS current can be calculated as

(2-15)

After vc2 is solved, vc1 and vo can be solved correspondingly. This completes the analytical

solution of the proposed voltage divider.

The peak and RMS current on each MOSFET is:

)(2 BACI peak +−=τ

2/2RMSQRMS II =

(2-16)

s

TT

RMS T

eAeABBCI

ss )1()1(4 /2

)2/(

222

−−−+=

−− ττ

τ


42

To normalize (2-15), we define:

oRMSN III /22 = sN T/ττ = )/( 312 CCCkN += (2-17)

Substituting (2-17) into (2-15), the normalized RMS current on C2 can be expressed as:

2/5.0

/12

22 )1(1)]1/(5.0[

)1()2(

−−+

++

+=

−

−

N

N

eek

kkk

IN

N

N

NNN τ

τ

τ

(2-18)

Because the average currents of C1 and C3 are zero, the output DC current has to be equal

to the sum of the currents of Q2 and Q3. It can be easily seen that the current of C2 is rectified by

Q2 and Q3 as the DC output current. Therefore,

oavg

II =2 (2-19)

Due to the charge balance of C2, the positive area of the current of C2 should be equal to its

negative area. According to (2-19), the average amplitude of either positive or negative current

pulse should be Io. It is known that Q1 conducts the positive current pulse of C2 in 50% duty

cycle, so the average input current should be:

2/oin II = (2-20)

.Based on the conservation of energy, the output voltage can be calculated with:

o

swrmsino I

PRIVV +−=

22

2 (2-21)

where Psw is the total switching-related loss, which could be limited to a tiny level by the

appropriate capacitor design.

2.4.5. Design of C1, C2 and C3

Capacitor C2 needs to be large enough to limit the peak current when the capacitors are in

parallel, as shown in Figure 2.24.


43

Figure 2.24 Peak current on MOSFET vs. C2 (R = 6mΩ, fs = 375kHz, Io = 12A)

Since the switching-related losses of the proposed voltage divide can be small enough to be

ignored, the MOSFET conduction losses are the only concern for efficiency in this area. Using

(2-18), Figure 2.25 shows the relationship of I2N with kN and τN. It is clearly shown that larger kN

or larger τN leads to lower RMS current. If kN and τN are determined, C2 and C1+C3 can be

determined as follows:

R

TkC sNN )1(

2+

=τ

RkTk

CCN

sNN )1(31

+=+

τ

(2-22)

(a) Normalized C2 RMS current I2N vs. kN (b) Normalized C2 RMS current I2N vs. τN

Figure 2.25 C2 RMS current vs. kN and τN

5.10 5 1.10 4 1.5.10 40

20

40

60

80

100

)

C2 (µF)I p

eak(A

)

τN increasesτN increaseskN increaseskN increases


44

Figure 2.26 C2 RMS current vs. kN for different C2 (each curve corresponds to one C2 value)

It is preferable that both kN and τN be large, whereas a large kN and τN require large

capacitors for C1 through C3, which means a large footprint and high cost as well. The trade-off

between the RMS current of C2 and total capacitance can be done in two ways: one is a large kN

and low τN, the other is low kN and large τN. Both of them can set the RMS current in the vicinity

of the minimum value.

Given (kN+1)* τN, C2 can be determined by Equation (2-22). Figure 2.26 clearly shows

how the RMS current C2 is impacted by kN for a given C2. A large C2 can greatly diminish the

effect of kN on the RMS current. Consequently, it is proposed that C2 be designed with a large

enough capacitance for high efficiency being the foremost consideration. After that, C1+C3 can

be determined taking other factors into consideration.

Normally C1 and C3 can be selected with consideration of output voltage ripple and input

AC current. Figure 2.27(a) shows an example of the influence of the C1+C3 on the output voltage

ripple. A proper C1+C3 should be selected to meet the ripple requirement. Figure 2.27(b) shows

an example of the influence of C1 on the input AC RMS current. An optimal C1 will give the

lowest input AC current.

For better understanding, a design example is shown as below.

Circuit configuration is: Vin=12V, Iomax=12A, R = 6mΩ (Device: Si7104), fs = 375kHz.

1 1.5 2 2.5 3 3.5 4 4.5 50.9

0.95

1

1.05

1.1

1.15I2N kN0.2

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.3

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.4

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.5

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.6

kN 1+,⎛

⎜⎝

⎞⎟⎠

kN

C2 increases

1 1.5 2 2.5 3 3.5 4 4.5 50.9

0.95

1

1.05

1.1

1.15I2N kN0.2

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.3

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.4

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.5

kN 1+,⎛

⎜⎝

⎞⎟⎠

I2N kN0.6

kN 1+,⎛

⎜⎝

⎞⎟⎠

kN

C2 increases


45

First, it is determined that kN=1.2 and τN=0.15 to achieve low RMS current and output

ripple. Then, from Equation (2-22) we see that C2 is equal to 130µF, and C1+C3 is 90µF. To

achieve the lowest input AC current, C1=45µF; then C3 = 45µF.

Finally the RMS current on each capacitor should be checked to decide how many

capacitors must be paralleled to satisfy the current rating requirement of each capacitor. Based

on calculations, the maximum RMS current for the three capacitors are:

I1RMS = 3A, I2RMS = 13A, I3RMS = 3A

Generally, low-ESR capacitors such as the multi-layer ceramic capacitor (MLCC) are

preferred for the proposed voltage divider, which can reduce the power losses of the capacitors.

Each 22µF TDK ceramic capacitor has a 2A RMS current capability. Two paralleled 22µF

capacitors are used for C1 or C3. For C2, six paralleled 22µF capacitors are needed.

(a) (b)

(a) Normalized Vo ripple vs. kN ((kN+1)τN=0.35, Io=12A)

(b)Normalized Input AC RMS current vs. C1/(C1+C3) (kN=1.2, 　τN = 0.14, Io = 12A, Iin = 6A)

Figure 2.27 Output ripple and input AC current vs. C1 and C3

2.4.6. Light-Load Efficiency and Gate-Driving Method

(A) Light-Load Efficiency

After the capacitor design is finished, τΝ and kN are determined. Then τN =τ*fs is

proportional to the switching frequency. Figure 3.24 shows that the lower the τN is, the higher the

kN

V orip

ple

/ Vo

kN

V orip

ple

/ Vo

C1/(C1+C3)

I inA

C/ I

in

C1/(C1+C3)

I inA

C/ I

in


46

C2 RMS current will be. This means that for a given load current, a lower frequency means a

higher conduction loss. Thus at heavy load, a higher frequency is needed. However, a lower

frequency also leads to lower gate driver loss, which is normally the dominant loss at light load.

Thus, lowering the switching frequency at light load can improve the light-load efficiency of the

proposed voltage divider. Figure 2.28(a) shows a batch of efficiency curves at different

frequencies. If the peak efficiency points of those curves are connected, an optimal efficiency

curve can be achieved by varying the switching frequency in respect to the load current, as

shown in Figure 2.28(b).

(B) Gate Driving Method

As mentioned above, there is not a stringent demand on gate driving for the devices. As a

result, the most cost-effective way of driving the devices is to use a driving transformer. In low-

voltage applications, the commercial boost trap gate driver IC can be utilized for concise

circuitry. Figure 2.29(a) shows the driving schematic. Two gate driver ICs are used to drive the

four MOSFETs. A boost trap scheme is used to get the PWM input signal for the upper two

MOSFETs. The voltages on C1 and C3 can also be utilized as the voltage sources of the gate

driver. Figure 2.29(b) shows the test gate signals for the proposed gate driving when Vin=12V

and Io=10A. It shows that the proposed gate driving works very well.

(a) Efficiency vs. Io for different frequencies

97.8%

98.0%

98.2%

98.4%

98.6%

98.8%

99.0%

0 5 10 15

Effic

ienc

y

Io (A)

300k

250k

200k

150k

100k

50k

fs decreases


47

(b)Boosting light-load efficiency by lowering switching frequency at light load

Figure 2.28 Light-load efficiency improvement for proposed VD

(a) Driving scheme (b)Tested gate signals

Figure 2.29 Proposed gate driving for VD

2.4.7. Prototype

One prototype has a 12V input with 6V/12A output for laptop applications. The

prototype has achieved 1kW/inch3 power density. For reference, Table 2.1 gives the component

90%91%92%93%94%95%96%97%98%99%

100%

0.1 1 10 100

Effic

ienc

y

Po (W)

Variable frequency

fixed frequency

Vin

Q1

Q2

Q3

Q4

VinVin

Q1

Q2

Q3

Q4

Vgs_Q4

Vg_Q1

paramete

which ha

Ca

The

efficiency

divider i

capability

C

ers. Since the

as better perf

Switching

apacitance of

Switches

Dri

Figu

e overall eff

y with 70W

is that it ha

y due to indu

9

9

9

9

9

9

9

9

9

9

1

Effic

ienc

y

Chapter 2. H

e voltage rat

formance tha

Table 2.1 Pa

frequency

f C1, C2 and

s, Q1~Q4

iver

(b) Tes

ure 2.30 Prot

ficiency is g

W output po

as very good

uctor core sa

90%

91%

92%

93%

94%

95%

96%

97%

98%

99%

00%

0.1

High Power De

ting for the d

an 30V MOS

arameters in t

C3

(a) Prototyp

sted efficiency

otype and effi

given in Fig

ower. One

d over-powe

aturation wit

1

variable frfixed frequOver powe

ensity Non-Is

48

devices is ha

SFET is app

the 70W Volta

C1, C3: 2

12V device

2× LM

pe of 70W vol

y (including ov

iciency of 70W

ure 2.30(b).

more benef

er capability

th high curre

Po (W)

requencyuencyer

olated Bus Co

alf of the inp

lied this volt

age Divider pr

375k

22µF MLCC

: Vishay Si7

2722, Nation

ltage divider

ver power effi

W voltage divid

It can be s

fit from the

y. However,

ent.

10

onverters

put voltage,

tage divider

rototype

kHz

C C2: 6 22µF

7104 (Rdson =

nal Semicon

iciency)

der for laptop

seen that it c

e switched-c

, buck has p

100

a 12V MOS

.

F MLCC

= 3.1mohm)

nductor

can achieve

capacitor vo

poor over-p

SFET

high

oltage

power


49

Another prototype has a 12V input/6V 25A output for server VR application. The circuit

parameters are shown in Table 2.2. Figure 2.31 shows the prototype and tested efficiency. The

power density is also about 1kW/in3.

Table 2.2 Parameters in the 150W Voltage Divider prototype

Switching frequency 350kHz

Capacitance of C1, C2 and C3 C1, C3: 2 44µF MLCC C2: 10 22µF MLCC

Switches, Q1~Q4 12V device: Ciclon 13301 (Rdson=1.3mΩ)

Driver 2× LM2722, National Semiconductor

(a) Prototype

(b) Tested efficiency

Figure 2.31 Prototype and efficiency of 150W voltage divider for server

95.5%

96.0%

96.5%

97.0%

97.5%

98.0%

98.5%

99.0%

99.5%

10 100

fixed frequency

variable frequency

Effciency

Po (W)


50

2.4.8. Effect of Parasitic Inductors for High Frequency Operation

If we look at the previous 375kHz 70W voltage divider design for laptops [33], [36], we

see there is too much capacitance (C1 = C3 = 44µF, C2 = 132µF), which adds more cost and a

larger footprint. In a 150W voltage divider design, the capacitance is even larger. Ideally, there is

no switching-related loss for the voltage divider except for capacitive turn-on loss. To keep the

same RMS current on devices (parasitic inductance is ignored), we should have:

sfC /12 ∝ (2-23)

where fs is the switching frequency. This clearly shows that the capacitance can be reduced by

raising the frequency of voltage divider.

The previous analysis does not include parasitic inductors since it works at a low switching

frequency and C2 is pretty large. It is a simplified first-order model. In the real circuit, there is

parasitic inductors, such as the inductor ESL, trace inductors, device parasitic inductors, etc., as

shown in Figure 2.32(a). Figure 2.32(b) shows the moment when Q2 and Q4 turn off, where Lp is

the total parasitic inductance in the loop. Then the total energy of the parasitic inductors when Q2

and Q4 are turned off is:

25.0 offpL ILE =

(2-24)

The following analysis focuses on the device packaging inductors [37]. Part or all of the

energy can be dissipated in the loop, which introduces turn-off loss. When the switching

frequency becomes high, the turn-off loss caused by parasitic inductors becomes high

correspondingly, and can no longer be ignored.


51

(a) Parasitic inductance in the voltage divider (b) Equivalent circuit when Q2 and Q4 are turned off

Figure 2.32 The influence from the parasitic inductors

After considering the parasitic Lp, the loss breakdown of the voltage divider at different

frequencies is obtained by SABER simulation, as shown in Figure 2.33. It clearly shows that at

low frequencies, switching loss is negligible, while at high frequencies, switching loss can be

very high. Another interesting phenomenon is that at high frequencies a higher C2 does not mean

lower loss, which cannot be predicted by the previous first-order model.

After considering the parasitic Lp, the proposed voltage divider is similar to the resonant

switched-capacitor converter [38] or three-level buck converter [39]. However, since the

parasitic inductors cannot be simply treated as the lumped inductance for the entire transition

time, it is more complex and the efficiency cannot be easily predicted.

(a) Switching frequency = 330kHz

(b) Switching frequency = 1MHz

Figure 2.33 Loss breakdown of voltage divider (Vin = 12V, Po = 70W, Lp = 3nH)

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

C1

C3

C2

Ld

Ls

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

-

+

VOVOVOVO

VinVin

Q1

Q2

Q3

Q4

C1

C3

C2

Ld

Ls

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

Ioff Lp

Coss

-

+

VOVOVOVO

VinVin

Q1

Q2

Q3

Q4

Ioff Lp

Coss

0

0.5

1

1.5

2

2.5

Total conduction

loss

Total switching

loss

Gate driving loss

Total loss

Loss

(W)

C2=66uFC2=132uF

00.5

11.5

22.5

33.5

Total conduction

loss

Total switching

loss

Gate driving loss

Total loss:

Loss

(W)

C2=10uFC2=44uF


52

With some assumptions, the switching losses and conduction losses can also be estimated

for the voltage divider with parasitic inductance. The assumptions are:

1) The loop inductance when Q1 and Q3 are on is the same as the loop inductance when Q2

and Q4 are on. When this is true is the device parasitic inductance (Ld+Ls) is dominant.

2) The inductance is small enough that the energy in the inductor is dissipated in the loop

when the devices are turned off. As a result, the current is zero when the switches are

on.

3) The output capacitance is large enough that it can be treated as a voltage source.

Based on the above assumptions, the equivalent circuit can be drawn as Figure 2.34. Since

the circuit is symmetrical, the solution for 0-Ts/2 is given in the following analysis.

Figure 2.34 The equivalent circuit of the voltage divider with parasitic inductance

Since the equivalent is a typical second-order system, the solution can be easily solved with

the following boundary conditions:

22 42

)0(CITVv osin

c −= 2

2 42)2/(

CITVTv osin

sc += 0)0( =Li (2-25)

The final solution for the C2 voltage within half of the switching cycle is:

(a) When 0)(4 222 >− RCCLP

C2

LP

Vin

Vo

Io

+_vc2

iL

C2

LP Vo

Iovc2

iL

+_

0~Ts/2 Ts/2~Ts

R


53

ointt

C VVteAteAtv −++= −− )cos()sin()( 212 ωω αα

1)2

cos()2

sin(

2/

22

22

−+=

−− ss T

s

T

s

os

eTeT

CITA αα ωωωα

ω

α21

AA =

24 22

inoso

VCITAV ++=

where )2/( PLR=α , and 2

222

2)(4

CLRCCL

P

P −=ω

.

(2-26)

(b) When 0)(4 222 <− RCCLP

ointftf

C VVeAeAtv −++= 21212 )(

122/2/

22 /)1(1

2/12 ffee

CITAss TfTf

os

−−−=

1

221 f

AfA −=

24)1(

21

22

inoso

VCIT

ffAV ++−=

where

2

22

22

24)(

1CL

CLRCRCf

P

P−+−= ,

2

22

22

24)(

2CL

CLRCRCf

P

P−−−=

(2-27)

Based on (2-26) or (2-27), the inductor current can be derived by:

)()( 22 tVdtdCti CL = (2-28)

The shape of the inductor current during half of the switching period is shown in Figure

2.35. It clearly shows that with a smaller C2, both turn-off current and RMS current are high.

With a larger C2, the RMS current can be reduced. However, the turn-off current is high. It

seems there should be an optimal C2 for each switching frequency.


54

Figure 2.35 Inductor current with different C2 for half of the switching period

( fs = 650kHz, Lp = 3nH, R = 6mΩ, Vin = 12V, Io = 12A)

With (2-28) and the circuit condition, the conduction losses and switching losses can be

estimated as follows:

2RMScond IRP ⋅=

soffpsineqsw fILfVCP 22 +=

∫=2/

0

2)(2 sT

Ls

RMS dttiT

I , )2/( sLoff TiI =

(2-29)

Figure 2.36 shows the relationship of the switching loss, conduction loss and total power

losses and C2. The minimum switching loss occurs when the resonant frequency of Lp and C2 is

equal to the switching frequency. It shows that there is an optimal C2 that can provide the

minimum total power loss, and the optimal C2 is not necessarily equal to the C2 value where the

switching loss is the minimum.

0 2 .10 7 4 .10 7 6 .10 75

0

5

10

15

20

25

t)

t)

t)

t

Indu

ctor

cur

rent

(A)

Time (s)

C2=40uF

C2=20uF

C2=15uF


55

Figure 2.36 Total power loss vs. C2 for a given switching frequency

( fs = 650kHz, Lp = 3nH, R = 6mΩ, Vin = 12V, Io = 12A)

Figure 2.37 shows the relationship between the total power losses and C2 for different

switching frequencies. It shows that there is a different optimal C2 for different frequencies that

can provide the minimum power loss.

Figure 2.37 Total power loss vs. C2 for different switching frequencies

( Lp = 3nH, R = 6mΩ, Vin = 12V, Io = 12A, driving loss not included)

1 .10 6 1 .10 5 1 .10 4 1 .10 30.1

1

10

)

C2

Pow

er L

oss

(W)

C2 (F)

Total loss

Conduction loss

Switching loss

1 .10 6 1 .10 5 1 .10 4 1 .10 31

10

)

)

C2C2 (F)

fs increases

Pow

er L

oss

(W)


56

Figure 2.38 shows that, as expected, C2 can be reduced by raising the frequency. However,

higher frequency also means higher power loss, so there is a trade-off in design between C2

reduction and voltage divider efficiency. In our design, a 700kHz frequency is chosen as the

starting point for the trade-off. The final frequency is based on the experimental result.

Figure 2.38 Optimal C2 and minimum power loss vs. frequency

( Lp = 3nH, R = 6mΩ, Vin = 12V, Io = 12A, driving loss included)

The above analysis is based on the given device parasitics, Ld = Ls=0.5nH and Lp = 3nH.

Figure 2.39 shows the impact from the different parasitic inductances with 700kHz frequency.

When the inductance decreases, a higher C2 is required to have lower power loss. In terms of C2

reduction, higher parasitic inductance is preferred. However, higher inductance also means

higher power loss, even at the optimal point. Another disadvantage of higher inductance is that

when Lp is higher, power loss is very sensitive to the C2 value. As we know, Lp cannot be

predicted very accurately, and capacitance has a large tolerance. Therefore it is better to decrease

parasitic inductance to minimize the negative effect from the sensitivity of C2.

To minimize parasitic inductance, at least two changes can be made. One is to choose

device packages with lower parasitic inductance, e.g. DirectFET, PolarPak, Powerpak1212, etc.

The other is to improve the PCB layout. Both possibilities need to be considered in real hardware

design.

1.51.71.92.12.32.52.72.93.13.3

020406080

100120140

200 700 1200 1700 2200

C2

(µF

)

fs (kHz)

C2 valuePower loss

Power Loss (W)


57

Figure 2.39 Power loss vs. C2 for different parasitic

Figure 2.40 shows the 70W 650kHz voltage divider for a laptop two-stage VR. Compared

with the 375kHz voltage divider, it doubles the power density (2200W/in3) and has a 47%

footprint reduction and a 70% capacitance reduction. The efficiency is around 97%, which is

only 0.5% lower than the 375kHz design.

Figure 2.40 650kHz, 70W voltage divider prototype and tested efficiency curve

1.3

1.5

1.7

1.9

2.1

2.3

2.5

0 20 40 60 80 100

Pow

er lo

ss (W

)

C2 (µF)

Ld=0.5nH

Ld=0.3nH

Ld=0.1nH

C1=C3=20µF, C2=35µF

375kHz VDFootprint: 1.2cm*2.2cm

Power density: 1000W/in3

C1=C3=44µF, C2=132µF

650kHz VDFootprint: 1.0cm*1.4cm

Power density: 2200W/in3

47% footprint reductionDoubled power density

70% capacitance reduction

94%

95%

96%

97%

98%

99%

100%

0 20 40 60 80

Effic

ienc

y

Po (W)

375kHz650kHz


58

2.5. Transient Analysis of the Proposed Voltage Divider

Since the voltage divider is used as the first stage and it can be followed by several

different second stages, two important concerns emerge. The first is the stability of the whole

system. The second concern is how the bus voltage, which is the output voltage of the voltage

divider, responds to the VR load transient. If the bus voltage changes a lot with one VR load

transient, it may cause undesirable voltage noise with other VRs. A transient analysis is required

to answer the above two questions.

2.5.1. Output Impedance

The most important performance parameter of the voltage divider is its output impedance,

Zo. The circuit necessary to derive the Zo is illustrated in Figure 2.41, where the input voltage is

shortened and Rc1, Rc2, and Rc3 represent the ESR values of the capacitors. Since C1 and C3 are in

parallel, they can be lumped with Co = C1+C3, Ro = Rc1||Rc3, assuming C1 and C3 are the same

type of capacitors. The equivalent circuit is shown in Figure 2.41(b), where R = 2RDSon + Rc2 and

RDSon is the on-resistance of each MOSFET. Normally, R >> Ro and C2 >> Co, so R and Co form

a low-pass filter in the circuit. If the low-pass filter corner frequency is much lower than the

switching frequency, we can apply the state-space average model [41], [42]:

During 0~Ts/2:

ooo

oo

co

c

oooo

oo

co

c iCRRR

CRRRvv

CRRCRRCRRCRR

dtdvdtdv

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+−+⎟⎟

⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛

+−+−+−+−

=⎟⎟⎠

⎞⎜⎜⎝

⎛])/[(

])/[(])/[(1])/[(1])/[(1])/[(1

// 22222

During Ts/2~Ts:

ooo

oo

co

c

oooo

oo

co

c iCRRRCRRR

vv

CRRCRRCRRCRR

dtdvdtdv

⎟⎟⎠

⎞⎜⎜⎝

⎛++

+⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛

+−+++−

=⎟⎟⎠

⎞⎜⎜⎝

⎛])/[(])/[(

])/[(1])/[(1])/[(1])/[(1

// 22222

Averaging the above two states with the same weight yields:

oooco

c

oo

o

co

c iCRRRv

vCRR

CRRdtdvdtdv

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛

+−+−

=⎟⎟⎠

⎞⎜⎜⎝

⎛])/[(

0])/[(10

0])/[(1// 222

(2-30)

Based on the average state equation, the output impedance of the voltage divider can be

easily derived:


59

)(1)1()(oo

ooo RRsC

RsCRsZ++

+=

(2-31)

Figure 2.41 Equivalent circuit to derive output impedance

This model matches very well with the SIMPLIS simulation, which can represent the

experimental result, as demonstrated in Figure 2.42(a). At low frequency, the impedance is

determined by R≈2RDSon. So the output impedance of the voltage divider is very low due to the

low on resistance of the low-voltage MOSFET.

Another interesting phenomenon is that the output impedance is independent of C2 as long

as the state space averaging is applied. This is verified by SIMPLIS simulation, as shown in

Figure 2.42(b).

In a real circuit, since there is parasitic inductance from the capacitor ESL, the device’s

parasitic inductance, PCB trace inductance, etc., at high frequencies the output impedance of the

voltage divider is dominated by the ESL in the circuit, which is shown in Figure 2.42(c).

-

+

VOVO

C2

ZoRc1

C1

Rc3

C3

+-

vC2

Rc2

Q1

Q2

Q3

Q4-

+

VOVO

C2

ZoRc1

C1

Rc3

C3

+-

vC2

Rc2

-

+

VOVOVOVO

C2

ZoRc1

C1

Rc3

C3

+-

vC2

Rc2

Q1

Q2

Q3

Q4-

+

VOVO

R

C2

Ro

Co

+-

vC2

OiO

vCo+- -

+

VOVO

R

C2

Ro

Co

-+

OiO

vCo+-

Q1 and Q3 on Q2 and Q4 on

-

+

VOVO

R

C2

Ro

Co

+-

vC2

OiO

vCo+- -

+

VOVOVOVO

R

C2

Ro

Co

+-

vC2

OiOOiO

vCo+- -

+

VOVO

R

C2

Ro

Co

-+

OiO

vCo+- -

+

VOVOVOVO

R

C2

Ro

Co

-+

OiOOiO

vCo+-

Q1 and Q3 on Q2 and Q4 on

1 .103 1 . 104 1 .105 1 . 106 1 .10780

70

60

50

40

30

20

Gain

Gain2

freqFrequency (Hz)

Gai

n (d

B)

SimplisModelSimplisModel

1 .103 1 .104 1 .105 1 .106 1 .10780

70

60

50

40

30

20

Gain1

Gain

freqfrequency (Hz)

Gai

n (d

B)

C2=132uFC2=220uFC2=132uFC2=220uF


60

(a) Comparison between model and SIMPLIS

simulation ( C2 = 132µF)

(b) Simulated Zo for different values of C2

(c) Simulated Zo after considering the ESL in the circuit

(C2=132µF, ESL of C2 is 1nH, ESL of Co is 500pH)

Figure 2.42 Output impedance of the voltage divider (R=10mohm, Ro=1mohm, Co=88µF)

2.5.2. Stability of Two-Stage VR with Voltage Divider as the First Stage

For a cascaded system, if the output impedance of the first stage (Zo1) and the input

impedance of the second stage (Zin2) meet (2-32) it is a stable system [40].

1|/| 21 <ino ZZ

(2-32)

Figure 2.43 shows an example of Zo1 and Zin2 (CPU VR input impedance). It is clear that

Zo1 is much lower than Zin2 for all frequencies, so the system is stable.

Figure 2.43 An example of Zo1 and Zin2

Figure 2.44 verifies the above analysis with experimental results. Although the CPU has a

fast load transient, the bus voltage only has low variation, and the output voltage of the CPU VR

1 .103 1 .104 1 .105 1 .106 1 .10780

70

60

50

40

30

20

Gain1

Gain4

freq

Gai

n (d

B)

Frequency (Hz)

w/o ESLWith ESLw/o ESLWith ESL

1k 2k 4k 10k20k 100k 400k 1M 2M 4M 10M

-50-40-30-20

-100

1020

30

Gai

n (d

B)

Frequency (Hz)

Zin2

Zo1


61

can meet the adaptive voltage position (AVP) requirement by Intel. The whole system is stable

and works very well.

(a)Experiment setup (b)Transient waveforms

Figure 2.44 Experiment setup and test results

2.5.3. Interaction between VRs

To save on cost, several VRs may share the same voltage divider as their first stage.

Therefore it is important to study if there is interaction between these VRs.

Figure 2.45 shows an example with two VRs sharing the same first stage. It is important to

know if VR #1 has fast load transient, and the nature of the voltage noise generated on VR #2.

That means the io1 to vo2 transfer function need to be studied.

Figure 2.45 Two VRs share the same voltage divider

Voltage divider CPU VRVo

VbusVin

io

Zo1 Zin2

Voltage divider CPU VRVo

VbusVin

io

Zo1 Zin2

Io

Vbus

Vo

50mV/div

20A/div

0.5V/div

t: 100us/DIV

20A/div

50mV/div

0.5V/div

Voltage divider VR #1vo1

vbus

vinio1

VR #2vo2

io2

ibus

iin1

iin2

Voltage divider VR #1vo1

vbus

vinio1

VR #2vo2

io2

ibus

iin1

iin2


62

Assume io1 has small signal perturbation, while io2 is constant. Then:

2

^

1

^

^

^

^

inin

bus

bus

busoVD

ii

v

i

vZ+

==

(2-33)

1

^

11

^

1

^/ inbusiiioin ZvGii +=

(2-34)

2

^

2

^/ inbusin Zvi =

(2-35)

where ZoVD is the output impedance of the voltage divider, Giii1 is the transfer function from io1

to iin1, and Zin1 and Zin2 are the input impedances of the two VRs.

Substituting (2-34) and (2-35) into (2-33), we have:

21

1

1

^

^

//1 inoVDinoVD

oVDiii

o

bus

ZZZZZG

i

v−−

=

(2-36)

Since ZoVD<<Zin1 and ZoVD<<Zin2, finally:

oVDiiivg

o

oo ZGG

i

vZ 12

1

^2

^

21 ≈=

(2-37)

where Gvg2 is the audio-suitability of VR #2.

Figure 2.46(a) is an example of Zo21. Again, due to the low output impedance of the voltage

divider, the gain of Zo21 is also very low (below -100dB). It means if io1 has 50A load step, the

maximum generated voltage noise on vo2 is 50/105=0.5mV, so there is almost no interaction

between the two VRs. Figure 2.46(b) shows the experimental results with CPU VR and DDR VR

sharing the same first stage. It shows that when CPU VR has a load transient, there is no voltage

noise observed on the output voltage of DDR VR.


63

(a)The simulated transfer function from io1 to vo2 (b)Tested waveforms

Figure 2.46 No interaction between different VRs due to low output impedance of voltage divider

In the above analysis, only two VRs are considered. Actually the results can also be applied

to the system with multiple VRs. Assume VR #n has a load transient, the transfer function to VR

#n current to VR #m output voltage is:

oVDiiinvgm

on

omomn ZGG

i

vZ ≈= ^

^

(2-38)

As a result, there should have no interaction among VRs with the voltage divider as the

first stage of two-stage power architecture.

As a comparison, Figure 2.47 shows the transfer functions from io1 to vo2 for voltage

divider as the first stage and buck as the first stage. They can achieve the similar peak gain.

However, buck first stage needs three 270µF output SP capacitors with 50kHz close-loop control

bandwidth. Voltage divide only has two 22µF ceramic capacitors with open loop.

-210

-190

-170

-150

-130

-110

-90

-70

-50

1.E+03 1.E+04 1.E+05 1.E+06

Gai

n (d

B)

Frequency (Hz)

Voltage dividerPo=70W CPU VR

DDR VR

Io_CPUVbus

Vo_DDR

Io_CPU

Vbus

Vo_DDR

20A/div

0.5V/div

0.1V/div


64

Figure 2.47 Comparison of transfer function from io1 to vo2 for voltage divider first stage and buck first stage

2.6. Startup and Protection of the Proposed Voltage Divider

2.6.1. Proposed Soft-Start Method for Switched-Capacitor Voltage Divider

As mentioned above, at steady state, since Vc2,Vc1 and Vc3 are very close, the current on

devices is relatively small. However, at startup, the voltage difference between capacitors is very

large, which causes a huge surge current on the devices. A huge input current is observed in

Figure 2.48 even with very low input voltage (Vin = 3V). This means the devices can be

destroyed at startup. As a result, a soft-start should be applied for the voltage divider.

Figure 2.48 Startup waveforms without soft-start (Vin=3V)

-210

-190

-170

-150

-130

-110

-90

-70

-50

1.E+03 1.E+04 1.E+05 1.E+06

Gai

n (d

B)

Frequency (Hz)

VD as first stage Buck as first stage

5A/div

2V/div

5V/div

Vin

Iin

Vo


65

The reason for the high current is the high voltage difference between the capacitors and

the small RDSon of the devices. The reason for the small RDSon is that a high gate-source voltage is

applied to the device. The MOSFET trajectory at startup (shown in Figure 2.49) verifies that the

high Vgs is one of the major reasons for a high startup current.

Figure 2.49 Device startup trajectory with Vgs = 5V (Device: HAT2165)

Since the MOSFET is a voltage-controlled current source when it operates in the saturation

region, the device current can be limited by reducing the Vgs at startup. Therefore, the gate-

source voltage of MOSFETs can be increased gradually from its threshold voltage to limit the

device current. Figure 2.50 illustrates the proposed soft-start scheme. C1 and C3 can be pre-

charged to half of the input voltage with RC network. After that, the gate driving voltage is

ramped up to charge C2 voltage to half of the input voltage smoothly. Figure 2.51 shows the

simulation result with the proposed soft-start method, where the device current can be limited to

a relatively low value during the voltage divider startup. Figure 2.52 verifies the device junction

temperature by treating the device’s power as a single pulse, which is worse than the real case.

The maximum junction-to-case temperature rise is only 10oC. Thus there should be no safety-

related problems for the device.

0

100

200

300

400

500

600

700

0 2 4 6 8 10 12

Vds(V)

Id(A

)

0

100

200

300

400

500

600

700

0 2 4 6 8 10 12

Vds(V)

Id(A

)

Vgs=5V

0

100

200

300

400

500

600

700

0 2 4 6 8 10 12

Vds(V)

Id(A

)

0

100

200

300

400

500

600

700

0 2 4 6 8 10 12

Vds(V)

Id(A

)

Vgs=5V


66

Figure 2.50 Proposed soft-start method for voltage divider

The experimental result shown in Figure 2.53 verifies the proposed soft-start method. It

works at no load, and the input current only has a small spike when the driver voltage reaches the

threshold voltage of the device.

Figure 2.51 Simulation result of the proposed soft-start method

Vin

Vbus

Vdriver

Io

PowerGood-

+Vin

Q1

Q2

Q3

Q4

C1

C3

C2

-

+

R

R

t


VoVin

Soft Start VR controller

Vdriver

PowerGood

Io

Vbus

Vbus

VC2

Vdriver

ID_Q1

VDs_Q1

VC2

Vo

ID_Q1*VDS_Q1

30A


67

Figure 2.52 Device junction temperature at startup

Figure 2.53 Experimental result at startup with the proposed method (Vin=12V)

2.6.2. Short Circuit and Over Current Protection

The general method used to protect the short circuit and over current is to sense the output

current and to take protective action correspondingly. However, this requires a current-sensing

circuit, which adds more cost and power loss. For the voltage divider, the load current can be

estimated as [33]:

PD

100µs

PDM=80W

Tjc = 0.03*Rjc*PDM = 0.03*4.17*80 = 10oC

0.03

100u

Simulate device power as a single pulse:

Vdriver (5V/div)

Iin (5A/div)

Vo (2V/div)


68

o

oino R

VVI −≈

2/

(2-39)

As long as the conduction loss is the dominant loss for the voltage divider, (2-39) is valid.

The test result shown in Figure 2.54 verifies the above equation. This means the voltage

difference between Vin/2 and Vo can represent the output current of the voltage divider. Thus no

current-sensing circuit is required.

Figure 2.54 Test result of Vin/2-Vo vs. Io ( Vin = 12V )

The above equation shows that the voltage difference will increase significantly at short

circuit, and will increase linearly at over-current, as shown in Figure 2.55.

Figure 2.55 Simulation result at short circuit and over current

00.020.040.060.080.1

0.120.140.160.18

0 5 10 15Io (A)

Vin/

2-Vo

(V)

Io

Vin/2-Vo

Short circuit

Io

Over current

Vin/2-Vo


69

The detailed protection scheme is presented in Figure 2.56, where Vth1 is much larger than

Vth2. If the voltage difference is larger than Vth1, the four MOSFETs are turned off

immediately. If the voltage difference is larger than Vth2, which is proportional to the maximum

load current, it will delay some time to avoid the noise problem. After that, if it is still larger than

Vth2, the four MOSFETs are turned off to shut down the voltage divider.

(a) Short circuit protection (b) Over current protection

oin VVV −=Δ 5.0

Figure 2.56 Protection of voltage divider based on the voltage difference between Vin/2 and Vo

2.7. Other Related Topologies

2.7.1. Controllability: Achieving Output Voltage Regulation

It has been demonstrated that the proposed voltage divider can achieve high efficiency and

high power density. Since it is used as the first stage of the two-stage solution, no regulation is

required. However, the ABVP concept cannot be applied with the switched-capacitor voltage

divider. Also, since it is unregulated, the voltage divider cannot work in parallel to extend the

current capability.

To achieve voltage regulation, one inductor must be inserted. Since we do not want the

inductor size to be large, a three-level resonant buck [39] is proposed for the voltage divider, as

shown in Figure 2.57. If the duty cycle for each switch is 50% and the switching frequency is

equal to the resonant frequency of C2 and Lo, all switches can achieve zero-current switching

(ZCS). As a result, the switching loss can be minimized and the size of Lo can be reduced.

VΔ

Shutdown

Vth1 VΔ

Shutdown

Vth2

Td

Vth1>>Vth2


70

Figure 2.57 Three-level resonant buck (fs = fo)

Figure 2.58 shows the efficiency comparison between the three-level buck converter and

the voltage divider with a similar cost. It can be seen that the three-level resonant buck converter

can achieve higher efficiency due to a lower switching frequency. Their footprints are the same,

but the voltage divider still has higher power density due to lower profiles.

Figure 2.59 shows two different control methods to regulate the output voltage. In terms of

voltage gain, the duty cycle control is more preferred since the gain is controlled with a wide

frequency range for frequency control.

-

+

VO

VO

Vin

Q1

Q2

Q3

Q4

C2

A

Co

Lo

221

CLfo

oπ=

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

C2

Co

Lo+vc- iL

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

C2

Co

Lo+vc- iL

fo = fs

VcN

ILN

Vin/2

fo = fs

VcN

ILN

Vin/20 0


71

Figure 2.58 Efficiency comparison between 3-level resonant buck and voltage divider

( C2 = 50µF, Lo = 25nH, fs = 160kHz for 3-level resonant Buck

C2 = 132µF, fs = 375kHz for voltage divider. Devices: 4*Si7104)

(a) Frequency control (b) Duty cycle control

Figure 2.59 Two control methods to regulate output voltage

94.0%

95.0%

96.0%

97.0%

98.0%

99.0%

100.0%

0 20 40 60 80

Effic

ienc

y

Po (W)

Voltage divider

3-level resonant buck

Vgs 50%Duty Cycle

Q1 & Q3

Q2 & Q4

Ts

fs=1/Ts

0

0.1

0.2

0.3

0.4

0.5

0.6

200 300 400 500 600 700

R=0.5ohm

R=5ohm

M=V

o/Vi

n

fs (kHz)

fofs

Q1

Q4

Q3

Q2 D

0

0.1

0.2

0.3

0.4

0.5

0.6

0 0.1 0.2 0.3 0.4 0.5 0.6

R=0.5ohm

R=5ohm

M=V

o/Vi

n

D


72

2.7.2. ZVS Voltage Divider

Now let us look at some other possible applications for the voltage dividers. Since the

proposed voltage divider can achieve extremely high power density, it is desirable for

applications where high power density is preferred. Bus converters are one possible application.

Figure 2.60 shows transformer-based step-down conversion bus converters to improve efficiency

[44]. The transformer is not necessarily required since the input 48V voltage is a safety voltage.

Figure 2.60 Low power density 48V bus converters

Figure 2.61 shows the proposed high power density bus converter with two voltage

dividers in series. The power density is about 1050W/in3, which is 10 times higher than the

conventional bus converters. The efficiency is about 96%, which is similar as the conventional

bus converters.

Figure 2.61 Proposed high power density 48V-12V bus converter

For a high input voltage, since there is capacitive turn-on loss for the voltage divider, ZVS

operation is preferred for higher efficiency. Again, to achieve ZVS turn-on, inductors must be

inserted to provide energy to charge and discharge the junction capacitors of the MOSFETs.

TransformerInductor

-

+

VOVO1

Vin

Q1

Q2

Q3

Q4

-

+

VOVO

Q5

Q6

Q7

Q8

48V 12VC2 C5

C1

C3

C4

C6

95.0%

96.0%

97.0%

98.0%

0 100 200 300 400

Po (W)

Effic

ienc

y


73

Figure 2.62 shows a proposed ZVS voltage divider. It adds a small inductor L resonating with

the output capacitor to create energy on L to achieve ZVS operation.

Figure 2.62 Proposed ZVS voltage divider

Figure 2.63 is the simulated waveforms to demonstrate that all of the switches can achieve

ZVS operation. As a result, the efficiency can be further improved.

Figure 2.63 Simulated waveforms for ZVS voltage divider

( L = 8nH, C1+C3=16µF, C2 = 66µF, Vin = 48V, Io = 20A, fs = 330kHz)

-

+

VOVO

Vin

Q1

Q2

Q3

Q4

L

Vgs_Q4

Vds_Q4

Vgs_Q1

Vds_Q1

IL1

Vo

ZVS is achieved

3.1. L

3.1.1.

For

in industr

MOS (L

trench M

switching

Rec

both the

trench M

Tra

evaluate

that this

means m

breakdow

Chapte

Chapte

Low Voltag

Introducti

r low-voltag

ry: the vertic

DMOS) [46

MOSFET ha

g speed. For

VDMOS

cently, the l

lateral MOS

MOSFET [47

aditionally Q

device perf

FOM is der

minimizing t

wn voltage

er 3. Two-Stag

er 3. Tw

S

ge Rating

ion of New

e application

cal diffusion

6]. These str

as the lowe

r sub-30V ap

Figure 3.1 T

lateral-trench

SFET and th

].

Qgd*Rdson, wh

formance [48

rived as a pa

the device’s

for differen

ge Architectu

wo-Stage

Second-S

Devices fo

w Device FO

ns, there are

n MOS (VDM

ructures are

est on-resist

pplications, t

Tren

Three basic str

h MOSFET

he trench MO

hich is know

8]. The defi

art of the de

s total loss

nt types of

re with Impro

74

e Archite

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Chapter 3. Two-Stage Architecture with Improved Second-Stage Efficiency

75

applications, and the devices for the same type of MOSFET are obtained from the same company

to make a fair comparison. It can be seen that most of the MOSFETs represented are trench

MOSFETs.

Figure 3.2 One example of lateral-trench MOSFET Structure

Figure 3.3 The definition of Qgd, Qgs2 and Qg

There are some trends clearly shown in Figure 3.4:

• For each structure, the FOM decreases when the breakdown voltage decreases; and

• With a lower breakdown voltage (below 20V), the LDMOS and the lateral-trench

MOSFET show significant benefits in terms of the FOM.

Qgate

Vgs

Vth

Vplt

Qg

Qgs2 Qgd

VDR


76

Figure 3.4 Figure of merit vs. breakdown voltage for different MOSFET structures

( All devices are for VRM applications)

The above FOM is actually derived from high-voltage applications, and it is not suitable

for low-voltage high-current applications since it neglects the Qgs2 effect, which is related to the

current rising time (for turn-on) or the current falling time (for turn-off). It also does not include

the impact of the gate-driving voltage. A better FOM that is more suitable for low-voltage high-

current applications was proposed recently by CPES. The new device figure-of-merit is proposed

in [49]:

2 2( )gd gs gs dsonFOM Q K Q R= + ⋅ ⋅

2

2 ( )( ) 1 plt DR pltDR

gs DRplt th in o g

V V VVK VV V V I R

−= +

− ⋅ ⋅

(3-1)

where Qgd, Qgs2, VDR, and Vth are shown in Figure 3.3, Vin is the input voltage, Io is the load

current, and Rg is the gate resistance of the MOSFET, including the driver resistance.

Figure 3.5 shows the new FOM vs. breakdown voltage. It can be observed that there are

some differences from Figure 3.4. For example, the 25V trench MOSFET from Vishay has a

higher new FOM than the 30V devices due to its larger Qgs2. It indicates that 25V may not be an

optimal design for VRM application.

0510152025303540

5 10 15 20 25 30 35Vds (V)

FOM=Q

gd*R

ds


Vishay ‐ Trench





IRDirectFET


77

Figure 3.5 New figure of merit vs. breakdown voltage for different MOSFET structures (All devices are for

VRM applications)

Let’s verify the new FOM by comparing the 20V Vishay Trench MOSFET (Si7106) with

the 30V Renesas D9 MOSFET (RJK0303), as shown in Table 3.1. The on-resistance of the two

devices is very close. Since the Si7106 has a much lower Qgd, its old FOM is lower than the

FOM of the RJK0303. However, due to a larger Qgs2, the Si7106 has a larger new FOM than the

RJK0303. As a result, the power loss of the Si7106 should be higher than the RJK0303 power

loss for VR applications.

Table 3.1 Comparison between Si7106 and RJK0303

Qgs2 (@20A) Qgd (@ 10V) Rds (@750C)

Vgs = 5V Old FOM New FOM

Vishay 20V

(Si7106) 6.6nC 2.8nC 5.62mΩ 15.7nC*mΩ 66.7nC*mΩ

Renesas 30V

(RJK0303) 2nC 5.2nC 4.6 mΩ 23.9nC*mΩ 36.9nC*mΩ

0

20

40

60

80

100

120

5 10 15 20 25 30 35Vds (V)

FOM=(Qgd+K

gs2*Qgs2)*R

ds

IRDirectFET


Vishay ‐ Trench



Renesas ‐ Trench D8Infineon ‐ Trench 3


78

Figure 3.7 shows the test result with a single-phase buck configuration. The bottom switch

and other circuit parameters are the same, but there are two different top switches. The figure

clearly shows that RJK0303 can achieve better full-load efficiency than the Si7106, which

matches the prediction from the new FOM, but would not be predicted if using the old FOM.

Figure 3.6 Test efficiency with Si7106 and RJK0303 as top switch

(Vin = 6V, Io = 20A, L = 200nH, fs = 600kHz, bottom switch: IRF6691 for both cases)

Another important factor in designing device packaging is the device packaging parasitics.

To operate, the MOSFET must be connected to the external circuit using a certain packaging

method. Different packaging methods use different ways to connect the MOSFET die to the pins;

for example, they might use wire bonding, a solid copper strap, and so on. These packaging

methods introduce packaging parasitics to the common-source inductor (Ls) and the drain

inductor (Ld). Both the turn-on and turn-off losses will increase by increasing the common-

source parasitic inductance (Ls). The total switching loss is tremendously impacted by the

common-source parasitic inductance (Ls). Increasing the drain-side parasitic inductor (Ld) would

decrease the turn-on loss, but would also increase the turn-off loss. In addition, it would not

significantly influence the total switching loss in some ranges, because the gain from the turn-on

loss and the loss from the turn-off loss would cancel each other out.

88%

89%

90%

91%

92%

93%

5 10 15 20 25

Efficien

cy

Io(A)

Efficien

cy

RJK0303Si7106


79

3.1.2. Efficiency Improvement by Great Wall LDMOS for Top Switch

Since our input voltage is about 6V, it is reasonable to use a 15V device from Great Wall

as the top switch [46]. We compare it with the best 30V trench MOSFET, which is from

Renesas. Table 3.2 shows that the Great Wall 15V MOSFET has a lower new FOM, which

indicates that, its efficiency could be better.

Table 3.2 Comparison between GWS15N15 and RJK0303

Qgs2 @

Id = 20A

Qgd @

Vds = 10V

Rds (@750C)

Vgs = 5V Old FOM New FOM

Great Wall 15V

(GWS15N15) 2.7nC 5.2nC 3.26mΩ 17nC*mΩ 29nC*mΩ

Renesas 30V

(RJK0303) 2nC 5.2nC 4.6 mΩ 23.9nC*mΩ 36.9nC*mΩ

Figure 3.7 shows that, as expected, the Great Wall 15V LDMOS can achieve about 1%

higher efficiency at full load than the RJK0303, which is the best 30V device. The efficiency of a

12V input buck converter with 30V devices is only 86%, which is 4% lower than a 6V buck

converter.

Figure 3.7 Efficiency improvement from Great Wall 15V devices

(Vin = 6V, Io = 20A, L = 200nH, fs = 600kHz, bottom switch: IRF6691 for both cases)

84%85%86%87%88%89%90%91%92%93%

0 4 8 12 16 20 24

GWS15N15RJK0303

Io(A)

Efficien

cy


80

3.1.3. Efficiency Improvement by Ciclon Lateral-Trench MOSFET

Let’s take a look at bottom switch. For the bottom switch, the new FOM does not apply

since there are no switching losses. Although there is a new bottom-switch FOM [49], since the

die size cannot meet the minimum power loss requirement, that FOM is not that helpful in

choosing a better bottom switch. Thus a very straightforward way to select a bottom switch is to

test the performance of the bottom switch by testing different bottom switches with the same top

switch. Table 3.3 shows the comparison between Ciclon’s 12V lateral-trench MOSFET with the

best bottom switches available before this switch was made available (IRF6691). It can be

observed that both the on-resistance and the total gate charge of the CSD13301 are lower than

that for the IRF6691. As a result, higher efficiency can be expected.

Table 3.3 Comparison between CSD13301 and IRF6691

Rds @750C and 5V Qg @ Vgs = 5V Rds*Qg

Ciclon 12V CSD13301 1.44mΩ 30nC 43.2nC*mΩ

IR 20V IRF6691 2.16mΩ 47nC 80nC*mΩ

Figure 3.8 shows that, as expected, the CSD13301 can achieve about 1.5% higher

efficiency at full load than the IRF6691 can.

Figure 3.8 Compare Ciclon devices with the best bottom switch

(Vin = 6V, Io = 20A, L = 200nH, fs = 600kHz, top switch: RJK0303 for both cases)

88%

89%

90%

91%

92%

93%

0 4 8 12 16 20 24

CSD13301 IRF6691

Io(A)

Efficien

cy


81

Since Ciclon does not design a good 12V MOSFET for the top switch, a 25V lateral-trench

MOSFET (CSD16402) is selected as a top switch and compared with what was previously the

best top switch, the Great Wall 15V MOSFET (GWS15N15). Table 3.4 shows that the Ciclon

25V lateral-trench MOSFET has a lower new FOM than the Great Wall 15V lateral MOSFET.

Table 3.4 Comparison between CSD16402 and GWS15N15

Qgs2

Id=20A

Qgd

Vds=10V

Rds (@750C)

Vgs=5V Old FOM New FOM

Ciclon 25V

CSD16402 1.6nC 2.3nC 4.6 mΩ 10.6nC*mΩ 21nC*mΩ

Great Wall 15V

(GWS15N15) 2.7nC 5.2nC 3.26mΩ 17nC*mΩ 29nC*mΩ

Figure 3.9 shows that the CSD16402 and the GWS15N15 can achieve similar efficiency.

The reason for this is the Great Wall 15V MOSFET’s lower packaging inductance, which

compensates the device performance. Since the packaging of CSD16402 is PowerPak, which can

be easily soldered, while Great Wall’s device has BGA packaging, the CSD16402 is selected for

the second stage.

Figure 3.9 Comparison of Ciclon devices with the best top switch

(Vin = 6V, Io = 20A, L = 200nH, fs = 600kHz, top switch: CSD13301 for both cases)

88%

89%

90%

91%

92%

93%

94%

0 4 8 12 16 20 24

CSD16402 GWS15N15

Io(A)

Efficien

cy


82

3.1.4. Applying Ciclon 12V Lateral-MOSFET to Top Switch using an Improved

Loss Model

3.1.4.1. An Accurate Loss Model

As shown in Figure 3.5, the Ciclon 12V lateral-trench MOSFET has the lowest FOM.

However, the device is only available for the bottom switches due to its large die size. In the

following section, a very accurate loss model is developed to see how the efficiency can be

improved if we change the die size of the 12V MOSFET to make it suitable for the top switch.

It has been proven that for high-frequency operation, the conventional model, which does

not include any parasitic inductance, is no longer suitable. To get an accurate value for the

power loss, a new analytical loss model is developed in [51] which includes the parasitic

inductance and non-linear capacitance of the devices, as shown in Figure 3.10.

(a) Parasitic inductance is considered

(b) Non-linear capacitors of the device are considered

Figure 3.10 A new device loss model which includes parasitic inductance and non-linear capacitors

LS1Ld1

LS2

Ld2

Driver

Vphase

Cgs1

Driver

Cds1

Cgd1

HAT2165

Cgd2

Cds2

Cgd2


83

Figure 3.11 shows the comparison between the loss model and the physical model, where

the power loss is absolutely correct. It can be observed that except for the top switch turn-off

loss, all of the loss model’s other losses are very correct.

Figure 3.11 Comparison between loss model and physical model

(1 HAT2168+1 HAT2165, Vin = 12V,Vo = 1.3V, Io = 12.5A, fs = 1MHz)

A piece-wise linear model is used in [51] for the calculation of the turn-off loss, as shown

in Figure 3.12. The reason for the inaccuracy for the turn-off loss is that the drain current (iD) is

treated as a constant current source during the t1 - t2 period. However, since the Vds of the top

switch increases during this period, the Vds of the bottom switch should decrease

correspondingly, which means there should be some current on Coss_bot. Since the load current

doesn’t change during this period, the drain current of the top switch should be changed during

this period.

Figure 3.13 shows a new piece-wise model for the calculation of the turn-off loss. The

main change is for the t1 - t2 period. Due to the large Coss of the bottom switch, there is some

amount of the load current shifted from the top switch to the Coss of the bottom switch during this

period. As a result, the Coss of the bottom switch serves as a snubber capacitor for the top switch,

which helps to reduce the turn-off loss of the top switch. During the turn-off period, the Cds of

the top switch is extremely small, so it is neglected during the calculation.

0

0.5

1

1.5physical modelLoss model

Power Loss (W

)


84

Figure 3.12 Piece-wise linear model for calculation of the turn-off loss in [51]

Figure 3.13 A new piece-wise linear model for calculation of turn-off loss

0 2 .10 9 4 .10 9 6 .10 9 8 .10 910

0

10

20

30

)

t

Io

Coss_bot

D

S

G I0

t1~t2

t2~t3

t1 t2

vDS

iD

t3t

t2~t3

Io

Coss_bot

D

S

G iD

t1~t2

0 2 .10 9 4 .10 9 6 .10 9 8 .10 95

0

5

10

15

20

25

30

id1_of t( )

vds1_of t( )

vds1_bot t( )

t

t3

vDS_top

iD

vDS_bot

t2t1t

+

_vDS_bot

vDS_top

+

_


85

With the improved method, it can be seen from Figure 3.14 that the turn-off loss of the top

switch is now more accurate.

Figure 3.14 Breakdown of the improved model shows more accuracy

( 1 HAT2168 + 1 HAT2165, Vin = 12V, Vo = 1.3V, Io = 12.5A, fs = 1MHz)

3.1.4.2. Sweeping the Die Size for Better Efficiency

Since the CSD13301 12V device is designed as a bottom switch, its efficiency is not good

if we use it as the top switch. Thus, if the die size can be reduced, we can use 12V devices for the

top switch as well.

With the help of the above improved loss model, it is easy to sweep the die size for

efficiency. The die size of CSD13301 is normalized to be 1, so the on-resistance is inversely

proportional to the die size (excluding the packaging resistance) while Cgs, Cgd , Cds and the

trans-conductance (gm) are proportional to the die size. In the loss model, these values are

changed correspondingly when the die size is swept.

Figure 3.15 shows the results from the model by sweeping the normalized die size from 0.2

to 1. Since the Ciclon 25V MOSFET (CSD16402) can achieve 91% efficiency, the Ciclon 12V

MOSFET with 30% die size as CSD13301, can achieve 0.7% higher efficiency.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6physical model

Improved loss model

loss model

Power Loss (W

)


86

Figure 3.15 Sweep die size of 12V device technology for top switch

(Vin = 6V, Io = 20A, L = 200nH, fs = 600kHz, bottom switch: CSD13301)

3.1.4.3. Final Efficiency Achievement with Low Voltage Rating Devices

Figure 3.16 shows the final efficiency achievement for the second stage with the low-

voltage-rating devices. The solid line is the test efficiency result with a Ciclon 25V top switch

and a 12V bottom switch. It can be observed that the efficiency at full load is about 91% for

600kHz switching frequency and 89% for the 1MHz switching frequency. The dashed line is the

projected efficiency result with an optimized 12V top switch and a 12V bottom switch. The

efficiency can improved to about 92% for 600kHz and 90% for the bottom switch.

Figure 3.16 Final efficiency achievement

(Vin = 6V, L = 200nH for fs = 600kHz, L = 100nH for fs = 1MHz)

90.4%

90.6%

90.8%

91.0%

91.2%

91.4%

91.6%

91.8%

0 0.2 0.4 0.6 0.8 1 1.2

NormalizedDie size

Effciie

ncy 0.7%

84%85%86%87%88%89%90%91%92%93%94%95%

0 4 8 12 16 20 24

CSD16402+CSD13301 600kHzCSD16402+CSD13301 1MHz(0.3XCSD13301)+CSD13301 600kHz(0.2 X CSD13301+CSD13301) 1MHz

Io(A)

Efficien

cy


87

3.2. Proposed System Level Two-Stage VR for Laptop and Server

Computers

3.2.1. New Situations for Two-stage VR

All of the previous research on two-stage VRs is based on cost savings for desktop PCs,

and on keeping a similar cost and reducing the footprint (for laptops). This is because the output

bulk capacitors (Oscon capacitors for desktops and SP capacitors for laptops) used to be very

expensive. The cost savings of the two-stage VR can compensate the additional first-stage cost.

However, capacitor costs have been greatly reduced due to large demand for capacitors. As

shown in Figure 3.17, in 2004, the Oscon capacitor cost was about 25% of the total VR cost.

However, the Oscon capacitor cost in 2008 is only about 15% of the total VR cost in 2004. As a

result, two-stage VRs are even more expensive than single-stage VRs.

Figure 3.17 Cost difference between 2004 and 2008 for desktop VR

( Cost is normalized to the total VR cost in 2004)

For laptop VRs, there is a similar situation. As a result, the previous argument of using a

two-stage VR to save costs is no longer true. A new architecture must be proposed to keep the

cost similar while improving efficiency or reducing the footprint.

3.2.2. Proposed System Level Two-Stage Power Architecture for Laptop

Computers

One example of the two-stage VR concept is Intel’s Narrow VDC [68], as shown in Figure

3.18. With the help of a system charger VR, the bus voltage is the same as the battery voltage, so

the voltage range is narrowed, which provides significant benefits for the VRs downstream.

Total VR Cost: “1”1st Stage Cost: “0.2”

Oscon Cap Cost: “0.25”Cost Reduction: 5%

Year 2004 Year 2008

Total VR Cost: “0.9”1st Stage Cost: “0.2”

Oscon Cap Cost: “0.15”Cost Increase: 5%


88

Figure 3.18 Intel’s Narrow VDC power architecture

The bus voltage of Narrow VDC structure is still too high (8.7V~12.6V). To reduce bus

voltage, one possible two-stage solution for laptop VRs is shown in Figure 3.19. Since the CPU,

graphics, DDR and the main power, which require 5V and 3.3V power, are four major loads, a

two-stage solution is applied for the VRs of these loads. However, this architecture is not

practical. First, there are too many first stages, which add more cost and footprint. Second, the

total first-stage power is too high at beyond 150W, assuming 85% VR efficiency. It is not an

effective solution.

Figure 3.19 One possible two-stage solution for laptop VRs

Batterypack

LCD

I/O powerLDO Keep alive

CPUMain power Graphics DDR

VRs VR and LDO

VR VRVR

5V 3.3V

Boost

AC/DC adapter

System charger VR

19V

AC input: 90~265V

VR VR

8.7V~12.6V

AC/DC adapter

Battery charger

Batterypack

Power pathswitch

LCD

I/O power

19V

8.7-16.8V

8.7-19V

LDO Keep alive


AC input: 90~265V

VR

VRs VR and LDO

VR VRVR VR

Boost

1st 1st 1st 1st 1st

25W 16.5W 54W 16W 18W


89

Actually, the laptop has a total load power regulation function to meet the system’s thermal

design power (TDP) requirement. For example, when the laptop detects that the total load power

is beyond a certain value, it will lower the CPU clock frequency to reduce CPU power. As a

result, although the peak power may exceed the system’s designed power for a very short period,

the thermal designed power can be greatly reduced. For example, in the above laptop power

architecture, the maximum load power can be as high as 110W, but the thermal design power is

only about 60W, which is around half of the maximum power. Therefore, if all of the VRs share

the same first stage, the first-stage thermal power can be as low as 70W (assuming 85% VR

efficiency). Figure 3.20 shows the proposed system’s two-stage power architecture. The low-

power first stage greatly reduces the cost and footprint when compared with the previous

architecture, so it is a promising power solution for laptops.

Figure 3.20 Proposed system level two-stage power architecture for laptop

This system’s two-stage VR can also be applied to the Narrow VDC power architecture, as

shown in Figure 3.21.

AC/DC adapter

Battery charger

Batterypack

Power pathswitch

LCD

I/O power

19V 8.7-19V

LDO Keep alive


AC input: 90~265V

VRs VR and LDO

VR VRVR

5V 3.3V

Boost

First stage with 70W power

VR

3 cells: 8.7-12.6V4 cells: 11.6V-16.8V

25W 16.5W 54W 16W 18W

VR


90

Figure 3.21 Two-stage system for Narrow VDC power architecture

From the proposed architecture we can see that the first stage is very important to the

system performance. First, the first stage should have high power density so that it occupies very

little of the real estate. Secondly, the first stage should have an extremely high efficiency so that

the overall efficiency of the two-stage VR is high. From Chapter 2 we can see that the proposed

switched-capacitor voltage divider is a perfect solution for the two-stage VR.

Now let us discuss how to design the output inductance and output capacitance for the

second stage of the two-stage VR. For simplicity, the CPU VR is used as an example, but the

concept can be applied to other VRs.

In laptop VRs, non-linear control methods, such as constant on-time control and hysteretic

control, are widely used. For non-linear control methods, the duty cycle of the buck converter is

saturated immediately after the load transient occurs. The delay time is ignored. As a result, the

inductor current slew rate at the transient is determined by the inductance value, as shown in

(3-2):

downstepfor

LVSR

upstepforL

VVSR

eq

oL

eq

oinL

=

−=

(3-2)

Batterypack

LCD

I/O powerLDO Keep alive


VRs VR and LDO

VR VRVR

5V 3.3V

Boost

1st Stage

AC/DC adapter

System charger VR

19V

AC input: 90~265V

VR VR

8.7V~12.6V


91

where Vin and Vo are the input voltage and output voltage, respectively, and Leq = L/N is the

equivalent transient inductance. L is the inductance of each phase, and N is the number of

phases of the VR. For a CPU VR, since the input voltage is much larger than the output voltage,

the voltage spike for the load step-down is dominant. The equivalent load step-down circuit is

shown in Figure 3.22(a), and current waveforms for different output inductances are shown in

Figure 3.22(b), where SRo is the load current slew rate. Then voltage deviation during the

transient can be calculated as:

dttdi

L c

c

t

co

cco dttiC

tiRtV)(

0

)(1)()( ⋅+⋅⋅+⋅=Δ ∫

(3-3)

where Rc is the total ESR of the output capacitors, Co is the total output capacitance and Lc is the

total ESL of output capacitors.

(a)Equivalent load step-down circuit

(b) Current waveforms at load step-down for different values of L

Figure 3.22 Inductance determines the transient performance for non-linear control

Figure 3.22(b) shows that the smaller the output inductance is, the lower the capacitor

current will be. This means fewer output capacitors are required to have the same voltage spike,

iL

io

icLeq LcRc

Co

voiL

io

icLeq LcRc

Co

io

icLeq LcRc

Co

vo

iL

ic

io

Slope: SR0

Slope: SRL1

Slope: SRL1Slope: SRo-SRL1

ΔIo

iL

ic

io

Slope: SR0

Slope: SRL2


ΔIo

L1 > L2

iL

ic

io

Slope: SR0

Slope: SRL1


ΔIo

iL

ic

io

Slope: SR0

Slope: SRL2


ΔIo

L1 > L2


92

so the output capacitance is determined by the output inductance instead of the switching

frequency. Figure 3.23 shows a calculated inductance-capacitance curve for a three-phase laptop

CPU VR based on (3-2), where L is the inductance per phase, and the bulk capacitor is a low-

profile 330µF/7mohm SP capacitor from Panasonic. It shows that lower inductance results in

fewer capacitors needed to meet the same transient requirement. For example, in current industry

practice, L is 600nH, so eight bulk capacitors are needed to meet the transient requirement. If the

inductance is reduced by half (L=300nH/phase), the bulk capacitors can be reduced to five . If

the inductance is reduced to 150nH, the bulk capacitors can be reduced to two. If the inductance

is reduced to 100nH, the bulk capacitors can be eliminated!

Once the number inductors and capacitors are determined, the switching frequency should

be determined correspondingly. For constant on-time control, the minimum switching frequency

needed to meet the output voltage ripple requirement should be selected. Figure 3.24 shows that

the switching frequency should be increased when the output inductors are reduced. If the output

inductance is further reduced, although the output capacitance can be reduced as well, the

required minimum frequency should be higher, which results in a lower VR efficiency.

Therefore there is a trade-off between the reduction of the output inductance (capacitance) and

the VR efficiency.

Figure 3.23 Number of bulk capacitors vs. inductance for CPU VR

(Vin = 6V, Vo = 1.2V, three phases, ∆Io =45A, ∆Vo = 65mV)

0

2

4

6

8

10

12

14

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Num of Cap

L (µH)


93

Of course, as explained above, the real frequency should be chosen to be larger than the

switching frequency to maximize VR efficiency.

Figure 3.24 Minimum switching frequency to meet the output ripple requirement

( Vin = 6V, Vo = 1.2V, three phases, Io = 0.1A, constant on-time control)

3.2.3. Evaluation of Two-Stage VR for Laptop

To evaluate the proposed solution, a two-stage evaluation board was built, as shown in

Figure 3.25. A CPU VR and a DDR VR are chosen as design examples. The MAX1545, which

uses constant on-time control, is used as the VR controller. For simplicity, the efficiency is

evaluated for a 3-cell battery, the input voltage of which is about 12V.

Figure 3.25 Evaluation board for two-stage solution

0

100

200

300

400

500

600

700

800

900

1000

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

fs (kHz)

L(µH)

DDR VR (18W)2-phase or single-phase

selectable

CPU VR (50W)2-phase or

3-phase Buck

Voltage dividerWith SO-8 device

DDR load emulator CPU load emulator


94

To evaluate the proposed power architecture from different angles, two designs are

compared, as shown in Figure 3.26. Design #1 focuses on the reduction of the footprint of the

output filters and reducing the cost, so the VR frequency is almost doubled and the output

inductance and capacitance are further reduced. Design #2 focuses on efficiency improvement

and the output filter size reduction. The two designs have the same switching frequency but the

second design use the best devices which have higher cost than the first design.

(a) Benchmark: single-stage solution (Single-stage: 3 phases, each phase: 1 IRF7821 + 2 IRF7822)

(b)Two-stage Design #1: reduce the cost and output filter size (similar devices as benchmark)

(1st stage: 70W voltage divider, 4*Si7104,2nd stage: 3 phases, each phase: 2 IRF7821 + 1 BSC024N025S)

(c) Two-stage Design #2: improve efficiency and reduce output filter size (best devices are used)

(1st stage: 70W voltage divider, 4*Si7104,2nd stage: 3 phases, each phase: 1 CSD16402 + 1 CSD13301)

Figure 3.26 Two different two-stage designs

8.7V~12.6V for battery

CPU VR

DDR VR

fs=300kHz, L=600nH

Benchmark: Single-stage

…fs=300kHz, L=1000nH


CPU VR

DDR VR

fs=300kHz, L=600nH



CPU VR

DDR VR

fs=300kHz, L=600nH





DDR VR

fs=550kHz, L=150nH




DDR VR

fs=550kHz, L=150nH




DDR VR

fs=550kHz, L=150nH




DDR VR

fs=550kHz, L=150nH



95

The CPU VR efficiency of Design #1 is shown in Figure 3.27. Although the frequency is

doubled, it can still achieve slightly higher efficiency than a single-stage solution. The CPU VR

efficiency of Design #2 is shown in Figure 3.28. It clearly shows that the efficiency of the CPU

sleep states can be improved by 3% and the efficiency of the CPU active states can be improved

by 3-5%.

Figure 3.27 CPU VR Efficiency comparison between single-stage and two-stage Design #1

Figure 3.28 CPU VR Efficiency comparison between single-stage and two-stage Design #2

The transient response of the CPU VR is shown in Figure 3.29. It demonstrates that both of

the designs can meet the transient and output voltage ripple requirements and both of them can

reduce the number of capacitors from eight to two.

80%81%82%83%84%85%86%87%88%89%

0.1 1.0 10.0 100.0

Effic

ienc

y

Io (A)

Single stage Two-stage overall

DCM, Vo=0.9V CCM, Vo=1.2V

80%

82%

84%

86%

88%

90%

92%

0.1 1.0 10.0 100.0

Effic

ienc

y

Io (A)

Single stageTwo-stage overall

DCM, Vo=0.9V CCM, Vo=1.2V


96

Since the voltage divider is the additional stage for the two-stage solution, it should be

counted together with the output filters. For two-stage design #1 and #2, the footprint reduction

from the CPU VR is much larger than the additional footprint from the voltage divider. In our

design example, the footprint reduction can be as high as 33%.

(a) Single-stage CPU VR transient waveforms. (c) Two-stage CPU VR transient waveforms.

Figure 3.29 Transient response of CPU VR

Figure 3.30 Footprint comparison for CPU VR

Figure 3.31 shows the efficiency comparison of single-stage and two-stage for DDR VR. It

shows that with the doubled frequency, two-stage DDR VR can even achieve higher efficiency

than single-stage DDR VR.

Io (20A/div)

Vo (50mV/div)

SP cap:330uF each

Io (20A/div)

Vo (50mV/div)

Io (10A/div)

Vo (50mV/div) 16mV16mV

same scale

Single-stage:CPU VR output

inductors and caps

Two-stage:CPU VR output

inductors and caps


97

Figure 3.31 DDR VR efficiency comparison

Singe stage: single phases, 1 IRF7821 + 1 IRF7822, L=1000nH, fs=300kHz

Two-stage: single phase, 1 IRF7821 + 1 Si4864, L=300nH, fs=550kHz

Table 3.5 gives a comparison between Design #1 and Design #2. It verifies that while

Design #1 is footprint and cost-oriented and Design #2 is efficiency-oriented.

Table 3.5 Comparison between two two-stage designs for laptop

CPU VR Light load

Efficiency

CPU VR Full-

load Efficiency

Footprint for

output filters Cost

Design #1 1% higher Similar ~33% reduction 5% reduction

Design #2 3% higher 3~5% higher ~33% reduction Similar cost

3.2.4. System Level Two-Stage Power Architecture for High-End Servers

As introduced in Chapter 1, Intel and other companies are now considering the Z-Axis

VRM (ZVRM) structure, as shown in Figure 3.32 [16]. The concept is to put VR as close as the

microprocessor to minimize the power delivery path.

Figure 3.32 ZVRM proposed by Intel

y

85.00%

86.00%

87.00%

88.00%

89.00%

90.00%

0 5 10 15Io(A)

Effic

ienc

y

two-stage overallsingle stage


98

In this arrangement, the VR must be very small to put it on (or around) the OLGA. As we

know, the bulky elements of the VR are the output inductors and output capacitors. The output

inductors can be reduced by raising the VR switching frequency. The output capacitors of the

VR, normally referred to as bulk capacitors due to their large capacitance and volume, can be

reduced by raising the VR control bandwidth. As described in Chapter 1, when the VR control

bandwidth is pushed to be around 350kHz~390kHz, the bulk capacitors can be eliminated.

Recent research shows that with a 1MHz switching frequency and coupled-inductor structure,

350kHz bandwidth can be achieved [69].

Server microprocessors consist of three major loads: core, cache and uncore. Previously,

only one VR was designed to feed these loads. However, since the load current is higher and thus

the transient speed becomes faster, a single VR cannot satisfy all the loads. Hence, three separate

VRs are required to power the three loads. Although the sum of the VRs’ power is around 190W,

there is a thermal design power (TDP) requirement for the three loads, which means the total

power cannot exceed a certain value, e.g. 130W. By taking advantage of the TDP requirement of

the server microprocessor, we can apply the two-stage architecture, as shown in Figure 3.33, to

reduce the power rating of the first stage for further cost and size reduction. In this structure, the

first stage only needs to be designed at 150W power for the three VRs, assuming 87% VR

efficiency.

Figure 3.33 Proposed two-stage power architecture for future server microprocessors

Vbus ≅ 6V High frequencyCore VR

High frequencyCore VR

High frequencyCache VR

High frequencyCache VR

High frequencyUncore VR

High frequencyUncore VR

TDP:130W

1st stageHigh efficiency andHigh power density

Voltage step-down converterVin=12V

50W

100W

38W


99

3.2.5. Evaluation of Two-Stage Architecture for High-End Servers

In our two-stage design, the high-frequency, high-power-density voltage divider is used as

the first stage. It can achieve over 97.5% efficiency for the entire load range.

With a high-frequency first stage design and a high-efficiency second stage design using

low-voltage-rating devices, the overall efficiency comparison of a core VR is shown in Figure

3.34. Compared with a 600kHz single-stage VR, which is the state-of-art design for server

applications, a 1MHz two-stage VR can achieve similar efficiency.

Figure 3.35 shows the control bandwidth [69] and the tested transient waveforms of the

two-stage VR without any bulk capacitors. For a typical 600kHz single-stage VR, the output

bulk capacitors are about five 100µF MLCC capacitors. Moreover, due to a higher switching

frequency operation, the output inductor size can also be greatly reduced. Overall, 1MHz two-

stage solution can achieve 45% output filter footprint reduction comparing with 600khz single-

stage solution. This is very important for the ZVRM.

As for the cost, although the two-stage architecture adds additional cost for the first stage,

it can reduce the bulk capacitors for the VRs. As a result, it has a similar cost to the single-stage

VR solution.

(a) Prototype – No bulk capacitors

1st stage

2nd stage


100

(b)Efficiency

Figure 3.34 1MHz two-stage VR prototype and efficiency (No bulk capacitors)

(1st stage: voltage divider: 4*CSD13301; 2nd stage: 6-phases, (1 CSD16402+1 CSD13301)/ phase)

(a) Control bandwidth (b) Load transient waveforms

Figure 3.35 Control bandwidth and transient waveforms

67%

72%

77%

82%

87%

92%

0 50 100 150

Effic

ienc

y

Io (A)

Single Stage 600kHz

Two-stage overall 1MHz

100 1 . 103 1 . 104 1 . 105 1 . 10640

20

0

20

40

60

100 1 . 103 1 . 104 1 . 105 1 . 106360

270

180

90

0

90

Frequency (Hz)

Phas

e (o

)M

agni

tude

(dB

)

fs=1MHz

fc=350kHz

φm=60o

Io

Vo

100A/div

50mV/div


101

3.3. Light Load Efficiency Improvement

3.3.1. Introduction

Laptop computers are gaining a greater share of the market share and are expected to

outsell desktop computers in the near future. Laptop computers utilize mobile microprocessors,

whose performance has greatly improved in recent years. For mobile devices, battery life is very

important. Figure 3.36 shows a typical power consumption breakdown in a laptop [52], in which

the power supply loss is around 14% of the total power. Therefore, the reduction of the power

supply loss is very important for battery life extension. For a typical design, a 30mW power loss

saving means a one-minute battery life extension. Since the CPU’s voltage regulator (VR) needs

to provide 57% of the power to the CPU, a method for reducing CPU VR power loss becomes a

very hot subject now.

Figure 3.36 A typical power consumption breakdown in laptop

In laptops, there are two categories of CPU VR efficiency requirements: one category of

requirement is full-load efficiency at the AC adapter voltage (19V) (the worst case in terms of

efficiency), as is required to meet thermal design; another category of efficiency requirement is

the efficiency for the entire load range at the battery voltage (16V for 4-cell battery or 12V for 3-

cell battery), which is important for battery life. To reduce the CPU’s average power, the CPU

goes into sleep mode frequently, and the VR spends 80% of the time at the light-load condition

[53], which is defined as all of the load conditions except for the full load.

The state-of-the-art VR design is based on the multi-phase buck converter. It is well known

that at a very light load of less than 20% of the full load power, the power loss of buck is

dominated by switching-related losses, e.g. gate driving loss and control switch turn-off loss


102

[54]. The most effective way of improving the efficiency for this load range is to apply variable-

frequency control, e.g. variable-frequency current-mode control [54], burst mode control [55]

and constant on-time control [56]. The idea is to decrease the switching frequency, or equivalent

switching frequency in the case of burst mode control, to reduce the switching-related losses. In

terms of the implementation, constant on-time control is the simplest method since it does not

need to sense the current. Hence constant on-time control is widely used in laptop VR

controllers.

Figure 3.37 shows how the inductor current changes with different loads for constant on-

time control. When the load current is larger than critical current (Icrit), the buck converter works

at CCM and the switching frequency is constant. When the load current is below Icrit, the buck

converter works at DCM and keeps the same on-time for the control switch. The voltage gain at

DCM can be easily derived using (3-4):

son fRTL

M

2811

2⋅

++=

(3-4)

where M=Vo/Vin, L is the output inductance, R is the load resistance, Ton is the on-time of

control switch, and fs is the switching frequency of the buck converter.

Figure 3.37 Inductor current waveforms for constant on-time control with different loads

From (3-4), we know that if Ton is constant, the switching frequency should be inversely

proportional to the load resistance to regulate the output voltage. This means that if the load

current decreases, the switching frequency decreases correspondingly. Since gate driving loss

iL

tIcrit/2

0Ton2Ts

iL

t

Icrit

0Ts

iL

t

Io

0Ts


103

and turn-off loss are the most dominant losses at light load, the light-load efficiency can be

improved by applying constant on-time control. Figure 3.37 shows that when the load current is

half of Icrit, the switching period is doubled, which indicates that the switching frequency

decreases by half.

Figure 3.38(a) shows the efficiency comparison between CCM operation and DCM

operation with constant on-time control from Maxim [56]. Figure 3.38(b) shows how the

switching frequency decreases with the loads during DCM operation.

(a) Efficiency vs. load current

(Solid line: CCM; Dash line: DCM at light load) (b) Switching frequency vs. load current

Figure 3.38 Improved light load efficiency with constant on-time control

From Figure 3.38(a), it can be seen that although the efficiency at very light load is

improved, there is no improvement in efficiency when the load is between 20% and 100%.

Especially, the efficiency drops very quickly when the load decreases from the peak efficiency

point (around 40% load), which indicates there is room for efficiency improvement during CCM.

Figure 3.38(b) shows that the switching frequency remains unchanged during CCM operation, so

we have opportunity to improve the efficiency by slightly varying the switching frequency. To

improve CCM efficiency, adaptive on-time control is proposed, which is described in 3.3.2.

Based on the constant on-time control, the non-linear inductor and its corresponding control

method is proposed to further boost DCM efficiency, as described in 3.3.3. It should be

mentioned that the proposed methods can be applied for both single-stage VR and two-stage VR.

0

50

100

150

200

250

300

350

0 10 20 30 40 50Io(A)

SwitchingFreq

uency (kHz)

DCM CCM


104

3.3.2. Proposed Adaptive On-time Control to Improve Buck CCM Efficiency

This section investigates how to improve CCM efficiency with constant on time control.

Figure 3.39 shows the scheme of the synchronous buck converter. Constant on-time control

means that the on-time for control switch Q1 is fixed and the off-time is variable to achieve

voltage regulation. In truth, the on-time does not need to be constant at CCM since the transient

performance is mainly determined by the output inductance instead of the on-time [57]. The

following section will describe how to select an on-time for higher efficiency with an example.

Figure 3.39 Synchronous buck converter

First let us review how to select an on-time for the constant on-time control. There are two

constraints to select an on-time [56]:

(a) Select an on-time to meet the output voltage ripple requirement. When Ton increases,

the inductor current ripple increases, which results in a larger voltage ripple. Figure 3.40 shows

the relationship between the output voltage peak-to-peak ripple vs. the on-time. For a laptop VR

application, the maximum voltage ripple is 20mVpp [53], so the maximum allowed on-time is

about 1µs. To leave some design margin, we select Ton(max) = 0.7µs.

Figure 3.40 Output voltage ripple vs. on-time

Vin = 6V,Vo = 1.2V,L = 150nH/phase, 3 phases, Co = 2*330µF SP Cap + 18*22µF MLCC

VinQ2

Q1

Co ProcessorLoad

L

Vo

GateDriver

DCRVinQ2

Q1

Co ProcessorLoad

L

Vo

GateDriver

VinQ2

Q1

Co ProcessorLoad

L

Vo

GateDriver

DCR

A

0

5

10

15

20

25

30

0 0.2 0.4 0.6 0.8 1 1.2 1.4Ton (µs)

Outpu

tVo

ltage

Ripple (m

V)


105

(b) Select a maximum on-time to avoid inductor core saturation and to limit the root mean

square (RMS) current. The equation for inductor peak current Ioff is shown in (3-5), while the

inductor RMS current is shown in (3-6):

LTVV

II onoinLoff 2

)( −+= (3-5)

22

222

12)(

onoin

Lrms TLVVII −

+=

(3-6)

where IL is the average inductor current. These equations clearly show that a larger on-time leads

to a higher RMS current and peak current. The inductor size for a low-voltage, high-current

application is mainly determined by the saturation current and the winding loss, which is

proportional to Irms2. Since the volt-second on the inductor is very small, the core loss is

negligible for the given inductor. Based on the calculation tool provided in [58], the core loss is

only about 20mW, while the winding loss is as high as 150mW for a 20A load current, 600kHz

switching frequency and 150nH inductance.

Based on (3-5) and (3-6) , we can derive the maximum on-time to meet both the saturation

current and RMS current requirements, as shown in (3-7):

)])/([32,)/(2min( 22max NII

VVL

VVNIILT oLrms

oinoin

oLsaton −

−−−

= (3-7)

where ILsat is the saturation current of output inductor, ILrms is the maximum RMS current of

inductors, Io is the total load current, and N is the phase number of the multi-phase buck

converter. Both ILsat and ILrms can be found in the inductor manufacturer datasheet. For example,

FP2-V150 from Cooper Bussmann has ILsat = 25A and ILrms = 37A [59]. Figure 3.41 draws the

maximum on-time with different load currents for a three-phase Buck converter. It can be seen

the maximum allowed on-time Combining both voltage ripple and inductor requirements, the

maximum on-times for different load currents are shown in Figure 3.42. This figure provides the

upper limit for the on-time.


106

Figure 3.41 Maximum on-time vs. load current to

meet inductor requirement

Figure 3.42 Maximum on-time vs. load current after

considering both ripple and inductor requirement

(Vin=6V,Vo=1.2V, N=3, Inductor: FP2-V150, L=150nH, ILsat = 25A, ILrms = 37A

Co=2*330µF SP cap + 18*22µF Ceramic )

Now let’s look at how to select an optimal on-time to achieve higher efficiency with

different loads. Since the three phases of the buck converter are the same, here one phase of the

buck converter’s power losses is considered.

For conduction losses, we have:

2_)(_)( ))1(( rmsbotondstopondscond IDCRRDRDP ⋅+⋅−+⋅=

22

22

12

12)(

onoin

orms TLVV

II−

+=

(3-8)

where Rds(on)_top and Rds(on)_bot is on-resistance for the top and bottom switch, respectively, and

DCR is the DC resistance of the output inductor. Irms is the inductor RMS current, D is the duty

cycle, Io1 = Io/N, and N is the phase number.

For given Vin, Vo, L and Io:

221 oncccond TKKP += (3-9)

where Kc1, Kc2 are constant values.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 10 20 30 40 50Io (A)

Maxim

umon

‐tim

e (µs)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 10 20 30 40 50Io (A)

Maxim

umon

‐tim

e (µs)


107

The total switching loss (Psw) consists of two parts: Q1 turn-off loss (PQ1_off), and the other

part of the switching loss (Psw1) [50].

1_1 swoffQsw PPP += (3-10)

Since

onin

os TV

Vf 1= (3-11)

Psw1 can be calculated as:

on

ssinrrdeadFoinbotossintopossgbotggtopgsw T

KfVQTVIVQVQVQVQP 1

1____1 )5.05.0( =+++++=

(3-12)

where Qg_top and Qg_bot are the total gate charges of the top and bottom switch, respectively, and

Qoss_top and Qoss_bot are the switch output charges of the top and bottom switch, respectively. Vg is

the gate-driving voltage, Tdead is the dead time between top switch gate signal and bottom switch

get signal to avoid shoot-through, and Qrr is the reverse recovery charge of the bottom switch.

)21()

21( 2

_1 fVi

QIfV

iQ

IP ing

gsoffin

g

gdoffoffQ ×××+×××= (3-13)

where Ioff is the turn-off current, Qgd is the voltage-rising-related charge, Qgs2 is the current-

decreasing-related charge, and Ig is gate current.

moffissgsonoin

ooff gICQL

TVVII /

2)(

21 =−

+= (3-14)

where Ciss is the input capacitance of the top switch, and gm is the trans-conductance of the top

switch.

Replacing (3-11) and (3-14) into (3-13), we can finally get:

onsson

soffQ TKK

TK

P 432

_1 ++≈

(3-15)

Finally, based on (3-12) and (3-15) we can get:

onsson

ssswoffQsw TKK

TKKPPP 43

211_1 ++

+≈+=

(3-16)

where Ks1, Ks2, Ks3 and Ks4 are constant values for given Vin, Vo, L and Io.


108

Figure 3.43(a-b) verified (3-9) and (3-16) using a very accurate analytical model developed

in 3.1.4.1. The figure indicates that when Ton increases, which means a decrease in fs, conduction

losses increase too. However, switching losses do not necessarily decrease. As a result, there is

an optimal Ton to achieve the lowest power losses, as shown in Figure 3.43(c). The optimal on-

time is about 0.5µs, which is lower than the maximum on time (0.7µs) when Io=30A (from

Figure 3.42), so we can select Ton = 0.5µs to achieve higher efficiency.

(a) Conduction loss vs. on-time (b) Switching loss vs. on-time

(c)Total power loss vs. on-time

Figure 3.43 Power losses vs. Ton at CCM for one-phase of a three-phase buck

(Vin = 6V, Vo = 1.2V, L = 150nH, Io = 30A for three-phase)

Figure 3.44 shows the test results by varying Ton at CCM for different load currents. The

experimental setup is as follows:

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 0.2 0.4 0.6 0.8 1 1.2Ton (µs)

Power Loss (W

)

1.3

1.4

1.5

1.6

1.7

1.8

0 0.2 0.4 0.6 0.8 1 1.2Ton (µs)

Power Loss (W

)

0.8

0.9

1.0

1.1

1.2

0 0.2 0.4 0.6 0.8 1 1.2Ton (µs)

Power Loss (W

)


109

Vin = 6V, Vo = 1.2V, three phases.

Each phase configuration: Q1: 2*IRF7821, Q2:1*BSC024N025S,

Inductor type: FP2-V150 (L=150nH).

Total output capacitance: 2*330µF SP cap from Panasonic+ 18*22µF ceramic cap from TDK.

It can be clearly seen that for each load current there is an optimal on-time that offers the

highest efficiency. Based on the allowed maximum on-time for each current, it can be seen that

the optimal on-time for efficiency is lower than maximum on-time for all three of the load

conditions. Thus we can choose the optimal on-time to achieve higher efficiency. Another

observation is that different loads require different optimal on-times, which indicates that the

optimal on-time must be adaptively adjusted with load current.

(a) Io = 9A

(b) Io = 30A

0.4

0.5

0.6

0.7

0.8

0.2 0.4 0.6 0.8

Pow

er L

oss

(W)

Ton (µs)

1.2

1.3

1.4

1.5

0.2 0.4 0.6 0.8

Pow

er L

oss

(W)

Ton (µs)


110

(c) Io = 45A

Figure 3.44 Tested power loss vs. on-time with different load currents

Figure 3.45(a) illustrates the proposed adaptive on-time control concept. Ton is adjusted

according to the load current to achieve the highest efficiency. The optimal Ton has an almost

linear relationship with the load current, so it is easily implemented by hardware. Up to 2%

higher light-load efficiency can be achieved by the proposed method, as demonstrated in Figure

3.45(b).

(a) Optimal on time vs. load current

1.7

2.2

2.7

3.2

0.2 0.3 0.4 0.5 0.6 0.7 0.8

Pow

er L

oss

(W)

Ton (µs)

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

5 10 15 20 25 30 35 40 45 50

Ton

(µs)

Io (A)

Constant on‐time

Adaptive on‐time


111

(b) Efficiency with adaptive on-time control

Figure 3.45 Proposed adaptive on-time control to improve CCM efficiency- Case 1

3 phases, Vin = 6V, Vo = 1.2V

Figure 3.46 shows another example of adaptive on-time control with 12V input voltage.

The efficiency can be improved by up to 2% with the proposed adaptive on-time control. The


Vin = 12V, Vo = 1.2V, three phases.

Each phase configuration: Q1: 1*IRF7821, Q2:2*IRF7822,

Inductor type: Sumida CDEP134H-0R6 (L=600nH)


(a) Optimal on-time vs. load current

86.0%

87.0%

88.0%

89.0%

90.0%

91.0%

92.0%

5 10 15 20 25 30 35 40 45 50

Effic

ienc

y

Io (A)

Constant on timeAdaptive on time

0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55

5 10 15 20 25 30 35 40 45 50

Ton

(µs)

Io (A)

Constant on‐time

Adaptive on‐time


112

(b) Efficiency with adaptive on-time control

Figure 3.46 Proposed adaptive on-time control to improve CCM efficiency – Case 2

3 phases, Vin = 12V, Vo = 1.2V

It is also worthwhile to mention that Figure 3.45(a) shows that the on-time increases with

the load current while Figure 3.46(a) shows that the on-time decreases with the load current. This

is due to different circuit conditions.

As mentioned above, the transient performance of VR is mainly determined by the output

inductance instead of the on-time. As a result, changing on-time should not affect the transient

performance. Figure 3.47(a) shows the simulation results of the transient response with the

SIMPLIS software. It can be seen that adaptive on-time control can achieve the same transient

performance as the constant on-time control and both of them can meet the load-line transient

requirement from Intel with 2mΩ load-line resistance (RLL) [53]. Figure 3.47(b) shows that at the

beginning of the load step-down, the duty cycle of VR is saturated to zero to achieve the smallest

output voltage variation. After that, the on-time of the adaptive on-time control changes from

0.33 µs to 0.5 µs, which helps to improve the light load efficiency.

85.0%

86.0%

87.0%

88.0%

89.0%

90.0%

5 10 15 20 25 30 35 40 45 50

Effic

ienc

y

Io (A)

Constant on-time

Adaptive on time


113

(a)Output voltage comparison during the load transient

( Upper: Io Middle: Vo with constant on-time control Lower: Vo with adaptive on-time control)

(b)PWM signal comparison during the load step-down

Upper: Io ( from 45A to 10A)

Middle: PWM with constant on-time control ( on-time is constant: 0.33 µs)

Lower: PWM with adaptive on-time control (on-time for 10A: 0.5 µs; on-time for 45A: 0.33 µs)

Figure 3.47 Transient performance comparison between constant on-time control and adaptive on-time

control

(Vin = 12V, L = 600nH/phase, 3-phase, RLL = 2mohm

Total output capacitance: 8*270µF SP cap from Panasonic+ 18*22µF ceramic cap from TDK)

I(I1-

pos)

/ A

-10

10

30

Vo

/ V

1.08

1.12

1.16

1.2

time/mSecs 50uSecs/div

1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8

Vo

/ V

1.08

1.12

1.16

1.2

I(I1-

pos)

/ A

0

20

40

D /

V

-2

2

6


2.21 2.215 2.22 2.225 2.23 2.235

D /

V

-2

2

6


114

3.3.3. Improve DCM Efficiency with Non-linear Inductor

(A) Proposed Non-Linear Inductor Concept to Improve DCM Efficiency

As mentioned before, when the load current is below the critical current (Icrit), the buck

converter runs under DCM operation and the switching frequency begins to decrease. Since it is

a synchronous buck converter, the current will become negative if we do not turn off the gate

signal of bottom switch Q2 when the inductor current decreases to zero. Thus the inductor

current must be sensed. When the inductor current decreases to zero, the bottom switch is turned

off and the buck converter will run under DCM operation.

Figure 3.48 shows a loss breakdown at DCM operation with an accurate loss model from

3.1.4.1. It clearly shows that the dominant loss is still the switching losses. Therefore

determining a way to effectively lower the switching frequency is the key to further improve

light-load efficiency.

Figure 3.48 Loss breakdown at DCM Vin = 12V,Vo = 0.9V, Io = 2A, Ton = 0.5µs, fs = 200kHz

A very straightforward idea is to increase the on-time at light load to further decrease

switching frequency, as shown in Figure 3.49. It shows that for a given load current, when the on

time increases (as shown in dashed curve), the switching frequency can be decreased. However,

the current ripple increases, which increases the output voltage ripple.

Figure 3.49 Inductor current with increased on-time ( Dashed line is with larger on-time )

turn-on

turn-off

HS cond

LS cond

Driving

core loss

Turn-off

Gate driving

iL

t

Icrit/20


115

To better understand the voltage ripple at DCM, Figure 3.50(a) shows the three-phase buck

current on the output side. During CCM operation, the output current ripple decreases due to

interleaving operation and current cancellation, as shown in Figure 3.50(b). This means the AC

current on the output capacitor is small, which leads to a small voltage ripple. However, with the

DCM operation shown in Figure 3.50(c), the current cancellation effect is lost, so the AC current

on the output capacitor increases in relation to the CCM operation, which leads to a higher

voltage ripple.

(a) Three-phase Buck on the output side

(b) CCM operation (c) DCM operation

Figure 3.50 Output current ripple increases under DCM operation, which increase the voltage ripple.

Figure 3.51 illustrates the conflict between efficiency and voltage ripple with 12V input. In

terms of efficiency, the on-time needs to be large during DCM. However, to meet the

requirements for the output voltage ripple, the maximum on-time needs to be decreased. As a

result, we must choose the maximum on-time instead of the optimal on-time for efficiency.

3 Phases VR

ESR

Co

ic

iL_t

ESL

iL

t0

t

t

0

0

CCM

iL_t

ic

iL

t0

t

t

DCM

iL_t

ic

0

0


116

Figure 3.51 Conflict between efficiency and voltage ripple at DCM

To solve the conflict, it is desirable to keep a similar inductor current ripple or to reduce the

output filter corner frequency, which means the inductance at DCM should be larger.

The on-time at DCM can be obtained from:

(3-17)

where Ipk is the peak inductor current at DCM. From (3-17) we can see that when the peak

inductor current at DCM is fixed, Ton is proportional to L. From (3-4) and (3-17) we can derive:

(3-18)

This means the switching frequency can be further decreased by enlarging the output

inductance at light load. In Figure 3.52, the inductance is doubled. To keep the same inductor

peak current, the on-time is also doubled; therefore the switching frequency can be decreased by

half. At the same time, since the inductor current ripple does not change, a similar voltage ripple

is expected.

Figure 3.52 Switching frequency is reduced by increasing output inductance at during DCM

Io

Ton

CCMDCM

Optimal on time for

efficiency

Maximum on time for voltage ripple

o

pkon VM

ILT

)1/1( −

⋅=

LRf s ⋅∝1

iL

t

Io/20 2Ton1

iL

t0

Ton1

Io/2

2Ts

4Ts

Ipk

IpkL

2L


117

Laptop CPUs use different operating states to save power [53]. During the CPU active

state, because there is a fast transient, the VR should also have a fast response to meet the

transient requirement. The VR should run at CCM operation for the active state. As a result, a

small inductance is required to meet the transient requirement at active state [57]. However,

since there is no stringent transient requirement at CPU sleep state (DCM operation), a large

inductance is preferred for light-load efficiency. Figure 3.53 shows the requirement of the non-

linear output inductance at different CPU states.

Figure 3.53 Preferred output inductance to improve light-load efficiency

(B) One Simple Non-Linear Inductor Implementation

There are several ways to create a non-linear inductor. One way is to use controlled

magnetics, e. g. a magnetic amplifier [60]. However, this is a little complicated since it requires

the control signal to switch between large inductance and small inductance. The second way is to

use a saturable inductor [61], [62]. However, it is not easy to accurately control the inductance

since we depend on the permeability of the material to get the inductance, which varies greatly

with different magnetics. The third way is to use low permeability magnetic material such as

MPP, iron power core or LTCC material [63]. The permeability of these materials decreases

when the current increases, which decrease the inductance. However, the inductance changes

with load current very gradually, no as required in Figure 3.53.

The simple proposed structure to achieve the non-linear inductor is to use a saturable core,

as shown in Figure 3.54. When the inductor current is larger than the given saturation current (

Isat ), a small part of the core is saturated. Hence the equivalent air gap is lg which creates small

inductance Ls. When the inductor current is lower than Isat, the small part of the core is not

Io

Lo

LL

Ls

Sleep state Active stateIo

Lo

LL

Ls

Sleep state Active state


118

saturated, and the equivalent air gap is lg1, which creates the large inductance LL. The large

inductance (LL) and the small inductance (Ls) can be designed using (3-19):

( ) Auull

AAul

nLr

gegs

10210

2

−+

−

=

Aul

Auull

Auull

nLg

r

ge

r

ggL

20

1

1020

1

2

+−

+−

=

(3-19)

The parameters are described in Figure 3.54: A1 is the main magnetic area, A2 is the

magnetic area of the small part, le is the effective magnetic length, n is the number of turns, and

µr is the relative permeability of the core.

There are other structures that can realize a non-linear inductor. As long as the structure

can achieve the required inductance shown in Figure 3.53, it can be used to improve light load

efficiency. Figure 3.54 just provides a simple example which can be easily implemented.

(a) iL > Isat

(b) iL < Isat

Figure 3.54 Proposed saturable core to achieve desired inductance

(C) Proposed Control Method

le

A2

lg lg1A1

AC flux

le

A2

lg lg1A1

AC flux

le

A2

A1lg lg1

AC flux

le

A2

A1lg lg1 le

A2

A1lg lg1 le

A2

A1lg lg1

AC flux


119

The control method is very simple. Since the CPU can send out a signal (PSI#) to indicate

its current state (active state or sleep state) [53], the on-time can be adjusted immediately

according to this signal. At CPU active state, constant on-time or adaptive on-time control can be

applied, as shown in Figure 3.55 (for constant on-time control). At CPU sleep state, on-time can

be increased to get the same current ripple as CCM operation. The benefit of this control method

is noise immunity, because it can be achieved by using available controllers (e.g. MAX1545

from Maxim [56]) without current sensing.

(a) Control at CPU active state (CCM)

(b) Control at CPU sleep state (DCM)

Figure 3.55 Increased on-time for DCM operation with the proposed non-linear inductor

The calculated switching frequency of one design example is shown in Figure 3.56. It

clearly demonstrates that the proposed control method can further reduce the frequency to

improve light-load efficiency.

t

iL

Isat

t

iL

Isat

Ton1Ton1

(Vin-Vo)/Ls

-Vo/Ls

t

Isat

Ton2

Ton2> Ton1

(Vin-Vo)/LL

(Vin-Vo)/Ls

-Vo/Ls

-Vo/LL


120

Figure 3.56 Calculated switching frequency with proposed control with non-linear inductor

(Ls = 600nH, LL = 3uH, 3 phases, Isat = 3A, Iomax = 45A, Ton1 = 330ns, Ton2 = 3Ton1)

Another concern is the core loss, especially foe the small saturable part. Figure 3.57(a)

shows the core loss estimation based on the core loss density curve in magnetic material

datasheet. It can be seen the maximum core loss is only about 17mW, which is negligible. Figure

3.57(b) shows the core loss of the small saturable part is only about 1mW. So there should have

no hot spot for it.

(a) Non linear inductor vs. regulator inductor (b) Main part vs. saturable part for non-linear

inductor

Figure 3.57 Core loss estimation (Material: 3F3)

(D) Design Guideline with the Proposed Control Method

The design parameters for this control method are: Ton2, Isat and LL. Ls and Ton1 are already

determined by the transient requirement and switching frequency at active state, so they are not

o2

0.1 1 10 1001 .103

1 .104

1 .105

1 .106

fs1Io2

3

⎛⎜⎝

⎞⎟⎠

fs2Io2

3

⎛⎜⎝

⎞⎟⎠

Io2

Constant on-time control with regular

inductor

Proposed control method with non-

linear inductor

fs(H

z)

Io (A)

0.1 1 10 1001 .10 4

1 .10 3

0.01

0.1

Pc_non Io2( )

Pcb Io2( )

Io2

non-linear inductor

Regular coreCore loss

(W)

17mW

0.1 1 10 1001 .10 5

1 .10 4

1 .10 3

0.01

0.1

Pc_main Io2( )

Pc_small Io2( )

Io2IL

Main part

Small saturable part

Core loss

IL

1mW

10mW


121

design parameters. Since at CCM the preferred inductance is the small inductance for all of the

instant inductor current, Isat can be determined by (3-20):

2min_ rippleas

sat

IN

II −=

(3-20)

where Ias_min is the minimum CPU current at active state, N is the phase number of the VR, and

Iripple is the peak-to-peak inductor current at active state, which can be determined by (3-21):

s

onoinripple L

TVVI 1)( −=

(3-21)

If Isat as calculated by (3-20) is too small, there will be no benefit from the large inductor at

DCM. In this case, we cannot determine Isat based on (3-20) . Therefore the large inductance will

be seen in CCM, as shown in Figure 3.58. However, since the period for large inductance is very

short, it will not hurt the transient performance that much. For example, if the inductor valley

current is 1.6A and Isat is 2A, the time interval for the inductor current rising from 1.6A to 2A is

about 100ns (assume LL = 3uH). Equivalently, there is 100ns additional delay in the system

when load step-up happens. This 100ns delay only adds 2mV more voltage spike with 45A full

load current and 8*270µF output capacitance.

Figure 3.58 Large inductance can be seen at CCM if Isat is large

Ton2 and LL can be designed by the desired inductor peak current during DCM operation.

As mentioned, to meet the output voltage ripple requirement, the inductor peak current during

DCM operation should be equal to the inductor peak-to-peak current during CCM operation.

Based on the inductor current waveform shown in Figure 3.55(b), (3-22) can be derived:

oin

satripples

oin

satLon VV

IILVV

ILT−

−+

−=

)(2

(3-22)

t

iL

Isat

Ton1


122

Once LL is determined, Ton2 can be determined correspondingly. If a larger LL is chosen,

the switching frequency can be further decreased, as shown in Figure 3.59(a). Although the

output-capacitor ESR caused voltage ripple is the same with the same inductor current ripple, the

capacitor-discharge caused voltage ripple increases with a larger LL due to lower switching

frequency. As result, larger LL causes larger voltage ripple, which is shown in Figure 3.59(b).

Hence the trade-off between the switching frequency and the output ripple should be considered

when choosing LL. In our design example, LL=5Ls is chosen to be a good trade-off since the

output voltage ripple is similar to the constant on-time control with regular inductor case.

(a) Switching frequency vs. LL (b) Output voltage ripple vs. LL

Figure 3.59 Trade-off design for LL

Ls=600nH, 3 phases, Vin=12V, Vo = 0.9V, Isat = 2A, Ipk =Iripple = 6A, Co = 8*270µF SP cap+18*22µF MLCC

(E) Experimental Results

Based on the above design guidelines, a design example is provided, and its efficiency and

ripple test results based on an industry laptop VR demo board [56] are shown in Figure 3.60. The


Vin=12V, Vo=1.05V, single-phase operation of three-phase Buck VR

Each phase configuration: Q1: 1*IRF7821, Q2:2*IRF7822, Inductor type:

Sumida CDEP134H-0R6 (L=600nH) for regular inductor.

Customized EI-18 core with 3F3 material (Ls=600nH, LL=3.1uH) as the non-linear inductor.


Ton1 = 330ns, Ton2 = 3Ton1 = 990ns

0123456789

10

0 5 10 15 20

fs (k

Hz)

LL:Ls

02468

10121416

0 5 10 15 20Vo

rippl

e (m

V)LL:Ls


123

Figure 3.60(a) shows that the non-linear inductor VR can achieve 1%~4% higher

efficiency at light load and the similar efficiency at heavy load as the regular inductor VR. There

is an efficiency jump at 2A since Buck enters DCM operation and switching frequency starts to

decrease, as shown in Figure 3.60(b).

It should be mentioned that the efficiency shape at light load is different from Figure

3.38(a). This is because our test focuses on how the power stage efficiency itself is affected by

the proposed method. So the quiescent power consumption of the controller (MAX1545) is not

included. From Figure 3.60(c) we can see that this design also meets the 20mVpp output ripple

requirement with enough design margins.

The similar method can be applied to 2nd stage of two-stage VR, as shown in Figure 3.61. It

can be seen that the light load efficiency can be improvement by about 4% with the non-linear

inductor design.

(a) Efficiency comparison

(b) Switching frequency comparison

78%80%82%84%86%88%90%92%

0.1 1 10 100

Effic

ienc

y

Io(A)

L=600nH regular inductor

LL=3.1uH non-linear inductor

`

10

100

1000

0.1 1 10 100

Fs (k

Hz)

Io(A)

L=600nH regular inductorLL=3.1uH non-linear inductor


124

(c) Output voltage ripple comparison

Figure 3.60 Experimental results with the non-linear inductor (Vin = 12V, Vo = 1.05V)

Figure 3.61 2nd stage of two-stage VR efficiency with non-linear inductor

Ls=150nH, LL = 600nH, Vin=6V, Vo = 0.9V, Ton1 = 250ns, Ton2 = 2Ton1 = 500ns

02468

101214

0.1 1 10

Vorip

pe (m

V)

Io(A)

L=600nH regular inductorL=3.1uH non-linear inductor

78%

80%

82%

84%

86%

88%

90%

0.1 1 10

Effic

ienc

y

Io(A)

L=150nH regulator inductor

LL=600nH non-linear inductor

`

Chapter 4. High Efficiency Quasi-Parallel Two-Stage Architecture – Sigma Voltage Regulators

125

Chapter 4. High Efficiency Quasi-Parallel Two-Stage Architecture

– Sigma Voltage Regulators

4.1. Introduction

It was demonstrated in Chapter 3 that a two-stage VR can achieve high efficiency and high

power density. However, since two stages are in series, each stage should be able to handle the

full power. The overall efficiency of the two-stage VR is the multiple of the first stage and the

second stage, which decreases the second-stage efficiency. For example, with a 600kHz VR

design, the second-stage efficiency is more than 91%. Although the first stage can achieve 98%

efficiency, the overall efficiency still drops 2% due to the series connection.

Another two-stage approach is known as factorized power architecture (FPA) [27], which

can be used for 48V to 1.2V VR applications. The idea behind FPA is to apply the unregulated

converter (DCX) to serve as the second stage to achieve higher efficiency. It is well-known that

the unregulated converter can be designed at an optimal point to achieve highest efficiency. For

example, if an LLC resonant converter works at the resonant point, it can achieve zero voltage

switching (ZVS) and almost zero current switching (ZCS) operation [72]. Thus the efficiency is

much higher than a hard-switching or ZVS PWM converter. However, since an unregulated

converter cannot regulate the output voltage, a pre-regulated first stage is required to achieve

voltage regulation.

The two converters of the previous two-stage structures are in series; thus each stage

should be able to handle the full power. A more efficient way to deliver power was proposed in

[24], as shown in Figure 4.1. The basic concept here is to deliver the power to the load in

parallel, and use a high-efficiency unregulated converter to handle most of the power. The

unregulated cell is a Class-E inverter plus a rectifier. It can achieve high output impedance and

thus acts as the current source. The regulated cell is a switched-mode converter or a linear

regulator. Low output impedance is required for the regulated cell to control dynamics of the

system.


126

Figure 4.1 Parallel power architecture proposed by MIT

Unfortunately, this architecture cannot be applied to VR applications due to the very fast

load transient of the CPU. During the transient, most of the current is offered by the regulated

cell, which is only designed at very low power at steady state.

4.2. Proposed Sigma VR Structure

To achieve high efficiency and low cost, a sigma VR structure is proposed [25], as shown

in Figure 4.2 It is composed of a regulated converter (buck) and a high-efficiency unregulated

converter (DC/DC transformer or DCX). The inputs of the two converters are in series, while the

outputs are in parallel. That is why it is also named the quasi-parallel VR. There are three aspects

in the proposed structure:

(1) The input current is equal: Iin1 = Iin2

(2) The input voltage can be designed by n: Vin1 = nVo, Vin2 = Vin - nVo , where n is the

DCX converter turns ratio.

(3) The current (power) ratio from the unregulated converter to the regulated converter is

determined by: Io1/Io2 = Vin1/Vin2.

As a result, the power ratio can be controlled by n. For example, if n=6, and Vo = 1.2V,

then Vin1 = 8V (considering there will be some voltage drop in the DCX converter), Vin2 = 4V,

Vin1/Vin2 = 2:1. This means a high-efficiency unregulated converter handles 67% of the output

power, while the regulated converter only needs to provide 33% of the output power.


127

Figure 4.2 Proposed sigma VR architecture

The voltage gain of the proposed sigma VR is:

Dn

DVVM

in

o

+==

1

(4-1)

where D is the duty cycle of the buck converter. The higher the duty cycle is, the higher the

voltage gain is.

Figure 4.3 shows how the sigma structure achieves voltage output regulation during the

transient. There are two feedback mechanisms:

(1) Feedback from the power stage. For example, if there is a load step-up, the output

voltage will drop correspondingly. Since an unregulated DCX is like a voltage sensor,

Vin1 drops immediately. As a result, Vin2 increases, and hence increases Vo.

(2) Feedback from the closed-loop control. This works the same way as the conventional

control method. The closed-loop control increases the duty cycle of the regulated

converter to increase the output voltage and to achieve tight voltage regulation.

One important concept is to regulate the output voltage by changing the input voltage. This

is different from the conventional structures.

Vin

Iin1

Iin2 Io2

Io1

Vo

Iod

+-

+-

Vin1

Vin2

Av

1* *

nDCX

Buck

isolation


128

Figure 4.3 Voltage regulation of sigma VR

The benefits of the proposed structure include:

(A) High efficiency

The overall efficiency of the quasi-parallel VR is:

2

21

1 ** ηηηin

in

in

in

VV

VV

+=

(4-2)

where η1 and η2 are the efficiency of the DCX and buck converters, respectively. Equation (4-2)

clearly shows that the sigma VR efficiency is mainly determined by the DCX efficiency if Vin1

>> Vin2. It is well-known that the DCX can achieve higher efficiency than a buck converter since

it can run at optimal operation points. It will be demonstrated later that the unregulated converter

efficiency can be as high as 90% at 600kHz switching frequency. The efficiency of the regulated

converter is also higher (~91% at 600kHz) due to its low input voltage (3V-4V). Thus, the

overall efficiency is about 90%, which is about 4% to 5% higher than the state-of-the-art multi-

phase buck VR solution, which has 85%-86% efficiency with the same switching frequency.

(B) Output capacitor reduction

With the help of the extra low output impedance of the unregulated converter [76], [78],

the transient performance of the proposed VR is better than that of a buck converter. The reason

for this is that high-voltage input capacitors can equivalently serve as the output capacitors with

n2 times higher capacitance. As a result, there is no need to put as many output capacitors there

to achieve transient requirement. This feature will be illustrated in detail later.

Vo↓

Vin1↓

io↑( load change)Vin2↑

Vo↑Vo

↑

Vin

n:1

+

-

+

-

Av

Vo=Vin*d/(1+nd)

1* *

n

d↑


129

4.3. Design Sigma VR with Scalability

4.3.1. Buck Converter Design in Sigma VR

For the buck converter, it is better to design the duty cycle to be 50% to have both good

step-up and step-down performance [57]. Since the output voltage is about 1.2V, the input

voltage should be around 2.4V. After considering the input voltage variation (11V~13V), the

nominal input voltage is chosen to be 4V, as shown in Figure 4.4. Based on the study in Chapter

3, high efficiency is expected for the buck converter due to low switching loss and low-voltage-

rating devices.

However, this buck converter is different from the previous 5V-6V buck converter used for

the second stage of the two-stage VR. The sigma VR can reach the input voltage (12V) at startup

and light-load operation (these will be explained later). Fortunately, the output current is very

low for these conditions. So there would be less resonance on the devices than with a 12V buck

converter running at full load. A 20V MOSFET can be selected instead of a 30V MOSFET.

As for the current, since the current 12V input VR has 20A for each phase, we just follow

the current practice.

Figure 4.4 Buck converter in sigma VR

4.3.2. DCX Design in Sigma VR

Since the buck current has been determined, the DCX current can be calculated based on

the power ratio between the DCX converter and the buck converter. For example, if a single-

phase buck is chosen with a 20A output current, the DCX should deliver about 40A. A high-

Vin

1.2V

Io

+-

+-

Vin1

Vin2

8V

3V~5V

11V~13V

1* *

nDCX

Buck

isolation

20A


130

efficiency DCX should be selected. The DCX converter can be any PWM converter or resonant

converter, as long as it can achieve high efficiency. For high-switching-frequency applications,

resonant converters are preferred to reduce the switching loss. Figure 4.5 shows an example of

an unregulated converter [75]. The leakage inductor (Lk) of the transformer resonates with the

output capacitor (Co) to achieve almost ZCS operation. Meanwhile, Q1 and S1 can achieve ZVS

by resonance between the magnetizing inductor of the transformer and the output junction

capacitor of the MOSFET. Therefore, the switching loss can be almost eliminated. The voltage

ratio can be designed by the transformer turns ratio. For example, if the input voltage is 8V and

output voltage is 1.2V, the transformer turns ratio should be 6 to leave some margin for the

voltage drop on Q1, S1 and the transformer windings.

It can be seen that this converter has the same number of devices and magnetic components

as the buck converter. As a result, it is reasonable to have a 20A output for this converter.

Ideally, if we need 40A, we can use two DCX converters in parallel. However, since the DCX

converter is unregulated, the current sharing cannot be guaranteed. Therefore, two DCX

converters are not recommended to be in parallel directly. To get 40A, we propose to use a

quasi-parallel structure again for two DCX converters, as shown in Figure 4.5. The inputs of the

two DCX converters are in series, while the outputs are in parallel. Based on the same theory as

the sigma VR, we can assume that since the input voltage is the same, the current of the two

DCX converters can be automatically shared.

Figure 4.5 DCX example 1: ZVS quasi-resonant converter proposed by CPES

* *

LK

LM

Q1S1

Cois1ip

One Transformer

DCX220A

DCX120A4V

4V

1.2V


131

Although the input voltage for each DCX is only 4V, Q1 should use a 30V MOSFET due to

the resonance between the output junction capacitors of Q1 and the magnetizing inductor of the

transformer [75]. As for S1, the voltage peak is about 10V. Thus a high-performance 12V

MOSFET can be used to get better efficiency. The transformer turns ratio is 3:1 for each DCX

converter. It should be mentioned that an additional auto-transformer is required to average the

output voltage of the two single-phase DCX and to reduce the output voltage ripple [25].

Another possibility is to find a DCX converter that can deliver 40V without further

paralleling. The LLC resonant converter is a good candidate [72], as shown in Figure 4.6. The

LLC resonant converter has an input voltage of 8V, n=3, and all switches are 12V MOSFETs.

Since it works at the resonant frequency, ZVS and almost ZCS can be achieved to get high

efficiency.

Figure 4.6 DCX example 2: LLC resonant converter working at fixed frequency

There is a special configuration for ZVS-QR DCX in order to reduce the output voltage

ripple, as shown in Figure 4.7. An additional auto-transformer is required to average the output

voltage of the two 40A DCX and to reduce the output voltage ripple. Figure 4.7 also provides the

test results. The voltage ripple of each DCX is high since Lk needs to resonate with output

capacitors. However, due to the interleaving and averaging effect of auto-transformer, the final

output ripple is very small. Another observation is that the volt-second on the auto-transformer is

very low (determined by Vo1-Vo2 and switching frequency). Therefore, the size of the auto-

transformer is very small. For LLC DCX, there is no such configuration since the output voltage

ripple is relatively low.

DCX40A8V

1.2V


132

Figure 4.7 Autotransformer is required to reduce output voltage ripple for ZVS-QR DCX

Figure 4.8 shows the efficiency comparison between ZVS-QR DCX and LLC DCX. It

shows that LLC DCX can get slightly higher efficiency but it needs 4 more MOSFETs.

4-phase ZVS-QR DCX (80A)

4*RJK0301 + 4*CSD13301 Total devices: 8

fs=600kHz, duty cycle: 75%

4EIR11 + 1EIR9.5, 3F3, Total magnetic components: 5

2-phase LLC DCX (80A)

12*CSD13301, total devices: 12

fs=530kHz, duty cycle: 50%

4 EIR14, 3F3, total magnetic components: 4

*

*1

1

Co

Vo

DCX1-240A

DCX3-440A

Vo2

Vo1

Vo1 Vo2

Vo5mV

Vo1 Vo2

Vo5mV


133

Figure 4.8 Efficiency comparison between ZVS-QR DCX and LLC DCX (fs = 600kHz)

Figure 4.9 shows the loss breakdown comparison between the two DCXs. Although LLC

DCX has more synchronous rectifiers (SR), the SR conduction loss is still higher than ZVS-QR

DCX. The reason is ZVS-QR DCX has 75% duty cycle for SR conduction while LLC DCX only

has 50%, and larger duty cycle results in lower RMS current. In the following design example,

ZVS-QR DCX is chosen to reduce the VR cost.

Figure 4.9 Loss break down of ZVS-QR DCX and LLC DCX @ 80A

70%

75%

80%

85%

90%

95%

0 20 40 60 80 100

4-P ZVS-QR DCX

2-P 40A LLC DCX

Io(A)

Efficien

cy

0

2

4

6

8

10

12

4‐P ZVS‐QR DCX

2‐P 40A LLC DCX

Power

loss (W

)


134

4.3.3. Sigma Cell Concept for Scalability

The above sigma VR can deliver 60A current. Comparing with a three-phase buck VR,

which also has 60A current, the sigma VR has the same number of devices and magnetic

components, which means a similar cost, as illustrated in Figure 4.10.

Figure 4.10 Comparing 60A sigma cell with 3-phase buck

The above structure can be treated as one sigma cell. Based on this cell, a scalable sigma

VR can be built to deliver more current. Figure 4.11 shows the basic concept, which has the

same basis as the multiphase buck VR. The only concern is current sharing among cells. Since

there is a fixed power ratio between the buck converter and the DCX converter for each sigma

cell, as long as all the buck converters in every cell can share the current, all the DCX converters

can share the current too. Moreover, the commercial VR controllers used to control the multi-

phase buck VR can be used to control all buck converters in the sigma VR.

For example, DCX1 and DCX2 which are ZVS quasi-resonant converters are the DCX

converters for different sigma cells. Assuming the on-resistance of Q1 and S1 differs by 20% for

two DCX converters in different cells, the DCX converter currents are different for the two DCX

converters, as shown in Figure 4.12(a). By slightly adjusting the buck duty cycle of the two DCX

converters, the current can be shared, as shown in Figure 4.12(b).

DCX20A4V

4V

1.2V4V DCX

20A

Buck20A

1.2V

12V

Buck20A

Buck20A

60A 60A

3-phase Buck -60A Sigma Cell -60A

12V

Buck20A


135

Figure 4.11 Scalable VR with sigma Cell

(a) Without current sharing (b) With current sharing

Figure 4.12 Current of DCX can be shared by controlling buck duty cycle

With the above configuration, the total load current is the multiple of 60A (e.g. 60A, 120A,

180A, etc). So if we need 120A, which is required for the VR11, two sigma cells should be

1.2V

60A*N

DCX20A4V

4V

4V DCX20A

12V

Buck20A

DCX20A4V

4V

4V DCX20A

Buck20A

.

.

.

Cell #1

Cell #N

U6-OUT / V

0

0 . 5

1

1 . 5

2

2 . 5

3

3 . 5

4

4 . 5

t i m e / m S e c s 5 0 0 n S e c s / d i v

4 . 9 3 8 5 4 . 9 3 9 4 . 9 3 9 5 4 . 9 4 4 . 9 4 0 5 4 . 9 4 1

U14-OUT / V

- 1

0

1

2

3

4

d1=46%, d2=46%

t i m e / m S e c s 1 u S e c s / d i v

4 . 9 5 1 4 . 9 5 2 4 . 9 5 3 4 . 9 5 4 4 . 9 5 5 4 . 9 5 6 4 . 9 5 7 4 . 9 5 8 4 . 9 5 9 4 . 9 6

A

0

2 0

4 0

6 0

8 0

1 0 0

IDCX1 = IDCX2

U6-OUT / V

0

0 . 5

1

1 . 5

2

2 . 5

3

3 . 5

4

4 . 5

t i m e / m S e c s 5 0 0 n S e c s / d i v

4 . 9 3 8 5 4 . 9 3 9 4 . 9 3 9 5 4 . 9 4 4 . 9 4 0 5 4 . 9 4 1

U14-OUT / V

- 1

0

1

2

3

4

d1=45.3%, d2=48%

t i m e / m S e c s 1 u S e c s / d i v

9 . 9 4 1 9 . 9 4 2 9 . 9 4 3 9 . 9 4 4 9 . 9 4 5 9 . 9 4 6 9 . 9 4 7 9 . 9 4 8 9 . 9 4 9 9 . 9 5

A

0

2 0

4 0

6 0

8 0

1 0 0

IDCX1 > IDCX2


136

used, as shown in Figure 4.13. The prototype has a two-phase buck converter and a four-phase

DCX converter, and the prototype has the same number of components as a six-phase buck

converter, which also delivers 120A.

Figure 4.13 One design example: 120A VR for VR11

Figure 4.14 shows the test efficiency of the sigma VR and its comparison with a six-phase buck

VR. The circuit setup is shown in Table 4.1.

Table 4.1 Circuit parameters for sigma VR and 6-phase buck VR

Configurations Devices Switching

frequency Magnetic components

6-phase buck VR 6 phases (1*RJK0305 +

1*IRF6635) /phase 600kHz 200nH/phase

Sigma VR

2-phase buck

and 4-phase

DCX

Buck: (1*Si7106 +

1*BSC019N02)/phase

DCX: (1*RJK0301 +

1*CSD13301)/phase

600kHz

Buck: 150nH/phase

DCX: EIR11/phase, 3F3

Auto-transformer:

EIR9.5, 3F3

The experimental results show that 90% efficiency can be achieved by the sigma VR, which is

about 3~4% higher efficiency than a single-stage VR. Thus it can meet the efficiency requirement from

IBM and Intel.

1.2V

120A

DCX120A4V

4V

4V DCX220A

12V

Buck120A

DCX320A4V

4V

4V DCX420A

Buck220A

Cell #1

Cell #2 2-phase Buck

4-phase DCX


137

Figure 4.14 Tested efficiency for sigma VR

The previous sigma cell current was 60A. Thus the sigma VR can only get: 60A, 120A, 180A,

240A, etc. Scaling down the cell current provides more flexibility. Figure 4.15 shows how to scale down

a 60A sigma cell to a 30A sigma cell.

Figure 4.15 30A sigma VR cell

This figure shows a sigma VR cell composed of one 20A DCX converter and one 10A buck

converter. The DCX design is slightly different with a 60A sigma cell since both the transform turns ratio

and the primary-side switch need to be changed, as shown in Figure 4.16. As for a 10A buck, we can just

borrow the design for another POL converter that has similar current. For example, the DDR VR

normally has about 10A current, so we can use that design. Basically, compared with the 20A buck

design, the 10A design just needs to have the die size of the devices reduced by half and have the inductor

70%

75%

80%

85%

90%

95%

0 20 40 60 80 100 120 140

Effic

ienc

y

Io (A)

Sigma VR 6-phase Buck VR

DCX20A4V

4V

1.2V4V DCX

20A60A

Sigma Cell -60A12V

Buck20A

DCX20A8V

4V

1.2V

30A

12V

Buck10A

Sigma Cell -30A

Scale Down


138

size reduced by half as well. Table 4.2 shows an example of a 10A buck design, which can also achieve

about 91% efficiency at 10A, which means that the 30A sigma cell can achieve about 90% efficiency.

Figure 4.16 30A sigma VR cell design

Table 4.2 An example of 10A buck design

20A Buck 10A Buck

Top Switch (20V) Si7106 (Rds=6mohm, Qgd=2.8nC) SiA430DJ (Rds=14.5mohm,

Qgd=1.4nC)

Bottom Switch

(20V)

BSC019N02 (Rds=1.6mohm,

Qg=60nC)

IRF6636 (Rds=3.5mohm,

Qg=21nC)

Inductor FP4-200, L=200nH.

Size: 10.8mm*6.2mm*5mm

FP2-D100, L=400nH

Size: 7.2mm*6.7mm*3mm

4.4. Modeling and Transient Analysis of Sigma VR

To close the loop and achieve AVP, first the small-signal model of the sigma VR must be

studied. Figure 4.17 shows the small-signal model of the power stage of the proposed converter,

where Rout and Lout represent the output impedance of the DCX converter [76].

DCX20A8V

4V

1.2V

30A

12V

Buck10A

Sigma Cell -30A

Select devices with half of the die size; inductor with half of the size comparing with 20A Buck

n:1* *

Q1S1

is1

Vin=8V

n=6

Q1: 60V MOSFET

S1: 12V/20V MOSFET

Co


139

Figure 4.17 Small-signal model for the power stage

Basically the power stage itself has closed-loop feedback from the DC/DC transformer,

which attenuates the gain of the open-loop transfer functions, in contrast with the buck converter.

Assume Rout and Lout is small enough, then the major transfer functions are shown in (4-3):

2

22

^

^

1

/11

oo

zcinovd s

Qss

DnV

d

vG

ωω

ω

+⋅

+

++

≈=

2

21

222

^

^

11

1

)/1()()1(

oo

z

in

inid s

Qsss

CDCnDnnV

d

iG

ωω

ω

+⋅

+

+⋅−+

−≈=

2

22

222

^

^

22

1

)/1()()1(

oo

z

in

inid s

Qsss

CnCDnV

d

iG

ωω

ω

+⋅

+

+++

≈=

)(/)1( 2ino CnCLDn ++=ω )()1(

1122

inco CnCDCRCRDnQ

++⋅⋅+⋅=

ω

CRczc

1=ω

inc

inz CnCR

CDnC ⋅−=1ω

212

2

2 CCCCCnRCnC

ininc

inz +=

+=ω

(4-3)

From (4-3) it can be observed that the double pole is moving with the duty cycle. However,

since other input voltage and output voltage range is narrow, the duty cycle does not change too

DCR

vo^ io

^

i2^

1 D

dVin/D

ILd^

L

Rc

C

* *

i1

1* *

nC1

C2

^

^

vin+-

Lout Rout

DCR

vo^ io

^

i2^

1 D

dVin/D

ILd^

L

Rc

C

* *

i1

1* *

nC1

C2

^

^

vin+-

Lout Rout


140

much at steady state. All of the other transfer functions can be derived based on the model and

they have the similar characteristics.

A CPU VR must achieve AVP to meet the Intel load line specifications. Generally the

current injection control method is applied to achieve AVP [77], as shown in Figure 4.18.

However, it is not easy to sense the DCX current since resonant type of DCX is used to improve

the efficiency.

Figure 4.18 Current injection control to achieve AVP from Intel

As explained before, the current ratio between DCX and buck is equal to the input voltage

ratio of them. As a result, we have:

22

oin

ino i

VVi =

(4-4)

Based on (4-4), a simpler way to achieve AVP is to only sense the buck current, as shown

in Figure 4.19(a). Figure 4.19(b) and (c) shows the desired output impedance to achieve AVP,

where Zo1c and Zo2c are the closed-loop impedance of the DCX and buck converters,

respectively; Zc is output capacitor impedance; and Zoc = Zo1c||Zo2c||Zc is the total closed-loop

output impedance of the sigma VR. The impedance of the DCX converter should be much lower

than the impedance of the buck converter within a wide frequency range to ensure that it also

handles most of the AC current during the load transient. Zoc should meet the impedance

requirement from Intel, which specifies that the impedance should be equal to or lower than RLL,

up to 2MHz [7].

Buck

DCX

Vin

n:1

Co

Vin1

io2

iin1

iin2

Vin2

io1

Vref

AVPWM

vo

++

+

+RLLIo

ioic Zc

Zo2c

Zo1c

Buck

DCX

Vin

n:1

Co

Vin1

io2

iin1

iin2

Vin2

io1

Vref

AVPWM

vo

++

+

+RLLIo

ioic

Buck

DCX

Vin

n:1

Co

Vin1

io2

iin1

iin2

Vin2

io1

Vref

AVPWM

vo

++

+

+RLLIo+

+

+RLLIo

ioic Zc

Zo2c

Zo1c


141

(a) Control diagram

(b) Equivalent circuit (c) Desired impedance

Figure 4.19 Control diagram and desired impedance by sensing buck current only

Figure 4.20 shows the small signal block diagram [77]. The definition of Tv, Ti and T2 is as

follows:

vdmvv GFAT = 2idmdroopVi GFRAT = i

v

TTT+

=12

(4-5)

High Freq. Buck

HF DC/DCtransformer

Vin

Co

Vin1

io2

iin1

iin2

Vin2

io1

Vref

AV

PWM

vo

++

Zo2

Zo1

io

Vin2 Vin

LLin

indroop R

VVR

2

=

Zc

Zo1c ioZo2c Zc

io1 io2 ic vo

Zo1c ioZo2c Zc

io1 io2 ic vo

ioZo2c Zc

io1 io2 ic vo

|Zo1c||Zo2c|

|Zo1c||Zo2c|

|Zc||Zc|

|Zo1c||Zo2c||Zo1c||Zo2c|

f

|Z|Desired impedance

f

|Z|

f

|Z|Desired impedance

|Zoc|RLL

2MHz

|Zoc||Zoc|RLL

2MHz


142

Figure 4.20 Small single block diagram of the sigma VR

Since the transfer functions of sigma VR is very similar to buck VR, we can just follow the

design guideline of buck VR to achieve constant output impedance [77]. The basic idea is to

push the current loop bandwidth higher than T2 bandwidth, so the inductor current of buck

converter can be treated as a current source, as shown in Figure 4.21.

(a) Inductor can be treated as a current source (b) Output impedance Zoi

Figure 4.21 Output impedance when the current loop closed (Zoi)

Small Signal Block

AvFM

Zo

Gvd

+

+

vo

d

Rdroop

--

Ti

Tv

Gii2

io

Gid2

++

i2 +

^

^

vo^ io

^

i2^

1 DRc

C

* *

i1

1* *

nC1

C2

^RoutLout

vo^

io^

Rc

C

Rout

Cin*n2

Lout


143

Figure 4.21 clearly shows that with the help of low output impedance of DCX (Rout and

Lout is low), the input capacitors is equivalently parallel with output capacitance with n2 times

capacitance. This explains why sigma VR has better transient performance than buck VR.

Figure 4.22 shows the benefit from sigma VR. Assume both buck VR and sigma VR has

the same output impedance, since sigma VR can get help from the input capacitors, Zoi of sigma

VR is lower than buck VR. Since the close-loop output impedance Zoc = Zoi/(1+T2), the required

T2 bandwidth of sigma VR is only 100kHz while the required T2 bandwidth of buck VR should

be 210kHz, by assuming the phase margin of T2 is 60 degree.

Figure 4.22 Reduced T2 bandwidth of sigma VR - with the same output capacitance with buck

( Co = 5 100µF + 18 22µF MLCC, Cin = 88uF for sigma VR, Rout = 1.3mΩ, Lout = 150pH)

Figure 4.23 Reduced output capacitance of sigma VR - with the same T2 bandwidth with buck

( Co = 5 100µF + 18 22µF MLCC for buck VR;

no bulk capacitor for sigma VR, Cin = 88uF, Rout = 1.3mΩ, Lout = 150pH)

1 .103 1 .104 1 .105 1 .106 1 .10780

70

60

50

40

30

20

gain Zc 2i π⋅ fnn⋅,( )

gain Zx 2i π⋅ fnn⋅,( )

gain Zo1_HF 2i π⋅ fnn⋅,( )

fnn

1/(sCinn2)+Rout

Zoi of multi-phase Buck VR

Zoi of sigma VR

T2 bandwidth:100kHz

T2 bandwidth:210kHz

Impe

danc

e

RLL=1mohm

1 .103 1 .104 1 .105 1 .106 1 .10780

70

60

50

40

30

20

gain Zc 2i π⋅ fnn⋅,( )

gain Zx2 2i π⋅ fnn⋅,( )

fnn

Zoi of multi-phase Buck VR with 5*100uF Bulk cap

Zoi of sigma VR with No Bulk Cap

T2 bandwidth:210kHz

Impe

danc

e

RLL=1mohm


144

Figure 4.23 shows the benefit from another angel. If the bandwidths of sigma VR and buck

VR are the same, sigma VR can eliminate all bulk capacitors with 210kHz control bandwidth,

while buck VR needs five 100 µF with the same bandwidth.

Figure 4.24 shows the SIMPLIS frequency-domain simulation results. Figure 4.25 shows

the time-domain simulation results. The circuit parameters are:

DCX: n=6, Rout = 1.3mΩ, Lout = 150pH, (DCX impedance) fs = 600kHz; Buck: fs =

600kHz, L=60nH. Vin = 12V, Vo = 1.2V, No Bulk Capacitors, decoupling capacitor: Co =

18*22µF, C1 = C2 = 2*22µF.

This suggests that the bulk capacitors can be eliminated, while a 600kHz buck converter

needs at least five 100µF ceramic capacitors to meet the transient requirement. It also shows that

the DCX converter takes care of most of the DC and AC current in the load transient condition.

Figure 4.24, Loop gain and closed-loop impedance Figure 4.25 Transient waveforms (Vo initial spike

can be ignored)

The above Lout and Rout value is from Vicor’s DCX [76]. Since they have advanced

packaging technology, both Lout and Rout are very small: Rout = 1.3mΩ, Lout = 150pH. In our

sigma VR prototype, all of the devices and magnetic components are discrete, which result in

larger Lout and Rout: Rout = 1.8mΩ, Lout = 3nH. Since Rout and Lout serves as ESL and ESR of the

1k 2k 4k 10k 20k 40k 100k 200k 400k 1M 2M 4M 10M-65-60-55-50-45-40-35-30-25-20

Zo1c( DCX)

Zo2c(Buck)

Zoc

Zc

1k 2k 4k 10k 20k 40k 100k 200k 400k 1M 2M 4M 10M-65-60-55-50-45-40-35-30-25-20

Zo1c( DCX)

Zo2c(Buck)

Zoc

Zc

-40

-20

0

20

40

1k 2k 4k 10k 20k 40k 100k 400k 1M 2M 4M 10M

-100

0

100

fc=230kHz, PM=75 degree

T2 (Gain)

T2 (phase)

-40

-20

0

20

40

1k 2k 4k 10k 20k 40k 100k 400k 1M 2M 4M 10M

-100

0

100

fc=230kHz, PM=75 degree

T2 (Gain)

T2 (phase) 4070

100

1.141.2

1.26


4.4 4.5 4.6 4.7 4.8 4.9205080

Vo

io

Io1 ( DCX current)

Io2 (Buck current)

4070

100

1.141.2

1.26


4.4 4.5 4.6 4.7 4.8 4.9205080

Vo

io

Io1 ( DCX current)

Io2 (Buck current)


145

equivalent input capacitors, the input capacitors cannot help too much for the transient

performance anymore. Figure 4.26 shows four 390µF SP capacitors are required to meet the

impedance requirement with 210kHz control bandwidth.

Figure 4.26 Bulk capacitors are required with large Lout and Rout

( Co = 4 330µF SP Cap + 18 22µF MLCC, Cin = 88uF, Rout = 1.8mΩ, Lout = 3nH)

Figure 4.27 shows the transient test results for sigma VR. It can achieve AVP requirement

from Intel.

(a) Load transient waveforms

1 .103 1 .104 1 .105 1 .106 1 .10780

70

60

50

40

30

20

gain Zx2 2i π⋅ fnn⋅,( )

fnn

Zoi of sigma VR with 4*SP Cap

Impe

danc

e

RLL=1mohm

fc=210kHz

Io: 30A/div

Vo:100mV/div


146

(b) Load step up waveforms (c) Load step down waveforms

Figure 4.27 Transient performance of sigma VR

( Co = 4 330µF SP Cap + 18 22µF MLCC, Cin = 88uF, Rout = 1.8mΩ, Lout = 3nH)

4.5. Startup and Light Load Efficiency Improvement of Sigma VR

From the information in the VR11 design guideline [7], the VR starts with a no-load

condition, as shown in Figure 4.28. After VR sends out VR_READY signal, CPU clock begins

to work, which means there is CPU current after that.

Figure 4.28 VR startup with no-load condition

Io: 30A/div

Vo:100mV/div

Buck PWM

Io: 30A/div

Vo:100mV/div

Buck PWM


147

For the startup of the sigma VR, the most challenging issue is how to let the DCX

converter soft-start. It is known that the DCX converter must have very small output impedance,

so the sigma VR cannot allow too much difference between the input and output voltages. Figure

4.29 shows that if there is a difference between Vin and the equivalent Vo on the primary side

(n*Vo where n is the transformer turns ratio), huge current can be observed.

Figure 4.29 Huge current observed if there is input and output voltage difference for DCX

The proposed soft-start method is shown in Figure 4.30. The basic idea is to soft-start the

output voltage reference. As a result, Vin1 will follow Vo with the fixed voltage ratio n. There is

no difference between the input voltage and equivalent output voltage for the DCX converter.

Therefore, no surge current can be observed. It also can be seen that the buck converter will see

12V input voltage for the soft-start case. However, since it is a no-load condition, there is no

high-voltage spike on the devices.

Figure 4.31 shows the experimental results for the soft start. It is not easy to get the current

information. However, based on the output voltage and input voltage from the buck converter

information, we can see there should be no surge current in the sigma VR during start-up.

* *

LK

LM

Q1S1

Cois10

2

4

6

8

10

time/uSecs 5uSecs/div

0 5 10 15 20 25 30 35 40 45-150-100-50

050

100150200

is1

Vin

Vo

More than 300A


148

Figure 4.30 Proposed start-up method for sigma VR

Figure 4.31 Experimental result for soft-start method

Another issue is the light-load efficiency of the sigma VR. In Figure 4.32, it can be seen

that the sigma VR has higher efficiency than the buck VR for all of the load conditions. A 60A

sigma cell is the minimum configuration. However, for the buck converter, the phase-shedding

strategy can be used to improve light-load efficiency. If we compare the sigma VR with the

phase-shedding buck VR, the light-load efficiency of the sigma VR is lower, as shown in Figure

4.32. Hence the light load efficiency must be improved.

Vgs(Q1)

0

Vgs(S1)

0Vin

* *

Vin

+-

+-

Vin1

Vin2

Q1

S1

Vin2

0

Vin

0

Vref

Gcv +-

Vref

Vo

Vo

Vin1 n*Vo

0

0

Q2 S2

Vgs(Q2)

0

VID

Vo

Vin2 (Buck input)


149

Figure 4.32 Light load efficiency comparison

If we look at a loss breakdown at light load for the sigma VR, it can be seen that the DCX

converter power loss is dominant, as shown in Figure 4.33. Therefore the key to improving light-

load efficiency is to improve the DCX converter efficiency.

Figure 4.33 Loss break at light load for sigma VR

The strategy for improving the light-load efficiency of the sigma VR is to change the

position of Vin1 and Vin2. At light load, if we can make the DCX converter input voltage zero,

70.0%

75.0%

80.0%

85.0%

90.0%

95.0%

0 10 20 30 40 50 60 70

Effi

cien

cy

Io (A)

Sigma VR3-phase Buck VR2-phase buck VR1-phase buck VRBuck with phase-shedding

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

0 2 4 6 8 10 12 14 16 18

Powe

r Los

s (W

)

Io (A)

DCX loss Buck loss


150

which means the buck converter takes all of the input voltage, the DCX converter will have no

power and the buck will take all of the power. As a result, the light-load efficiency can be

improved. Moreover, all of the methods used to improve the buck converter’s light-load

efficiency can also be used for the sigma VR. The sigma VR can achieve the same light-load

performance as the multi-phase buck VR.

Figure 4.34 shows the control strategy of shutting down the DCX at light load. Actually,

the CPU will send out a Power State Indicator (PSI#) signal to the VR to indicate that the CPU

will go into sleep mode and the VR should work at light-load condition. When the VR receives

the PSI# signal, it will always turn on Q1 and always turn off S1. Therefore, Vin2 will keep

increasing until it reaches the input voltage.

Figure 4.34 Shut-down DCX at light load to improve light load efficiency

However, when the sigma VR has a heavy load, we need to activate the DCX converter to

deliver more power, since the buck converter is designed to deliver a small part of the output

power. Figure 4.35 shows the control strategy of activating the DCX at heavy load. When the

VR receives the PSI# signal that the CPU will go into the active state, Q1 is turned off. Since

there is no energy transferred from the input side, Vin2 decreases quickly, and Vin1 increases

correspondingly. When Vin1 hits n times Vo, we can let Q1 and S1 work at normal condition and

Vgs(Q1)

0

CPU Active state

i s1

Vgs(S1)

0

CPU Sleep State

Vin2

0

0

0

V s

Vin

Vo

PSI# Signal

0Vin

* *

Vin

+-

+-

Vin1

Vin2

Q1

S1

Vref

Gcv +-

Vo

n:1

Q2 S2


151

there is no surge current, since the input voltage and equivalent output voltage of the DCX is the

same.

Figure 4.35 Activate DCX at heavy load for sigma VR

Figure 4.36 shows the light-load efficiency comparison again. It can be seen that the sigma

VR can achieve similar light-load efficiency with a buck VR, while having higher efficiency at

heavy load.

Figure 4.36 Light-load efficiency comparison by shutting down DCX at light load

Vgs(Q1)

0

i s1

Vgs(S1)

0

Vin2

0

0

Vin

0

CPU Active state

PSI# Signal

CPU Sleep State

Vin1n*Vo

0

Vin

* *

Lr

LM1

Vin

+-

+-

Vin1

Vin2

Q1

S1

Vref

Gcv +-

Vo

n:1

Q2 S2

70.0%

75.0%

80.0%

85.0%

90.0%

95.0%

0 10 20 30 40 50 60 70

Effi

cien

cy

Io (A)

sigma VR with DCX sheding

buck VR with phase shedding


152

4.6. Comparison between Sigma VR and Two-Stage VR

If we only compare the sigma VR and the two-stage VR, the sigma VR can achieve higher

efficiency, since the power is delivered to the load in parallel instead of in series. However, this

does not mean the sigma VR can replace the two-stage VR. Each of these VR designs can be

used in different applications.

1) The sigma VR cannot be used in laptop applications due to its wide input voltage range,

as shown in Figure 4.37. Two-stage power architecture is a better solution for laptop

computers.

Figure 4.37 Wide input voltage range for buck converter if the input voltage range is wide

2) To power the Itanium CPU which is for high-end servers, since there are three VRs to

power three different loads, using the sigma VR would be more complicated than using

the two-stage VR. As a result, the two-stage VR is preferred.

3) To power the Xeon CPU, since there is only one VR required and high efficiency is

very important, the sigma VR can be used to improve the efficiency.

4) For desktop computers, since the cost is still the most important thing, sigma VR is

more preferred due to its ability to reduce the output capacitors. More research is

required if sigma VR is applied to desktop computers.

Vin

1.2V

Io

+-

+-

Vin1

Vin2

7V

2V~12V

9V~19V

1* *

nDCX

Buck

isolation


153

4.7. Three Other Implementations of Sigma VR

The above just shows one implementation of the sigma VR, where the regulated converter

has the same ground for both the input and the output, and the DCX converter is isolated. Both

the DCX converter and the buck converter deliver the power to the load. We call this first

implementation, Implementation #1.

The most challenging part of implementing the proposed concept is the high-side converter

selection, since the input and output of the high-side regulated converter do not share the same

ground. One possible alternative implementation is to use an inverting buck-boost converter to

serve as the regulated converter in Implementation #2, as shown in Figure 4.38. However, the

drawback of Implementation #2 is that the unregulated converter should provide more current

than the load current, since the buck-boost converter is circulating power. It is not an efficient

implementation, especially for high-current applications.

Figure 4.38 Implementation #2 of sigma concept

To solve the grounding problem, it is better to use an isolated converter as the high-side

regulated converter, as shown in Figure 4.39. This third implementation works exactly the same

as the concept in Implementation #1, so it is an efficient converter. The regulated converter can

be a half-bridge PWM converter, a forward converter, etc.

Vin n:1 Io1

Io2

Vo

Io

+

-

+

-

Vin2

Vin1

AvInverting Buck-Boost

converter

Unregulated converter


154


There is one more implementation, which is shown in Figure 4.40. It has a similar working

principle as Implementation #2, so the efficiency is not good. However, Implementations #2 and

#4 do not require the transformer to perform isolation, so they may be used for low power POL

applications.


4.8. Other Applications for Sigma Architecture

4.8.1. Sigma Architecture for Low Current POL Converters

For low-power POL converters, high power density is required, since they are mostly for

portable applications. The simplest way to improve the power density is to raise the switching

frequency and further integrate the converter. Figure 4.41 shows that even when we push the

Vin n:1 Io1

Io2

Vo

Io

+

-

+

-

Vin2

Vin1

AvIsolated

D2D


isolation

Vin

n:1

Io1

Io2 Vo

Iod

+

-

+

-

Vin1

Vin2

Boost Converter

Unregulated Converter

Av


155

POL converter frequency up to 5MHz, the inductor size dominates the overall size. It is possible

to further reduce the inductor size by raising the switching frequency even higher, but the

efficiency would drop too much.

Figure 4.41 Inductor size is too large for POL converters

Let us determine which sigma structure is suitable for the POL converter. Since it is low

power, isolation is not preferred. Thus we select Implementation #2.

Figure 4.43 shows the detailed circuit diagram. Two voltage dividers are in series to get 4:1

voltage gain. As discussed in Chapter 2, the power density of the voltage divider is very high

because it doesn’t include any magnetic components. Although the regulated buck-boost

converter includes one inductor, it only needs to handle 2.5A current, which is 25% of the load

current. As a result, the inductor size can be greatly reduced compared with 10A buck POL

converters.

Figure 4.42 Implementation #2 is selected for POL converters

Die LIntegrated L

L Volume 16*Die

DieL

Integrated L

L Volume 13*Die

The size of the magnetic component dominates the overall size

Fs=1.5MHz Fs=5MHz

LTM460X EN536X

≈ ≈

Vin n:1 Io1

Io2

Vo

Io

+

-

+

-

Vin2

Vin1

AvInverting Buck-Boost

converter



156

Figure 4.43 Detailed circuit diagram for POL application

Figure 4.44 shows the inductor size comparison. The benchmark POL converter is from

Linear Technology (LTC3418) with a 1MHz switching frequency [79]. It shows that the sigma

POL converter can achieve 68% footprint reduction and 80% volume reduction. Figure 4.45

shows the efficiency comparison.

Figure 4.44 Inductor size comparison of sigma POL and buck POL converters

VD

Vin1

Vin

Vo

Co

Vin2

4:1

Q1

L

Q2

-

+

Q1

Q2

Q3

Q4

C2

C1

C3

Vin1

-

+

Q1

Q2

Q3

Q4

C2

C1

C3

Vin1

-

+

Q1

Q2

Q3

Q4

C2

C1

C3

Vin1

-

+

Q1

Q2

Q3

Q4

C2

C1

C3

Vin1 10.5A 10A

2.5A0.5A

Coilcraft

L=0.33uH, Isat=5A

DCR=23mohm

Dimension: 4.0*4.0*1.2mm

Toko

L=0.2uH, Isat=16A

DCR=4.5mohm

Dimension: 6.7 x 7.4 x 2.0 mm

Inductor for Sigma Converter Inductor for Buck Converter

68% footprint reduction

80% volume reduction


157

Figure 4.45 Efficiency comparison

It should be mentioned that although the sigma POL converter can greatly reduce the

inductor size, it also increases the silicon size significantly. As shown in Figure 4.43, a total of

ten MOSFETs are used in the sigma POL converter while only two MOSFETs are used for the

benchmark buck POL converter. However, based on the information from Figure 4.41, which

indicates that the inductor size is much larger than the silicon size, the sigma POL converter can

make a better trade-off between the silicon size and the size of the magnetic component.

To better understand the above argument, let us take EN536X as an example. The inductor

size of EN536X is about 13 times as the die size. With sigma configuration, the die size will

increase about 4 times, but the inductor size can be reduced by 80%, assuming the above ratio

still holds. Finally, the total size can still be reduced by around 50% with sigma power

architecture.

4.8.2. Sigma Architecture for Server and Telecom Applications

To embrace the traits of the LLC resonant converter running at the resonant point and

achieve the output voltage/current regulations, the sigma DC/DC architecture is proposed for

server and telecom applications [80], as shown in Figure 4.46. It features:

(1) High overall efficiency which is determined by the DCX at full load.

(2) High light load efficiency by shutting down DCX at light load.

60%

65%

70%

75%

80%

85%

90%

0 2 4 6 8 10

Io (A)

Efficiency

Benchmark: LTC3418single-phase Buck, fs=1MHz

Sigma POL converter


158

(3) Simple SR driving of the DCX due to the fixed switching frequency at resonant

frequency.

(4) With the help of the regulated converter, the output current can be easily controlled for

the modular paralleling, soft start and output current limiting/protection.

Figure 4.46 Sigma architecture for server and telecom applications

Vin

Iin1

Iin2

Iin1

Iin2 Io2

Io1

Io2

Io1

Vo

Iod

+

-

+

-

Vin1

Vin2

+

-

+

-

Vin1

Vin2

~98% IO

Av

1* *n 1* *n

DCX

isolation

1* *n 1* *n

~2% IO

PWM

Chapter 5. Conclusions and Future Work

159


This dissertation tackles two major challenges in VR design: achieving high efficiency and

achieving high power density. Two different power architectures are studied for this purpose.

5.1. Improvements of Series Two-Stage Power Architecture

The first power architecture is a two-stage architecture, and it has been investigated before.

Using the ‘divide and conquer’ concept, the single-stage VR is split into two stages to get even

higher efficiency and higher power density.

The first stage just reduces the input voltage from 12V to 6V, and the second stage can be

used to raise the frequency to reduce the output filter size.

In this dissertation, some improvements to the standard two-stage VR architecture are

made to make the two-stage design more attractive:

1. A higher-efficiency and higher-power-density switched-capacitor voltage divider is

proposed as the first stage to replace the buck converter first stage used previously.

• By analyzing the switching losses and conduction losses carefully and considering

parasitic inductors in the real circuit, 2000W/in3 power density voltage dividers are

designed with more than 97% efficiency. The light-load efficiency can be as high as

99%.

• Transient performance of voltage divider is analyzed in detail to make sure there

are no instability or interactions when the voltage divider is used as the first stage of

two-stage VR.

• Start-up and protection methods are proposed to make sure the safe operation of the

proposed voltage divider.

• Besides the switched-capacitor voltage divider, some other related topologies are

also studied. The three-level resonant buck converter can achieve similar efficiency

as the switched-capacitor voltage divider, but with lower power density. However,


160

with the help of the small inductor, voltage regulation can be achieved, which may

be helpful for current-sharing if paralleling is necessary.

2. Some improvements are made to the second stage. First, low-voltage-rating devices are

applied in the second stage, which leads to a 89% efficiency with 1MHz frequency.

Then, an adaptive on-time control method is proposed to improve the buck converter’s

efficiency at CCM operation. Up to 2% higher CCM efficiency can be achieved with

the proposed control method. A non-linear inductor with advanced control strategy is

proposed to improve the buck converter’s efficiency at DCM operation. Up to 4%

higher DCM efficiency can be achieved with the proposed method.

3. According to new situations, the two-stage VR architecture is no longer cost-effective

if one first stage is only used to power one second stage. To get better performance, the

two-stage power architecture is applied to laptop systems and high-end server systems,

and we call them as system level two-stage architecture. For laptop applications, it has

been demonstrated that a two-stage VR can achieve 5% lower cost and 45% footprint

reduction if the power density is the major concern. If efficiency is the primary

concern, it can achieve 3% higher efficiency with a similar cost. For high-end server

microprocessors, since high power density is required in the VR, 1MHz two-stage VRs

are designed to achieve similar efficiency as the single-stage VR, but with a 45%

footprint reduction.

5.2. Analysis and Design on Proposed Sigma Power Architecture

The two stages of the above architecture are in series, so the power is processed two times.

If the two stages are in parallel, the efficiency should be even higher. Sigma architecture is

based on this concept. The proposed sigma VR takes advantage of the high-efficiency, fast-

transient unregulated converter and relies on this converter to deliver most of the output power,

while it uses a low-power buck converter to achieve voltage regulation.

My contributions for this part include:

1. We proposed the sigma power architecture.

2. Ninety percent efficiency, which is required by IBM and Intel, has been demonstrated

for the sigma VR. Different DCX converter structures are discussed in the dissertation

to provide more flexibility for the sigma VR.


161

3. The sigma cell concept is introduced in the dissertation for scalability of sigma VR.

4. Modeling and design on sigma VR is illustrated in the dissertation and AVP is achieved

with experimental results. It demonstrated that the proposed sigma VR can achieve

33% output capacitor reduction.

5. Some other possible applications for sigma architecture are also investigated in the

dissertation. One example is that sigma architecture can play better trade-off between

the die size and the inductor size to reduce the total size of POL converters.

I do not assert that the sigma VR can replace the series two-stage VR. The drawback for

the sigma VR is that the input voltage range should be narrow (+-10%). Additionally, DCX

converter design is more complicated than buck converter design. As a result, both the sigma

VR and the two-stage VR can be applied in applications that can best make use of their

respective strengths.

5.3. Future Work

There are still some remaining works to be done which are related to this dissertation:

1. The detailed analysis on three-level resonant buck. This topology is only slightly

touched in this dissertation, thus thorough study on it, e.g. how to control three-

level resonant which can achieve both high efficiency and output voltage

regulation, should be a very good topic.

2. Evaluation on low-voltage lateral MOSFET for the bottom switch. It has been

demonstrated that lateral MOSFET can achieve higher efficiency than trench

MOSFET for the top switch, but due to the reverse-recovery problem of the body

diode, it cannot be used as the bottom switch of the buck converter. As body diode

performance is improved, the benefits of lateral MOSFET as the bottom switch

needs to be investigated.

3. Magnetic integration of DCX for sigma VR to reduce the leakage inductance. It has

been verified by simulation that with about 150pH equivalent output inductance for

DCX, the output bulk capacitors of the sigma VR can be eliminated with only

600kHz switching frequency. However, the current discrete version has about 3nH

output inductance for DCX and needs about four SP capacitors. Some magnetic

integration work may be done to reduce the leakage inductance of DCX.


162

4. Investigation of sigma VR for desktop computers. In this dissertation, the major

applications are laptop and server computers. Ideally, sigma VR is more suitable

than two-stage VR for desktop VR since the cost is its most concern. With careful

design, the sigma architecture could reduce the VR cost significantly while

achieving similar efficiency.

163

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Investigation of Alternative Power Architectures for CPU ... · Investigation of Alternative Power Architectures for CPU Voltage Regulators Julu Sun Dissertation submitted to the