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VLSI Design1994, Vol. 1, No. 4, pp. 277-284Reprints available directly from the publisherPhotocopying permitted by license only

(C) 1994 Gordon and Breach Science Publishers S.A.Printed in the United States of America

Resolution Enhancement in Iooofor Large ICs*t

Testing

YASHWANT K. MALAIYADept. of Computer Science, Colorado State University, Ft. Collins, CO

ANURA P. JAYASUMANA, CAROL Q. TONG, and SANKARAN M. MENONDept. of Electrical Engineering, Colorado State University, Ft. Collins, CO

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and isnormally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Manyfaults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders ofmagnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected bytraditional IC test techniques.

In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due tonormal parameter variations. A statistical characterization of the problem is presented. This can be used todetermine the optimal size of partitions. A new information compression scheme is presented which can signif-icantly enhance resolution.

Key Words: Iooo Testing; Built-in Current Sensing; Current Monitoring; Iooo Signatures; VLSI Testing

he use of leakage current measurement to detectfaults in CMOS iCs has been under considera-

tion for a number of years [1]. Recent studies onleakage current based testing techniques [2], [3] haveconcluded that it is necessary to include IDDQ mon-itoring to obtain highly reliable CMOS ICs. The datapresented for four sample CMOS ICs showed thatthe defect detection increased between 60% to 180%when IDDQ monitoring is added to a functional testset [2].

In the next section we review the research on cur-rent testing. We then discuss the statistical charac-terization of the currents of the circuits, and analyzethe partitioning of a circuit for the purpose of im-proving the resolution of the current testing. We pro-pose a new signature scheme for IDDQ testing andsummarize our findings in the conclusion.

"t’A preliminary version of this paper was presented at the 1991VLSI Test Symposium.

*This research was supported by a SDIO/IST funded projectmonitored by ONR.

BACKGROUND

There are several reasons for using IDDQ monitor-ing for testing of ICs [4], [5]. Traditional IC testingtechniques are not effective in detecting a numberof failure modes in CMOS ICs. In general, faultssuch as gate oxide shorts [4], [6]-[10], certain bridg-ing faults [11]-[14], certain open faults, stuck-onfaults [7], punch-through faults, operation inducedfaults [15], parasitic devices, pn junction leakage,and abnormally high contact resistance, may notmanifest as logic faults and therefore will not be de-tected by traditional tests which monitor the outputlogic levels. These localized defects degrade the elec-trical performance of the circuit without affecting thelogical operation performed by the circuit. Para-metric faults such as incorrect threshold voltage, ex-cessive parasitics, etc., are also difficult to detect bytraditional test techniques, and often affect circuitsignal delays as well as the power consumption. Im-plementing IDDQ testing prior to burn-in has re-suited in a significant decrease in the fall-out [5].

277

278 YASHWANT K. MALAIYA, ANURA P. JAYASUMANA, CAROL Q. TONG, and SANKARAN M. MENON

A major traction of failures caused by circuit fa-tigue will first appear as parametric drifts. Progres-sive gate oxide leaks, for example, may not initiallyaffect the functionality of a device, but could becomeshorts during a short time leading to the failure of adevice [7]. Eventually some of them will advanceenough to alter the logical behavior or circuit failure.Leakage current based testing will detect these para-metric drifts before they actually change the circuitbehavior. Data exists that show that a device thatfully passes the logic functional tests but fail theIDDQ test, fall in a significant category that func-tionally fail more frequently in early life than normal[4].

Current testing also is an invaluable tool for de-tecting faults in devices that contain both analog anddigital functions on a single substrate [16]. In nearfuture, a large fraction of devices are expected tocombine digital and analog functions on a single sub-strate [17].The off-chip current testing has several other ad-

vantages over the traditional functional testing tech-niques [1]. In functional testing, the site of a faulthas to be excited and the effect of the fault has tobe propagated to the output. In IDDO testing, thepropagation of the effect is automatic. Further, itcan provide transistor level resolution as opposed togate level resolution. Off chip current testing hasproved to be very efficient for circuits like staticRAMs [181.Most of the gate oxide shorts cannot be modeled

as stuck-at faults, especially for transistors with W/L >> 1 [19]. The use of current measurement tech-niques to find the gate oxide leaks is investigated in[20], and techniques are presented to test quiescentIDDQ to a 1 /za limit on every clock phase of afunctional test. It also identifies several problems as-sociated with the measurement of IDDQ. The cur-rent drawn by I/O circuits, for example, could maskthe current drawn by a fault. Other problems iden-tified include wideband noise across the load capac-itance, dielectric absorption in output pads, inputcapacitance offered by the VDD pin, and the pres-ence of mixed logic and redundant cells. To over-come these problems, use of several techniques dur-ing the design of ICs has been proposed, includingthe use of separate VDD pins for output buffers andinternal logic.

Stuck-on faults in CMOS circuits cannot be de-tected using traditional functional fault testing tech-niques. Test generation for detection of such faults,when IDDQ testing is used, is considered in [21].Different decision processes involved in detectingsuch faults have been examined. The voltage level

under stuck-on or bridging faults in CMOS circuitsdepend on the relative impedances of the transistorsinvolved and the bridge [22]. This makes detectionof such faults difficult using voltage measurementtechniques. However, IDDQ testing detects suchfaults. It has been shown that IDDQ testing alsodetects multiple stuck-at faults as well as logicallyredundant faults [22], [23].Most of the research in this area considers the use

of IDDQ measurement techniques for detection offaults in CMOS circuits. This can be attributed tothe fact that the static quiescent current drawn by aCMOS circuit is very small and therefore the detec-tion of a fault which increases the IDDQ is relativelyeasy to detect. With technologies such as NMOS andTTL, the quiescent current can be fairly large, andthe increase in current drawn due to a fault may notbe significant enough to be detected by measuringequipment.. Even so, current testing techniques havebeen successfully used to detect faults in TTL circuits[24]. The faults that have been detected include opencircuits, stuck at faults and multiple faults.The supply current measurement has been sup-

plemented in [25] with the measurement of low fre-quency noise in supply current, the circuit delay asa function of the supply voltage, transient current asthe circuit switches between states, and the noise intransient current to provide indication of incipientfailure of CMOS integrated circuits.

Several factors could complicate the testing of anIC by current measurements. One such example isthe strong non-linear characteristics of certain de-fects. It has been suggested that IDDQ be measuredat the highest possible VDD to overcome this prob-lem. It has, however, been observed that a mea-surement of IDDQ vs VDD could often identify thenature of the defect causing IDDQ elevation [2].High IDDQ logic states are inherent in some designsand may occur unintentionally in others. Examplesof such conditions include internal bus contentionstates in microprocessors, and IC’s with analog cir-cuitry [26].One obstacle for commercial acceptance of current

testing of ICs has been the relatively slow measure-ment rate compared to normal logic testing. Typi-cally, current testing is done at a rate less than 100Ktest patterns per second [20], whereas the functionaltesting can be carried out at the normal operatingfrequency of the device under test. The speed ofIDDO testing is limited by several factors. The widthof transient current pulse, loading of VDD pin dueto output buffers and the impedance of the probingcircuitry are some of them. It has been demonstratedthat the rate of testing can be increased by several

RESOLUTION ENHANCEMENT IN TESTING 279

orders of magnitude by isolating the output buffersof an IC from the VDD pin [2]. IDDQ testing wasdemonstrated to reduce line fallout after 99.6%stuck-at fault testing failed to achieve desired qualitygoals [27]. The high resolution required for currenttesting has been cited as another problem that makesacceptance of current testing difficult at present [3].The key to performing an effective IDDQ test is

the probe circuit used to measure the current. Sucha circuit should be capable of measuring small cur-rents, without affecting the supply voltage especiallyduring transients, and must be capable of fast mea-surements [28]. The different types of current probesin use are examined in [28], and a probe circuit hasbeen proposed which allows a system to performdynamic IDDQ tests as an integral part of the func-tional testing of a CMOS device.

Built-in current sensing techniques have been pro-posed to overcome the disadvantages of existing off-chip current testing techniques. Current sensors havebeen proposed and implemented using CMOS tech-.nology, some capable of detecting currents as smallas 2 a at 1 MHz clock frequency [3], [4]. In BICtesting, an IC is implemented using a number ofmodules and each module is connected to the powersupply through a current sensor. Another circuit de-sign for built-in current testing has recently been pro-posed [29]. The output of the current sensor of amodule is observed with the proper input vectors todetect faults in that particular module. Limitationsof BIC sensors due to virtual ground is given in [30].

STATISTICAL CHARACTERIZATION

Some approaches suggested for current testing in-volve recording the entire waveform or recording thevalue of IDDQ once each cycle. These approachesinvolve recording and processing a large amount ofinformation. They may not be suitable for testing alarge volume of devices or for a built-in-test appli-cation. The best approach is to make a binary de-cision each time. The IDDQ value is compared witha previously decided threshold value. If the measuredvalue exceeds the threshold, a fault is considered tohave been detected. We assume this approach in thediscussions below.IDDQ based testing requires measurement of an

analog quantity rather than a digital signal in case ofvoltage testing. Both the normal and faulty valuescan vary significantly. To arrive at an upper limit ofnormal IDDQ and to examine limitations of IDDQbased testing, a statistical characterization of theproblem is needed.

Resolution for Current Testing

In a normal CMOS device, one may view the overallconductance of the device (IDDQ/VDD) as the sumof conductances of individual cells, all connected inparallel (Figure 1). If the supply voltage is assumedto be fixed, we can write

IDDQ ioo (1)j=l

where ijDDQ is the quiescent supply current throughcell ], and n is the total number of cells.For each normal cell, iDQ will vary depending on

the parameter values as well as the input logic signals.It can therefore be regarded as a random variable.At this time not enough data exists that will enableus to find the applicable distribution. However for afirst approximation using the central limit theorem[31], we can assume that IDDQ, being a summation,has a distribution which is approximately Gaussian.If the current through an average cell, iA is charac-terized by /J,iADDQ and O’iADDQ then we can assume,

U,IDDQ n./.I,iADDQ

IDDQ V.ADDQ (2)

Let us now assume that at most one leakage defectexists. This is not a limiting assumption as a multipleleakage defect is likely to be tested more easily. Letus assume that the additional quiescent supply cur-rent, ir, is characterized by the parameters Iir(iU,IDDOf U,IDDO) and O’if(O’if-- O’IDDQf O’IDDO) Then

VDO

Cell Cell Cell

FIGURE 1 The parallel current paths in a CMOS device.


the overall supply current in the presence of a defectis given by IDDQ + i with the distribution given by

[J’IDDQf--n/J,iADDQ "- l,if (3)

o’moo x/no.aooo + cr (4)The distinction between the normal IDDQ and the

faulty IDDQ is easy if the two distributions are wellseparated. As most of the distribution is centeredwith (/x +_ 3r), we can define the separation betweenthe two distributions as (Figure 2):gap (/J’IDDQf- 30"IDDOf) (/J’IDDQ d- 30"IDDQ)

/-*if- 3(X/no’/2ADDQ + O’ + X.O’iADDO)

(5)

Deciding the Threshold Value

As we have discussed above, the most convenientsetup for current monitoring compares the measuredIDDQ with a preselected IDDoth" If the measuredvalue is higher, the device is regarded to be faulty.As discussed above, for larger devices, the dis-

tinction between the normal and faulty values maybe hard to make. A more strict screening will use alower value of IDDoth. However, this will result in alarger number of good devices being rejected.Below we obtain an expression for the probability

of incorrectly rejecting a good device.Let IDDOm be a measured value. Consider the fol-

lowing (Eqn. 6).

Prob{device is goodllDDOm > IDDoth}Prob{IDDOm > IDDQthldevice is good}.Prob{device is good}

Prob{IDDOm > IDDothldevice is good}.Prob{device is good} ]+ Prob{IDDo > IDDOthldevice is bad}.Prob{device is bad}J

(6)

This expression (Eqn. 5) illustrates the basic prob-lem in testing large devices. As n increases, thespread of the distributions also increase. For devicesthat are sufficiently large, the gap will become neg-ative, i.e. the two distributions will overlap.

where the right hand side is obtained by using theBayes’ rule.An optimal value of IDDQth would be arrived at by

considering the cost of rejecting a good device versusthe cost of passing a bad device. Many devices are

Densi tyfunction

Normal

FaulLy

OlDD#IDDQ

FIGURE 2 The ’gap’ between normal and faulty value.

IDDQr

#IDDQrCurrent


marginal, allowing a larger supply current, but thelogical operation is correct. The cost of using thesedevices is the higher drain on the power source aswell as significantly reduced reliability because of theheat generated.

PARTITIONING

From the discussion in the previous section, we haveseen that the gap between the normal and faultydistributions will decrease when the number of cellsn increases. If the number of the cells of a deviceexceeds a certain value, the gap becomes negative,i.e., the two distributions overlap. Under this situ-ation, it would be difficult to distinguish the faultycurrent from the normal one. The solution to thisproblem will be to partition the device under testinto modules. Each module will have its own currentsensor. Thus these modules can be tested indepen-dently. Similar equations about the parameters ofthe distributions can be established for each module.And the size of each module can be controlled suchthat the faulty and normal distributions within eachmodule can be distinguished.Below we obtain the criteria for a valid partitioning

for this device.The same equation for the gap applies for each

module:

gap /xi, 3(V’nO’iADDQ2 -t- O’/ d" nO’iADDQ)

(7)

Hence the device can be partitioned into moduleswhose sizes will not exceed rib, and all the moduleswill have approximately the same number of cells.CMOS circuits of different levels (1, 3, 5 and 10

levels) were chosen for simulation with BICS (Built-in Current Sensor) to determine the time for currentto settle. The number of levels indicate the numberof gates connected in series with one another. Forexample, simulation for 5 levels totaling 500 gateshas 5 gates connected in series with 100 such seriesof gates in parallel. Figure 3 shows plots for IDDsettling time vs. total number of gates for differentlevels of CMOS circuits. The current is sampled bythe BICS only after all the transients due to switchinghave completed and the current has settled to asteady low current value [3]. The settling time shownin Figure 3 shox0s the time when the current hassettled to about 5% of the steady low current valuefor sampling by the BICS. The settling time for a 10-level circuit for example, is greater than that of a 5-level circuit with the same number of gates due tothe larger propagation delay in the former. For acircuit with a given level, the settling time increaseswith the number of gates. The settling time thus hastwo components, one due to the propagation delay,and the other due to the capacitance at the node towhich the current sensor is connected. Thus thelarger the circuit that is covered by a current monitor,the longer the second component of the transienttime will be. Another advantage of partitioning isthe reduction of this component of settling time dueto the total capacitance.

where n is the number of cells in one module.Let us assume that maximum size of each module

is determined by letting gap by 0. Although we haveto use numerical methods to obtain the exact valueof n, we can derive the upper bound of n as follows:

/zi 3(X/n + + (8)

Since the term (/nr/2ADDO + cr/) in the aboveequation is greater than (X/-trinDDO), tz, can be writ-ten as:

>- 6X/-riaooo (9)

So the upper bound of maximum n, denoted byrib, is

no (10)\60"iADDQ/

A NEW SIGNATURE SCHEME

Here a new scheme is presented, which reduces theprobability of making an incorrect decision. It also

60.0

50.0i 40.0

_.O30.0

20.0

II} 10.0._0.0

10-1evel .."..-’*"

....

l02 4 102 6 102 102 l03Number of Gates (n)

FIGURE 3 IDDQ settling time vs. number of gates for differentlevels.


allows for high IDDQ states, which may occur insome normal devices for some test vectors [20].

Consider application of a set of test vectors forwhich current monitoring is done. The output of thesensing circuit is a binary sequence where a ’1’ rep-resents the fact that IDDQm is greater than IDDQth forthat vector. Rather than basing a decision on a single’1’, the string can be compressed into a signature,which can be used for evaluation. Since the faultscause a unidirectional error (i.e. 0 to 1) adding thenumber of ’l"s can be an appropriate signature. Ifthis signature S is greater than a preselected valueSth, the device is rejected.The effectiveness of this scheme is due to the fact

that by multiple samplings, more information is usedfor decision making.

Consider a situation when m randomly chosen vec-tors are applied, where m > Sth. The probability ofrejecting a good device then is given by the following:

Prob{S > Sthldevice is good}

s=-, (1 p)Sp,.-s (11)

where

P Prob{IDDOm < IDDothldevice is good} (12)

It is easy to see that this probability declines withincreasing Sth. Let us also consider the probability ofincorrectly accepting a bad device,

Prob{S < Sthldevice is bad}

(sm), (1 q)Sqm-S (13)

where

q Prob{IDDOm < IDDothldevice is bad} (14)

Again it is easy to see that this probability increaseswith increasing Sth.Thus the optimal value of Sth can be obtained only

by obtaining a suitable cost function involving thesetwo probabilities.The simplest current sensor can be built with either

a resistive or a capacitive element (labeled by ’X’ inFigure 4) along with a voltage comparator, as shownin Figure 4. The current flow will cause a voltagedrop on the element X and the voltage on X is fedto the comparator [28], [32]. The other input of thecomparator is the standard voltage which would re-

I-- --I

CUT

I--- F---I Comparator

Circuit

_L _k

FIGURE 4 A general current sensor.

suit from IDDOth on the same capacitor. Therefore, ifthe measured current IDDO is greater than IDDQth, theoutput of the current sensor is 1. If IDDO is equal toor smaller than IDDoth, the output of the current sen-sor is 0.The signature is obtained by counting the number

of times when the detected current flow exceedsIDDoth, which is denoted by S. If S -> Sth as discussedin the previous paragraph, then the device is re-garded to be faulty. The logic circuit that is used toextract the information about the signature is calledsignature extractor.

Since each module or subcircuit has its own currentsensor, it is impractical to observe the output of everycurrent sensor. One solution to this problem is topropagate the outputs of all the sensors to one ob-servable output pin which is designed solely for thesignature extractor. This signature extractor may beimplemented simply by an OR gate. The outputsfrom all the current sensors are fed to the OR gate.A counter is connected to the output of the OR gate,as shown in Figure 5, to calculate the total numberof times that the detected current IDDO exceeds/DDOth, which is nothing but the signature S.

=S

BICS Built-in Current Sensor

FIGURE 5 Partitioning and information compression.


This signature extractor also works correctly ifthere are more than one faulty module since in thatcase S will be even greater than that when there isonly one faulty module.

CONCLUSIONS

Testing of large ICs using IDDQ monitoring requirelarger test times and exhibits lower resolution be-tween faulty and fault-free devices. A statistical char-acterization of the quiescent current of a circuit mod-ule under normal and faulty conditions waspresented. The characterization was used to obtaina criterion for optimally partitioning a large circuitinto smaller modules for higher resolution in currentmonitoring. The partitioned circuits need lower testtime and result in enhanced resolution for IDDQmonitoring. A new signature scheme is proposedwhich allows the BICS outputs from several parti-tions to be compressed. It is shown that this schemewill further enhance resolution.

References

[1] Y.K. Malaiya and S.Y.H. Su, "A new fault model and test-ing technique for CMOS devices," Proc. Int. Test Conf.,pp. 25-34, 1982.

[2] C.F. Hawkins, J.M. Soden, R.R. Fritzemeier and L.K.Horning, "Quiescent power supply current measurementfor CMOS IC defect detection," IEEE Trans. IndustrialElectronics, pp. 211-218, May 1989.

[3] W. Maly et al., "Built in Current Testing," Research ReportNo. CMUCAD-88-27, Carnegie Mellon University.

[4] K. Baker and B. Verhelst, "IDDQ testing because ’ZeroDefects isn’t Enough’: A Philips Perspective," Proc. IEEEInt. Test Conf., pp. 253-254, 1990.

[5] S. McEuen, "IDDq Benefits," Proc. IEEE VLSI TestSymp., pp. 285-290, 1991.

[6] C.R. Barrett and R.C. Smith, "Failure Modes and Reli-ability of Dynamic RAMs," Proc. Int. Electron DevicesConf. (IEDM), pp. 319-322, Dec. 1976.

[7] C.F. Hawkins and J.M. Soden, "Reliability and ElectricalProperties of Gate Oxide Shorts in CMOS ICs," Proc.IEEE Int. Test Conf., pp. 443-451, 1986.

[8] S. Holland, I. Chen, T. Ma and C. Hu, "On Physical Modelsfor Gate Oxide Breakdown," IEEE Electron Dev. Ltr., pp.302-305, Vol. EDL-5, No. 8, Aug. 1984.

[9] C. Hu, "Thin Oxide Reliability," Int. Electron DevicesConf. (IEDM), pp. 368-371, Dec. 1985.

[10] J.M. Soden and C.F. Hawkins, "Electrical properties anddetection methods for CMOS IC defects," Proc. 1st Eu-ropean Test Conf., pp. 159-167, Apr. 1989.

[11] J.M. Acken, "Testing for Bridging Faults (Shorts) in CMOSCircuits," Proc. IEEE/ACM Design Automation Conf., pp.717-718, June 1983.

[12] F.J. Ferguson, M. Taylor, T. Larrabee, "Testing for Para-metric Faults in Static CMOS Circuits," Proc. IEEE Int.Test Conf., pp. 436-443, 1990.

[13] Y.K. Malaiya, A.P. Jayasumana and R. Rajsuman, "A De-tailed Examination of Bridging Faults," Proc. IEEE Int.Conf. on Computer Design, pp. 78-81, 1986.

[14] S.D. Millman and E. J. McCluskey, "Detecting BridgingFaults with Stuck at Test Sets," Proc. IEEE Int. Test Conf.,pp. 773-783, 1988.

[15] R. Rajsuman, A.P. Jayasumana, Y.K. Malaiya and J. Park,"An analysis and testing of operation induced faults in MOSVLSI," Proc. VLSI Test Syrup., pp. 137-142, 1991.

[16] J.E Frenzel and P.N. Marinos, "Power supply current sig-nature analysis: A new approach to system testing," Proc.Int. Test Conf., 125-129, 1987.

[17] A. Santoni, "Mixed-Signal Devices Create Testing Head-aches," Electronic Test, Feb. 1987.

[18] R. Meershoek, B. Verhelst, R. Mclnerney and L. Thijssen,"Functional IDDQ Testing on a Static RAM," Proc. IEEEInt. Test. Conf., pp. 929-937, 1990.

[19] M. Syrzycki, "Modeling of gate oxide shorts in MOS tran-sistors," Res. Rep. CMU CAD-88-22, Carnegie Mellon Uni-versity, Apr. 1988.

[20] C. Crapuchettes, "Testing CMOS IDD on large devices,"Proc. Int. Test Conf., pp. 310-315, 1987.

[21] Y.K. Malaiya, "Testing stuck-on faults in CMOS integratedcircuits," Proc. Int. Conf. on Computer Aided Design, pp.248-250, 1984.

[22] N.K. Jha and Q. Tong, "Detection of multiple input bridg-ing and stuck-on faults in CMOS logic circuits using currentmonitoring," Computers & Elec. Engg., Vol. 16, No. 3, pp.115-124, 1990.

[23] R.R. Fritzemeier, J.M. Soden and R.K. Treece, "IncreasedCMOS IC Stuck-at Fault Coverage with Reduced IDDQTest Set," Proc. Int. Test Conf., pp. 427-435, 1990.

[24] M. Hashizume, K. Yamada, T. Tamesada and M. Kawa-kami, "Fault detection of combinational circuits based onsupply current," Proc. Int. Test Conf., pp. 374-380, 1988.

[25] A.P. Dorey, B.K. Jones, A.M. Richardson, P.C. Russelland Y.Z. Xu, "Reliability testing by precise electrical mea-surement," Proc. Int. Test Conf., 369-373, 1988.

[26] L.K. Horning, J.M. Soden, R.R. Fritzemeier and C.EHawkins, "Measurement of Quiescent Power Supply Cur-rent for CMOS ICs in production testing," Proc. Int. TestConf., pp. 300-309, 1987.

[27] R. Perry, "IDDo testing in CMOS digital ASIC’s--Puttingit all together," Proc. Int. Test Conf., pp. 151-157, 1992.

[28] M. Keating and D. Meyer, "A new approach to dynamicIDD testing," Proc. Int. Test Conf., pp. 316-321, 1987.

[29] Y. Miura and K. Kinoshita, "Circuit design for built-in cur-rent testing," Proc. Int. Test Conf., pp. 873-881, 1992.

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Biographies

YASHWANT K. MALAIYA is a Professor in Computer ScienceDepartment and also in Electrical Engineering Department atColorado State University. He has published widely in the areasof fault modeling, software and hardware reliability, testing, andtestable design. He has also been a consultant for industry.He was the general chair of the 24th Int. Symp. on Microar-

chitecture and 6th Int. Conf. on VLSI Design. He is the generalchair of the 4th Int. Symp. on Software reliability Engineering.He has co-edited the IEEECS Tech. Series books "Software Re-liability Models, Theoretical Developments, Evaluation and Ap-plications" and "Bridging Faults and IDDQ Testing." He was aguest editor of special issues of IEEE Software and IEEE Design& Test. He has been the chair of TC on Microprogramming and


Microarchitecture. He is the chair of software test subcommitteeof TTFC and a vice-chair of the TCSE subcommittee on softwarereliability engineering. He is also a member of the IEEECS TABexecutive committee.He received B.Sc. from Govt. Degree College, Damoh, M.Sc.

from University of Saugor and M.Sc. Tech. from BITS, Pilani inIndia. In 1978 he received PhD in Electrical Engineering fromUtah State University. He was with State University of New Yorkat Binghamton during 1978-82.

DR. ANURA ,IAYASUMANA is an Associate Professor in theElectrical Engineering Department and the Computer ScienceDepartment at the Colorado State University. He received hisPh.D. degree in electrical engineering and the M.S. degree inelectrical engineering from the Michigan State University in 1984and 1982. He received his B.Sc. degree in electronics and tele-communication engineering, with first class honors, from the Uni-versity of Sri Lanka, Moratuwa, in 1978. Anura worked as anelectrical engineer at the National Engineering Research and De-velopment Center of Sri Lanka and as an assistant lecturer in theelectronics and telecommunication engineering department at theUniversity of Sri Lanka, from 1979 to 1980. Since January 1985he has been with Colorado State University. His research interestsinclude VLSI design and testing, design automation and data com-munication networks. He has served as a consultant to NCR Mi-croelectronic Division on CAD tool development since 1988.

Dr. Jayasumana is a member of Phi Kappa Phi, the IEEEComputer Society, the IEEE Industrial Electronics Society, theIEEE Communications Society, the IES Technical Committee onFactory Communications, and the CS Technical Committee onMicroprogramming. He was the winner of the award for the best

student in electrical engineering at the University of Sri Lanka,Moratuwa, in 1978, and the College of Engineering OutstandingAcademic Achievement Award, Michigan State University, in1982 and 1983. In January 1990, he received the OutstandingFaculty of the Year Award from the American Electronics As-sociation.

CAROL QIAO TONG received her B.S. degree in Electronicsand Electrical Engineering from Beijing University, Beijing, P.R.China in 1985, M.S. degree in Electrical Engineering from Prince-ton University in 1988, and Ph.D. degree in Electrical Engineeringfrom Princeton University in 1990. She is currently an AssistantProfessor of Electrical Engineering at Colorado State University.Her research interests include digital system testing, VLSI de-

sign, computer-aided design of integrated circuits and fault-tol-erant computing.

SANKARAN M. MENON is a Research Associate in the Com-puter Science Department and is a Ph.D. candidate in the Elec-trical Engineering Department at the Colorado State University.He received the Bachelor of Engineering in 1979, M. Tech in

Advanced Electronics from Jawaharlal Nehru Technological Uni-versity, Hyderabad, India in 1986 and M.S. in Electrical Engi-neering from Colorado State University in 1989. During his un-dergraduate studies, he continually received National Scholarshipsfrom the Government of India. He worked in the area of High-Speed digital design for Satellite Applications from 1979 to 1986.His research interests include VLSI Design, Testing, Fault Model-ing, Design for Testability and Fault-Tolerant Computing. He isa member of the IEEE Computer Society and Eta Kappa Nu.

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Iooo for Large ICs*t - Hindawi Publishing Corporationdownloads.hindawi.com/journals/vlsi/1994/027973.pdf · VLSIDesign 1994, Vol. 1, No. 4, pp. 277-284 Reprints available directly