IPP PSLF Stability Program Model - Block Diagrams · High-level block diagrams are provided as an aid in general understanding of the models. Note that the intent of this document

HVDC

Document number, revision Page Language

IPP STS HVDC Upgrade

1JNL635836, 1 of 30 en Status Resp.dept Class.no

Approved PG,PGGI,2861 - FG-746 Prepared Approved

Dave L. Dickmander, 2018-03-21 Radbrandt Ulf, 2018-04-10 Title

IPP PSLF Stability Program Model - Block Diagrams

Summary

PROPRIETARY AND SECRET INFORMATION

This report provides a very high-level (general) description of the stability program

model of the IPP STS HVDC system developed for the GE-PSLF program. The

PSLF program model of IPP HVDC has been delivered in two versions as follows:

Preliminary model: Code Version 3.4

Final model: Code Version 4.0

The preliminary model (Version 3.4) was originally developed during studies of the

Milford Wind project, and was later updated for the planned upgrade of the IPP

HVDC from 1920 MW to 2400 MW. The final model (Version 4.0) corresponds to

as-built conditions from the Dynamic Performance Study (DPS) for the 2400 MW

IPP HVDC Upgrade project, in which the IPP HVDC control systems were fully

replaced. The final model (4.0) also includes the same level of detail as the final

PSS/E program model for IPP. Both versions (3.4 and 4.0), include representations

of the following systems:

Bipole controls

Pole controls

DC Power Schedule Calculator, DCPSC

Fast DC Power Schedule Calculator, FDCPSC

Integration of Milford Wind into DCPSC and FDCPSC

Frequency control with deadband

Constant frequency control

Voltage dependent current order limit, VDCOL

DC current regulator

Simplifications exist in the preliminary model (3.4), while the final model (Version

4.0) includes all features of the PSS/E model.

The model represents the Intermountain Power Project HVDC system in normal

operation with the AC ties to Mona and Nevada either in service (synchronized with

Utah and Nevada) or out of operation (islanded), and with normal synchronous

bipole power control. Bipolar operation is assumed for pre-disturbance conditions,

but the model of the pole power control includes the features for pole loss

compensation so that tripping of a pole can be simulated.

The model is intended to represent IPP for stability study cases of approximately

10 seconds duration. This report describes the following EPCL files:

IPP_wecc_3_4.p: preliminary model

IPP_wecc_4_0.p: final model

High-level block diagrams are provided as an aid in general understanding of the

models. Note that the intent of this document is not to describe all details of the IPP

controls. The document is written to provide very basic and general information as

an aid in general understanding of the models by WECC. The actual IPP controls

and PSLF models are highly complex and include many functions that are beyond

the scope of this document. Detailed questions about the models should be referred

to LADWP and/or ABB.

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Table of Contents

Introduction ..................................................................... 3

Basic Concepts ............................................................... 4

Control Principles ............................................................. 4

Closed Loop Current Control ............................................ 4

Coordination of Two Closed Loop Current Controllers ..... 5

Voltage Dependent Current Order Limit (VDCOL) ........... 6

Overview of IPP PSLF Stability Models ........................ 9

IPP Bipole Controls ...................................................... 10

DC Power Schedule Calculator (DCPSC) ...................... 10

Thermal Generation ........................................................ 10

Wind Generation ............................................................. 11

Constant Frequency Control ........................................... 11

IPP Pole Controls ......................................................... 12

Power and Current Order Stepping Modules ................. 12

Fast DC Power Schedule Calculator (FDCPSC) ............ 12

Power Order Calculation ................................................ 12

Current Order Calculation ............................................... 13

Frequency Control with Deadband ................................. 13

Current Order Synchronization ....................................... 13

IPP Converter Controls ................................................ 15

Automatic Power Control, APC ...................................... 15

Voltage and Angle Reference Calculation, VARC .......... 15

Udi0 Calculation ............................................................. 15

Converter Firing Controls, CFC ...................................... 15

VDCOL ........................................................................... 15

Rectifier Alpha Minimum Limiter (RAML) ....................... 15

Inverter AlphaMax .......................................................... 16

Voltage Regulator (VCAReg) ......................................... 16

Current Control Limits, CCALim ..................................... 16

Current Control Amplifier ................................................ 16

CCA Gain Linearization .................................................. 17

Appendix A: PSLF Code Version 3.4 .................................. 18

Appendix B: PSLF Code Version 4.0 .................................. 24

Revision History ..................................................................... 30

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Introduction This report provides a very high-level (general) description of the stability program

model l of the IPP STS HVDC system developed for the GE-PSLF program. The

PSLF program model of IPP HVDC has been delivered in two versions as follows:

Preliminary model: Code Version 3.4

Final model: Code Version 4.0

The preliminary model (Version 3.4) was originally developed during studies of the

Milford Wind project, and was later updated for the planned upgrade of the IPP

HVDC from 1920 MW to 2400 MW. The final model (Version 4.0) corresponds to

as-built conditions from the Dynamic Performance Study (DPS) for the 2400 MW

IPP HVDC Upgrade project, in which the IPP HVDC control systems were fully

replaced. The final model (4.0) also includes the same level of detail as the final

PSS/E program model for IPP. Both versions (3.4 and 4.0), include representations

of the following systems:

Bipole controls

Pole controls

DC Power Schedule Calculator, DCPSC

Fast DC Power Schedule Calculator, FDCPSC

Integration of Milford Wind into DCPSC and FDCPSC

Frequency control with deadband

Constant frequency control

Voltage dependent current order limit, VDCOL

DC current regulator

Simplifications exist in the preliminary model (3.4), while the final model (Version

4.0) includes all features of the PSS/E model.

The model represents the Intermountain Power Project HVDC system in normal

operation with the AC ties to Mona and Nevada either in service (synchronized with

Utah and Nevada) or out of operation (islanded), and with normal synchronous

bipole power control. Bipolar operation is assumed for pre-disturbance conditions,

but the model of the pole power control includes the features for pole loss

compensation so that tripping of a pole can be simulated. The model is intended to

represent IPP for stability study cases of approximately 10 seconds duration.

This report describes the following EPCL files:

IPP_wecc_3_4.p: preliminary model

IPP_wecc_4_0.p: final model

The report presents some basic introductory information on the principles of HVDC

controls. After this introductory material, high-level block diagrams of the IPP

controls are provided along with general descriptions of the block diagrams.

Note that the intent of this document is not to describe all details of the IPP controls.

The document is written to provide only basic information as an aid in general

understanding of the models. Detailed questions about the models should be referred

to LADWP and/or ABB.

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Basic Concepts In their most basic form, HVDC converter controls include the following

fundamental parts:

DC Current Regulator

VDCOL

Inverter Alpha Max

An HVDC system can be fully controlled with the above systems alone, but other

considerations typically introduce additional controls to meet various requirements.

The IPP HVDC converter controls include the above parts in the converter control

system, with additional higher-level controls in the pole control and bipole control

for DC power scheduling, control of the DC power, current order synchronization,

frequency control, etc.

Control Principles

In order to illustrate the coordination of the controls between the rectifier and the

inverter, a monopolar line commutated HVDC transmission is shown below in

Figure 1. Note that IPP is modeled as a bipole with two independent poles, but the

principles in the following discussion apply equally to each pole of the IPP STS.

Figure 1. Basic Monopolar HVDC Transmission

In the above system, the transmitted power is proportional to the difference between

rectifier and inverter DC voltages, and thus will vary with changes in either of these

voltages. Therefore, the transmitted power in an HVDC transmission can be

controlled by changing the direct voltage in the rectifier or inverter. Since the

resistance of the DC line is relatively small, a change in the DC voltage in either end

can give a large change in the DC current, and DC power. The HVDC controls are

however very precise, and this means that HVDC systems offer excellent

controllability of the transmitted DC power during both steady-state and dynamic

conditions.

Closed Loop Current Control

In a normal two terminal HVDC transmission, one converter controls the DC

voltage, while the other controls the DC current. Both converters are equipped with

closed-loop DC current controls, coordinated as described below.

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A basic closed loop current control is shown below in Figure 2, comprising a Current

Control Amplifier (CCA), a Firing Control (FC) and a Control Pulse Generator

(CPG).

The CCA is designed with suitable settings for stable and fast control of the DC

current. The control error (Iorder - Iresp) is supplied to the CCA, which computes

the firing angle (-order) for input to the FC. The internal phase controlled oscillator

of the FC makes the appropriate corrections to the instant of firing to achieve the

ordered . The firing pulses are then distributed to the valves by the CPG.

The CCA normally includes a proportional part and an integrating part. In operation,

this means that the current control error will be minimized, and for steady-state

conditions it will be nearly zero.

Figure 2. Closed Loop Current Control

Coordination of Two Closed Loop Current Controllers

In a line commutated converter (LCC) HVDC transmission, all converters are

provided with a basic closed loop current controller. In a normal two terminal

transmission, the rectifier end normally controls the DC current, while the inverter

controls the DC voltage. This is done by subtracting a current margin (the magnitude

of which is normally 10% of nominal current) from the current order in the inverter.

Thus, the effective current order in the inverter is lower than that of the rectifier.

Since the closed loop current controller tries to establish ordered current, the

controller in the inverter end will increase its firing angle in order to lower the current

on the DC transmission. It will increase alpha until it reaches the maximum allowed.

Under this condition, with maximum alpha or minimum extinction angle , the

inverter is establishing the DC voltage for the system.

In short, the converter with the highest current order will operate as rectifier, and the

other as inverter. Figure 3 below shows the coordination between the two

controllers.

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Figure 3. Basic V-I Characteristics for HVDC

For a very basic inverter characteristic, with the inverter operating in minimum

extinction angle (-min) mode alone, the rectifier sees the inverter as a negative

impedance; i.e. the counter voltage produced by the inverter decreases with

increasing current. This “negative impedance” behavior creates a destabilizing

situation for the current control loop. To improve the stability, a positive slope

modification is made to the inverter characteristic at the operating point, as seen in

Figure 3 above. This function is referred to as the Alpha Max function.

Note that in Figure 3, the inverter is controlling the DC voltage, while the rectifier is

controlling the DC current. This applies for steady state and for a dynamic reduction

in the AC voltage near the inverter station (for example for a remote fault in the

inverter AC network), which would result in a momentary downward shift in the

inverter’s V-I characteristic.

For a fault near the rectifier station, a downward shift would occur in the rectifier’s

V-I characteristic, resulting in a temporary mode shift to rectifier voltage control and

inverter current control. Note however that a stable operating point is reached even

for this condition, since the current margin in the inverter ensures a clearly defined

operating point even if the rectifier’s V-I characteristic shifts downward.

Voltage Dependent Current Order Limit (VDCOL)

The characteristic shown in Figure 3 results in a constant current behavior for the

converters, regardless of the AC voltage level at the rectifier and inverter. This may

be acceptable in applications involving extremely strong AC networks at the two

HVDC stations, but would be problematic for normal to weak (low short circuit

capacity) AC networks. In order to improve the behavior of the HVDC transmission

during disturbances in the AC network or for temporary DC line faults, a function

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called the Voltage Dependent Current Order Limiter (VDCOL) is included in both

the rectifier and the inverter.

The voltage dependent current order limiter will reduce the current order for a

reduction in the direct voltage. The main reasons for the VDCOL function are to:

Avoid power instability during and after disturbances in the AC network.

Define a fast and controlled restart after clearance of AC and DC faults.

Reduce stresses on the thyristors by avoiding continuous commutation

failure.

Figure 4. Voltage Dependent Current Order Limiter (VDCOL)

The static characteristic of the VDCOL is shown in Figure 4. The output from the

VDCOL function is the limited current order, which is passed to the current control

amplifier (CCA). The influence of the VDCOL on the V-I characteristic is shown

below in Figure 5.

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Figure 5. V-I Characteristics with VDCOL

The VDCOL function also includes filtering on the DC voltage input. The time

constants for decreasing DC voltage and increasing DC voltage are different, with a

small time constant chosen for decreasing DC voltage and a larger time constant

chosen for increasing DC voltage, in order to preserve current margin and to control

the recovery rate of the HVDC system.

Note that the VDCOL characteristics of the rectifier and inverter are coordinated in

such a way that current margin is preserved for dynamic reductions in inverter AC

voltage or rectifier AC voltage. This ensures that a stable operating point is reached

during dynamic conditions, in the same manner as described previously.

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Overview of IPP PSLF Stability Models

The preliminary IPP PSLF stability model (Version 3.4) represents the system design

conditions at the conclusion of the Milford Wind integration studies, with features

planned for implementation in the controls for the IPP 2400 MW HVDC Upgrade.

The final IPP PSLF stability model (Version 4.0) is a functional replica of the final

PSS/E program model issued for the IPP HVDC Upgrade, which is based on the

controls at the conclusion of the IPP HVDC Upgrade dynamic performance study

(DPS). The IPP STS Upgrade HVDC model in PSS/E, which the PSLF model

replicates, consists of:

ABB HVDC Classic model for PSS/E, CDCAB3: Standard ABB HVDC

converter control model with project-specific parameters for IPP STS

IPP STS Auxiliary model: Named IPPAUX in PSS/E, this model represents

all high level controls (pole controls and bipole controls)

Both models (3.4 and 4.0) include the following control features:

High Level control:

o Bipole power control

o Pole power control

o Frequency control

o DC power schedule calculator

o Fast DC power schedule calculator

Converter firing control:

o DC current control amplifier

o Voltage dependent current order limiter

o Rectifier alpha minimum limiter

o Alpha max controller

Certain simplifications were made in the Version 3.4 code, while the Version 4.0

code is fully detailed and representative of as-built conditions.

High-level block diagrams are provided for the models as follows:

Appendix A: Model Version 3.4

Appendix B: Model Version 4.0

Descriptions of the functions shown in the block diagrams are provided in the

following sections.

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IPP Bipole Controls The Bipole Control System includes a number of subsystems, of which the

subsystems of main interest for use of the PSLF model are the DC Power Schedule

Calculator (DCPSC) and the Constant Frequency Control (CFC). These systems

are shown on Sheets 2 and 3 in Appendices A and B, and are described below.

The IPP bipole control system and the PSLF models of the system include numerous

functions beyond those described below. The intent of the following information is

only to provide a brief high-level overview.

DC Power Schedule Calculator (DCPSC)

Thermal Generation

The DCPSC determines the power flow on the DC line based on the net thermal

generation at the Intermountain Generating Station and scheduled interchange for

the DC line. The DCPSC considers two main factors:

K_DCPSC: the fraction of thermal power to be scheduled over IPP STS

SIP_DCPSC: The scheduled interchange power; i.e. the thermal power to

be transmitted over the interconnecting AC lines at Intermountain

In the plant, the K and SIP values are either set by the operator on the Bipole control

interface or transmitted to Intermountain remotely. In the PSLF model, the K and

SIP values are determined from the Intermountain generation and flows on the AC

lines and IPP STS in the solved powerflow case.

The scheduled power on the IPP STS is computed at both the 345 kV AC bus and at

the DC side of the converters, with an estimation of the converter losses taken into

account. The IPP STS power at the 345 kV AC bus at Intermountain is computed

from the expression:

P345 = NET_GEN*K_DCPSC – SIP_DCPSC

Where

NET_GEN is the Intermountain net generation (at the 345 kV AC bus)

K_DCPSC, SIP_DCPSC as described earlier

The IPP STS power at the DC side of the converters is then computed from the

quadratic expression:

BPO_DCPSC=a *P3452+b*P345+c

Where

a, b, c are coefficients used to approximate the converter losses.

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Wind Generation

Scheduling of the Milford wind generation uses a similar approach based on separate

K and SIP factors:

W_KDCPSC: the fraction of wind power to be scheduled over IPP STS

W_SIP: The scheduled interchange power; i.e. the wind power to be

transmitted over the interconnecting AC lines at Intermountain

The wind power scheduled over the IPP STS is then added to the scheduled thermal

generation.

Constant Frequency Control

The integrating part of the frequency control, referred to as the Constant Frequency

Control, is located in the Bipole Control. The Constant Frequency Control is not in

service during normal conditions with the Mona 345 kV and Gonder 230 kV lines

connected (non-islanded conditions). The Constant Frequency Control is of interest

only for studies of islanded conditions with the Mona and Gonder lines open.

The Frequency Control with Deadband is, however, in service during normal (non-

islanded) conditions. This function is included in the PSLF model of the Pole

Controls described later.

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IPP Pole Controls In the sections below, the referenced control functions are shown on Sheets 2 and 4

of Appendices A and B.

The IPP pole control system and the PSLF models of the system include numerous

functions beyond those described below. The intent of the following information is

only to provide a brief high-level overview.

Power and Current Order Stepping Modules

In the actual controls, the power and current order stepping modules perform the

functions needed for operator-initiated ramping of the power order (when power

control is used) or current order (when current control is used). These functions,

SLFBPO, and SLFPCO, are not fully implemented in the PSLF models since the

bipole power order is established in the powerflow case. In PSLF, the solved

powerflow conditions are used to initialize the HVDC controls.

The current order stepping function, SLFPCO, performs the functions for operator-

initiated ramping of the current order when a pole is operated in current control

mode. This operating condition is not common and therefore these functions are not

included in Version 3.4 of the model. The functions are included in Version 4.0.

Fast DC Power Schedule Calculator (FDCPSC)

The DCPSC in the Bipole Controls (Section 4.1) is designed to track normal changes

in scheduled generator power at Intermountain. For sudden contingency events such

as generator tripping, additional functions in the Pole Controls are used to initiate

fast changes in the HVDC power order. These functions are referred to as the Fast

DC Power Schedule Calculator (FDCPSC).

For the two Intermountain 950 MW (gross capacity at machine terminals) steam

turbine generators, the FDCPSC initiates a fast change in the power flow on the DC

line when a generator or steam turbine trip occurs. If a generator trips, the HVDC

power order is changed in a step equal to the power output of the generator just

before it was tripped. For a turbine trip, the power order on the DC line rapidly

tracks (fast tracking) the remaining generated power, thus taking into account the

rapid reduction in generated power from the tripped turbine.

The FDCPSC is modeled in detail in the PSLF models, including logic to detect an

electrical trip of a generator. The functions to perform fast power tracking for turbine

trip are included in the PSLF models. The PSLF program itself, however, does not

include functionality to perform turbine tripping simulations.

Power Order Calculation

The bipole power order from the Fast DC Power Schedule Calculator,

BPO_DCPSC_L, is limited in this module and then passed to the Current Order

Calculation (Section 5.4).

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Current Order Calculation

The normal operating mode of IPP HVDC is synchronous power control in both

poles. For this condition, the DC current order is calculated by dividing the bipole

power order by the sum of the two pole voltages.

The current order calculation includes the capability to respond to loss of a pole by

stepping the DC current order on the remaining pole up to a value that compensates

for the lost pole. This is implemented in the plant controls and in the PSLF model

by logic that detects sudden reduction in the total DC voltage across the bipole, and

responds accordingly by increasing the current order in the remaining pole.

Following addition of contributions from the frequency controls (Sections 4.2 and

5.5) and consideration of valve current limits, the result is signal IO_IPPAUX, which

is passed to the converter controls in both poles.

Frequency Control with Deadband

As described in Section 4.2, the Constant Frequency Control is not in service during

conditions with the Utah 345 kV lines in operation (normal, non-islanded

conditions). The Frequency Control with Deadband is, however, in service during

normal conditions. This function is included in the PSLF model of the Pole Control.

The function calculates a contribution to the pole DC current order that is added to

the current order generated by the DCPSC and FDCPSC functions (Section 5.4).

Current Order Synchronization

The most usual mode of operation for the Pole Power Control, and the mode

represented in the PSLF model, is Synchronous Bipole Power Control (SBPC). In

this mode, the bipole power order is divided by the bipole voltage and a current order

is calculated. Telecommunications are used to ensure that both HVDC stations,

Intermountain and Adelanto, are working from the same current order.

Variations in the bipole power order, for example as ordered from the DCPSC

system, are performed at Intermountain. For the purposes of SBPC, Intermountain

is therefore normally the “lead” station. Synchronous (SBPC) control means that the

lead station is automatically followed by the trail station as far as current orders are

concerned, and this is coordinated over the telecommunications system. In the event

of telecommunications system failures, a backup system called Backup Synchronous

Control (BSC) is used (not included in the PSLF model).

In SBPC mode, the current order calculated at the lead station is transmitted over

telecommunications to the trail station, which then echoes the current order back to

the lead station. This coordination is necessary to preserve the current margin.

It is not possible to reduce the current order in the rectifier without reducing first in

the inverter; otherwise, the current margin would be lost. Therefore, for conditions

with decreasing current order, the new current order is not executed in the lead

station (rectifier) until after confirmation of the new current order is echoed back

from the trail station (inverter).

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However, for conditions with increasing current order, the new current order can be

executed at the lead station (Intermountain) without waiting for the trail station’s

echo response. This is possible because current order in the rectifier can be increased

without increasing the current order at the inverter (current margin is increased in

this situation).

The above coordination of the lead and trail stations, and associated

telecommunications delay, is represented in the PSLF models.

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IPP Converter Controls In the sections below, the referenced control functions are shown on Sheets 5 and 6

of Appendices A and B.

The IPP converter control system and the PSLF models of the system include

numerous functions beyond those described below. The intent of the following

information is only to provide a brief high-level overview.

Automatic Power Control, APC

ABB’s standard Common Component model for HVDC converters includes a

representation of constant power control in the converter control system. In the case

of IPP, the constant power control function is located in the bipole and pole controls

as described earlier. Therefore, in Version 3.4 of the IPP PSLF model, the APC

function is omitted from the converter controls. In Version 4.0, the code for the APC

function is implemented, but disabled by parameter selection.

Voltage and Angle Reference Calculation, VARC

The objective of the Voltage and Angle Reference Calculation function (VARC) is

to calculate target (reference) values for DC voltage, extinction angle , and firing

angle . This function is implemented in Version 4.0 of the code, but omitted in

Version 3.4. This is because the main focus of the preliminary model (Version 3.4)

was on normal conditions with nominal reference values for Ud, , and .

Udi0 Calculation

The converter firing control system includes consideration of the ideal no-load DC

voltage, Udi0, in its calculations. Udi0 can be thought of as the DC voltage that

would be produced by the valves for conditions with zero DC current and zero

control angle, and thus the value of Udi0 depends on the AC voltage on the valve

side of the converter transformer. Udi0 can therefore be calculated from the bus

voltage on the network side of the converter transformer, the transformer turns ratio,

and the tap changer position.

Converter Firing Controls, CFC

VDCOL

After consideration of telecommunications delays as described in Section 5.6, the

current order from the Pole Power Control is limited by VDCOL action during

dynamic events that result in reduction of the DC voltage, as described earlier in

Section 2.4. The output of the VDCOL is a limited current order that is supplied to

the current control amplifier (CCA).

Rectifier Alpha Minimum Limiter (RAML)

When a nearby fault occurs in the rectifier AC network, the rectifier enters UMIN

firing with the firing angle at its minimum value. This results in current control

being transferred from the rectifier to the inverter in accordance with the V-I

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characteristics of the converters (Figure 5). At fault clearing, full AC voltage is

restored to the rectifier, and unless special control actions are taken, a surge in the

DC current will occur due to the low in the rectifier. This surge in the direct current

could then result in commutation failure in the inverter.

This is avoided by a special control function called the Rectifier Alpha Minimum

Limiter (RAML). RAML increases the minimum alpha limit in the rectifier

immediately after an AC system fault is cleared. In this way, RAML forces the

inverter into current control during the post-fault recovery, improving the recovery

characteristics.

Inverter AlphaMax

As shown in Figure 5, the inverter’s Ud-Id characteristic is modified at the operating

point in order to give a positive slope as viewed from the rectifier. This helps to

ensure that there is a well-defined operating point in the event of a small reduction

in the rectifier Ud, and this also enhances the stability of the rectifier current control

amplifier. This positive slope in the inverter characteristic is created in the controls

by an AlphaMax regulator.

Voltage Regulator (VCAReg)

In Version 4.0 of the IPP PSLF model, a DC voltage controller is implemented. The

main function of this controller is for reduced voltage operation. The VCAReg

controller acts on the minimum and maximum limits of the current controller. In

inverter operation, VCAReg decreases the maximum alpha limit of the CCA.

The VCAReg function is not implemented in Version 3.4 of the IPP PSLF model.

Current Control Limits, CCALim

Several limits are applied on the current control amplifier (CCA), including the

RAML, AlphaMax, and VCAReg functions described above, and other limits not

described here. The various limits are collected and prioritized in the CCALim

function. The result is a final set of maximum and minimum limits passed to the

current control amplifier.

In Version 4.0 of the PSLF model, the CCALim function is fully implemented.

Simplifications are made in Version 3.4 of the model.

Current Control Amplifier

The Current Control Amplifier (CCA) compares the ordered DC current from the

VDCOL to the actual DC current and calculates an ordered firing angle ord. In the

rectifier, the measured DC current is subtracted from the ordered DC current to form

a difference signal that is fed to the CCA. In the inverter, the same comparison is

made, but the current margin is subtracted from the difference signal. This has the

effect of forcing the inverter CCA to its limit (as defined by maximum or minimum

).

The CCA includes a proportional part and an integral part as described earlier in

Section 2.2. The transfer function of the CCA is designed to obtain stable and fast

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response to changes in the DC current order, as well as fast response to changes in

other parameters such as the AC bus voltages. The output signal, ordered firing angle

ord, is limited by the minimum and maximum values from the CCALim function.

CCA Gain Linearization

There is a nonlinear (cosine) relationship between changes in firing angle and

changes in the direct voltage across the converter. This means that the overall gain

of the current control system has a significant dependence on the firing angle. The

CCA is therefore designed to take the nonlinear characteristic into account by

adjusting the proportional gain as a function of the firing angle . This adjustment

is implemented in the PSLF models.

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Appendix A: PSLF Code Version 3.4

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Appendix B: PSLF Code Version 4.0

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HVDC


1JNL635836 , 26 of 30

Title



HVDC


1JNL635836 , 27 of 30

Title



HVDC


1JNL635836 , 28 of 30

Title



HVDC


1JNL635836 , 29 of 30

Title



HVDC


1JNL635836 , 30 of 30

Title



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IPP PSLF Stability Program Model - Block Diagrams · High-level block diagrams are provided as an aid in general understanding of the models. Note that the intent of this document