IR Drop Reduction via via Addition

8/3/2019 IR Drop Reduction via via Addition

1/4

Chip IR Drop Reduction through Automated ViaChecking and Addition

Arya RaychaudhuriFastrack DesignSan Jose, CA

Complex physical designs (layouts) in 65 nm and belowprocess nodes often use ten (10) or more layers ofmetallization. So, the length of supply (power/ground)nets as well as that of clock and signal nets is typicallylong, and the nets involve multiple layers of Vias. TheseVias tend to dominate the impedance due to these nets.It is, therefore, often the case that insufficient Viaplacements on the junctions between Metal(N) and

Metal(N+1) turns out to be the root cause of the IR dropfailures, and net delays giving rise to setup and hold timeviolations. The other detrimental effect of Via-deficient

junctions is increased heat dissipation and currentcrowding leading to electro-migration. Wide metalswarping resulting in unreliable Via connections requireredundant Via placements. Some Via-deficient junctionsmay barely meet redundant Via requirements, butadditional Vias often make the junctions more robust.

This paper discusses a simple Perl-Calibre approachto check for and add Vias to M(N)-M(N+1) junctions thathave insufficient Vias or no Vias, but could hold more

Vias without violating the topological design rules checks(DRCs). The Vias are checked for and added to

junctions on user-specified nets. Although, typicallysupply nets (VDD,VSS) are handled by the code, thereare actually no restrictions on the net names as long asthey are top-level net names that can be traceddownwards along metal and via lines, or even otherconnectivity layers.

The CodeIn principle, the code is organized as follows. A simplePerl routine that reads in the list of top level net namescomputes all the M(N)-M(N+1) junctions that the user-

specified nets traverse. The Perl routine shown in Fig.1reads in the list of net names supplied in a file calledvia_check_add_net_names. In our test example, we

just used:

VDD

VSSas the net names specified in this file. But, there is norestriction on the net names, as long as the physicaldesign (layout) is LVS correct, and the top-level textingis available for the net names.

Figure 1: Calibre SVRF Include File Generating Perl

#! /usr/bin/perl -w

$infile = "via_check_add_net_names";

open(F, $infile);

$i = 0;

while() {

$pg_name = $_;

chomp $pg_name;

$i = $i + 1;

$m8_pg_name ="M8_".$pg_name." = "."metal8 NET

". $pg_name;$m7_pg_name ="M7_".$pg_name." = "."metal7 NET

". $pg_name;

:::::::::Similar Lines of Code

deleted:::::::::::::::::::::::::::::::::::::::::::::

$m1_pg_name ="M1_".$pg_name." = "."metal1 NET

". $pg_name;

$m8_m7_pg_name_int = "M8_M7_".$pg_name."_INT =

"."M8_".$pg_name. " AND ". "M7_".$pg_name;




deleted:::::::::::::::::::::::::::::::::::::::::::::



if ($i == 1) {

$m8_m7_all_int = "M8_M7_".$pg_name."_INT";

$m7_m6_all_int = "M7_M6_".$pg_name."_INT";:::::::::Similar Lines of Code

deleted:::::::::::::::::::::::::::::::::::::::::::::

$m2_m1_all_int = "M2_M1_".$pg_name."_INT";

}

if ($i == 2) {

$m8_m7_all_int = $m8_m7_all_int. " OR

"."M8_M7_".$pg_name."_INT)";


"."M7_M6_".$pg_name."_INT)";


deleted:::::::::::::::::::::::::::::::::::::::::::::


"."M2_M1_".$pg_name."_INT)";

}

if ($i > 2) {

$m8_m7_all_int = "(".$m8_m7_all_int. " OR

"."M8_M7_".$pg_name."_INT)";$m7_m6_all_int = "(".$m7_m6_all_int. " OR

"."M7_M6_".$pg_name."_INT)";


deleted:::::::::::::::::::::::::::::::::::::::::::::

$m2_m1_all_int = "(".$m2_m1_all_int. " OR

"."M2_M1_".$pg_name."_INT)";

}

print "$m8_pg_name\n";



deleted:::::::::::::::::::::::::::::::::::::::::::::

1


2/4


print "$m8_m7_pg_name_int\n";



deleted:::::::::::::::::::::::::::::::::::::::::::::


}

$m8_m7_all_int =

"M8_M7_ALL_INT_ = ". $m8_m7_all_int;

$m7_m6_all_int =


:::::::::Similar Lines of

Codedeleted:::::::::::::::::::::::::::::::::::::::::::::

$m2_m1_all_int =


chop $m8_m7_all_int;


:::::::::Similar Lines of

Code

deleted:::::::::::::::::::::::::::::::::::::::::::::


print "$m8_m7_all_int\n";



deleted:::::::::::::::::::::::::::::::::::::::::::::


As shown in Fig. 1, the Perl routine computes the metal

junctions from M8 through M1, and combines them intosingle SVRF junction variables for all user-specifiednets. For our example of the two nets VDD, VSS, theSVRF include file looks like the one shown in Fig. 2.

Figure 2: Calibre SVRF Include file that computes the

candidate metal junctions for Via Checking and Addition

M8_VDD = metal8 NET VDD



deleted:::::::::::::::::::::::::::::::::::::::::::::


M8_M7_VDD_INT = M8_VDD AND M7_VDD


:::::::::Similar Lines of Codedeleted:::::::::::::::::::::::::::::::::::::::::::::


M8_VSS = metal8 NET VSS



deleted:::::::::::::::::::::::::::::::::::::::::::::


M8_M7_VSS_INT = M8_VSS AND M7_VSS



deleted:::::::::::::::::::::::::::::::::::::::::::::


M8_M7_ALL_INT_ = M8_M7_VDD_INT OR M8_M7_VSS_INT

M7_M6_ALL_INT_ = M7_M6_VDD_INT OR M7_M6_VSS_INT


deleted:::::::::::::::::::::::::::::::::::::::::::::

M2_M1_ALL_INT_ = M2_M1_VDD_INT OR M2_M1_VSS_INT M8_M7_ALL_INT_CAND_VIA_DEF = M8_M7_ALL_INT_CANDENCLOSE MORE_NEW_VIA7_ALL

The SVRF include file shown in Fig. 2 clearly indicatesthat the net-based intersections are computed net-by-net, and M(N)-M(N+1) pair-by-pair, and then ORedtogether for each pair of consecutive metallization levels.This via_check_add_include_file forms a part of themain Calibre deck that checks for and adds Vias in Via-deficient junctions.

In general, Via deficiency can be of two types, Viascompletely missing from a junction, or a junction havinginsufficient Vias. In the main Calibre deck for Viaschecking and adding (via_check_add.deck), we definea Via deficiency factor called VIA_FACTOR which is setto 2 for our test case. It means that, only those Via-deficient junctions will be flagged, that could hold morethan twice (2-times) the number of existing Vias. Weshow an excerpt from the via_check_add.deck todepict the central algorithm involved, in Fig. 3.

Figure 3: Excerpt from the Via checker-adder Calibre

deck showing the checking for V7-deficiency and

additional V7 creation in the variable VIA7_ALL_ADD

VARIABLE VIA_FACTOR 2

INCLUDE "via_check_add_include_file"

CONNECT M8_M7_ALL_INT_

VIA7_COPY = COPY VIA7

CONNECT VIA7_COPY

M8_M7_ALL_CORNERS = SIZE (EXT metal8 metal7

2 SPACE < VIA7_S_2_S

NEW_VIA7_ALL_3_NEIGHBORS_ERR = EXT

NEW_VIA7_ALL_3_NEIGHBORS NEW_VIA7_ALL < VIA7_S_2

ABUT < 90 SINGULAR REGION

M8_M7_ALL_INT_SHRUNK_ERR =

M8_M7_ALL_INT_SHRUNK INTERACT

NEW_VIA7_ALL_3_NEIGHBORS_ERR

NEW_VIA7_ALL_S1 = NEW_VIA7_ALL NOT INSIDE

M8_M7_ALL_INT_SHRUNK_ERRNEW_VIA7_ALL_S2 = RECTANGLES VIA7_W_1 VIA7_W_1

VIA7_S_2 INSIDE OF LAYER M8_M7_ALL_INT_SHRUNK_ERR

NEW_VIA7_ALL_ALL = NEW_VIA7_ALL_S1 OR

NEW_VIA7_ALL_S2

CONNECT NEW_VIA7_ALL_ALL M8_M7_ALL_INT_CAND

MORE_NEW_VIA7_ALL = NET AREA RATIO

NEW_VIA7_ALL_ALL VIA7_COPY > VIA_FACTOR

MISSING_V7_ALL_NET {@This junction has no V7

(M8_M7_ALL_INT_CAND_0

ENCLOSE NEW_VIA7_ALL_ALL) NOT NEW_VIA7_ALL_ALL

}

V7_OPPORTUNITY_ON_ALL_NET {@More V7s are

possible on this junction

M8_M7_ALL_INT_CAND_VIA_DEF NOT MORE_NEW_VIA7_ALL

}

VIA7_ALL_ADD_ = (NEW_VIA7_ALL_ALL INSIDE

M8_M7_ALL_INT_CAND_0) OR (MORE_NEW_VIA7_ALL NOT

(SIZE VIA7_COPY BY VIA7_S_2))

VIA7_ALL_ADD_HIER = M8 AND (RECTANGLE

VIA7_ALL_ADD_ ==VIA7_W_1 BY ==VIA7_W_1)

VIA7_ALL_ADD = FLATTEN VIA7_ALL_ADD_HIER

2


3/4

The Via checker adder routine uses the VARIABLEnames like VIA7_W_1, VIA7_S_1, etc. and their valuesfrom a standard TSMC 65 nm DRC deck. As is seen inFig. 3, the SVRF include file,via_check_add_include_file is an INCLUDE file in thismain routine. Although it is not always necessary in thisroutine, we prune the set of all intersections read in fromthe Include file, to treat only those junctions wheremetals completely cross one another and form a +sign. This is normally the situation for power/groundgrids, like our test layout shown in Fig. 4. In the Viachecker-adder algorithm, we capture the DRC flags forVia deficiency in the rulechecks such asMISSING_V7_ALL_NET, andV7_OPPORTUNITY_ON_ALL_NET.

The first category flags the junctions that are completelylacking in Vias, and the second one the junctions thathave insufficient Vias. Both flags are present in the error

junctions with the Calibre computed possible Viassubtracted from them. This way, we economize on thenumber of flags generated, as well as presentcomprehensive Via deficiency pictures with the single

flags. As is evident from the code, DRC correctness ismaintained for the newly generated Vias. The Viadeficiency is computed by taking the NET AREA RATIObetween the generated Vias and the pre-existing Vias,and comparing it with the VIA_FACTOR, as mentionedearlier. The DRC flags are reported in an ASCII db filethat is viewable through the RVE GUI. TheVIA7_ALL_ADD variable in the code captures all theadditional VIA7s that are output in a GDS file by theCalibre deck.

The additional Vias from the GDS file can be added toexisting layout as an overlay cell, since they maintain

design rules compliant spacing to the existing Vias.

The Results

For this test run, we used a Calibre-generated VDD/VSSgrid consisting of M4 through M8, and connected by V4through V7. This grid is shown in Fig.4. The verticalgrids, 2 um wide and 100 um long are in M7 (purple) andM5 (golden), while the horizontal grids are in M8 (lightblue), M6 (white), and M4 (pink). As is seen in Fig. 4, thegrids are texted VSS, VDD at the top level with M8 texterlayer. The grids are connected by DRC correct Vias (V7,V6, at 0.36 um square, and V5, V4 at 0.10 um square,

as per TSMC 65 nm design rules). The grid iscompletely checked for connectivity issues (for example,shorting of VDD, VSS) before application of our Viachecker adder script. We intentionally deleted Vias fromsome junctions, or under-populated them to see if theroutine flags the Via deficient junctions and adds theVias properly, see Figs. 5 & 6.

Figure 4: Test VSS/VDD grid in M4 through M8

connected by V4 through V7

Figure 5: DRC Flags showing Via-deficient junctions, as

well as possible DRC-correct Via positions

In Fig. 5, we clearly see that our routine clearly flags thejunctions where the Vias are either completely missing

or insufficient. On the lower left, you see a M7-M8junction being flagged, that was completely missing theV7s. On the upper right, you see a M5-M6 junction beingflagged, that had just one Via (red) near the center,clearly insufficient compared to the size of the junction.In both cases, the flags are showing how many DRCcorrect Vias were possible and where! This feedback isoften useful for the physical layout designer, who canthen go ahead and add those Vias at those locations.

3


4/4

Figure 6: Additional Vias added through the Via checker

adder procedure

In Fig, 6, we show the Calibre generated *additional*Vias at the Via-deficient junctions. In this case, theadditional V4 (pink) and V5 (golden) have been addedon junctions with just one Via near the center of theintersections. So, the additional generated Vias subtractthat Via and the design rules compliant spacings aroundit, giving rise to the hole near the center of the Viapatterns. In the case of the additional V7s near the rightside of the picture, there was only one Via near theleft/bottom corner of the M7-M8 junction. So, only 3 V7shave been added. While in the case of the V7s added onthe left side of the picture, the junction was completely

lacking in V7s, so all the 4 V7s have been added. Insome of the real layouts on which we tried the routine,we could add tens of thousands of Vias through thisprocedure; thus, significantly reducing the overall IRdrops and net delays.

ConclusionIn this paper, we discuss a Perl-Calibre based Viaoptimization procedure that can be applied to anyphysical designs with multiple levels of metallizations.The procedure searches for Via deficient junctions andflags them in a simple but comprehensive DRC resultsdatabase formatthat can help in manual correction of

the junctions. The routine also features an automatic Viageneration feature that involves outputting a GDS filecontaining all the additional Vias that could be added tothe junctions. The user can then simply add theadditional Vias from the GDS as an overlay cell to theexisting physical design, which will save the time andresources needed to manually correct the junctions.

4

Documents

IR Drop Reduction via via Addition