IRI Frankfurt · 2012. 4. 16. · History Norbert Abel & Christian Stüllein, IRI Frankfurt Page 2 ISE 1 ISE 2 ISE 3 ISE 4 ISE 5 ISE 6 ISE 7 ISE 8 ISE 9 ISE 10 ISE 11 ISE 12 ISE 13

Partitions and Partial Reconfiguration

IRI FrankfurtNorbert Abel, Christian Stüllein, Udo Kebschull

History

Page 2Norbert Abel & Christian Stüllein, IRI Frankfurt

ISE 1 ISE 2 ISE 3 ISE 4 ISE 5

ISE 6 ISE 7 ISE 8 ISE 9

ISE 10 ISE 11

ISE 12 ISE 13

No PR at all

PREApatch

New approach based on Partitions& official support

Motivation

Page 3

Black, Donovan, Bunton, Keist„SystemC: From the Ground Up“

Norbert Abel & Christian Stüllein, IRI Frankfurt

Motivation

Page 4

● High Level Synthesis

● Team Design

● Hierarchical Design & Re-Use


Partitions

Page 5

Partitions are Xilinx's approach to Team Design and Hierarchical DesignTool: PlanAhead


RTL Project


RTL Project


RTL Project

Page 8

clkbufds: ibufgds port map (O=>clk, I=>clk_p, IB=>clk_n); team1_inst: team1 port map (clk=>clk, led=>led1);

team2_inst: team2 port map (clk=>clk, led=>led2);


RTL Project

Page 9

process (clk) begin if rising_edge(clk) then c <= c + 1; end if; end process;

led(3 downto 0) <= c (31 downto 28);


RTL Project

Page 10

process (clk) begin if rising_edge(clk) then c(31 downto 0) <= c(30 downto 0) & c(31); end if; end process;

led(3 downto 0) <= c (31 downto 28);


RTL Project


RTL Project


RTL Project


RTL Project


RTL Project


RTL Project


RTL Project


RTL Project


RTL Project

Page 19

3 Levels of Design Preservation:● Synthesis● Placement● Routing


NGC Project


NGC Project

Page 21

Differences to the RTL Project:

Sources: NGC files (netlists)==> Requires external synthesis

top.ngc

team1.ngc team2.ngc

general Synthesis hints:- deactivate automatically generated I/O buffers- instantiate all I/O buffers directly

Instantiates team1 andteam2 as black box


NGC Project

Page 22

Differences to the RTL Project:

3 Levels of Design Preservation:● Synthesis (same as Implement)● Placement● Routing


Partial Reconfiguration

Page 23

Requires a specialPR-License

No patches neededany longer!



Page 24

PR designs are NGC designs

Sources: NGC files (netlists)==> Requires external synthesis

top.ngc

recoModule1.ngc recoModule2.ngc

general Synthesis hints:- deactivate automatically generated I/O buffers- instantiate all I/O buffers directly

Instantiates subcomponentsas black boxes

staticModule.ngc

no BUFGs, PLLs,DCMs, etc. allowed
































!!



FPGA

staticModule

recoModule1

recoModule2

proxy logic (LUT1)





Conclusion


FPGA

staticModule

recoModule1

recoModule2

proxy logic (LUT1)

Problems:● Timing● change of static Module causes rebuild of all Modules

● a Areas using m Modules => m configurations => m full implementation runs => m full bitfiles => a • m partial bitfiles● no support of Spartan-6

Our aims:● clear Timing● strict module separation● movable bitfiles

Questions?


Documents

IRI Frankfurt · 2012. 4. 16. · History Norbert Abel & Christian Stüllein, IRI Frankfurt Page 2 ISE 1 ISE 2 ISE 3 ISE 4 ISE 5 ISE 6 ISE 7 ISE 8 ISE 9 ISE 10 ISE 11 ISE 12 ISE 13