ITC Program 2008

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At-a-Glance Tutorials WorkshopsExhibitsAncillaryEventsPanels Registration Venue

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ITC Test Week 2008

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On behalf of the over 100 volunteers, International Test Conference(ITC) is proud to present our 39th technical program featuring a full-week of test-focused technical activities. The volunteer organizers worktirelessly to bring you a comprehensive program that includes papers,panels, lectures, advanced industrial practices, exhibits, tutorials andworkshops on IC test, board test and system test. The 2008 technical

program will also include embedded tutorials and a poster session.Some of the week's highlights include:

Tutorials: Test Week opens with 17 tutorials covering such diversetopics as high-speed interface testing, design-for-manufacturing, silicondebug and diagnosis, statistical screening, delay test, scan compression,failure mechanisms and high-quality test methods for nanometertechnologies, analog mixed-signal and RF test, memory test, IEEE Std.1500, system-in-package test, and wafer-probe. Leading industry expertsprovide a wide breadth of knowledge to assist the test engineer inkeeping up with new and changing technologies.

Keynote Address: The conference opens with the plenary session.Mike Lydon, Cisco, will deliver the keynote address Managing Test inthe End-to-End, Mega Supply Chain.

Exhibits: After the plenary session, be sure to visit our dynamic exhibitfloor where major industry suppliers will be displaying their latestproducts and technologies.

Invited Talks: There will be three invited speakers making theirpresentations after lunch on Tuesday, Wednesday and Thursday

Tuesday: Jan Rabaey, University of California, Berkeley, deliversthe invited address Computing at the Crossroads (and What Does it

Mean to Verification and Test?)

Wednesday: Bob Pease, National Semiconductor, has an interactiveconversation onHaving FUN with Analog Test

Thursday: Jeff Rearick, AMD, discusses the issue This is a Test:

How to Tell if DFT and Test Are Adding Value to Your Company

Technical Program: Our exciting technical program begins after tinvited address on Tuesday, and extends for three days and 35 sessioFind out the latest advances in such hot topics as design-fomanufacturability, power-aware test, recent advances in delay test, logdiagnosis, silicon debug, and high-quality test methods. Learn moabout whats going on in traditional topics such as analog, mixed-sign

RF, microprocessor test and DFTas well as defects, memory, ATand board test.

Lecture Series and Advanced Industrial Practices: We continuesupplement the program with the lecture series and advanced industrpractices sessions. This year we have sessions on high-speed interfatesting, board testing, automotive test, practical test engineering, andspecial joint session with the Autotestcon conference on system test.

Embedded Tutorials: New for 2008, we will be having on Tuesdtwo tutorials as part of the regular technical program. One will be mixed-signal production test, and the other on defect-based test.

Posters: Another new feature for 2008 is a poster session during tpost-panel party on Wednesday. The poster session provides opportunity for presenting late-breaking results and getting feedback

innovative methods. It allows for greater interaction between tattendee and presenter.

Workshops: Closing out Test Week are three workshops on design freliability and variability, defect- and data-driven testing, and ATvision 2020.

As you can see, Test Week 2008 is packed with numerous opportunitifor education and the exploration of exciting new technologies. Wencourage you not to miss the industry's leading test conference. Ycan find more at our Web site http://itctestweek.org. We look forwato seeing you in Santa Clara this October.

Douglas Young Nur ToubaGeneral Chair Program Chair

Sponsors

Test Technology Technical

Council

Philadelphia Section

Corporate Supporters

Diamond

Platinum

Gold

Silver

Intro

Highlights

Welcome Message


Plenary &Addresses

TechnicalPapers

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ITC Test Week 2008 1

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Become an ITCcorporate supporterTake advantage of numerousadvertising opportunities.

http://www.itctestweek.org

SUNDAY

MONDAY

TUESDAY

WEDNESDAY

THURSDAY

FRIDAY

Seventeen New or Updated Full-Day TutorialsA great way to prepare for the ITC Technical program

Six Panels

Two Embedded Tutorials

Plenary Session and Keynote

100 Technical Papers

Three Invited AddressesHot topics of current interest

Lecture SeriesSpecial sessions containing introductory and broadening material

Advanced Industrial PracticesReal-world solutions to tough problems

Hot Topic Background SessionsAn early-morning prep for the sessions to follow

Poster SessionWorld-Class ExhibitsFree exhibits-only admission on Wednesday afternoon andAll day on Thursday

Corporate PresentationsThe latest technical innovations from or exhibitors andcorporate supporters

WorkshopsFinish your Test Week experience with a choice of three

Fringe Technical Meetings

Networking and Social Events


Plenary &Addresses

TechnicalPapersIntro

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Welcome Message

Test Week Highlights

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SUNDAY, OCTOBER 26 FULL-DAY TUTORIALS

8:30 a.m.

4:30 p.m.Tutorial 1Topics andAdvances inSilicon Debugand Diagnosis

Tutorial 2DelayTesting: APracticalApproach

Tutorial 3IEEE 1500 Building aCompliantWrapper

Tutorial 4AdvancedMemoryTesting

Tutorial 5MicroelectronicWafer TestTechnology

Tutorial 6Design forManufacturability,Yield andReliability

Tutorial 7Design-for-Testability forRF Circuits andSystems

Tutorial 8Scan CompressionTechniquesTheory

and Practice

MONDAY, OCTOBER 27 FULL-DAY TUTORIALS

8:30 a.m.4:30 p.m.

Tutorial 9DFTFundamentalsfor DigitalTest

Tutorial 10DFx: TheConvergenceof Test,Manufacturingand Yield

Tutorial 11Analog,Mixed-Signal andRF Testing

Tutorial 12Digital BecomesAnalog: Interfacesin High-Speed Test

Tutorial 13DelayTesting:Theory andPractice

Tutorial 14Memory Test:Practical andImplementationViewpoint

Tutorial 15Scan-based YieldImprovement,Debug andDiagnosis

Tutorial 16StatisticalScreeningMethods forQuality &Reliability

Tutorial 17TestStrategies foSystem-in-Package

MONDAY, OCTOBER 27 SPECIAL PANEL

5:00 p.m.6:30 p.m. Panel 1 Power-aware DFTDo We Really Need It?

TUESDAY, OCTOBER 28 TECHNICAL SESSIONS

8:00 a.m.9:15 a.m.

Embedded Tutorial E1Outliers and the Testing Tools that Reveal Them: A Fair andBalanced Introduction to Statistics in Test

Embedded Tutorial E2A Brief Overview of Mixed-Signal Production Test for theBeginner

9:30 a.m.10:30 a.m. Plenary Session / Keynote Address:Managing Test in the End-to-End, Mega Supply Chain

10:30 a.m.5:45 p.m. Exhibits

11:00 a.m.4:30 p.m. Corporate Presentations

12:00 p.m.1:15 p.m. Lunch - Complimentary Lunch in Exhibit Hall at Noon

1:15 p.m.1:45 p.m. Invited Address: Computing at the Crossroads (And What Does it Mean to Verification and Test?)

2:00 p.m.3:30 p.m. Session 1Dealing with Outliersand Variation in Today'sICs

Session 2Microprocessor Test

Session 3Embedded MemoryDiagnosis andCharacterization

Session 4High-Speed I/O Testingin the Real World

Advanced IndustrialPractices 1Automotive Test Practices

4:15 p.m.5:45 p.m. Session 5Defect Avoidance andCost Modeling

Session 6Delay Testing andChip Performance

Session 7ATPG and SAT Session 8High-PerformanceInterfacing

Lecture 1Basics of Test EngineeringSeries

TUESDAY, OCTOBER 28 WELCOME RECEPTION

6:15 p.m.8:00 p.m. Hyatt Regency Hotel - Santa Clara Ballroom


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WEDNESDAY, OCTOBER 29 TECHNICAL SESSIONS

8:00 a.m.8:30 a.m. Hot-Topic Background Session Overview of Power and Its Impact on Test

8:30 a.m.10:00 a.m. Session 9Power-aware DFT Methods

Session 10Opens + Shorts

Session 11Advances in Board

Interconnect TestTechnology

Session 12System-level

MicroprocessorOnline Test

Lecture 2Jitter and Signal Integrity

for Gbps I/O

8:30 a.m.4:30 p.m. Corporate Presentations

9:30 a.m.5:45 p.m. Exhibits Free entry 1:00 p.m. 5:45 p.m.

10:30a.m.12:00 p.m. Session 13Power Impact on Compressionand At-Speed Scan

Session 14Diagnostics

Session 15Access and Opens atBoard Test

Session 16Innovative Solutionsto Complex SOCs

Lecture 3Elevator Talks

12:00 .m.1:00 .m. Lunch - Complimentary Lunch in Exhibit Hall at Noon.

1:00 p.m.1:45 p.m. Invited Address:Having FUN with Analog Test

2:00 p.m.3:30 p.m. Session 17Advances in Defect

Diagnosis and SiliconDebug

Session 18Industry Experience with

Complex Designs

Session 19Poster Previews

Session 20RF Testing

Lecture 4Practical Issues in Board

Test

4:15 p.m.5:45 p.m. Panel 2Analog Test Technology:Stable or Open Loop

Panel 3Will Test CompressionRun out of Gas?

Panel 4 Panel 5Yield LearningWho Gains,Who Picks Up the Tab?

Panel 6The University DFT ToolShowdown

WEDNESDAY, OCTOBER 29 POSTER SESSION/OCTOBERFEST PARTY

5:45 p.m.7:15 p.m. Posters Party Santa Clara Convention Center Great America Ball Room

THURSDAY, OCTOBER 30 TECHNICAL SESSIONS

8:00 a.m.8:30 a.m. Hot-Topic Background Session Overview of Test Generation and Analysis for Reducing Test Escapes

8:30 a.m.10:00 a.m. Session 21Test Quality -Defects, DPPM andPatterns, Oh My!

Session 22Software to theRescue!

Session 23"Outside the Box"DFT Solutions

Session 24Systems Effects ofErrors and ProtectionMethods

Session 25EmbeddedMemory Test

Advanced IndustrialPractices 2STDF Failed Datalog Std

9:30 a.m.2:00 p.m. Exhibits Free entry 9:30 a.m. 2:00 p.m.

10:30 a.m.12:00 p.m. Session 26Reliability andPower SupplyNoise Analysis

Session 27ATEInstrumentationDesign Ideas

Session 28Path and Small-Delay Fault ATPG

Session 29Test Standards I

Session 30Test for PhysicalDefects inMemories

Advanced IndustrialPractices 3New Frontiers in Test

12:00 .m.1:00 .m. Lunch - Complimentary Lunch in Exhibit Hall at Noon

1:15 p.m.1:45 p.m. Invited Address: This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company

2:00 p.m.3:30 p.m. Session 31

EmergingTechnologiesTest

Session 32

Data ConverterTesting

Session 33

Testing forInterconnect Opensand Crosstalk

Session 34

Test Standards II

Session 35

Scan-basedCompression andTransition Tests

Advanced Industrial

Practices 4ITC/AUTOTESTCONSession

THURSDAY, OCTOBER 30 WORKSHOPS

4:00 p.m.6:30 p.m. Automated Test Equipment Vision 2020 Design for Reliability and Variability Defect- and Data-driven Testing

7:00 .m.9:00 .m. Reception

FRIDAY, OCTOBER 31 WORKSHOPS

8:00 a.m.4:00 p.m. Automated Test Equipment Vision 2020 Design for Reliability and Variability Defect- and Data-driven Testing



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TTTC TEST TECHNOLOGY EDUCATION PROGRAM (TTEP) 2008

The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes a comprehensive set of Te

Technology Tutorials to be held in conjunction with several TTTC-sponsored technical meetings worldwide. The mission of the Test Technolo

Educational Program (TTEP) is to serve test and design professionals by offering fundamental education and expert knowledge in state-of-the-art te

technology topics. TTEP offers tutorial participants the opportunity to earn official certification from IEEE Computer Society TTTC. Each full-dtutorial corresponds to four TTEP units. Upon completion of sixteen TTEP units, official recognition in the form of an IEEE TTTC Test Technolo

Certificate will be presented to the participant. For further information regarding TTEP, please visithttp://tab.computer.org/tttc/teg/ttep/

At ITC08, TTTC/TTEP is pleased to present seventeen full-day tutorials on topics of current interest to test professionals and researchers. All tutori

qualify for credit towards IEEE TTTC certification under the TTEP program. Eight tutorials are held on Sunday, October 26th, and nine on Monda

October 27th.Each tutorial requires a separate registration fee(see ITC registration form or www.itctestweek.org for further information).Admissi

for on-site registrants is subject to availability.

Tutorial attendees receive study material, breakfast, lunch, and coffee breaks. The study material includes a hardcopy of the presentation abibliographical material. Tutorial registration, coffee and pastry are available at 7:00 a.m. on Sunday and Monday.

Sunday 8:30 a.m. 4:30 p.m.

TUTORIAL 1

Advanced Topics and RecentAdvances in Silicon Debug andDiagnosis

PresentersS. Venkataraman,M. Abramovici, R. Aitken

Description Silicon debug and defectdiagnosis activities have become a time-consuming phase in the development cycle of anew design. This tutorial covers the state of theart in silicon debug and defect diagnosisranging from the basic concepts to advancedapplications and new DFD techniques. After abrief review of the basic concepts and

applications of diagnostics over the life-cycle ofa product, design for debug and silicon debugmethods are discussed. Next, recentenhancements and advanced diagnosis topicsare covered, including methods for at-speeddebug and implementing assertions in silicon,diagnosis for delay-faults, debug of clockingand power networks, and establishingcorrelation between simulation and silicon. Thetutorial finishes with scan-chain diagnosis,BIST-based diagnosis, and diagnosis for yieldlearning.

TUTORIAL 2Delay Test: A Practical Approach

PresentersA. Cron, B. Cory

Description This tutorial provides anintroduction to path and transition delay testtechniques. It concentrates on design, vectorgeneration methods, and vector applicationrequirements. Attendees of the tutorial shouldbe able to dive right into their next delay testchallenge.

TUTORIAL 3

IEEE 1500Building a CompliantWrapper

PresentersT. McLaurin, T. Waayers,F. Da Silva

DescriptionThe purpose of this tutorial is toeducate the audience with the challenges andbenefits associated with implementing IEEE1500 compliant wrappers for core test. It willalso give an understanding of the reasonsbehind some of the rules in the standard. A1500 wrapper, with CTL, is built piece-by-piece around an example bare core forillustration purposes. The pros and cons ofdifferent choices that are available to the user ofthe 1500 standard, all rules, integration of coresand SOC test scheduling are all discussed.

TUTORIAL 4Advanced Memory Testing

PresenterA. van de Goor

Description The tutorial covers SRAM faultmodeling, test generation, tests and stresses,DFT, BIST and BISR. Spice simulation andIFA establishes faults in SRAMs; e.g., SAFs,transition and coupling faults. The fault space isestablished; address and data scrambling areaddressed together with data backgrounds andaddressing schemes, speed-related andperipheral circuit faults require nonlinear testssuch as MOVI, GalRow, etc. A large set ofSRAM tests (GalPat, MATS+, March C-,March LR, etc.) are covered; DFT, BIST andBISR are presented. The tutorial ends with acase study, in which a set of tests is applied tohigh speed industry SRAMs, using algorithmstresses, such as Fast-X/Fast-Y, different databackgrounds, etc.; together with voltage and

timing stresses. The results give the attendan

good insight into the effectiveness of talgorithms and stresses.

TUTORIAL 5

Microelectronic Wafer TestTechnology

PresentersJ. Broz, W. Mann

Description This is broad tutorial coverimechanical and electrical aspects of wafer sand the impact wafer sort practices can have assembly and device reliability. A geneoverview of wafer processing, device testinand package assembly demonstrates importan

of wafer sort and exactly where sort fits into toverall manufacturing process. General prorequirements discuss probe/bond pconfigurations on the DUT needed for wafsort, good/bad die identification, feedback the fab, thoroughness of test, temperatueffects, and cost pressures. Each component

a wafer test cell, e.g., the probe cards, tprober, and the ATE, are individually discussin detail. High-volume manufacturing (HVMsort-floor challenges discuss probe-cametrology, online cleaning to maintain hiyield and throughput, and I/O damage control

WorkshopsExhibitsAncillaryEventsAt-a-Glance Panels Registration Venue

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Monday TTTC Full-Day Tuesday Embedded

Tutorials

more Sunday tutorials >

ITC Test Week 2008 5TTTC Full-Day Tutorials

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Discount Rates!Register by

September 29
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Sunday 8:30 a.m. 4:30 p.m.

TUTORIAL 6Design for Manufacturability, Yieldand Reliability

PresentersY. Zorian, J.-A. Carballo

Description In addition to designing thefunctionality, todays SOC necessitatesdesigning for manufacturability, yield andreliability. Such requirements arefundamentally transforming the current SOCdesign methodology. Techniques for enhancingmanufacturability, yield, and reliability, orDFX, include yield enhancement techniques,resolution enhancement techniques, new orrestricted design rules, variability-aware design,and the addition of a special family ofembedded IP blocks, called Infrastructure IPblocks. The latter blocks are meant to ensuremanufacturability of the SOC and to achieveadequate levels of yield and reliability. Theinfrastructure IP leverages the manufacturingknowledge and feeds back the information intothe design phase. This tutorial analyzes the keytrends and challenges resulting inmanufacturing susceptibility and fieldreliability that necessitate the use of the aboveDFX techniques and provides related examples.

TUTORIAL 7Design-for-Testability for RFCircuits and Systems

PresentersM. Margala, S. Osev

Description As the level of integrationcontinues to increase, the test cost escalates.This issue only becomes aggravated as ICs arebeing designed with faster speed, morecomplexity, and higher density. Traditionaltesting mechanisms are specification-based andincapable of meeting current trends in test costreductions. In addition, with the rapid growth ofthe wireless telecommunications industry,testing of RF circuitry has gained significantattention. The test costs associated with RFsystems is considerable, affecting both time-to-market and product cost requirements. The

number of ATEs available with RF testingcapabilities is sparse, and, therefore, thesetesters are exorbitantly expensive. The purposeof this tutorial is to educate the audience withefficient embedded DFT methods for RFcircuits and systems. Its main focus is onpractical and implementation aspects. Thepresented techniques and methodologies areextensively supported by silicon data.

TUTORIAL 8Scan Compression Techniques:Theory and Practice

PresentersR. Parekhji, T. W. Williams,R. Kapur, J. Abraham

Description This tutorial provides comprehensive coverage of scan compressioIt begins with cost models to help designeunderstand the choices available to theThereafter, a more detailed view compression with mathematical underpinniof the different techniques is presenteImplementation techniques and tradeoffs adescribed. Diagnostics, which is an importapart of deep-submicron designs, are aldiscussed within the realm of compressioFinally, compression results are be presentedillustrate how best the theory and practice

together.

Monday 8:30 a.m. 4:30 p.m.

TUTORIAL 9

DFT Fundamentals for Digital TestPresenter G. Perry

Description Digital component test hasundergone significant change over the past fewyears. Circuit complexity, reliabilityrequirements, the cost of test, and many otherfactors are demanding improvements in testmethodologies. This tutorial has beendeveloped to help test, product and applicationsengineers better understand the variousdisciplines and motives that have contributed tothe advances in test technology. Design-for-testability (DFT) is now included in mostdigital circuits. Although information on DFT is

available, the majority of it focuses on chipdesign, rather than test. The goal of this tutorialis to provide a fundamental understanding ofDFT test-related issues. Subjects include: faultmodels, automatic test pattern generation, logicscan, boundary scan, BIST, DFT test techniquesand analysis, and reduced-pin-count testing.

TUTORIAL 10

DFx: The Convergence of Test,Manufacturing and YieldPresenterR. Aitken

DescriptionThe tutorial goal is to show howdesign-for-yield (DFY) and design-for-manufacturability (DFM) are tightly coupledinto what we conventionally think of as test,and that as process geometries shrink, the linebetween defects and process variation blurs tothe point where it is essentially nonexistent. InDFM/DFY circles, it is common to speak ofdefect-limited yield, but it is less common tothink of test-limited yield, yet this concept iscommon in DFT (e.g., IDDQ testing, delaytesting). This tutorial provides backgroundneeded for DFT practitioners to understandDFM and DFY, and see how their work relatesto it. The ultimate goal is to spur attendees toconducting their own research in the area, andto apply these concepts in their jobs.

TUTORIAL 11

Practices in Analog, Mixed-Signaland RF Testing

PresentersS. Abdennadher, S. Shaikh

DescriptionThe objective of this tutorial ispresent existing industry ATE solutions aalternative solutions to ATE testing for mixesignal and RF SOCs. These techniques grearely upon DFT and BIST structures. Ttutorial presents the basic concepts in analand RF measurements (eye diagram, jitter, gapower compression, harmonics, noise figuphase noise, BER, etc.). Several industrexamples of production testing of mixed-signand RF devices, such as, SERDES transceive

PHYs, HSIO, and RF transceivers are alpresented. The block-DFT solutions apresented for PLLs, CDR, equalizers, filtemixers, AGC, LNAs, DACs and ADCs. Ttesting of high-speed IO interfaces, such PCIe, and SATA, etc, and the new desitrends in RF systems such as MIMO and SIbased systems and their testability are alpresented.

Monday TTTC Full-Day Tuesday Embedded


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Monday 8:30 a.m. 4:30 p.m.

TUTORIAL 12When Digital Becomes Analog

Interfaces in High-Speed TestPresenter W. Maichen

Description Successful high-speed digitaltest requires understanding the behavior of allcomponents involved (device, test equipment,interface), as well as the interaction betweenthem. The boundaries between digital andanalog disappear. Connections have to betreated as transmission lines, with every littleimperfection impacting system performance,deteriorating test accuracy, and reducingyield. Maintaining signal integrity isparamount in order to achieve meaningfulresults, and it requires good knowledge of

signal-path behavior, proper choice oftermination techniques, and good design ofthe interface. While the tester itself is usuallygiven and not easily modified, largeimprovements are possible by careful designof the interconnecting load board or probeinterface. Apart from theoretical knowledge,methods to quantify the performance of agiven design by measurements are necessaryas well.

TUTORIAL 13Delay Testing: Theory and Practice

PresentersS. Patil, S. Chakravarty

Description The goal of this tutorial is toprovide the background and knowledge ofDFT methods, tools/methodologies and best-known industry practices necessary forimplementation of delay-test methodology onboth custom and ASIC designs. To that end, itcovers the following key aspects of delaytests: delay-test models and test applicationtechniques, incorporating environmentalconditions such as cross-talk and power droopin delay tests, DFT design techniques tosupport scan-based delay test, relevant toolsand methodologies and representative testcase studies from the industry. The focus of

the tutorial is primarily scan-based delay testswith emphasis on real-world implementationusing industrial case studies. On the theoryfront, the emphasis is on the easy-to-understand theoretical concepts related todelay test, and not on the complicated algebraand theory which accompanies manytheoretical works on delay test.

TUTORIAL 14Memory Test from a Practical and

Implementation ViewpointPresenters V. Jayaram, S. Lai

Description The task of optimallyconfiguring memory BIST and implementingit is becoming increasingly difficult in todaysdeep-submicron designs. Design and testengineers are facing issues with test planning,design integration and silicon debug flows.All of these are coupled with reduceddevelopment cycle-times, and that is makingthe overall process harder. In this tutorial,options available to test memories are coveredat a high level and challenges associated withimplementing memory BIST are covered indetail. Topics include test approaches used in

the industry, algorithm effectiveness, BISTarchitecture, implementation techniques,physical design challenges, verification,silicon debug and memory repair. Emphasis isgiven to both compile-time and run-timeprogrammable memory BIST solutions.

TUTORIAL 15Scan-based Yield Improvement,Debug and Diagnosis

Presenters G. Eide, A. Crouch

Description Most digital IC designs todayuse DFT techniques like internal scan and

BIST to increase the designs testability andautomate the test generation process. Thistutorial is an investigation into detecting andisolating design errors, implementation errors,logic and manufacturing problems usingstructural techniques and scan architectures.When implemented correctly, scan and otherDFT techniques can be used to simplify debugand diagnosis of silicon during device bring-up on the tester, characterization, failureanalysis and initial and ongoing yieldanalysis. The tutorial covers how to utilizeexisting DFT structures as well as how tosuccessfully apply design-for-debug (DFD)and design-for-yield (DFY) techniques andhow to collect and relate fail data from the testprocess to reduce the time to identify theproblem or its root cause.

TUTORIAL 16Statistical Screening Methods

Targeting "Zero Defect" IC Qualityand Reliability

PresenterA. Singh

Description Integrated circuits hatraditionally all been tested identically in tmanufacturing flow. However, as tdetection of subtle manufacturing flabecomes ever more challenging and expensiin aggressively scaled nanometechnologies, innovative new statisticscreening methods are being developed thattempt to improve test effectiveness aoptimize test costs by adaptively subjectisuspect parts to more extensive testing. Tidea is similar to security screening at airpor

Such methods fall into two broad categoriethose that exploit the statistics of defedistribution on wafers, and those that explthe correlation in the variation of process aperformance parameters on wafers. Thtutorial presents test methodologies that spboth these categories, and illustrates theffectiveness with results from a number recently published experimental studies real production circuits by key manufacturer

TUTORIAL 17Test Strategies for System-in-Package

PresenterY. ZorianDescription Todays miniaturization aperformance requirements result in the usaof high-density advanced packagitechnologies, such as system-in-packa(SIP), direct-chip-attach, chip-scale packagi(CSP), and ball-grid arrays (BGA). Due their physical access limitation, tcomplexity and cost associated with their tand diagnosis are considered major issufacing their use. This tutorial providcomprehensive knowledge of test solutiofor advanced packages by placing particuemphasis on: test and debug approaches bare dies; testing schemes for flip-chips us

in direct-chip attach, CSP and SIP packagetesting bare substrates, and finally, tediagnosis and repair techniques for assemblmodules.


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Tuesday 8:00 a.m. 9:15 a.m.

These two tutorials are part of the ITC technical program, and are provided free-of-charge to all registered ITCconference attendees.

TUTORIAL E 1Outliers and the Testing Tools that Reveal Them: AFair and Balanced Introduction to Statistics in Test

PresenterRobert Daasch, ICDT Laboratory, Portland StateUniversity

This tutorial is an introduction to statistics and their uses in semi-conductor test specifically, outlier screening. Outlier parts are revealedbecause their test response differs from a statistical model. The tutorialis grouped into three sections each with three ideas. The tutorial startswith a review of three common statistics used in screening outliers;mean and its nonparametric cousin median, variance (inter-quartile

range) and correlation. Next are the three components of any statisticalmodel; input, output and error. Third, there are three steps to computea model; selection of input and output, estimation of model parametersand evaluation of performance. The statistics are combined with themodeling basics to show how regression models detect outliers.Finally, an introduction to statistics is incomplete without a few wordsof caution such as undersampling, overuse, and overgeneralization.The presenter is not related to Al Franken despite a passingresemblance of the tutorial's title to a book by the comedian, critic,and most recently Democratic candidate for the US Senate.

About the speaker: Dr. Robert Daasch is Professor of Electrical andComputer Engineering at Portland State University and Co-Director ofthe Integrated Circuits Design and Test Laboratory. His researchinterests are digital and analog IC design and test. He hasthree patents. Dr. Daasch and his team have received two best paperawards at International Test Conference 2001 and VLSI TestSymposium 2003, and honorable mention at the ITC in 2004. Dr.Daasch presented plenary addresses at ITC in 2006 and the Defect-based Testing Workshop in 2007. He was coordinator and coauthorof the ITC Outstanding Lecture Series in 2005.

TUTORIAL E 2A Brief Overview of Mixed-Signal Production Test fothe Beginner

PresenterGordon Roberts, McGill University

This tutorial will attempt to describe the basics of mixed-signproduction test in less than 1-1/2 hours. Well start by having a brilook at ATE hardware and the importance of the tester interface in trole of mixed-signal test. This will then be followed by a discussionthe three fundamental impairments of analog and mixed-signcircuitsthese being: signal transmission loss, noise, and distortion

and how each are tested using ATE. As accuracy and precision acentral to any discussion on production test, well look at timplication of these issues on the test process (yield and test timeFinally, well look specifically at the ways in which amplifiers, filtedata converters, SERDES and RF-type devices are tested production. We shall close out on a short discussion on design-for-tand BIST techniques for mixed-signal testing.

About the speaker: Dr. Gordon Roberts is a professor and JamMcGill Chair of Electrical and Computer Engineering at McGUniversity. He has co-written five textbooks related to analog design and mixed-signal test and he has contributed numerochapters to industrially focused textbooks. Dr. Roberts together whis students have won numerous awards including the ITC 2000 BePaper Award, ITC 1994 Honorable Mention Paper Award and the IT1993 Honorable Mention Paper Award. He has also won seveawards for teaching including the 2000 Best Tutorial Award from tTest Technology Technical Council of the IEEE Computer Society.2003 he took leave from McGill to help start DFT Microsystems, Ina company specializing in high-speed timing measurement. DRoberts received the B.A.Sc. degree from the University of Waterlin 1983 and the M.A.Sc. and Ph.D. degrees from the University Toronto, in 1986 and 1989, respectively. Dr. Roberts is a Fellow of tIEEE.


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Exhibits opening:Tuesday 10:30 a.m. 5:45 p.m.Wednesday 9:30 a.m. 5:45 p.m., Thursday 9:30 a.m. 2:00 p.m.

ITC is offering free exhibits-only registration to visit the exhibit hall on Wednesday from 1:00 p.m.to 5:45 p.m. and on Thursday from 9:30 a.m. to 2:00 p.m. On-site registration for this special opportunitybegins on Wednesday at 1:00 p.m. at the ITC registration area in the Santa Clara Convention Center.

Visit the international exhibition that includes the latesthigh-technology test, design and service products.

Exhibitors Corporate Presentations ITC Test Week 2008 9

Tutorials WorkshopsExhibitsAncillaryEventsAt-a-Glance Panels Registration Venue

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Exhibits


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Aehr Test SystemsAntares Advanced Test TechnologiesArdent Concepts, Inc.ARM, Inc.

Asset InterTech, Inc.Atrenta, Inc.Azimuth Electronics, Inc.AsterionBucklingBeamCadence Design Systems, Inc.CarsemCascade MicrotechCentellax, Inc.Chip Scale ReviewCMR Summit Silicon ValleyCorad Technology, Inc.Corelis, Inc.Credence Systems Corp.Dynamic Test Solutions

EE Evaluation EngineeringElectroglas, Inc.ELES Semiconductor Equipment SpaEvans Analytical GroupEverett Charles TechnologiesExatronFinley Design Services, Inc.Focused Test, Inc.FormFactor, Inc.GE Fanuc Intelligent PlatformsGeotest-Marvin Test Systems, Inc.GOEPEL electronic GmbHHamamatsu CorpHiLevel Technology, Inc.Inovys Corporation

Integra TechnologiesIntegrated Test CorporationIntellitech CorporationinTest Silicon ValleyJD Instruments, LLCJohnstech InternationalJTAG Technologies, Inc.Lambda AmericasLogicVision, Inc.

M&M Specialties, Inc.MEIMentor Graphics CorporationMicro Control Company

MicroProbeNano Integrated Solutions, Inc.NHK Spring Company, Ltd.OptimalTestPhoenix Test Arrays, LLCPickering Electronics Ltd.Pickering Interfaces Ltd.Pintail TechnologiesPresto Engineering, Inc.ProligentProtos ElectronicsQ-Star TestQualiSystemsR&D CircuitsRied-Ashman Manufacturing

Roos Instruments, Inc.Rucker and Kolls, Inc.Sanyu Electric, Inc.Semiconductor Test ConsortiumSiliconAid SolutionsSimutest, Inc.Springer Science & Business Media, Inc.SV Probe, Inc.Synopsys, Inc.SynTest Technologies, Inc.TaconicTeledyne RelaysTeraVicta TechnologiesTeseda CorporationTest Coach Corp.

Test InsightTest & Measurement WorldTokyo Electron America, Inc.TSSIUnitechno USA, Inc.Virage LogicWorld Test SystemsYamaichi Electronics USA, Inc.

*As of publication date.

Exhibits Schedule Corporate Presentations

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Tuesday 9:30 a.m. 10:30 a.m.

Opening Remarks

Douglas Young,ITC General Chair

ITC 2007 Paper Awards PresentationJanusz Rajski,ITC 2007 Program Chair

Keynote AddressManaging Test in the End-to-End, Mega Supply Chain

Mike Lydon,Vice President, Technology and Quality, Global Supply Chain Management, Cisco

Todays connected environment has created significant growth

opportunities in the electronics industry. Products have never been sodiverse, ranging from phones that can play movies and give directions tosuper routers that can move terabits worth ofdata around the worldinstantly. It is now possible to access the internet from areas which oncehad little to no contact at all with the rest of the world. This growth inopportunities has spurred significant supply chain growth with significant

growth in both consumers and suppliers. The challenges for todayssupply chain have also grown significantly with much greater diversity inproducts; increasing customer requirements (lower cost, faster deliver,better quality and faster time-to- market); smaller, denser, faster and morecomplex technology and a supply chain that now consists of thousands ofsuppliers and thousands of customers all over the world. All of this witha totally virtual, global supply chain. Mike Lydon will highlight thesechallenges and discuss how test, and the data produced by test can eitherenable or disrupt these virtual supply chains. He will talk aboutcommunication in the virtual supply chain and how test can enable realtime, end-to-end adjustments over the product lifecycle. Mike willconclude by presenting his vision of the test and data managed,optimized, end-to-end, global, virtual supply chain.

About the speaker: Mike Lydon, Vice President Technology and Quality (T&Q), oversees the advancmanufacturing engineering, test, and technology procdefinition and management. This includes componengineering management, central test development, amanufacturing quality process oversight. Mike has bewith Cisco Manufacturing for nine years where hes h

a number of roles of increasing responsibility. Prior to current role, he was in the Product Operations growhere he led a team responsible for manufacturproduct and test engineering, DfX, lifecycle margmanagement, value engineering, and product supstrategy for Internet Systems Business Unit (ISBUApplication Delivery Business Unit (ADBU), and tSecurity Technologies Group (STG). Mike has extensexperience in production operations, product introductiand R&D at Cisco and elsewhere. In 1998 Mike arrivedCisco through an acquisition where he reported to CEO, responsible for the entire supply chain and sourcstrategies, quality oversight, manufacturing engineeriand product cost accountingafter building th

capabilities from the ground up. Mike earned a BSMdegree from the University of California, Davis.

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Tuesday, 1:15 p.m. 1:45 p.m.

Computing at the Crossroads (And What Does it Mean to

Verification and Test?)

Jan N. Rabaey,Donald O. Pederson Distinguished Professor,University of California at Berkeley

When looking back over the past six or seven decades, one can only be awedby the tremendous strides computation has made. The nature of the problemswe can tackle today is truly astounding. Yet, when speculating about what thecoming decades will bring, one cannot escape a perception that somefundamental changes in the computation arena are afoot. Today, we areinterpreting computation as the execution of complex algorithms that areexecuted in sequential fashion and are bound to deliver deterministic answers.A number of factors are conspiring to fundamentally change that model,namely the scaling of technology to the nanoscale dimensions; the emergenceof distributed computation and the changing nature of computation and theunderlying hardware platforms from a cognitive/perceptive model to statisticalmodel. These trends will have a profound effect on the way we verify and testdesigns. It is paramount that we start to explore what all of this means today if

we want to be prepared for what tomorrow will bring.

About the speaker: Jan Rabaey received the EE anPh.D degrees in applied sciences from the KatholiekUniversiteit Leuven, Belgium. From 1983-1985, hwas connected to the UC Berkeley as a Visitin

Research Engineer. From 1985-1987, he was research manager at IMEC, Belgium, and in 1987, hjoined the faculty of the Electrical Engineering anComputer Science department of the University oCalifornia, Berkeley, where he is now holds thDonald O. Pederson Distinguished ProfessorshipFrom 1999 until 2002, he was the Associate Chair othe EECS Dept. at Berkeley. He is currently thscientific co-director of the Berkeley WirelesResearch Center (BWRC), as well as the director othe MARCO GigaScale Systems Research Cente(GSRC). He is an IEEE Fellow, and recipient of th2008 IEEE CAS Mac Van Valkenburg Award.

Wednesday 1:00 p.m. 1:45 p.m.

Having FUN with Analog Test

Robert A. Pease,Staff Scientist, National Semiconductor

Bob Pease is a legend in the analog design community. Bob has designedanalog circuits for over 48 years, including 25 linear ICs and dozens of op ampsand discrete circuits. As a designer for 48 years, Bob understands theimportance of test engineers, test plans and test design. He also understands theimplications of not getting the test done right. Bob will share the good, the badand the ugly test experiences he's had over the years (in a way that only Bob cando). Bob will also answer pre-submitted questions during the session, makingthis the first interactive invited talk in ITC history.

About the speaker: Robert A. Pease graduated frMIT in 1961 with a BSEE degree. He was originaemployed by Philbrick Research, designing seveoperational amplifiers and analog computing modulPease joined National Semiconductor in 1976. He hdesigned over 25 analog ICs including powregulators, voltage references, and temperature sensoHe has written about 65 magazine articles and hoabout 21 US patents. Pease is a Senior Member of IEEE and is the self-declared Czar of Bandgaps sin1986. He was also inducted into the Electron

Engineers Hall of Fame in October, 2002. He written the definitive book, Troubleshooting AnaCircuits (May 1991), now in its 17th printing. It hbeen translated into French, German, Dutch, RussiChinese, and Polish. Pease is a columnist in ElectronDesign magazine, with over 250 columns publishThe column, PEASE PORRIDGE, covers a wide ranof technical topics. Many of Pease's recent columns

posted at Electronic Designs web site.

Wednesday 1:15 p.m. 1:45 p.m.

This is a Test: How to Tell if DFT and Test Are Adding Value to

Your Company

Jeff Rearick,AMD Fellow, Mile High Design Center, AMD

As cost pressures on electronic products continually increase, the urge to triminvestment in test-related circuitry, activity, and equipment increasescorrespondingly. Not only can this strategy backfire if taken too far, but it alsoignores the opportunity for test to actually add value to products. Thispresentation will examine the positive role that test can play and give audiencemembers a set of guidelines to take back to their own companies so that they canperform their own analyses. Numerous examples from a variety of differentelectronic industries show a wide range of possible solutions.

About the speaker: Jeff Rearick leads the Design FTestability Center of Expertise at Advanced Micro

Devices. He has been an AMD Fellow since 2006 anworks at AMDs Mile High Design Center in Fort

Collins, Colorado. Prior to joining AMD, Jeff workefor 22 years at HP and Agilent Technologies. Jeff habeen active in the test community, serving on theworking groups for IEEE1149.6 and IEEE P1687 (forwhich he is the editor) as well as the ITC programcommittee. He has published numerous technicalpapers and has received over 20 patents. He holds aBSEE from Purdue University and a MSEE from theUniversity of Illinois.

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2:00 p.m. 3:30 p.m.

SESSION 1Dealing with Outliers and Variation inToday's ICs

P. Maxwell, Aptina Imaging (Chair)

1.1 A Study of Outlier Analysis Techniquesfor Delay TestingS. Wu,D. Drmanac,L-C. Wang, University ofCalifornia-Santa Barbara

1.2 Production Multivariate OutlierDetection Using Principal ComponentsP. O'Neill, Avago Technologies

1.3 Unraveling Process Variability forProcess/Product Improvement

A. Gattiker, IBM

SESSION 2Microprocessor Test

D. Josephson, Intel (Chair)

2.1 The Test Features of the Quad-CoreAMD OpteronTM MicroprocessorT. Wood, G. Giles, C. Kiszely, M . Schuessler,

D. Toneva, J. Irby, M. Mateja, AMD

2.2 DFx Features of a 3rd

-Generation, 16-Core/32-Thread, UltraSPARC CMTMicroprocessor

I. Parulkar, S. Anandakumar, G. Agarwal,

G. Liu, K. Rajan, F. Chiu, Sun Microsystems;R. Pendurkar, RMI

2.3 Test Access Mechanism for MultipleIdentical CoresG. Giles, J. Wang, A. Sehgal,

K. Balakrishnan, J. Wingfield, AMD

SESSION 3Embedded Memory Diagnosis andCharacterization

R. Adams, Magma Design Automation (Chair)

3.1 High-Throughput Diagnosis via

Compression of Failure Data inEmbedded Memory BIST

J. Tyszer, A. Pogiel, Poznan University of

Technology; N. Mukherjee, J. Rajski, Mentor

Graphics

3.2 A History-based Diagnosis Techniquefor Static and Dynamic Faults in

SRAMs

A. Ney, A. Bosio, L. Dilillo, P. Girard,

S. Pravossoudovitch, A. Virazel, LIRMM;

M. Bastian, InfineonTechnologies

3.3 Analysis of Retention Time Distributionof Embedded DRAM A New Methodto Characterize Across-Chip ThresholdVoltage VariationW. Kong, P. Parries, G. Wang, S. Iyer, IBMSemiconductor R & D Center

SESSION 4High-Speed I/O Testing in the Real World

M. Li, Altera (Chair)

4.1 External Loopback TestingExperiences with High-Speed SerialInterfaces

A. Meixner, S. Bedwani, A. Kakizawa,

B. Provost, Intel

4.2 Low-Cost Testing of Multi-GBit DevicePins with ATE-assisted LoopbackInstrumentW. Fritzsche, A. Haque, Credence Systems

4.3 Efficient High-Speed InterfaceVerification and Fault AnalysisT. Nirmaier, J. Zaguirre, Infineon; E. Liau,

A. Rettenberger, W. Spirkl, Qimonda;D. Schmitt-Landsiedel, Technological

University of Munich

4:15 p.m. 5:45 p.m.

SESSION 5Defect Avoidance and Cost ModelingS. Patil, Intel (Chair)

5.1 Implementation Update: Logic MappingOn SPARC Microprocessors

A. Vij, R. Ratliff, Texas Instruments

5.2 Failing-Frequency Signature AnalysisJ. Lee, E. McCluskey, Stanford University

5.3 A Cost Analysis Framework forMulticore Systems with SparesS. Shamshiri, P. Lisherness, S-J. Pan,

K-T. Cheng, University of California-SantaBarbara

SESSION 6Delay Testing and Chip PerformanceMaximization

M. Tehranipoor, University of Connecticut (Chair)

6.1 Scan-based Testing of Dual/MulticoreProcessors for Small Delay Defects

A. Singh, Auburn University

6.2 On-Chip Programmable Capture forAccurate Path Delay Test andCharacterization

R. Tayade, J. Abraham,The University ofTexas at Austin

6.3 An Automatic Post-Silicon ClockTuning System for Improving ChipPerformance Based on TesterMeasurementsK. Nagaraj,S. Kundu, University ofMassachusetts

SESSION 7APG and SAT

I. Polian, Albert-Ludwigs-University ofFreiburg(Chair)

7.1 CONCAT: Conflict-driven Learning in

ATPG for Industrial Designs

S. Bommu, K. Chandrasekar, R. Kundu,

S. Sengupta, Intel

7.2 SAT-based State Justification withAdaptive Mining of InvariantsW. Wu, M. Hsiao, Virginia Tech

7.3 RTL Error Diagnosis Using a Word-level SAT-SolverS. Mirzaeian, K-T. Cheng, University ofCalifornia- Santa Barbara; F. Zheng, ZhejiaUniversity

SESSION 8High-Performance Interfacing

H. Zhang, Texas Instruments (Chair)

8.1 Embedded Power Delivery Decouplingin Small Form Factor Test SocketsO. Vikinski, S. Lupo, G. Sizikov,

C-Y. Chung, Intel

8.2 Measurement Repeatability for RFTest Within the Loadboard Constrainof High-Density and Fine-Pitch SOCApplicationsT. Warwick, EPE; G. Rivera, D. Waite,

J. Smith, Qualcomm; J. Russell, R&D Circu

8.3 Wafer-level Characterization ofProbecards Using NAC ProbingG-Y. Kim, E-J. Byun, K-S. Kang,

Y-H. Jun, Samsung Electronics;B-S. Kong, Sungkyunkwan University

Wednesday A.M. Wednesday P.M. Thursday A.M. ThursdayP.M. ITC Test Week 2008 13

TechnicalPapersTutorials WorkshopsExhibits

AncillaryEventsAt-a-Glance Panels Registration Venue

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8:30 a.m. 10:00 a.m.

SESSION 9Power-Aware DFT Methods

L. Basto, Cadence Design Systems (Chair)

9.1 A Power-aware Test Methodology forMultisupply Multi-Voltage DesignsV. Chickermane, P. Gallagher, J. Sage,

P. Yuan, K. Chakravadhanula, Cadence

Design Systems

9.2 Peak Power Reduction ThroughDynamic Partitioning of Scan ChainsS. Almukhaizim, O. Sinanoglu, Kuwait

University

9.3 Power-aware At-Speed Scan TestMethodology for Circuits withSynchronous Clocks

B. Nadeau-Dostie, K. Takeshita,

J-F. Ct, LogicVision

SESSION 10Opens + ShortsC. Henderson, Semitracks (Chair)

10.1 Time-dependent Behavior of Full-Open

Defects in Interconnecting LinesR. Rodrguez-Montas, D. Arum,

J. Figueras, Universitat Politcnica de

Catalunya; S. Eichenberger, C. Hora,

B. Kruseman, NXP Semiconductors

10.2 Statistical Yield Modeling for

Subwavelength LithographyA. Sreedhar, S. Kundu, University ofMassachusetts at Amherst

10.3 Detection of Internal Stuck-OpenFaults in Scan ChainsF. Yang,S. Reddy, University of Iowa;S. Chakravarty,

N. Devta-Prasanna, LSI;I. Pomeranz, Purdue University

SESSION 11Advances in Board Interconnect TestTechnology

R. Jukna, Jabil Circuit (Chair)

11.1 Engineering Test Coverage on

Complex SocketsM. Schneider, Agilent Technologies;

A. Shafi, Advanced Micro Devices

11.2 Solving In-Circuit Defect Coverage

Holes with a Novel Boundary-Scan

ApplicationJ. Grealish, B. Van Dick, D. Dubberke, Intel

11.3 Augmenting Boundary-Scan Tests forEnhanced Defect Coverage

D. Norrgard, K. Parker, AgilentTechnologies

SESSION 12System-level Microprocessor Online TestS. Seshadri, Intel (Chair)

12.1 Low-Energy Online SBST ofEmbedded Processors

A. Merentitis, N. Kranitis,

A. Paschalis, University of Athens;

D. Gizopoulos, University of Piraeus

12.2 Online Failure Detection in MemoryOrder Buffers

J. Carretero, X. Vera, P. Chaparro,

J. Abella, Intel

12.3 VAST: Virtualization-assistedConcurrent Autonomous Self-Test

H. Inoue, NEC; Y. Li, S. Mitra, StanfordUniversity

10:30 a.m. 12:00 p.m.SESSION 13Power Impact on Compression and At-Speed ScanK. Arabi, PMC Sierra (Chair)

13.1 Reducing Power Supply Noise in

Linear-Decompressor-based Test DataCompression Environment for At-

Speed Scan Testing

M-F. Wu, J-L. Huang, National Taiwan

University; X. Wen, K. Miyase, Kyushu

Institute of Technology

13.2 Low-Power Scan Shift and Capture inthe EDT Environment

J. Tyszer, D. Czysz, Poznan University of

Technology; M. Kassab, X. Lin, G. Mrugalski,

J. Rajski, Mentor Graphics

13.3 Frequency and Power CorrelationBetween At-Speed Scan andFunctional TestsS. Sde-Paz, E. Salomon, FreescaleSemiconductor

SESSION 14Diagnostics

M. Ward, LSI (Chair)

14.1 Deterministic Diagnostic PatternGeneration for Compound DefectsF. Wang, Y. Hu, H. Li, X. Li,Institute of

Computing Technology, CAS;

Y. Huang, Mentor Graphics, Y. Jing, Peking

University

14.2 Diagnosis of Design-Silicon TimingMismatch with Feature Encoding and

Importance RankingThe

Methodology ExplainedP. Bastani, N. Callegari, L- C. Wang,

University of California-Santa Barbara;

M. Abadir, Freescale Semiconductor

14.3 Efficiently Performing YieldEnhancements by Identifying PhysicaRoot Cause from Test Fail Data

M. Sharma, B. Benware, L. Ling,

D. Abercrombie, L. Lee, M. Keim, H. Tang,

W-T. Cheng, T-P. Tai, Mentor Graphics;Y-J. Chang, R. Lin, UMC; A. Man, AMD

SESSION 15Access and Opens at Board Test

J. Burgess, Intel (Chair)

15.1 Solder Bead on High-Density

Interconnect Printed Circuit BoardB. Chu, Intel

15.2 Finding Power/Ground Defects on

ConnectorsCase StudyS. Hird, R. Weng, Agilent Technologies

SESSION 16Innovative Solutions to Complex SOCsS. Pendharkar, Advanced Micro Devices (Chair)

16.1 Architecture for Testing Multi-Voltag

Domain SOCL. Souef, C. Eychenne, E. Ali, NXP

Semiconductors

16.2 Integration of Hardware Assertions i

Systems-on-Chip

J. Geuzebroek, B. Vermeulen, NXPSemiconductors

16.3 Distributed Embedded Logic Analysifor Post-Silicon Validation of SOCs

H-F. Ko, A. Kinsman, N. Nicolici, McMasteUniversity

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2:00 p.m. 3:30 p.m.

SESSION 17Advances in Defect Diagnosis and SiliconDebug

E. Amyeen, Intel(Chair)

17.1 An Effective and Flexible Multiple-

Defect Diagnosis Methodology UsingError Propagation Analysis

X. Yu, R. Blanton, Carnegie Mellon University

17.2 Detection and Diagnosis of Static

Scan Cell Internal DefectR. Guo, L. Lai, Y. Huang,

W-T. Cheng, Mentor Graphics

17.3 Optical Diagnostics for IBM

POWER6 Microprocessor

P. Song, S. Ippolito, F. Stellari, J. Sylvestri,

T. Diemoz, G. Smith, P. Muench, N. James,

S. Kim, H. Saenz, IBM

SESSION 18Industry Experience with ComplexDesigns

D. Belete, FreescaleSemiconductor(Chair)

18.1 Functional Test and Speed/Power

Sorting Enablement of the IBMPOWER6 and Z10 ProcessorT. Pham, F. Clougherty, G. Salem, J. Crafts,

J. Tetzloff, P. Moczygemba, T. Skergan, IBM

18.2 Transition Test on UltraSPARC T2

MicroprocessorL-C. Chen, P. Dickinson, P. Mantri, M. Gala,

P. Dahlgren, S. Bhattacharya, O. Caty,

K. Woodling, T. Ziaja, D. Curwen, W. Yee,

E. Su, G. Gu, T. Nguyen, Sun Microsystems

18.3 DFT Architecture for Automotive

Microprocessors Using On-ChipScan Compression Supporting Dual

Vendor ATPGH. Ahrens, R. Schlagenhaft,

H. Lang, Freescale Semiconductor;

E. Bruzzano, V. Srinivasan,

STMicroelectronics

SESSION 19Poster Previews

R. Datta, The University of Texas at Austin (Chair)

Each poster presenter will give a five-minute summary of their work. Theposters session will take place during theOktoberfest reception following theWednesday afternoon panels.

SESSION 20RF TestingY. Makris, Yale University(Chair)

20.1 Octal-Site EVM Tests for WLAN

Transceivers on Very Low-Cost ATEPlatformsG. Srinivasan, H-C. Chao, F. Taenzler, Texas

Instruments

20.2 Optimized EVM Testing for IEEE

802.11a/n RF ICsE. Acar, S. Ozev, Duke University;

G. Srinivasan, F. Taenzler, Texas Instruments

20.3 Efficient EVM Testing of Wireless

OFDM Transceivers Using Intelligent

Back-End Digital Signal ProcessingAlgorithms

V. Natarajan, H. Choi, D. Lee,

R. Senguttuvan, A. Chatterjee, GeorgiaInstitute of Technology

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8:30 a.m. 10:00 a.m.

SESSION 21Test QualityDefects, DPPM and Patterns,Oh My!K. Kim, Intel (Chair)

21.1 Towards a World Without Test

Escapes: The Use of Volume Diagnosisto Improve Test QualityS. Eichenberger, J. Geuzebroek, C. Hora,

B. Kruseman, A. Majhi, NXP Semiconductors

21.2 Modeling Test Escape Rate as aFunction of Multiple Test CoveragesK. Butler, J. Carulli, Jr., J. Saxena, TexasInstruments

21.3 Evaluating the Effectiveness ofPhysically-aware N-Detect Test UsingReal SiliconY-T. Lin, O. Poku, S. Blanton, CarnegieMellon University; P. Nigh, V. Iyengar,P. Lloyd, IBM

SESSION 22

Software to the Rescue!R. Arnold, Infineon (Chair)

22.1 A Method to Generate a Very Low-Distortion, High-Frequency SineWaveform Using an AWG

A. Maeda, Verigy

22.2 Leveraging IEEE 1641 for Tester-independent ATE Software

B. Van Wagenen, J. Vollmar,D. Thornton, Teradyne

22.3 Bridging the Gap Between Design andTest Engineering for FunctionalPattern Development

H. Ahrens, E. Aderholz,

M. Rohleder, Freescale Semiconductor

SESSION 23"Outside-the-Box" DFT Solutions

A. Jas, Intel(Chair)

23.1 Plug & Test at System Level viaTestable TLM Primitives

H. Alemzadeh, F. Refan, Z. Navabi, Universityof Tehran; S. Di Carlo, P. Prinetto,Politecnico di Torino

23.2 Design-for-Test of AsynchronousNULL Convention Logic (NCL) CircuitsW. Al-Assadi, S. Kakarla, Missouri Universityof Science and Technology

23.3 Noncontact Testing for SOC (SIPs)and RCP at Advanced Nodes

B. Moore, C. Sellathamby, M. Reja, T. Weng,B. Bai, E. Reid, S. Slupsky, Scanimetrics;M. Mangrum, Freescale Semiconductor;I. Filanovsky, University of Alberta

SESSION 24Systems Effects of Errors and ProtectionMethodsK. Mohanram, Rice University (Chair)

24.1 On the Correlation between ControllerFaults and Instruction-level Errors inModern Microprocessors

M. Maniatakos, Y. Makris, Yale University;N. Karimi, University of Tehran; A. Jas, Intel

24.2 Using Implications for Online ErrorDetectionK. Nepal, Bucknell University; N. Alves,

J. Dworak, R. Bahar, Brown University

24.3 A Field Analysis of System-level

Effects of Soft Errors Occurring inMicroprocessors Used in InformationSystems

M. Baradaran Tahoori, S. Shazli, M. Abdul-

Aziz, D. Kaeli, Northeastern University

SESSION 25Embedded Memory Test

M. Sonza Reorda, Politecnico di Torino(Chair)

25.1 Direct Cell-Stability Test Techniquesfor an SRAM Macro with AsymmetricCell-Bias-Voltage Modulation

A. Katayama, T. Yabe, O. Hirabayashi,Y. Takeyama, K. Kushida, T. Sasaki,

N. Otsuka, Toshiba

25.2 A Shared Parallel Built-in Self-RepairScheme for Random Access Memoriesin SOCsT-W. Tseng, J-F. Li, National CentralUniversity

25.3 Testing Methodology of EmbeddedDRAMsC-T. Chao, C-M. Chang, National Chaio-TungUniversity, R-F. Huang, MediaTek;

D-Y. Chen, TSMC

10:30 a.m. 12:00 p.m.

SESSION 26Reliability and Power Supply NoiseAnalysis

M. Sachdev, University of Waterloo (Chair)

26.1 Optimized Circuit Failure Prediction forAging: Practicality and Promise

M. Agarwal, AMD; V. Balakrishnan,W. Wang, B. Yang, Y. Cao, Arizona StateUniversity; A. Bhuyan, K. Kim,

B. Paul, S. Mitra, Stanford University

26.2 SOC Test Architecture Design andOptimization Considering PowerSupply Noise EffectsF. Yuan, Q. Xu, The Chinese University ofHong Kong

26.3 Observation of Supply-Voltage-NoiseDispersion in SubnanosecondK. Takeuchi, G. Tanaka, H. Matsushita,

Renesas Technology; K. Yoshizumi,

Y. Katsuki, T. Sato, Hitachi ULSI Systems

SESSION 27

ATE Instrumentation Design IdeasD. Oka, LOA Technology (Chair)

27.1 A Hybrid A/D Converter with 120-dBSNR and125-dB THD

M. Tamba, Yokogawa Electric

27.2 Generating Test Signals for Noise-based NPR/ACPR-type Tests inProductionS. Aouini, G. Roberts, McGill University

27.3 An Electronics Module for 12.8-GbpsMultiplexing and Loopback Test

D. Keezer, A. Majid, Georgia Institute ofTechnology; D. Minier, P. Ducharme, IBM

SESSION 28Path and Small-Delay Fault ATPGS. Chakravarty, LSI (Chair)

28.1 On Accelerating Path Delay FaultSimulation of Long Test Sequences

I-D. Huang, Y-S. Chang, S. Natarajan,R. Sharma, Intel; S. Gupta, USC

28.2 Implicit Identification of NonrobustlyUnsensitizable Paths Using theBounded Delay Model

D. Jayaraman, E. Flanigan, S. Tragoudas,Southern Illinois University Carbondale

28.3 Interconnect-aware and Layout-oriented Test-Pattern Selection forSmall-Delay Defects

M. Yilmaz, ; K. Chakrabarty, DukeUniversity; M. Tehranipoor, University ofConnecticut

SESSION 29Test Standards I

A. Cron, Synopsys (Chair)

29.1 Boundary-Scan Testing ofPower/Ground PinsK. Parker, Agilent Technologies;

N. Jacobson, Xilinx

29.2 IEEE 1500 Core Wrapper OptimizatioTechniques and Implementation

B. Mullane, M. Higgins,C. MacNamee, University of Limerick

29.3 Turbo1500: Toward Core-based Desigfor Test and Diagnosis Using IEEE St1500

L-T. Wang, R. Apte, S. Wu, B. Sheu, H-J.

Chao, J. Guo, J. Liu, Y. Niu, Y-C. Sung,

C-C. Wang, F .Li, SynTest Technologies;K-J. Lee, National Cheng Kung University;

X. Wen, Kyushu Institute of Technology;W-B. Jone, University of Cincinnati;C-H. Yeh ,W-S. Wang, Silicon Integrated Sy

SESSION 30Test for Physical Defects in Memories

A. Virazel, LIRMM (Chair)

30.1 Defect-oriented Testing of the StrapProblem Under Process Variations inDRAMs

Z. Al-Ars, S. Hamdioui,A. van de Goor, DeUniversity of Technology; G. Mueller, Qim

30.2 A New Wafer-level Latent-DefectScreening Methodology for HighlyReliable DRAM Using a ResponseSurface Method

J. Nam, S. Chun, S. Kang,YonseiUniversity; G. Koo, Y. Kim, B. Moon,J. Lim, J. Joo, S. Kang, H. Kim, K. Shin,K. Kang, Samsung Semiconductor

30.3 A High-Speed Structural Method forTesting Address Decoder Faults inFlash MemoriesO. Ginez, J-M. Portal, H. Aziza, Aix-Marseille Universit, IM2NP

TuesdayA.M. Wednesday A.M. Wednesday P.M. ThursdayP.M.




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8:00 a.m. 8:30 a.m. Hot-Topic Background SessionOverview of Test Generation and Analysis for Reducing Test Escapes J. Dworak, Brown University


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2:00 p.m. 3:30 p.m.

SESSION 31Emerging Technologies Test

V. Iyengar, IBM (Chair)

31.1 Fabrication Defects and Fault Models

for DNA Self-AssembledNanoelectronicsV. Mao, C. Dwyer, K. Chakrabarty, Duke

University

31.2 Built-in Self-Test and Fault Diagnosis

for Lab-on-Chip Using DigitalMicrofluidic Logic Gates

Y. Zhao, T. Xu, K. Chakrabarty, Duke

University

31.3 Testing Techniques for Hardware

SecurityM. Majzoobi, F. Koushanfar, Rice University;M. Potkonjak, University of California, LosAngeles

SESSION 32Data Converter Testing

D. An, CMC Microsystems(Chair)

32.1 Linearity Test Time Reduction for

Analog-to-Digital Converters Using the

Kalman Filter with ExperimentalParameter Estimation

L. Jin, National Semiconductor

32.2 Built-in Self-Calibration of On-ChipDAC and ADCW. Jiang, V. Agrawal, Auburn University

32.3 A New Method for Measuring ApertureJitter in ADC Output and ItsApplication to ENOB TestingT. Yamaguchi, M. Kawabata, M. Ishida,

K. Uekusa, Advantest Laboratories;M. Soma, University of Washington

SESSION 33Testing for Interconnect Opens andCrosstalk

D. Walker, Texas A&M University(Chair)

33.1 Test Generation for InterconnectOpens

X. Lin, J. Rajski, Mentor Graphics

33.2 A Novel Pattern GenerationFramework for Inducing Maximum

Crosstalk Effects on Delay-sensitivePaths

J. Lee, M. Tehranipoor, University of

Connecticut

33.3 Extraction, Simulation and TestGeneration for Interconnect Open

Defects Based on EnhancedAggressor-Victim ModelS. Hillebrecht, I. Polian, P. Engelke,

B. Becker, Albert-Ludwigs UniversityM. Keim, W. Cheng, Mentor Graphics

SESSION 34Test Standards IIC. Barnhart, Cadence Design Systems (Chair)

34.1 The Advantages of Limiting P1687 to aRestricted Subset

J. Doege, AMD;A. Crouch, ASSET InterTech

34.2 A New Language Approach for IJTAG

M. Portolan, S. Goyal, Bell Labs Ireland;

B. Van Treuren, C-H. Chiang,

T. Chakraborty, T. Cook, Alcatel-Lucent Bell

Labs

34.3 Problems Using Boundary-Scan forMemory Cluster Tests

B. Van Treuren, C-H. Chiang, K. Honaker,

Alcatel-Lucent

SESSION 35Scan-based Compression and TransitionTests

G. Mrugalski, Mentor Graphics (Chair)

35.1 Increasing Scan Compression byUsing X-ChainsP. Wohl, JA. Waicukauski,

F. Neuveux, Synopsys

35.2 Align-Encode: Improving theEncoding Capability of Test StimuluDecompressorsO. Sinanoglu, Kuwait University

35.3 Launch-on-Shift-Capture TransitionTests

I. Park, E. McCluskey, Stanford University

Tuesday A.M. Wednesday A.M. Wednesday P.M. Thursday A.M.




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FreeExhibits Admission

Wednesday 1:00 p.m.5:30 p.m.

Thursday 9:30 a.m.2:00 p.m.


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Advanced Industrial Practices sessions provide an opportunity for attendees to learn the latest methods and techniques used by industry leadein addressing some of todays most important test challenges. This years AIP sessions include an introduction to automotive test, including DFTproduction flow, and zero defects practices, followed by a tutorial on the STDF Fail Datalog Standard, and a session covering diverse topics sucas optical test, high performance probe test, and the test implications of new design techniques. The final session outlines practical methods for

justifying DFT at the system level

AIP SESSION 1 Tuesday 2:00 p.m.3:30 p.m.

Automotive Test Practices

K. Mandl, Teradyne (Chair)

A 1.1 DFT Implementations for Striking the Right Balance BetweenTest Cost and Test Quality for Automotive SOCs

R. Parekhji, Texas Instruments (India)

A 1.2 A Cooperative Effort Between Design and Production Flowsto Meet Automotive Quality Requirements

F. Melchiori,D. Pandini,S. Pugliese,D. Appello,STMicroelectronics;

P. Bernardi, Politecnico di Torino

A 1.3 Achieving Zero Defects for Automotive Applications

R. Raina, Freescale Semiconductor

AIP SESSION 2 Thursday 8:30 a.m.10:00 a.m.

STDF Fail Datalog Standard

R. Aitken, ARM (Chair)

A 2.1 A Tutorial on STDF Fail Datalog StandardA. Khoche, P. Burlison, Verigy; J. Rowe, Teradyne;

G. Plowman, Qualcomm

AIP SESSION 3 Thursday 10:30 a.m.12:00 p.m.

New Frontiers in Test

R. Aitken, ARM (Chair)

A 3.1 Parametric Testing of Optical InterfacesB. Achkir, B. Eklow, Cisco Systems

A 3.2 POWER6 Reliability Screens and Test MethodologyF. Clougherty, J. Crafts, J. Dery J. VanHorn IBM

A 3.3 New Circuit Design Techniques that Every Test EngineerShould Know AboutS. Naffziger, AMD

AIP SESSION 4 Thursday 2:00 p.m.3:30 p.m.

Special Joint ITC/AUTOTESTCON Session

A. Ambler, University of Texas at Austin

A 4.1 Justifying DFT with a Hierarchical Top-Down Cost ModelS. Davidson, Sun Microsystems

A 4.2 The Economics of Harm Prevention Through Design forTestability

L. Ungar, A.T.E. Solutions

A 4.3 DFT, Starting at the Beginning with Knowledge of the EndJ. Lauffer,C. dePaul, DSI International

Lecture Series Corporate Presentations Posters



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Tuesday 11:00 a.m. 4:30 p.m. Wednesday 8:30 a.m. 4:30 p.m.

The corporate track allows you to stay on top of the latest commercial products in the semiconductor test industry and helps youunderstand how the innovations behind the products can add value to your employer. Whereas the technical program allows you to gai

an in-depth understanding of the latest technical innovations, the corporate track allows you to actually gain an in-depth understandingof how some of the technology innovations impact the product portfolios of companies. In this interactive forum, executives of ITCexhibitors or sponsors will present their latest products and sometimes product roadmaps. Moreover, company representatives are freeto hand out relevant literature such as papers or marketing material. Typical presentations include case studies, best practices, andtestimonials. For example, last years corporate track covered innovative products in the area of EDA, ATE, test software, yieldlearning, adaptive test, probe-cards, high-speed test, boundary scan, STIL, and switching technologies. Attendance to the sessions willbe open to all conference attendees.

Thirty-six companies participated in 2007, and we expect a similar representation this year. Check future issues

of this advance program to obtain further information and a schedule.



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Lecture Series Advanced Industrial Practices Posters

Corporate Presentations


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Wednesday 5:45 p.m.7:15 p.m. held in conjunction with the Oktoberfest reception.

Poster previews will be given in Session 19 on Wednesday at 2:00 p.m.

N. Touba, University ofTexas at Austin (Chair/Coordinator)

PO 1 Overview of IEEE P1450.6.2 Standard: Creating CTL Modelsfor Memory Test and RepairS. Adham, LogicVision

PO 2 IEEE P1581 Drastically Simplifies Connectivity Test forMemory Devices

H. Ehrenberg, GOEPEL Electronics

PO 3 Low-Power TestS. Bahl, R. Sakar, A. Garg, STMicroelectronics

PO 4 IEEE 1500-compatible Secure Test Wrapper for Embedded IPCores

J. Li, G-M. Chiu, National Taiwan University

PO 5 Test-Access Solutions Three-Dimensional SOCsX. Wu, Y. Chen, Y. Xie, Penn State University; K. Chakrabarty, DukeUniversity

PO 6 SOC Test Optimization with Compression TechniqueSelectionA. Larsson, X. Zhang, E. Larsson, Linkping University;K. Chakrabarty, Duke University

PO 7 SOC Yield Improvement: Redundant Architectures to theRescue?

J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch,

A. Virazel, LIRMM

PO 8 Platform-independent Test Access Port ArchitectureMargulis, T. Wood, S. Metsis, Advanced Micro Devices;

D. Akselrod, McMaster University

PO 9 NoC Reconfiguration for Utilizing the Largest Fault-freeConnected Substructure

A. Alaghi, M. Sedghi, N. Karimi, Z. Navabi, University of Tehran

PO 10 VLSI Test Exercise Courses for Students in EE DepartmentS. Komatsu, University of Tokyo

PO 11 Hardware Overhead Reduction for Memory BISTM. Arai, K. Iwasaki, Tokyo Metropolitan University; M. Nakao,I. Suzuki, Renesas Technology

PO 12 A Low-Cost Programmable Memory BIST Design forMultiple Memory InstancesC-F. Lin, C-F. Huang, D-C. Lu, C-C. Hsu, W-T. Chiu,

Y-W. Chen, Y-J. Chang, Faraday Technology

PO 13 The Importance of Functional-like Access for Memory TestJ. Phelps, C. Johnson, C. Goodrich, A. Kokrady, Texas Instruments

PO 14 An Efficient Secure Scan Design for an SOC EmbeddingAES Core

J. Song, T. Jung, J. Lee, H. Jeong, B. Kim, S. Park, HanyangUniversity

PO 15 Diagnosis of Mask-Effect Multiple Timing Faults in ScanChains

J. Ye, F. Wang, Y. Hu, X. Li, Institute of Computing Technology, CA

PO 16 Diagnosis of Logic-to-Chain Bridging FaultsJ. Li, W-C. Liu, W-L. Tsai, H-T. Lin, National Taiwan University

PO 17 Power Distribution Failure Analysis Using Transition-DelaFault Pattern Generation

J. Lee, J. Ma, M. Tehranipoor, University of Connecticut;

PO 18 Is It Cost-effective to Achieve Very High Fault Coverage foTesting Homogeneous SOCs with Core-level Redundancy

L. Huang,Q. Xu, The Chinese University of Hong Kong

PO 19 System JTAG Initiative Group AdvancementsB. Van Treuren, Alcatel-Lucent

PO 20 A Generic Framework for Scan Capture Power Reduction Test Compression Environment

X. Liu,F. Yuan,Q. Xu, The Chinese University of Hong Kong

PO 21 High Test Quality in Low-Pin-Count ApplicationsJ. D'Souza,S. Mahadevan,N. Mukherjee,G. Rhodes, MentorGraphics; T. Droniou,J. Moreau,P. Armagnat,D. Sartoretti,STMicroelectronics

PO 22 Capture and Shift Toggle Reduction (CASTR) ATPG toMinimize Peak Power Supply Noise

H-T. Lin, J-Y. Wen, J. Li, National Taiwan University; M-T. Chang,M-H. Tsai, S-C. Huang, C-M. Tseng

PO 23 Test Quality Improvement with Timing-aware ATPG:Screening Small Dely Defect Case Study

J. Chang, AMD; T. Kobayashi, Mentor Graphics

PO 24 FPGA-based Time Measurement Module: PreliminaryResultsW. Bowhers, Merrimack College

PO 25 Wireless Test Structure for Integrated SystemsZ. Noun, P. Cauvet, NXP Semiconductors;M-L. Flottes, D. Andreu,S. Bernard, LIRMM

PO 26 Overview of a High-Speed Topside Socket SolutionJ. Stewart, T. Animashaun, Intel

PO 27 Improving the Accuracy of Test Through Adaptive TestUpdateS. Biswas, Nvidia; R. Blanton, Carnegie Mellon University



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Monday, 5:00 p.m. 6:30 p.m.

Panel 1 Power-aware DFTDo We Really Need It?K. Butler, Texas Instruments (Moderator) N. Mukherjee, Mentor Graphics (Organizer)

Scan-based vectors dissipate much more power compared to the functional operation of a device. These vectors are known to cause IR drop, voltagedroop, hot spots, etc. Consequently, there is an increase in demand for power reporting, insertion of DFT logic to control power dissipation during shas well as capture, design partitioning, imposing power threshold limits during ATPG, etc. But there are some basic questions that need to be answereIs there a real power dissipation problem during test mode? Is it impacting yield today? How do we make sure that power dissipation during testcorrelates well with the functional mode? Are we under-testing our design if we restrict power? This panel provides a forum to ask these toughquestions to the experts and help us understand how to address the challenges in the near future.

Panelists:R. Galivanche, Intel W. Huott, IBM P. Krishnamurthy, LSI B. Pouya, Freescale Semiconductor J. Rearick, AMD

Wednesday, 4:00 p.m. 5:30 p.m.

Panel 2 Analog Test Technology: Stable and Grounded, or Open Loop and Spurious?

T. Lee, Stanford University (Moderator) M. Purtell, Intersil (Organizer)

Reuse spanning decades of analog test circuits (Op-amp measurement loops), ATE, and test methodology will be discussed with solutions for

the future. DSP, BIST, ATE vs. load board solutions, trimming, precision measurements and other analog topics will be discussed.Panelists: T. Anderson, TeradyneS. Goyal, National Semiconductor T. Schmitz, Intersil S. Sunter, LogicVision

Panel 3 Will Test Compression Run Out of Gas?

J. Rearick, AMD(Moderator) E. Marinissen, NXP Semiconductors,S. Goel, LSI (Organizers)

This panel addresses the question if test data compression was only a temporary fix, or a truly future-proof solution. Interoperability, low-power test,high-volume diagnosis, digital vs. analog testing, built-in self-test and low-cost ATEs will all be discussion in the scope of the future of testcompression.

Panelists: S. Bhatia, Cadence Design Systems S. Pateras, LogicVisionJ. Rajski, Mentor Graphics J. Rivoir, Verigy

Panel 4 Debug War Stories

M. Abadir, Freescale Semiconductor (Moderator) L. Winemberg, Freescale Semiconductor (Organizer)

A panel of experts in silicon debug will describe their most difficult/challenging debug scenarios. While describing their scenarios they will stop atvarious points and ask the audience what they think the next step should be. Are you ready to match wits with our panelists to help debug this war?

Panelists:R. Aitken, ARMR. Antley, Texas InstrumentsD. Carder, Freescale Semiconductor J. Carulli, Texas Instruments

Panel 5 Yield LearningWho Gains, Who Picks Up The tab?

R. Nelson, Reed Business Information (Moderator) P. Burlison, Verigy (Organizer)

Expanding the role of test into improved yield learning has been a recent hot topic. This panel of executives representing fabless, foundry,outsourced semiconductor assembly and test (OSAT) and ATE segments will discuss who gains from this effort and how, and perhaps morecontroversially, who should pick up the tab.

Panelists: D. Ahlgren, Verigy C. Cheung, ASE

Panel 6 The University DFT Tool ShowdownS. Davidson, Sun Microsystems (Moderator/Organizer)Think that university DFT work can't handle real designs? Think again. This panel highlights work by four university researchers on theOpenSparc T1 and T2 processors, open source versions of commercially available multicore microprocessors. Come see which universities canbest beat industry in handling real designs.

Panelists: D. Gizopoulos, University of PiraeusI. Polian, Albert-Ludwigs-University of FreiburgI. Parulkar, Sun Microsystems M. Sonza ReorPolitecnico di Torino L. Wang, University of California



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IEEE Computer Society Test Technology Technical Council Workshops

Thursday and Friday

General Workshop InformationThree workshops are being held in parallel immediately following ITC 2008 at the Santa Clara Convention Center. Theystart with an opening address on Thursday afternoon, October 30, followed by a technical session. A reception for all

workshop participants will be held on Thursday evening. The remaining the technical sessions will be held on Friday,October 31. The technical scope of each workshop is described below.

Workshop RegistrationAll workshop participants require registration. To register in advance for one of the workshops, do so online or by faxing the downloform. Otherwise, register on-site at regular rates during Test Week at the ITC registration counter at the Santa Clara ConventiCenter. Admission for on-site registrants is subject to availability. Discount workshop registration rates apply until September 22008. See pages 25 and 26 for details. Workshop registration includes the opening address, technical sessions, digest of paperworkshop reception, break refreshments, continental breakfast and lunch .

Digest of Papers

A digest of papers will be distributed only to attendees at the workshops as an informal proceedings.

Workshop ScheduleAll three workshops will adhere to the same schedule:

Thursday, October 30 Friday, October 31Registration 2:00 p.m.7:00 p.m. Registration 7:30 a.m.10:00 a.m.

Opening Address 4:00 p.m.4:30 p.m. Technical Sessions 8:00 a.m. 4:00 p.m.

Technical Session 4:30 p.m.6:30 p.m.

Reception 7:00 p.m.9:00 p.m.

Note: Workshop schedule is subject to change

Further InformationFor more information on the three workshops contact their organizers by e -mail or check the TTTC Web site http://computer.org/tttc

Workshop Summaries


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https://www.badgeguys.com/reg/itc2006/register.aspxhttp://www.itctestweek.org/RegistrationForm2006.pdfhttp://www.itctestweek.org/RegistrationForm2006.pdfhttp://computer.org/tttchttp://computer.org/tttchttp://computer.org/tttchttp://www.itctestweek.org/RegistrationForm2006.pdfhttp://www.itctestweek.org/RegistrationForm2006.pdfhttp://www.itctestweek.org/RegistrationForm2006.pdfhttps://www.badgeguys.com/reg/itc2006/register.aspx


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ATE Vision 2020: IEEE International Workshop on Automated Test Equipment Vision 2020

Scope: This workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuiget denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test qualitarget. Certain dies require known-good-die (KGD) quality levels, whereas more complex failure modes already challenge our yielearning curves. These issues, when added to increasing cost-of-test (COT), time-to-volume (TTV), and time-to-market (TTM

pressures, driven by todays high-volume market applications, pose significant challenges to the ATE industry. To meet thochallenges the industry needs to innovate in areas such as test methodologies, interconnection technologies, architectures, and desigfor-testability (DFT) technologies. The goal of this workshop is to create an informal forum to discuss those innovations relevant ATE developers and users. We are looking for solutions to the issues of 2020 and beyond, not those of 2008. Are our roadmapaddressing future test challenges? Do we have the right business models in place to succeed in the future? Join the discussioRepresentative topics include, but are not limited to the following:

ATE for statistical testATE/EDA link

Lost-cost ATEAdaptive design techniques

RF and high-speed I/O testTest methods for future defects

General Chair: Erik Volkerink,[email protected] Chair: Scott Davidson,[email protected]

DRV: IEEE Workshop on Design for Reliability and Variability

Scope: As silicon-based CMOS technologies are fast approaching their ultimate limits reliability is threatened by issues such process, voltage and temperature variability, accelerated aging and wearout, radiation-induced soft-errors and crosstalk. These problemare creating barriers to further technology scaling and are forcing the introduction of new process and design solutions aimed maintaining acceptable levels of reliability. As elimination of these issues is becoming increasingly difficult, various design techniquincluding self-calibration and fault tolerance are emerging as the most promising design approaches to circumvent them. However, thetechniques may incur significant area, power or performance penalties. Thus, to enable their adoption by industrial teams, there is nefor new solutions which minimize these penalties, together with automation tools. The goal of this workshop is to create an informforum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable coTopics to include:

Reliability issues in advanced CMOSVariability-aware designRadiation effects in advanced CMOSDesign-for-Reliability

Fault-tolerant architecturesVariability mitigationSelf-calibrating architecturesOnline monitoring of circuit parameters

Design automation for fault toleranceVariability-insensitive architecturesReliability assessment tools

General Chairs: Yervant Zorian,[email protected], Michael Nicolaidis,[email protected]

D3T: IEEE Workshop on Defect- and Data-driven Testing

Scope: New test-data-based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-5nm technology nodes. Data-driven testing (DDT) has been in practice for a number of years. It is now gaining attention more than evin adaptive test. DDT can provide feedbacks on which tests to add/remove, or test subsets (e.g., reduced MINVDD test sets.) It can alsbe utilized for improving quality of logic test patterns (e.g., small delay defect, defect-based) vs. outlier analysis tests (e.g., MINVDDIDDQ). However, test data has not been easily accessible by smaller companies and researchers in academia. These issues will bdiscussed in this years D3T workshop. The D3T is aimed at addressing these issues and others related to this years theme D aDriven Testing (DDT). Paper presentations on topics related to the workshops theme and to those given below are expectedgenerate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade:

Outlier identificationData-driven testingTest data analysisAdaptive testing

Data mining methods for test data processingLow voltage testingNoise and crosstalk testingNanometer test challenges

Defect coverage and MetricsMixed-current/voltage testingEconomics of defect-based testingFault localization and diagnosis

General Chair: Rob Aitken,[email protected]

Program Chair: Mohammad Tehranipoor,[email protected]


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mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:zorian@viragel

Documents

ITC Program 2008