ITRS Design ITWG 2012 1 ITRS Design + System Drivers July 9-10, 2012 Design ITWG Masaru Kakimoto (Japan) Juan-Antonio Carballo (USA) Gary Smith (USA) David

ITRS Design ITWG 2012 1

ITRS Design + System Drivers

July 9-10, 2012

Design ITWG

Masaru Kakimoto (Japan)Juan-Antonio Carballo (USA)Gary Smith (USA) David Yeh (USA)Andrew Kahng (USA)


Design and System Drivers – Messages

1. Design technology continues to add low power roadmap techniques

2. Design technology, still unclear how new devices affected it (FinFET)

3. Design technology for 3D continues to spread across chapter

4. Design technology for resilience a fundamental portion of DFM

5. Non-Moore fabrics will require increasingly specialized DT

6. Memory an increasingly important factor for design technology

7. Push to integrate AMS/RF on SoC/SiP despite positive 3D prospects

8. Soaring applications may overhaul driver list: DTV, microservers…


Highlights of 2012-2013 Plans1. Design Chapter

• Review/next ver of Power-Aware DT roadmap (2012-13) - DONE• Special DT for non-Moore fabrics (SW, AMS/RF, MEMS) (2013) - PENDING• Updates on LCP, DFT, Design Verification; v2 of 3D section (2013) - PENDING• Additional content on (design for) resilience, memory (2012) - PENDING• 2012 (September) – need to have updated tables (ext by 1 yr) (2012) - PENDING

• System Drivers Chapter• Revisit the AMS/RF “sub-driver” of Consumer SOC driver (2013) - PENDING• Overhaul SOC-CP & CS (TV) models, Embedded Memory (2013) - PENDING• Overhaul Driver list ? Is SOC-CS really a driver? Who is ? (2012) - PENDING

• What's the next driver ? Automotive, Medical, Energy. 1. Update MPU model (&frequency). What about microservers ? (2012) - PENDING

• Cross-TWG1. CTSG: node timing, additional A-factor updates (2012) - PENDING2. How will FinFET, UTBB SOI timing change PPA projections? (2012) - PENDING3. Renewal of PIDS roadmaps (compact modeling interaction) (2012-13) - PENDING4. 3D effort with the other TWGs (2012-13) - PENDING






• Cross-TWG• CTSG: node timing, additional A-factor updates (2012-13) - DONE• How will FinFET, UTBB SOI timing change PPA projections? (2012-13) - DONE• Renewal of PIDS roadmaps (interaction on compact modeling) (2012-13) - DONE• 3D effort with the other TWGs (2012-13) - PENDING


Design Cost Chart

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2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

ITRS 2011 Cost Chart

Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

Total HW Engineering Costs + EDA Tool Costs (smoothed) Total SW Engineering Costs + ESDA Tool Costs (smoothed)

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Power Design Technology Roadmap


Power Design Technology Roadmap

NEW: approximate computing, dark Silicon, extreme heterogeneity


New Power Design Technology1. Approximate computing

• Variable-accuracy computing (e.g., flexibly going from 64b to 16b)

• 4D computing: reconfiguration on the fly

• AVS ? (e.g., part of DVFS). Margin reduction?

2. Dark Silicon

• “normally-off computing” = “extreme power gating”

3. Extreme heterogeneity

• “coprocessor-dominated architectures” (pervasive heterogeneity; energy-

efficiency from specialization; HW accelerators)

• “10 x 10”, “13 dwarves”, …

• Cf. Intel “accelerators for MPU” vs. Tensilica (or, GPUs, xPUs)

NOTES

• Not every product can use all the techniques

• Asynchronous could be too late

• HW Virtualization and Superscalar factors need to be examined






• Cross-TWG• CTSG: node timing, additional A-factor updates (2012-13) - DONE• How will FinFET, UTBB SOI timing change PPA projections? (2012-13) - DONE• Renewal of PIDS roadmaps (interaction on compact modeling) (2012-13) - DONE• 3D effort with the other TWGs (2012-13) - PENDING


Memory as a Key Factor in Future DT

Figure DESN12 Possible Variability Abstraction Levels

PhysicalPhysical

DeviceDevice

GateGate

ChipChip

Bit CellBit Cell

CircuitCircuit ArrayArray


Memory as a Key Factor in Future DT

Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types






• Cross-TWG1. CTSG: node timing, additional A-factor updates (2012) - PENDING2. How will FinFET, UTBB SOI timing change PPA projections? (2012) - PENDING3. Renewal of PIDS roadmaps (interaction compact modeling) (2012-13) - PENDING4. 3D effort with the other TWGs (2012-13) - PENDING


MTM – AMS/RF “Subdriver”

Several emphases in DT, DFT: System verification, Hetero systems

Plan: paste high-level block model from AMS/RF -- “core model”

– Hope to obtain model from additional groups, market analysis

– E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator

blocks


Generating Mixed-Fabric Drivers

Primitive models(Digital)

Functional blocks (digital)

SoC / SiP Drivers (SoC-CP)

Device models (PIDS)

Technology models (A&P)

Technology models

(Interconnect)

Device models(ERD)

Primitive models (Other)

Primitive models

(AMS/RF)

Functional blocks (non-

Moore)

SoC / SiP Drivers (SoC-CS)

GAP

…


What Drivers? 1. SOC-Consumer Portable (CP) Driver

• What will be future driving applications ?

• What Geos would drive them moving forward ? US ?

• Are phone and tablet similar enough for SOC-CP projection?

2. SOC-Consumer Stationary (CS) driver

• Is it still a driver ? (orginially abstracted from Cell)

• Smart TV processor ?

• Kinect ?

• Is Signal processing on mobile similar to stationary ?


Proposed changes to MPU Model

Item Current (2011) model

Proposed model

Die area 140mm2 (CP), 260mm2 (HP)

140mm2 (CP), 260mm2 (HP)

Area ratio Core :: 1 Core : LLC : UnCore :: 1: 1: 1

LLC NA 12MB (2011) + 1.4x every tech node[Borkar10, Borkar07]

UnCore NA Uncore Scaling

SRAM A-factor (USRAM)

60F2 (6T), 84F2 (8T) (bulk)

60F2 (6T), 84F2 (8T) (bulk, FinFET)40F2 (6T), 56F2 (8T) (high-density FinFET) ***

* CP – Cost-Performance; HP – High Performance** L2$ and L1$ is per core


“Uncore” (increasing portion of MPU) consists of:– Memory controller(s)– Graphics and display controller(s)– I/O and bus interface controller(s)

Updated MPU Model: UnCore Scaling

Item Proposed model

Memory controller N/2 (CP), N (HP); N = # cores[Borkar07, Borkar11, 80-core, IVB]

Graphics and Display controller 2x every tech node[NHM, SNB, NVIDIA]

I/O and bus interface controller N/6[SNB, IVB]

Logic (# transistors) growth Same as core

Logic density Same as core

SRAM (# bitcells) growth 512MB * # GPU-Cores[IVB, NVIDIA]

SRAM density Same as core


SoC / MPU Potential Driver Convergence ?

Ongoing product roadmap and More-Than-Moore impact analysis (WIP)

Recent SoC clock and #cores frequency scaling trends

May need to re-examine existing MPU and/or create new driver

1. Clock frequency growing at 1.5X every 2 years.

2. Number of cores growing at 2X every 4 years.

3. Networking-like SoC scaling: off-chip latency, accelerators, L3 cache

4. Power limitation under 4W per core (HPC example).

5. Off-chip speed can be as high as 204 Gbits / sec.

6. “Mobile” Computing SoCs increasingly competing in server space

• Beginning to be used in data centers and cloud computing

• Extreme core efficiency (active power <4W, sleep power< 0.5W)

• Cores and frequency scaling similar to conventional MPUs


Special DT for non-Moore fabrics

• SW, AMS/RF, MEMS, 3D / novel packaging ?

• Current design technology still insufficient

• Design technology will continue to broaden

• What design technology is needed beyond current ideas ?

• New 3D / TSV design flows

• New multi-physics modeling, simulation, analysis tools

• Example: thermal / mechanical analysis (base station)

• Example: MEMS + electrical analysis (mobile gaming)

• Example: sensors + signal processing (industrial, medical)

• Example: software + HW simulation (data center network)


Device Model / PIDS interaction

• Agreed to only one low power device in the roadmap

• Removed LOP device flavor from 3 to 2 devices

• Still questioning how much CD variation can be tolerated

• Should Design content change as we move toward 450 mm ?

• Should Design care about node definitions ?

• (foundry names vs. ITRS)


Design and System Drivers – Messages

1. Design technology continues to add low power roadmap techniques

2. Design technology, still unclear how new devices affected it (FinFET)

3. Design technology for 3D continues to spread across chapter

4. Design technology for resilience a fundamental portion of DFM

5. Non-Moore fabrics will require increasingly specialized DT

6. Memory an increasingly important factor for design technology

7. Push to integrate AMS/RF on SoC/SiP despite positive 3D prospects

8. Soaring applications may overhaul driver list: DTV, microservers…

Documents

ITRS Design ITWG 2012 1 ITRS Design + System Drivers July 9-10, 2012 Design ITWG Masaru Kakimoto (Japan) Juan-Antonio Carballo (USA) Gary Smith (USA) David