Naval Command.Control and Ocean San Diego, CA

Surveillance Center RDT&E Division 92152-5001

AD-A278 610

Technical Document 2610December 1993

iWarp Display Module

J. J. Symanski S L C

S APR 2 6 1994

IMP

94- 12705

iiPf . Approved for public releaae disrbution is unlimited.

fHow 1n4 4II

Technical Document 2610December 1993

iWarp Display Module

.CSSon ForJ. J. Symanski NTIS CRA

unannounced

justitication------By -...............-

DistribUtiofl"AvailabilitY Codes

Avil and I or

Dist Special

NAVAL COMMAND, CONTROL ANDOCEAN SURVEILLANCE CENTER

RDT&E DIVISIONSan Diego, California 92152-5001

IL E. EVANS, CAPT; USN R. T. SHEARERCommanding Officer ExecuUve Director

ADMINISTRATIVE INFORMATION

The work documented in this report was performed by Jerry Symanski of theTechnology Research and Development Branch (Code 761) within the SurveillanceDepartment of the Naval Command, Control and Ocean Surveillance Center, Research,Development, Test, and Evaluation Division.

Released by Under authority ofG. W Byram, Head J. R. Wangler, HeadTechnology Research and Space Systems andDevelopment Branch Technology Division

ACKNOWLEDGMENTS

Sponsorship was provided by the HPC for "Infra-Red Focal-plane-array Sensor Pro-cessing" task of the High Performance Computing project, which is, in turn, part of theComputer Technology Block Program from the Office of Naval Research.

The author is indebted to Dr. Keith Bromley, Mr. Robert Wasilausky, and Mrs.Elizabeth Wald for their support. The author also wishes to thank Dr. Jon Webb ofCarnegie-Mellon University for modifying the Adapt compiler and assembly coderoutines.

SM

CONTENTS

INTRODUCTION ................................................. 1

DISPLAY MODULE DESCRIPTION ................................ 1

BASIC OPERATION ............................................... 5

DESIGN RATIONALE AND APPROACH ........................ 6

DESIGN ENTRY AND SIMULATION ........................... 8

FABRICATION OF THE DISPLAY BOARD ...................... 8

TEST BOARD ................................................. 9

MONITOR REQUIREMENTS ................................ 9

INSTALLATION ............................................... 9

TEST SOFTWARE ............................................. 10

CONCLUSIONS ................................................... 10

FIGURES

1. Display module ................................................. 3

2. Layout of image board components ................................ 4

3. Test board . .................................................... 7

TABLES

1. Image characteristics for the iWarp image display module for a1024-x-1024 pixel display ......................................... 2

ill°*

INTRODUCTION

The increasing speed and precision of weapons has made high-speed processing and theinterpretation of data essential to Navy missions. The only viable long-term answer to theseincreased processing requirements is to combine the processing speed of many processors in par-allel systems. NRaD has been involved in this critical area of research since the first systemswere developed in 1989. Pioneering work at Carnegie-Mellon University has lead to the InteliWarp processor, of which NRaD has two 64-node processors. Current work in the High-Performance Computing for Infrared Sensor Processing Program (NRaD project ECB2) utilizesthe iWarp processor. With the high-speed processing capability of the iWarp, we need high-speedand high-resolution display capabilities to fully exploit the potential of the iWarp hardware. Thegoal of this work is to provide a high-resolution real-time image display module and softwarefor the iWarp. Software will be written to program the display to work with the high-level Adaptimage processing language. This will enable researchers to program in a high-level language andevaluate sensor data processed on the iWarp in real-time.

This report will describe the highlights of the design of the display module and the softwaredeveloped in the course of this work. Complete schematics for the display module are presentedin Appendix A. Software for testing and running demonstrations are contained in Appendix B.

DISPLAY MODULE DESCRIPTION

The display module is a custom circuit board designed specifically for the iWarp processor.The module attaches to the external memory bus of an iWarp cell. Direct attachment to an iWarpcell will take maximum advantage of the processing power of the iWarp, the high bandwidth ofthe iWarp cell I/O, and the existing image processing software for the iWarp.

With software written during this development, the board generates video signals to drive ahigh-resolution display, with images processed within the iWarp.

The module contains 4 megabytes of VRAM which will hold images of user-determinedpixel depth and size. Image data are converted to analog video signals by the Inmos G364 colorvideo controller chip. Image sizes can range from 1024-by-1024 24-bits-per-pixel true-colorimages to 1-bit-per-pixel monochrome images. The user is able to choose pixel depth via soft-ware. The Inmos G364 allows many choices from 600-by-400 to 1280-by-1024 pixel imagesizes. The trade-off is made depending on the depth of color and monitor used. Table 1 showsthe flexibility the 4-Mb VRAM and the Inmos video controller give the user. The frame rate islimited by the rate at which the iWarp can generate and transmit image data to the VRAM.

Table 1. Image characteristics for the iWarp image display module for a 1024-x-1024 pixeldisplay.

Characteristic True-Color Pseudocolor Monochrome

Pixel depth 24 16/15 8 4 2 1(bits-per-pixel)

Frames stored 1 2 4 8 16 32(pixels x depth)

Frame load rate 4/20 8/40 16/80 32/160 64/320 128/640(frames per second)

Note: Image resolution is limited by the bandwidth of the Inmos video generator, which is currently 135 MHz.

Figure 1 shows the completed circuit board. Figure 2 shows the component layout. The max-imum size allowable for the circuit board is 4.2 by 8.9 inches. A board this size fits over thefront or rear half of a Quad Cell Board (QCB). Due to the physical constraints, the VRAMs aremounted at an angle. Heat dissipation of about 0.5 watt per package requires that the packagesbe mounted both top and bottom to spread out the heat and maximize the effect of the coolingair, which flows upward in the chassis. The G364 is a programmable color video controllerwhich supports a total of seven different pixel depth-operating modes: four pseudocolor modesand three true-color modes. The pseudocolor modes have pixel depths of 2, 4, 8 bits-per-pixel.True-color modes of 15, 16, and 24 bits-per-pixel use the look-up-table for gamma correction.The Inmos G364 has a 64-bit-wide data bus to input the serial data from VRAMs, so using the256K by 4 VRAMs requires 16 packages. Furthermore, the G364 supports the interleaving oftwo banks of VRAMs, for a total of 32 VRAM packages. The iWarp memory interface is also64-bits wide but has two bits of parity on each 32-bit word. Thus there must be another 4VRAMs to contain the parity data, which the iWarp cell computes on each 32-bit word written tomemory. Control circuitry is implemented in Programmable Logic Devices (PLDs) and a num-ber of standard integrated circuits. The red, green, and blue (RGB) analog outputs of the G364connect to the high-resolution monitor via three coaxial cables.

2

0ECu

a-

3

.01 1.80" t*o 2.40

:i4 AS27-05 -EA 7-WRIT

S175Test Points:

20ASOS 062 20-GD 19-WL

IL2CSr-- -------7sO1i 16 -1015 RW N

*1 20 AS2TRC7 ON 130-3.LP

SEce 124 20 SAS 11 -7G WT

2436 SPR 10-1021T-9 M A

24 PM 9024

5POnA C1025

r,2.AS80817 -____S!

RCT20 3028 S

CAS24C 2IC66 1C32 PS

246 HLCW 0 20 ASSOS -106 C173P L0-300C

24 TE G3 h4 SE -C36 120 45-ld n I C71 bIad.U.aw.s st 3 i __Also. ~ ~ ------ -----~du~ipnadeW h i oeeerqte0.4 .. 0 pae il

Figure1 2.LyuIfiae orCopnns

R IC24

BASIC OPERATION

Conceptually, the operation of the module is quite simple, due to the design of the board andthe capabilities of the Inmos G364 graphics controller chip. The details of the operation of thelogic will not be described here. Those interested in details should contact the author. Onceinstalled, the module is reset with the same reset signal as the iWarp cell. The display is turnedon by setting the control registers of the G364. The software to accomplish this is described inthe ib.h header file in Appendix B.

Once initialized to a specific format, the module continuously displays the data in the VRAMwithout further intervention or control from the iWarp. The initialization is done once to start thedisplay. The image is updated by writing into VRAM.

The display board circuitry must select between three sources, which need control of theVRAM: the iWarp, the VRAM refresh circuitry, or the G364 video controller. For a clean dis-play, the G364 controller must be able to load a new row of data into the VRAM serial accessregisters at a rate dependent on the number of pixels and the pixel depth. For a 1024-by-10248-bits-per-pixel display, the G364 must have control of the VRAM for 2 p.s every 128 pts. Duringthis time, the iWarp and the refresh circuitry are ignored. If a request comes from the iWarp orthe refresh circuitry, the request will be held until the G364 is finished, and then it will be serv-iced.

The VRAM can be written to in two ways: random addresses and page mode. In randomaddressing, any 32-bit integer (4 bytes) can be written into any of the 1,048,576 VRAM memorylocations. The random write takes 650 ns since row addresses and column addresses must begiven to the VRAM. The page mode write is used for the sequential writing of data. This is theusual case for an image which has been formatted into raster lines. This mode writes at about250 ns for 8 bytes or a peak rate of 32 MB/s.

The control of the operation and the determination of the status of the display are achievedvia a 4-bit control register. Control bit 0 latc.,es in the page address for the page mode of opera-tion. Bit 1 enables the event signal from the iWarp, which enables a quick response of the iWarpcell to the G364 requests for VRAM access. Bit 2 resets the G364 graphics chip. The reset of theG364 has special timing requirements. Bit 3 is a test bit.

As part of the development and operation of the display module, several iWarp programswere developed to aid in the use of the display. Three types of software were provided: (1) rou-tines for the initialization of the graphics controller chip, (2) test programs for generating anddisplaying data on the cell with the display, and (3) Adapt high-level language routines to pro-vide a basis upon which further image processing programs can be built.

Dr. Jon Webb at Carnegie-Mellon University has written a special version of Adapt whichmakes it very simple to use the display board. He has also supplied assembly code routineswhich minimize the time to write to the VRAM.

To the image processing application developer, data can be displayed with a simple one-linesubroutine call:

ad_collect_imageport(outO, imageid).

5

Built-in Adapt routines gather the data from individual cells and write the data to the cellwith the display board.

DESIGN RATIONALE AND APPROACH

The display module drives a high-resolution monitor capable of displaying pixel depths from1-bit (black and white) to 24-bit true-color images, of at least 1024-by-1024 pixels. These capa-bilities are required to fully utilize the capabilities of the iWarp processor and achieve maximumflexibility and potential for iWarp users. The chip chosen to generate the video is the InmosG364. This chip has a 64-bit-wide data input bus which matches the memory bus of the iWarpprocessor. This enables maximum data transfer to the video RAM. Another factor favoring theInmos G364 is that it can be programmed in software to generate many display formats. Thechip is simple to use. There are only the digital data input, digital control registers, and analogvideo output. This one chip contains circuitry to read the image data from standard VRAM, gen-erate control signals for multiple formats, and perform sophisticated digital-to-analog signal con-version. The G364 also has 50-0 line drivers which can be connected directly to the monitor.

The display of a 1024-by-1024 24-bit image requires 4 MB of RAM storage. At the time ofthe design, the 262,144-word by-4-bit VRAM was the state-of-the-art device. Availability in theplastic ZIP package made the packing of 4 MB onto the allowable circuit board possible.

PLDs are used to the largest degree possible. This is both to attain high density of logic andto ensure that even after the printed circuit board had been fabricated, there would be an abilityto modify circuit operation to adjust to problems which were not anticipated.

The display module is memory mapped into the iWarp local memory address space. Thisprovides the simplest control circuitry and the simplest functional description. There are twotypes of memory writing and reading. The user has the ability to read or write into random cellsof the display as well as write a raster line of sequential pixels at a faster rate in page mode.

The G364 graphics chip is also memory mapped. The specific registers and values which ini-tialize the controller for selected modes are described in the ib.h header file in Appendix B.

In ordei to simplify testing and minimize the impact of the initial debugging and generationof test software on iWarp users, the display module was installed in the iWarp only after the cor-rect operation of the board was verified. A test board (figure 3) hosted by an IBM PC, wasdesigned which emulated the hardware interface of the iWarp cell. Test images were written tothe display board, using the PC so that there was a minimum of programming when the modulewas installed in the iWarp. This saved time and effort since the PC has a more direct interactionwith the display module. The C language was used to generate the test software, so the test codewas easily ported to the iWarp with only minor changes.

6

cc

I-

7

DESIGN ENTRY AND SIMULATIONThe complexity of a graphics board demands that we use advanced computer-aided engineer-

ing (CAE) tools to simulate and verify the operation of the circuit to the greatest extent possible,to insure the highest probability of a correct design on the first board. NRaD has a Dazix/Inter-graph CAE system to perform this task. The complexity of the design makes it imperative thatthe design be simulated before the fabrication of the printed circuit board. The use of PLDs willincorporate a degree of flexibility into the design, even after the board has been fabricated. Inany design of this size, there are unforeseen problems which only come to light after the designhas progressed to the final stages.

Design entry is a highly complex and iterative process. First the components to be used inthe design must be available in the CAE tools. If they are not, they must be generated in soft-ware and added to the library of available devices. The generation of models for use in simula-tion is a highly specialized skill in itself and can be time consuming. This design uses devicesavailable in the Dazix design system library, with the exception of the Inmos G364 and theToshiba Video RAM.

After components are chosen, they are connected to implement the desired logical functionsusing the schematic editor. Care must be taken to partition the logic in a way which will notexceed the limitations of the design system, i.e., gate counts and wiring limits. As one proceedsthrough the design, putting together portions of the design, simulations are run to verify that thedesired operation is achieved. Careful attention must be paid to the test signals to be sure thatthey actually are the signals which the host system will be supplying to the board beingdesigned. This portion of the design can generate problems if the signals described in the avail-able documentation are inaccurate or misinterpreted.

This design was captured in 30 pages of schematics. The schematics are presented in Appen-dix A. Due to the complexity, the design will not be fully discussed here. Readers interested inthe details of the design should contact the author directly. The first schematic shows the toplevel of the design. This takes three pages and shows the major blocks of the design and the con-nections to the iWarp cell signals as well as test points which aid in the debugging process. Thecontrol block contains nine PLDs which control the operation of the display. The logic in thePLDs is shown in corresponding schematics.

FABRICATION OF THE DISPLAY BOARD

The completed display board is shown in figure 1. This is an eight-layer printed circuitboard. The net list for the board was generated by the Dazix system and converted for use on aRacal Visula system for layout. The process of generating the printed circuit board from a net listand layout schematic is a complex task in itself and was performed by engineers who haveexpertise in this area. The net list must be converted to the format of the layout system. Then thephysical package corresponding to the components used in the logic must be taken from the lay-out system's library, or created, and placed on the circuit board. Physical constraints caused bythe iWarp forced a high density of components. This made it necessary to try several approachesto the physical layout of the components. The final layout of the components is shown in figure2. Components are placed on both sides of the board. Many test points are used to ease the test-ing process.

8

TEST BOARD

The test board is shown in figure 3. This board greatly eased the initial debugging of the dis-play module by allowing a much simpler hardware and software interface for testing. Note theconnector on the left side of the board. This is identical to the connector on the iWarp quad cellboard onto which the module is to be installed. While the speed at which the data can be trans-mitted to the display is much lower with the PC than the data rate of the iWarp, the correctoperation of the logic can be verified. The software developed during this initial checking of theboard was also used to verify the functionality in the iWarp. The parameters necessary to set upthe different modes of operation of the Inmos G364 graphics chip were determined using the testboard. Only by using it, does one gain a real understanding of how a complex device such as theG364 really works. This type cuf knowledge is best gained in the simplest environment possible,i.e., without the complicating factors of the UNIX/Sun/iWarp software and hardware to furthercloud the issues.

MONITOR REQUIREMENTS

The display module is designed to work with a high-resolution, noninterlaced monitor suchas the Sony GDM-1953. The horizontal frequency of the Sony GDM-1953 is 63.34 kHz and thevertical frequency is 59.98 Hz. Resolution is 1280 by 1024. A Hitachi HM-4119 is also usable.The Inmos graphics chip is supplying red, green, and blue signals with vertical and horizontalsync signal on the green signal. The video format is composite video with plain (not tessellated)sync. There is no blanking pedestal. The interlace standard is EIA.

The parameters needed to drive the Sony monitor were derived from the Inmos G364 usermanual. The parameters for several formats are documented in the header file in Appendix B.

INSTALLATION

The installation of the board into the iWarp is simple, requiring about 10 minutes. We startwith a running system.

First, the iWarp must be powered down to avoid the possible crash of the host system.Change to the /iwarp/diag directory and run iwconf. When iwconf comes up enter: dep gcr=Ofa.This will put the iWarp into a safe state for powering down.

Power down the iWarp. Open the chassis and remove the board to which you wish to attachthe module. The module can be attached to any QCB, but some boards may be easier to workwith than others. The board can mount in either the northeast or southwest comer of the QCB.However, if mounted in the southwest comer, the board will extend beyond the edge of theQCB. Thus it is best to mount the board in the northeast comer of the QCB.

The board attaches to the QCB with four Phillips head screws. Be sure to align the connectorso that the screws will enter smoothly. Tighten down the screws in an "X" sequence to even outstresses.

Once the module is attached, carefully slide the QCB into the chassis. This must be donewith extreme caution since the VRAMs may contact the surface mount resistors on the back of

9

the adjacent QCB. If there are problems, remove the QCB which the display module mightbump, and slide both into the chassis together, so that there is no relative movement between theboards.

The coaxial cables which drive the monitor can be routed out the front of the chassis orthrough the rear and connected directly to the monitor.

TEST SOFTWARE

Appendix B contains several test programs which demonstrate the operation of the displayboard. These programs also act as templates as how to set up the G364 and write to VRAM ineither the random or page mode. Also the event-handling code and its operation are shown.

Finally, a sample Adapt program is provided as a set of four files. The files begin with thenames master.c., frame.c., frame.ad. and fastio.h. These four files are required to compile pro-grams for Adapt. As shown in the master.c.addonebw program module, display of the resultsof image processing is accomplished with one call, namely:

adcollectimage port(outO, outid)

This one line is all that is necessary. The routine gathers the data from the cells, stores theimage on the System Interface Board (SIB) and streams the data from the SIB directly to the dis-play.

CONCLUSIONS

The design fabrication and integration of the high-resolution display module for the iWarpprocessor has been completed. The real-time display of images processed using the Adapt high-level programming language has been demonstrated.

10

Appendix A

DISPLAY MODULE SCHEMATICS

A-1

0, x mL

ac~u ut

- ý0

'.t Li 004 -9

4 rr.

~ ~C35 4 'A0 0u-

9-booa

In LLII a1C -~'- ~ 1u

V) g1Tzlf 0 -0A- . V )C) 1 'A 't UJ

40

uV; X

mma

A-

C.) -, >, -P i

.N C c C.~

00000 cin~c ; 0

x & . 0 . .

-0- c

002

00.00

0 E CL .J -a -I

1. -- -. - -

00vCv u -

-. 0. o* i 000 -- .

00

0 0 c~

C0 ft I

x I,

In w- I0 CC.

03 . .n 0 .. .. . ,NI

%A V , 'A VC 06 C 'tX . . u . .. .

-.A

0 A CA In

so 00

3c Q:0 m O- a -SI

32 V c. u. wIA~ Sc v C*z M

c c

Is ~i .a 'x w

43 0.0

U199999,990£0

0A 0g P00 In. w wOIinin .IA' CD CD D 0C

%A o 1 w It 010. C4 ,I0n C.

CO v4 00 ,.

a - C- c a INC~ 00Cmo*-. 0 -~ ->

1. 0 0 0£00 0c .3.c

* ~ C CLi

zu v . OO 94200 0

*wo ..'!Wni 602. u 0 .ou

£c 0 o".. I V,0

L., b A-c4

aD cc aL u m a %A a a a

w wW- 4-A -6 , - o

.. : 0

'A'4 4A V

0 0

c.1 f an z- IHHO Io*-N~.u, or 41 .0..-- XvELLELLL

-a 4A' CP i

u444 4 A44 4 44 4 4 44 4 4 4 4 .

U, 'A V.

0 * U.9 lS)I GIN O-ON 1W.NICOaC 11~'' S~ .4 40. .9If-U3fljaa a

o coA # A co 40 OD Sf

'0 111111 A 1111

n n

AA L A Aa

-------------------- 5 '55 -S19 4iolA.-~~~~N maa a a aa a ao W..N~S

a-s a a

at n an 9aa- V

V, OII nII a-I

V: 0 99 ,2 99

tl 0 2* ' ~ n

02 9 2 2~ -. f

mm U- C ai*a ,a a

0 1

40 . -

.Sz j a

'n >n~a

cfli

U~j, C-000 000000 c

-i - 0Ca4ar.'

as0 a- 00 00 00 0

't! a- -L

x am w i

0co u' a a.

0 a- 0- x S* AC

a-a.

g On aa.a' a LJ ISt LD 4 a- -4a A

-' aC

a; C; > 3t3

A-6

40 -C -.

rt U, -An0 4,fl 111~ AA0

(D GD D 0) 0IN It It f

y a0 '- . a

.- 0 * 0L

0 "d 0 ) *ft fz it x C

00 Ai -C-: K:CL x -

UD U) I a

att a- ax a S1

cc.A 0 'A 0 -wI

II vi II In IA 1

0 3ft U A t L 3IyL

-A A , Ao AIN

,AN nA) Al A.A l f n n. A

U1~~- a)~ cr 31 ).. * )

A.A a- AD CL.

0~~. ft , .cftf x It z x 0

o ~~ a' a 37 In a ai 'a

aL a 4- a a n f

00

aAU A4

0~I ~ -C A

aa &A %> >>Ia 9.

>. >I > ' L 4 f

-~ U)40 ~, a

A-7

old ~ ~ 0 WEX t

o _. .

a u' I a

0 a CL

4 y 40 v* U. 'A

-a =

a.. - NY (0%Uc

'A )..cc 0a- at

w aa ft4 CLt CL

.JJ laze 41 ~ ~z t 0 CL!I

id ~ a~la,

CCl3 CL a ,S

4A '5a9 '3In 9

u - a.,66

-~ ~~ w. a c n , a

-a4 W M~o fta~aCL 0L-

4 L

Zi *v,* 3-p

9 C4. InN-VqUA

v~ a c'

19 . .a -

a0 it~ 2CL ..- c. 0

o. C

> 0

ao 4A f

,.ft c 0 a t.

c C, a .%

.C cgo~~ C3 Zz

coco

0t6 Ufft a

X,,

cc CL 0k a c A *

A-8

0 a- u

C aa

-- 0 10

j..

v v 0 p0

0 a5

-." c A

~~0a~ UU c

a. >0, u

x 0. 00

Oc a

a a

iA 40 0 (3 .3 (PLO 0 00a t

ff 0

a (%

%A3

-~o 0 .*.. C(31L0OaU q

IN C . 1" -.O 4 . c

I(1 CU-IIU L

0 ~ ~ W * P3

(A a aC,

0 0* - d

0 Iwo

a 4A

CL 0-

-0 aL

b1 a

0 0 .0a C

- V -;. 3 u.

0. a a.5 -1

&IA'- a'cr Iio.

Dj, a

a 0. -Db Va.. - C . P~~ L a ,a -C- -

.. we-a 2 b

*ca @0 . 0.

(&A

* , .- z- W,.6 -.5 . .ii-. C.. .4 O C

,c0 C%3 *

A31

I"

a~ to

a. -

* L

0 0 * 0 1

"00

ft- I..

.n.'A',

00

cz cz

4A 04

CV C,,

*C b

.- !-.t

CL a&~

C, .C ,odao

*-, -2 T .. 64

8= -Or c2 e0~C 0t o vac .

cc L 0 *@ Caa C

a, or

%; 0 10 4

2c . '0 0.I.6

0S OA

0 2c4

2 f~t * C -Lt.

q. ; L

i.; ix . Ift ft In

0 cc - Cc!.--.C

A-10

'A a'V,. w a

ft

AAA l-, U, SV SS

c -0 0 -i

ft10

VS VU, c, d

0 0

ftc ftN5

0 PO 0 a1

9 - Oft :5-~~~.

u05 I0 V

aU ;,g -'

ovicct m

ISS.

5-5 1.3*

on

..-

ft - f o

CL o

-- US

!r 0,

4 0 %A0c

r Ca,

A-1

0 -w

IrJ

CD In c vic 01

> c

IA, Ce'C - C. S £

u 3k

u U.4 3, > 10 0

. C. C9 >31

1 00

0U - 0 U

'U. M35- io32 -00

C.I

cc -i 2

~II I

0 '50 0 CL Q'

C&-

o 0 ~ 0g

1* C.0

'Z D - ft -! nt4 ,- '6 4

Lo V. Cc %A IAIdU - ' _-- 2

a o *uc 0

N~ 'A

- 0-2 (A

0.

C.C>

C%

ic L 'Ac* > 2.

30 0 I6

~ A 012

'~ C 0 li ,; 8

"aS

1010

-t .1 .~ * I A

xo £0

U Pq

a 0

az dý CD

14 %A

000U a 4

0 40

a 0 10d

1C,0 10

a a0

N U'

0

o Uw

IN-j .-- l

4A up

u 3t C-

A-1

a a

cu .4 C

wD . z 0v.u -. :a

a C

in'

440ii~I

f,

o 1*i0.c~

&4 > 4

o 4

a i

A ' cf 4> **o CI a >

4.

A4a

o m

0 c 0 0 -

ac . 0-i --

<< > V

ImI

Nt

mm

"0

LA .

oo

,-,o

A-4

0 0

N X~

0 -..

a!IL2W

o 44

-A 15

(A a .aC, 0

tt b

C. 4

o~ ~ b 0. a-v c - u *' .-U c. jn

C 3 CL ou.0 - -a.L 00 -s - e

C o- of80 aoM2oC- V O a 0" v. *>.! *.SIool

g~oi -abcc -,

!0 bc* %A . tC A

L.N if,; !:5 i

""I w in

ft -i >

N 00

%A 1z4

a

in f

4A

0 10 0 01 r0

C,,b f

an ioI

cc4 Ci

9 It

a 8A-1

c a?

C U _

9; 0 C

N x . C-

CL a C'. '. 4L CL CL

I C CC

* ~ =5 L** .2

a9 ora a .

CL CL 0L a

10 c * .. 00 0a u4

IA u

ar C9, Cc 9

C'.ýCL

C,4

N C

a;; Us c C-

C9 ax -W 6

cea E 0.6,

4l 0. ;;.o

-c c

CA, luOa imb CL3.

s W. C C

0 b0

CO~A 17 & u

f: ( .1 cr. -

a Q 0 .S.,at 4A

ft ft.~ ft ftI.

%At 0t 0 at ~f f*

-0

0

ft'a Ila ft0 0

-A 1

C0 at

w. 0 , C

Ix ofC a'

at 0 ~ .4 4: (A. f t ~3 5 -(] ý 3 3 3 0 t Ct. C3

a ~t 0

S IZ

9 CL

Cac

-a

0 a - SO M- -0 0 -

A-1

0 00

Ur z IU

-*00~

0x

A~ 'ASH0 0

00100 mXII 0000 xIII

-229 22 2 929 Z- 0900

*r %1 . % v Is

c, 6% C CC

UU'

-C I- >4 >4

0

4,4 1 E-

0 0 4 4 * 4 % >

x ' 4

LD x'N 3t>13

c 4i

'N .

A-20

x xx x -z xlix

*0000 *000

04UZ' -C,

0 0 C3 x x z In

C, ~ ~ a 0. ,g -l

C,

0Ig)-S

aM

0.*C%

IA %0 WU BEU

u 4. 4< .aI-I1

(.1' -. 1 1 iiW Ii li 4 '-2 4 1 * , , '9 au

>> >>>n~m.. x x >>> >I axaC wL,-~Ia

Kn-UU~ 0 0'On'O UN . 0n a

39 a

E I ('Wu6U1

0

IA.2

Sý R

I'

-, R.- .-I .li C

aoo 010 0 0 x4 x

x x X ! 2 4' 4 x x

C.~ ~ ~~ u..C l- .u

4' 44 z 4S444 N0 A0WXX0 % I4

Unv I,

C, 140No

00l

> x>>

S. umTx

>Q9 > I >QQ ZZ >AIIA

U08)VIx

co C% -q 'A>

> !itA An X M 4

< 'A

00043 X x A-200

> >

.0000 * 000_

v~ 0 W1 A

A~~ ~ , . % *- % b

-9 -, "z- -a 99i -

hI !t' U'Ut4AWn -4w I DZ

i i 1 1 I Sm m C4% wine u

ol4141, 4A4

4Ai0 00X I

voI XX

11 Im o* -,

0 N *: :;C- 44 %81 C- Wchf~04 C C WCCW W O 4nn~.%C C 1CCx- *x

m~~~ ? ~ u 00 aa' 0 Bc

4A -cA - o i 4

-D x -o

o -

4-l

oc 0

-A-2

- *0000 * 000

(WWLAS

A- 'A us L- w 0 9- 2- %A 0 V$

444 9494oaoa Voo 6W K

v~22 n mm~~~AI cc I'O ,f ,C

1ý -Pill 'Til 19 1In

*00 C.. 6 .-

11 -. C

W IA U

4 an.0 9.0: u)4Aau3A o

-A-2

U' :0~~000UII

0 to. -

( 9:; 1 yAS

1ISSIYAS

-9999 . 0009 ýA LJU 3999>

-929 z''U rn Q92 9z U' U 9

1 1A

In ~ %A~ 4A44 44 %n.- 5

N 444C% 44 'oU ftn ON

0C

Ina

0 0 09~v 4AW4 0aC

0%mC4n'

v 0q

'c5 ! .

-A-2

-, .0000 * 000

00 0,c tI

S 05-~ - C -I

H " C4 In ft 'u 'u 14

27 CA w a W A at 0v n% 'A C

ydUU d

(9'D

acaC

C4 u ILI

IMPa U' U00 0 v n- 9z V 1A

3n

N NC M

li ~Id) 4 1a 'AI a4 4 444i

b >

A-26

10 106 aO-110f.%C~r.N C

In to*01140 w, 4A .4 l ,V

N N qC 4 2 l

IV -u J, 0 N nC

4. u. CA V. M. w l -, r, l

46 UI Ul

w 'nC4 (N N NN

Ul

a

- I

v VC.1 to IIC ý46.' mAO A0 cCW . fc ý

C4 d

om V1 A W V V1 7

4 4

Z3~ ~ ~ n 4, -Q u 00000I

vi J A 92.; %A 0 0

r ft

Ci I

00a

N R~

co ar

>) 44 >44

5,, 0A 28

u OZ

u> u 0 * U44 4% z--~. -z

a a z a xII032~40

SCA Sd xN s

WAH 6,04 CHO E U ~ ~~ ,4Z~

94 AH VLd ,'0-D0

91 AN rt C-H00V6L AN CINl r 0 f

FZ ýA~rIV 1-0

9VAHi CID . 0

IV A Lii CD

O(-6VAN CIO D C

91-AN &INVI I AN tI N JCLAN £150 V-00

6LAH C ia . 04

*VAN CDV U03IVAme liv 30

-- F AH C t30 Ot

PVAlN 1 9-30o

1-30

PEAN O 6- 3004

V5 T ANl I d r30 7j->__EC Al 1N O-0 C0 )

I rAN CIn L300

itMA ViI 1-30 " . .

9cA1 vi VOO009C1 & COOr 0 H S_

6C-A1 CID 9-o

6- L A-1 ~I t: L60-

I I -Al OLD C-80C

*.6 _71 Ai 0 L -N 00

T CCAl C6O U00 b0

E3~ PlO u0

W-Al ItSw8

r- Al I 0VOw

9 i-I So 9 80* U P9 1 gr 99o

-Al £0 V .t

c" 1 H C-va

*w w. I , T

4~~ 0~ u0Cv

IE~* C K, A,4 4 4,444

0. 2ao --.1 .3L)u 0 U44O~ wo, 0 li 0

* 4 ~~~~~~~~-29'~n 4r444' li O

0 a,

>.1

- 01 ft0 -0- - - - -

* In

iIn

UD- Qn C', ft ft.~~ !S Cf

CL >

2 4 m~ W3 an C% n

In~~ ar a a L

-C -C_ __ _ IA. aaaC

ort

* 4 0

* a. Li

A-30

0 0

0 0

4 4 4w co ca 0 oMW0CD aI n

- 0 f

a R

*IN M V

vi .2 I 14 a aN* ~ ~ < 4,uba-a,

4

IA00000000 0 00000000 .4

CL - j C)

10

In "at w u

a I 4-S

0 It -K .A-3 o

0

cc,0 Q

000

Ii ft a w a a

:I d SJ d

: n, I ac

coo cc L- E -

0 CD

- c 00W a,0 u mm m m

O2 cc (A

x8 -180 .)OQmW>aaa

00 0 0 0 0044~ N 44v444w4

C'C.r0.CC cc ;- N-n,,- -Do ei- ---

A-3

w c -,n 93

TA

cr L) q OD

to

cc

OD ir

co Cý

tn

lk0

0 - 10- 0 co

ISO

3t 4, ftN C3

'a ev 0

ctc voQD -0 ft

'A

'n <iA

Cý cr-0 0

crcr

0 0 F b cec

S3b

cc

me-ft, S Itte foON 40!Cc

00

v

SS,

v

14

ID u

t Ax (A

: bT,.T

coo

of 'A'ntee

b At z -6 w -CIt! ". ft v

v ", " , I = g owt '. ,* . t. N 'o,blo ý 0 E- -

"Cts

CUAj u w -1

C, d

Q3 0

10

or 0

LDcx

A-33

0 2 120n0cl0001 0

A~ 10 '

:.1~ 00U

-C 14 . W "'

0. a,. Itq, 3

00

C3 a

VI I

c m W O I 4c o0 1 G 34 wo ' O 1 0-0 u' w 4

-m 44 4 4U 1 " 444444440v5C%

Cd,,

F I

C3 -n

a; 0;a c 0

C U 01

-A-3

000 000 8 co i0 0 00 0II.-~~LIw,~ - ,NIIIOei4(*(~~fON00--IiI1 0 .I-rI.eI

***I''e'' ~ ~ ~ ~ U (NI (S N e0,',I

*~~~ x (N0fl(

444

A 000 0 0 ca in4 wI OC D9 %

in00 0 lo0000 we .101 .

0

0 0D

vn InwI a4-I:

- OD

000O C300 0 0 0 C, 000c 000 ,-ewa o0~a a Q 0 N 0 -- 0 cmC'cC:E~~ a4o.

0 C.e-00 ~ (NN a ( NO

- okN - ~* 0%

o smso CO)C, ccc 0a 0c ýa ý02 N40U09 , eneC

'he00 V4 - 00

00000000 ~0000~0

clN -

leS . 0 e3

$ 00

T. 'E C

A-35

a. -, X. X I

0 0 0 0 .) 7

.' 0

C4 In 40 v M n

on ~ ~ 00 Wl 10 0 0

w" ~ ~ ~ ~ ~ .o -- 0?, 00 'a, ,7wv A m '

-c - ) -, ) -- - -zi

0A-3

0 0. V0 . :

d91 65 I '.":

aJIe a 0ji: oil a

pra C3 CL

O~flmgD ojnns93

0A~vLO: ainiS O.nIgta :

Ot dV33 9C dV3 dVO3

Fý-2

9 dV73: PC dWD: Ow dyD:

I dV:)A

zz

ojn 0.193 ointe:) O34993

9 dVDI

Oizi anis OZ Oi ODV199 s;

'I dVa.I

I~dVr LrdV1

CinIS ajnISnl OJA953

O dV Sc~do3 PrdV:)CdO

I dWY)J

naD aa am5 2 - 2 o2Oýi9D

O~nLS o~ne~ ~' OA-37

Appendix B

TEST SOFTWARE

B-1

1 - ib.h - HEADER FILE FOR DISPLAY MODULE PROGRAMS

/* FILE: /home/white/symanaki/iwarp/documents/report/ib.h September 1993

* Header file for Image Board programs

* Author: Jerry Symanski

* The GAD must have bits 8 and 9 set to address CTLA = 0x060.1 15 14 13 12 1 11 10 9 8 1 7 6 5 4 1 3 2 1 0 1

*GAD 1 0 0 0 0 1 0 0 1 1 1 0 00 0 1 0 x x x I GAD ignores x bits* l\ / \ -------- / I 0x0060 - GAD address*PTR 1 0 0 0 0 1 0 0 1 1 1 00 00 0 1 0 0 0 0 1 0Bx30 - Byte address* \/

/* VRAM pixels: 24bpp-1048576 - 16bpp=524288 - 8bpp=262144 */#include <stdio.h>#include <iwsys/getcfg. h>#include <regnums.h> /* Harish Nag */#include <asm/gen asm.h> /* Harish Nag */#include <ksupp/blink.h> /* To control the QCB LEDs */#include <ksupp/cs.h>#include <ksupp/event.h>static int *PMWR = (int *)0x2000000; /* Function 8h=l000b - PM RW AB FAST WRITE */static int *FCSW = (int *)0x2400000; /* Function 9hfl00lb - FAST CS WRITEstatic int *PM•D = (int *)0x2800000; /* Function Ah=1010b - PM RN AB FAST READ */static int *FCSR = (int *)0x2c00000; /* Function Bh=101lb - FAST READ: Not used */

static int *VRAM = (int *)0x3000000; /* Function Ch=101lb - VRAM base address */

static int *G364 = (int *)0x3400000; /* Function Dh=101lb - G364 base address */

static int *CSRG = (int *)0x3800000; /* Function Eh101lb - Slow Control read */

static int *RESET = (int *)Ox3cOOOOO; /* Function Fh=1011b - Software RESET */static int *HALF SYNC = (int *)0x3400108; /* GAD 0x021 - SET TO: 15 */

static int *BACKi7PRCH = (int *)0x3400110; /* GAD 0x022 - SET TO: 50 */

static int *DISPLAY = (int *)0x3400118; /* GAD 0x023 - SET TO: 256 */static int *SHRT DISP - (int *)0x3400120; /* GAD 0x024 - SET TO: 87 */

static int *BROAD PLS = (int *)0x3400128; /* GAD 0x025 - SET TO: 164 */static int *V SYNC = (int *)0x3400130; /* GAD 0x026 - SET TO: 6 */static int *V PRE EQ = (int *)Ox3400138; /* GAD 0x027 - SET TO: 2 */

static int *V POST_EQ = (int *)0x3400140; /* GAD 0x028 - SET TO: 2 */

static int *V BLANK = (nt *)0x3400148; /* GAD 0x029 - SET TO: 56 */

static int *VDISPLAY - (int *)0x3400150; /* GAD OxO2A - SET TO: 2048 */static int *LINE TIME = (int *)0x3400158; /* GAD OxO2B - SET TO: 352 */

static int *LINESTRT = (int *)0x3400160; /* GAD 0x02C - SET TO: 0 *1

static int *ME4 iNIT = (int *)0x3400168; /* GAD OxO2D - SET TO: 2000 */

static int *TRAN DLAY = (int *)0x3400170; /* GAD OxO2E - SET TO: 48 */static int *MASKHEG - (int *)0x3400200; /* GAD 0x040 - SET TO: ff ffff */static int *MREG = (int *)0x3400200; /* GAD 0x040 - SET TO: ff ffff */static int *CTLA = (int *)0x3400300; /* GAD OxO6O - SET TO: 3C 3011 */

static int *CTLB = (int *)0x3400380; /* GAD 0x070 - SET TO: FFFF FFFF */static int *CURSORPOSITION = (int *)0x3400638; /* GAD Oxc7 - Variable: +/- 4K */

static int *CURSORPALETTE = (int *)0x3400508; /* GAD 0x0Al to A3: 3 x 24-bpp lut */static int *CLUT ffi (int *)0x3400800; /* GAD Oxl00 TO Oxlff: Color LUT*/static int *CURSORSTORE = (int *)0x3401000; /* GAD 0x200 to 3ff - 512 x 16 bits *//* COPY NEXT TEREE LINES TO ALL PROGRAMS TO INITIALIZE LMSIZE

AND LOAD A NOP PARITY HANDLER *//*

ENABLE IMAGE BOARDO; Initialize LMSIZE - Load NOP parity handler - No event reportDISABLE_PARITY(;

B-3

DISABLEEVENTJPPTO*//* FUNCTION: DISABLE EVENT RPT - Turn off bit 31 in event report enable register */void DISABLEEVENTRPT (){register int eventr; /* XXX */

/* turn off bit 31 in event report enable register */eventr - asmreadcsreg(CSREVENTR); /* XXX */asmwritecareg(CSREVENTR, (eventr & Ox7FFFFFFF)); /* XXX */

S/* EiND OF DISABLE EVENTRPT *//* FUNCTION: ENABLEIMAGE BOARD - Write L4_SIZE register to enable Image board */void ENABLEIMAGEBOARD (){/* The RTS must be lied to in the config file so that it does not write

"* into the Image board VRAM locations or the Image board control register."* The config file specifies only normal fast RAM up to OxO7ffff. This routine"* sets the IN SIZE register enabling the cell with the image board to use"* the high memory locations without causing L eory access errors.

* The least significant byte sets how much memory is available in eight"* steps: bit 0 = 128K words, bit 1 = 256K words, ... bit 7 - 16 Megawords."* All bits are set because we want to use the whole memory space. The image"* board uses the top half of the memory space.* The second byte sets how much FAST memory is available in eight"* steps: bit 0 - 128K words, bit 1 = 256K words, ... bit 7 = 16 Megawords"* Our iwarp has 512 megabytes which is 128 K words.*/

asm writecsreg(CSR LMSIZE, OxOOOOOlff ); /* set LMSIZE to enable image board */} /* end of ENABLEIMAGEBOARD *//* FUNCTION: DISABLE PARITY - This function disables the Im parity event.

"* It should ONLY be called by the cell with the frame buffer."* It disables parity by loading a no-op parity event handler.

* Written by William Shubert of Intel.*/

void DISABLEPARITY(){static unsigned handler[] = {OxOe40005e, /* ldlithz 0x8000,evO */

OxOOaOldde, /* movecsr ev0,eventc */Oxllce0000}; /* retmfe */

unsigned int **xbase;xbase = (unsigned mnt **)asmreadcsreg(CSRXBASE);xbase[31] - handler;xbase[63] = handler;

} /* end of DISABLE PARITY *//* FUNCTION: CLEAR DISPLAY - Write zeroes to all VRAM locations.void CLEARDISPLAY()iint pixel=0, p=0;

for ( p=0; p<1048576; p++ ) /* 24bpp=1048576 - 16bpp=524288 - 8bpp=262144 */

FCSW[O] = Ox00; /* enable G364 - clear bit 2 */VRAM[ p ] - pixel;

} /* end of for p */} /* end of CLEARDISPLAY *//* FUNCTION: LOAD DISPLAY - Write an 8-bit color to all VRAM locations. */void LOADDISPLAY( color )int color;

B-4

int p-0;color - ( color & OxOOff );color - ( ( color << 8 ) I color );color - ( ( color << 16 ) 1 color );for ( p-0; p<10 4 85 7 6; p++ ) /* 24bpp=1048576 - 16bpp=524288 - 8bpp-262144 */

FCSW[0] = Ox00; /* enable G364 - clear bit 2 */VRAM[ p ] - color;I /* end of for p *,

I /* end of CLEAR DISPLAY *//* FUNCTION: RAMP - Write a one raster line ramp for the 1024 pixel display */void RAMP()

unsigned int row, col, pixel=0, start;

for ( row-0; row<4096; row++ )fstart = (row * 256);for (col=0; col,256; col++ )

{pixel - ( col );pixel = ( ( pixel << 8 ) I pixel );pixel = ( ( pixel << 16 ) I pixel );FCSW[0] = Ox00;VRAM[ start + (col)] = pixel;} /* end of col *//* end of row */

} /* end of RAMP *//* FUNCTION: LOAD_24BPP - Setup the G364 for 24 bit-per-pixel display.void LOAD_24BPP ()fint n=0, lut=0, val=0, data=0, k=0;asmwr~tecsreg(CSRLMSIZE, Ox000001ff );/* set LM SIZE register to enable image board */

PESET[O] = 0; /* software reset the IB */for ( n=0; n<50; n++ ) ; /* wait 50 microseconds */FCSW[0] = 0x04; /* RESET the G364 */for ( n=0; n<25; n++ ) ; /* wait 25 microseconds */FCSW[0] = 0x00; /* ENABLE the G364for ( n=0; n<25; n++ ) ; /* wait 25 microseconds */G364[0] = 0x69; /* set PLL - Ox 69 = 90 MHz *Ifor ( n=0; n<40; n++ ) ; /* wait 40 microseconds */CTLA[0] = 0x00000000;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */CTLB[0] = OxOOOOOOOO;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */HALFSYNC[0] = 15;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */BACKPRCE[ 0] = 50;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */DISPLAY [0] = 256;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */SHRT DISP[0] = 87;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */BROADPLSE0] = 164; /* GAD 0x025 - SET TO: 164 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */V SYNC [0] = 6; /* GAD 0xO26 - SET TO: 6*1for ( n=O; n<10; n++ ) ; /* wait 10 microseconds */

V PREEQ [0] = 2; /* GAD 0x027 - SET TO: 2*1

B-5

for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V_POSTEQ(0] = 2; /* GAD 0x028 - SET TO: 2 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V BLANK [0] - 56; /* GAD 0x029 - SET TO: 56*/for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VDISPLAY[O] - 2048; /* GAD OxO2A - SET TO: 2048 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */LINETIME[0] = 352; /* GAD OxO2B - SET TO: 352 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */LINESTRT[01 - 0; /* GAD OxO2C - SET TO: 0 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */MM INIT [0] - 480; /* GAD OxO2D - SET TO: 2000 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */TRANDLAY[0J = 32; /* GAD OxO2E - SET TO: 48 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */MASK BEG (0] - Ox00ffffff; /* GAD 0x02E - SET TO: OOffffff */for ( n-0; n<10; n++ ) ; /* wait ie microseconds */CTLA[0] - OxOOec3Ol1; /* bc30ll=8bpp - ec30ll=24bpp *1

/* See the Inmos IMS G364 colour video controller manual, page 42, for* complete information on the use of the control register.* The "ec 3011" sets up 24 bit per pixel mode, cursor disabled.* IIli--- Bit 0 enables the display.* ---- . Plain composite sync - composite video + sync - no blank pedestal.

11 I.----- Blanking.*I .------ Non-interlace increment is 1024. The "3" must be used because

* Iof an error in the design. The G364 address lines are incorrect* Iand the VRAM address increment must be 1024 instead of 512, which* Iis the VRAM row size. ( See page 24 of the Inmos manual. )* ------- The "c" selects interleaved mode and enables delayed sampling.* -------- The "e" selects 24 bits per pixel and disables the cursor.*/

for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */for ( lut=0; lut<512; lut=lut+2 )

{ /* inc by 2 since LUT is lower int only */val = (lut>>l); /* divide by 2 since lut is double */data = ( (val<<16) I (val<<8) I val );CLUT[ lut ] = data; /* load through lut */for ( k=0; k<5; k++}/* end of for lut */

}/* end of LOAD 24BPP *1/* FUNCTION: LOAD 16BPP - Setup the G364 for 16 bit-per-pixel display */void LOADl 6BPP(){int a=0, lut=0, val=0, data=0, k=0;asm.-iritecsreg(CSRLMSIZE, OxO0000lff );/* ..e: LM SIZE register to enable image board */

RESET[O] = 0; /* software reset the IB */for ( n=0; n<50; n++ ) ; /* wait 50 microseconds */FCSW[0] = 0x04; /* RESET the G364for ( n-0; n<25; n++ ) ; /* wait 25 microseconds */FCSW[0] = Ox00; /* ENABLE the G364for ( n-0; n<25; n++ ) ; /* wait 25 microseconds */G364(0] - 0x69; /* set PLL - 0x 69 = 90 MHz */for ( n=0; n<40; n++ ) ; /* wait 40 microseconds */CTLA[0] = OxOOOOOOOO;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */CTLB[0] = OxOOOOOOOO;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */

B-6

HALF..SYnC(0 o 15;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */BACKPW [0] - 50;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */DISPLAY [0] - 256;

for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */SHRT DISP[0] - 87;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */BROADPLS[0] - 164; /* GAD 0x025 - SET TO: 164 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V SYNC 10] = 6; /*GAD 0x026 - SET TO: 6*/for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V PREEQ (0] = 2; /* GAD 0x027 - SET TO: 2 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VPOST_EQ[0] = 2; /* GAD 0x028 - SET TO: 2 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V BLANK (0] = 56; /* GAD 0x029 - SET TO: 56 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VDISPLAY[0] = 2048; /* GAD OxO2A - SET TO: 2048 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */LINETIMEC0] = 352; /* GAD OxO2B - SET TO: 352 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */LINE STRT[0] = 0; /* GAD OxO2C - SET TO: 0 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */NEM INIT [0] = 992; /* GAD OxO2D - SET TO: 992 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds *1TRANDLAY(0] = 32; /* GAD OxO2E - SET TO: 32 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */MASK REG [0] = Ox0Offffff; /* GAD OxO2E - SET TO: O0ffffff */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */CTLA[0] = OxOOdc3Oll; /* bc30ll=8bpp - dc30ll=l6bpp - ec30ll=24bpp */

/* bit 23=1 to DISABLE the cursor */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */for ( lut=0; lut<512; lut=lut+2 )

/* inc by 2 since LUT is lower int only */val = (lut>>l); /* divide by 2 since lut is double */data = ( (val<<16) ( val<<8) I val );CLUT[ lut I = data; /* load through lut */for ( k=0; k<5; k÷+ ) ;}/* end of for lut */

}/* end of LOAD_16BPP *//* FUNCTION: LOAD_8BPP - Setup the G364 for 8 bit-per-pixel display. */void LOAD_8BPP(){int n=0, lut=0, val=0, data=0, k=0;asmwritecsreg(CSR_IMSIZE, OxO0000lff );/* set LM SIZE register to enable image board */

RESET[0] = 0; /* software reset the IB *1for ( n=0; n<50; n++ ) ; /* wait 50 microseconds */FCSW[0] = 0x04; /* RESET the G364for ( n=0; n<25; n++ ) ; /* wait 25 microseconds */FCSW[0] = OxOO; /* ENABLE the G364for ( n=0; n<25; n++ ) ; /* wait 25 microseconds */G364[0] = 0x69; /* set PLL - Ox 69 = 90M•z *Mfor ( n=0; n<40; n++ ) ; /* wait 40 microseconds */CTLA[0] = OxOOOOOOOO;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */CTLB[0] = OxOOOOOOOO;for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */

B-7

HALFSYT(0] - 15;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */BACK•_PCH(0] - 50;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */DISPLAY [0] - 256;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */SERT_DISP[0] - 87;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds *1BROADPLS[0] - 164; /* GAD 0x025 - SET TO: 164 */

for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V SYNC [0] - 6; /* GAD 0xO26 - SET TO: 6*1for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VPREEQ [0] - 2; /* GAD 0x027 - SET TO: 2*for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V_POSTEQ[0] - 2; /* GAD 0x028 - SET TO: 2 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V BLANK [0] - 56; /* GAD 0x029 - SET TO: 56*/for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V DISPLAY[0]- 2048; /* GAD OxO2A - SET TO: 2048 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */LINETIME[0] - 352; /* GAD 0x02B - SET TO: 352 */

for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */LINESTRT[0] - 0; /* GAD 0x02C - SET TO: 0 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */ME4 INIT (0] = 2000; /* GAD OxO2D - SET TO: 2000 */

for ( n=-; n<10; n++ ) ; /* wait 10 microseconds */TRANDLAY[0] = 48; /* GAD 0x02E - SET TO: 48 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */MASK PEG [0] = OxOOffffff; /* GAD OxO2E - SET TO: O0ffffff */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */CTLA[0] = OxOObc3Oll; /* bc3011=bpp - dc30ll=l6bpp - ec3011=24bpp */

/* bit 23=1 to DISABLE the cursor */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */for ( lut=0; lut<512; lut=lut+2 )

{ /* inc by 2 since LUT is lower int only *1val - (lut>>l); /* divide by 2 since lut is double */data = ( (val<<16) I (val<<8) I val );CLUT( lut ] = data; /* load through lut */for ( k=0; k<5; k++ ) ;}/* end of for lift */

}/* end of LOAD_8BPP *//* FUNCTION: LOAD 4BPP - Setup the G364 for 8 bit-per-pixel display. */void LOAD_4BPP()

{int n=0, lut=0, val-0, data=0, k=O;asmwritecsreg(CSR_IMSIZE, Ox0000lff );/* set LM SIZE register to enable image board */

RESET[OI = 0; /* software reset the IB */for ( n=0; n<50; n++ ) ; /* wait 50 microseconds */FCSW[0] = 0x04; /* RESET the G364for ( n-0; n<25; n++ ) ; /* wait 25 microseconds *1FCSW[0] = Ox00; /* ENABLE the G364 */for ( n-0; n<25; n++ ) ; /* wait 25 microseconds */G364[0] = 0x69; /* set PLL - Ox 69 = 90 MHz /for ( n=0; n<40; n++ ) ; /* wait 40 microseconds */CTLA[0] = 0x00000000;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds *1CTLB[O] - 0x00000000;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds *1

B-8

HALF SYNCo ] - 15;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */BACK PRC E0 1 - 50;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */DISPLAY (0] - 256;for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */SERT_DISP1o] = 87;

for ( n-0; n<l0; n++ ) ; /* wait 10 microseconds */BROADPLSE0] - 164; /* GAD 0x025 - SET TO: 164 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V SYNC (0] - 6; /* GAD 0x026 - SET TO: 6*/for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VPR*_EQ (0] - 2; /* GAD 0x027 - SET TO: 2 */

for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */V_POST EQ(0] - 2; /* GAD 0x028 - SET TO: 2 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */

V BLANK [0] - 56; /* GAD 0x029 - SET TO: 56*1for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */VDISPLAY(0] = 2048; /* GAD OxO2A - SET TO: 2048 */

for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */LINE TIME[0] = 352; /* GAD OxO2B - SET TO: 352 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */LINE STRT[0] = 0; /* GAD OxO2C - SET TO: 0 */for ( n-0; n<10; n++ ) ; /* wait 10 microseconds */ME4 INIT (0] = 4048; /* GAD OxO2D - SET TO: 2000 */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */TRAN DLAY[0] = 48; /* GAD OxO2E - SET TO: 48 */

for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */MASK REG [0] - Ox00ffffff; /* GAD OxO2E - SET TO: 00ffffff */for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */CTLA[O] = OxOOac3Oll; /* ac=4bpp - bc=8bpp - dc=16bpp - ec=24bpp */

/* bit 23=1 to DISABLE the cursor */

for ( n=0; n<10; n++ ) ; /* wait 10 microseconds */for ( lut=0; lut<512; lut=lut+2 )

f /* inc by 2 since LUT is lower int only */val = (lut>>l); /* divide by 2 since lut is double */data = ( (val<<16) I (val<<8) I val );CLUT[ lut ] = data; /* load through lut */for ( k=0; k<5; k++}/* end of for lut */

}/* end of LOAD_4BPP *//* FUNCTION: LOAD CECKES - Write a checker board pattern for 24 BPP mode */void LOAD _CHZCMi( red, green, blue )int red, green, blue;

fint pixel=0, p=O;

pixel = ( ( red << 16 ) + (green<<8) + blue ); /* build rgb integer *1for ( p=0; p<1048576; p++ ) /* 24bpp = 1048576 words */

iif ( p%32-0 ) pixel ( pixel A 0x00ffffff ); /* horizontal blocks */if ( p%32 7 68 -=0 ) pixel = ( pixel A 0x00ffffff ); /* vertical blocks */

FCSW[0] = Ox00; /* enable G364 - clear bit 2 */VRAM[ p ] = pixel;} /* end of for p */

1 1* end of LOADCBECKERS *//* FUNCTION: LOADCHECKERS8 - Write a checker board pattern for 8 BPP mode *Ivoid LOAD_ CHECKES8( pixelunsigned int pixel;

B-9

mnt p-0;pixel = ( pixel & OxOOff ); /* build integer with four pixels */pixel - ( ( pixel << 8) I pixel ); /* fill lower two bytes - lower half int *

pixel = ( ( pixel << 16) I pixel ); /* fill upper two bytes - upper half integer */for ( p-O; p<262144; p++ ) /* 24bpp=1048576 - 16bpp=524288 - 8bpp=262144 */

fif ( pt32-=0 ) pixel ( pixel ^ Oxffffffff ); /* horizontal blocks */if ( pt32768=-0 ) pixel C pixel ^ Oxffffffff ); /* vertical blocks */FCSW[0] - Ox00; /* enable G364 - bit 2 */VRAM(p] = pixel;

} /* end of for p */} /* end of LOADCBECKERS8*//* FUNCTION: LOADLUT8 - Load the G364 Color LUT for 8 bit-per-pixel display

"* This color look-up table goes from black to red, yellow, orange, green, blue,"* violet to white in seven sections. It is strictly a mathematical generation."* No physiological basis was used.

"* Note that red is in the least significant byte of the 24 bit LUT word."* Ie., blue-green-red.

*/

void LOADLUT8()

unsigned int red, grn, blue, lut[256], val=0, data=O, lut data[512];int n=0, k=0;

for ( n=0; n<=31; n++ ) /* black at 0 to pure red at 32 */

blue= n * 8 ); grn= 0; red = 0;lut[n] = ( (blue << 16 ) (grn << 8 ) (red));I /* end of first 32 */

for ( n=32; n<=63; n++ ) /* red at 32 to pure yellow at 63 */

iblue = 255; grn= ((8* (n-31 ) ) -1); red =0;lut[n] = ( (blue << 16 ) I (grn << 8 ) I ( red ) );I /* end of first 64 */

for ( n=64; n<=95; n++ ) /* pure yellow at 64 to pure green at 95 */

fblue= (255- (8* (n-64) ) ); grn =255; red =0;lut~n) = ( (blue << 16 ) I grn << 8 ) I C red ) );I /* end of first 96 */

for ( n=96; n<=159; n++ ) /* turquoise at 159 */

Iblue= 0; grn= (255- (4 * (n-96 ) ) );red= ( ( (n-95 ) * 4)- 1);lut[n) = ( (blue << 16) I (grn«8 ) I (red));} /* end of first 160 */

for ( n=160; n<=223; n++ ) /* pure blue at 160 - violet at 223 */

Iblue= ( n- 159) *4 ) 1 ); grn =0; red = 255;lut[n] = ( (blue << 16) (grn«8 ) I (red));} /* end of first 224 */

for ( n=224; n<=255; n++ ) /* violet at 224 - white at 256 */

fblue = 255; grn= ( ( (n-223) *8 ) -1); red =255;lut[n] = ( (blue << 16) I (grn << 8 ) I (red));} /* end of lut */

for ( n=0; n<512; n--n+2 ) /* LOAD CLUT */

/* inc by 2 since LUT is lower int only */

B-10

val - (n>>l); /* divide by 2 since lut is double */data- ((val<<16) I (val<<8) I val );CLUT( n ] - lut[(n>>l)]; /* load through lut h/

for ( k-0; k<5; k++W/h end of for lut */

} /* end of LOAD LUT8 */* FUNCTION: LOADLUT24 - Load the G364 Color LUT for 24 bit-per-pixel display

* This function loads the LUT with a ramp going from 0 to 255. Thus the* three bytes of the 24 bit color integer will be interpreted just as they* are. This is a one-to-one mapping.*/

void LOADLUT24(){unsigned int lut=0, val=O, data=0;int n=0, k-0;

for ( lut-0; lut<512; lut=lut+2 ){ /* inc by 2 since LUT is lower int only h/

val = (lut>>1); /* divide by 2 since lut is double */data- ( (val<<16) I (val<<8) I val );CLUT( lut ] = data; /* load through lut h/

for ( k=O; k<5; k++}/* end of for lut */

} /* end of LOADLUT24 h/

/* FUNCTION: LOAD LUT4 - Load the G364 Color LUT for 8 bit-per-pixel display */void LOADLUT4(){unsigned int red, grn, blue, lut[256], val=0, data=0, lut data[512];int n=0, k=O;

for ( n-0; n<512; n=n+2 ) /* LOAD CLUT */{ /* inc by 2 since LUT is lower int only */val = (n>>l); /* divide by 2 since lut is double */data = ((val<<16) I (val<<8) I val );CLUT[ n ] = lut[(n>>l)]; /* load through lut h/

for ( k=0; k<5; k++ )}/* end of for lut */CLUT[ 0 ] = 0x00000000; /* load the first 16 locations for 4 bpp h/

CLUT[ 2 ] = 0x00800000;CLUT[ 4 1 = 0xO0ff0000;CLUT[ 6 ] = OxOOfffOOO;CLUT[ 8 ] = OxOOffffOO;CLUTt 10 1 = OxOO7fffOO;CLUT[ 12 ] = 0xOOOff0O;CLUT[ 14 1 = Ox00007fOO;CLUTC 16 ] = Ox0000007f;CLUTC 18 ] = OxOOOOOOff;CLUT[ 20 ] = 0x00000080;CLUT( 22 ] = 0x00000040;CLUT( 24 ] = 0x00040040;CLUT[ 26 ] = 0x00800080;CLUT[ 28 J = OxOOffOOff;CLUT[ 30 ] = Ox0Offffff;

/* end of LOAD LUT4 *//* FUNCTION: disablelm parity - Disable the IM parity reporting h/

disablelmyparity (){asmwritecsreg(CSREVENTR, asm_readcsreg(CSREVENTR) & Ox7FFFFFFF);

B

B-if

/* FUNCTION: enable-ln~yarity - Enable the LMi parity reporting ~enable Im~parityo(

asm -writecareg(CSREVENTR, asm readcsreg(CSREVENTR) I Wx0000000);I/* FUNCTION: INIT - B -Do ENABLEIMAGEBOAP.D and DISABLE-PAR.ITY ~void INIT-lBOf

ENABLE IMAGE BOAPD 0;DISABLiPARITY 0;LOADBE3PP();LOADCHECKERS8( 0 )}/* end of INIT-lB ~

B-12

2 - vram.c - TEST VRAM WRITING/* File: -/symanski/iwarp/documents/report/vram.c

* Test the VRAM of the image display board.

* Author: Jerry Symanski with added XXX code by Harish Nag of Intel* History: 8 September 1993

#include "ib.h"#define LOOPS 100000#define LIOD 100main()

int vdata-0, wdata=0, loops=0;int 1-0, i-0, k-0, n=0, errn=0, adr=0;int loc[256], err[256];register int eventr; /* XXX */struct iwcfg cfg;getcfg (&cfg);fprintf(stderr, "vram: Starting in cell %2d - %4d loops:\n", cfg.cellid, LOOPS );fflush(stderr);ENABLEIMAGEBOARD ~DISABLEPARITY(;LOAD_24BPP(;LOAD CHECHRS( 128, 32, 64 );for ( 1=0; 1<256; 1++ ) { loc[1]=0; err[1J-0; } /* clear arrays */for ( loops-0; loops<LOOPS; loops++

{for ( adr-0; adr<1048576; adr++

fwdata = (rand() << ( loops & Oxf ) );VRAM(adr] = wdata; /* WRITE = 450 nanosec */FCSW[0] = 0x08; /* WRITE to CS to setup addresses */vdata = VRAM(adr];FCSW[0] = Ox00; /* WRITE to CS to setup addresses */if ( ( vdata 1= wdata ) && ( errn <=255 ) )

err[errn] = ( wdata );loc[errn] - adr;errn++;I

I /* end of for all adr */if ( loopsIMOD == 0 )

{fprintf(stderr, "vram: Did t4d loops. Errors: %d\n", loops, errn ); fflush(stderr);}/* end of for loops */

fprintf(stderr, "vram is done. Errors: %8d\n", errn ); fflush(stderr);if ( errn>0 )

for ( n=0; n<10; n++printf("Error Number: %8d X: %8x Loc: %8d\n", n, err[n], loc[n]);

exit (0);} /* end of vram ./

B-13

3 - testg3.c - TEST G3%4 VIDEO CONTROLLER

/* File: -symanski /iwarp/ report /testg3. c September 1993

*Test program to read the G364 control registers. Note that the G364 must be*disabled to read the registers.

*Author: Jerry Symanski with Disable of Parity by Bill Shubert of intel*History: 25 Feb 1993

# include "ib.h"maino(

struct iwcfg cfg;mnt gdata-O, n=0;

getcfg (acfg);printf ("testg3: Cell #1d: \n", cfg.cellid )ENABLE_-IMAGEBOARDO0DISABLEPARITY 0;LOAD_-8BPP0; LOADLUT80;LOADCHECKERS8( 64 )gdata - CTLA[0];printf ("CONTROL BEFORE: %6x\n", (gdata & Ox00ffffff) ); I OK *CTLA(01 = 0x00bc3010;for ( n=0; n<10; n++ ) ; /* MUST wait 10 microseconds after messing with VTG *gdata = CTLA(01;for ( n=0; n<10; n++ ) ; /*' MUST wait 10 microseconds after messing with VTG ~printf ("CONTROL AFTER: %6x\n", (gdata & Ox00ffffff) );gdata = HALF SYNC[0]; printf("HSALF SYNC: [ 15] %6d\n", (gdata 8 OxOOOOffff) )gdata = BACK PRCE (0]; printf ("BACK PORCH: 1 50] t6d\n", (gdata & OxOOOOffff) )gdata = DISPLAY[0]; printf ("DISPLAY: ( 256] %6d\n", (gdata & OxOOOOffff) )gdata = SEPTDISP[O]; printf ("SHORTDISPLAY: 1 87] t6d\n", (gdata & OxOOOOffff) )gdata = BROAD_-PLSfO]; printf("BROADPULSE: C 164] t6d\n", (gdata & OxOOOOffff) )gdata = VSYNC[0]; printf("V SYNC: 1 6] %6d\n", (gdata G CxOOO0ffff) )gdata = V PRE -EQ(0]; printf ("V -PRE -EQ: 1 2] %6d\n", (gdata & OxOOOOffff) )gdata = VPOSTEQ(0]; printf ("V POSTEQ: 1 2] lt6d\n", (gdata 8 OxOOOOffff) )gdata = V BLANX[0J; printf("V BLANK: [ 56] t6d\n", (gdata G OxOOOOffff) )gdata = VDISPLAY(0]; printf ("VDISPLAY: E 2048] t6d\n", (gdata & OxOOOOffff) )gdata = LINETIME[O]; printf ("LINETIME: ( 352] %6d\n", (gdata & OxOOOOffff) )gdata = LINESTRT[0]; printf("LINE START: 1 0] t6d\n", (gdata & OxOOOOffff) )gdata = MEM INIT[01; printf("MEK INIT: [2000] t6d\n", (gdata & OxOOOOffff) )gdata = TRAii DLAY[0]; printf ("TRA-NSFERDELAY: ( 48] t6d\n", (gdata 8 OxOOOOffff) )MASKREG[0] : OxOOOOfffff;gdata = MASKREG[0]; printf ("MASKPEG: [ffffff] %O6Xh\n", (gdata & OxOOffffff) )gdata = CTLA[0]; printf ("CONTROL_-A: [BC3Ol1] %O6Xh\n", (gdata 8 OxO~ffffff) )for ( n=O; n<10; n++ ) ; /* MUST wait 10 microseconds after messing with VTG ~CTLB (0] = OxOOOOOOOO;for ( n=0; n<10; n++ ) ; /* MUST wait 10 microseconds after messing with VTG ~gdata = CTLB[01; printf ("CONTROLB: [000000] tO6Xh~n", (gdata 8 OxOOffffff) )CURSORPOSITION(0] = OxOOOOOO;gdata Z CURSORPOSITION[0];printf("CURSORPOSITION:[000000] 't06Xh\n", (gdata 8 Ox00ffffff) )LOADCEECKERSý(- 100 );CTLA[0] - OxO0bc3Oll;for ( n=O; n<10; n++ );/* MUST wait 10 microseconds after messint with VTG ~gdata = CTIA[0];printf ("CONTROL NOW: t6Xh~n", (gdata 8 Ox00ffffff) )

B-14

printf ('testg3 is done. \n');exit (0) ;I /* end 3f testg3For the 8 EPP display:do testg3Loading iwarp with testg3SIB 0 on teal has been locked.testg3 has finished....SIB 0 on teal has been unlocked.testg3: Cell #21:CONTROL BEFORE: bc30llCONTROL AFTER: bc3010HALFSYNC: [ 15] 15BACK POCH: [ 50] 50DISPLAY: [ 256] 256SRORT_DISPLAY: 87] 87BROADPULSE: [ 164] 164V SYNC: [ 6] 6vPEEQ: ( 2] 2VPOST EQ: [ 2] 2V BLANKU: C 56] 56VDISPLAY: [ 2048] 2048LINE TIME: 352] 352LINESTART: 0] 0MEM INIT: [ 2000] 2000TRAMSFERDELAY: C 48] 48MASK PEG: [ffffff] OFFFFFhCONTROL_A: [BC3011] BC3010hCONTROL B: [000000] 000000hCURSOR_POSITION: [000000] 000000hCONTROL NOW: BC3011htestg3 is done.

*/

B-15

4 - maxf5l2.c - TEST EVENT AND PAGE MODE OPERATION

/* File: -symanski/iwarp/documents/report/maxf512 .c

* Test writing a buffer into the center 512x512 window of* the 1024x1024 8 BPP display. This code uses the Serial Access Memory* Transfer(SAMT) event with John Webb's asm copy_64 routine.

"* This program wirtes double words into VRAM at 250 nanoseconds per write."* The efficiency is about 62%. The viewed frames per second is about 60 fps.

* Peak data rate is 32 MBytes per second or 128 512x512 frames/sec.* Efficiency could be improved with a more clever event handler.

* Note that care must be taken to catch every event request. Too long a* write period, will cause some requests to be missed, lowering efficiency.

* Note: Can not do I/O from event handler. 26244

#include "ib.h"#include "asm copy_64.h"#define LOOPS 400000#define FRAMES 8192void vram writeo;struct iwcfg cfg;unsigned int PAGE=32, LINE'=0, FRAME=0, vrampage, now-0, old=0;double *DPMWR = (double *)0x2000000; /* Page mode VRAM base address */double dbuf [1024];static union { double dwd; int wd[2]; } img;main (){unsigned int n=0, j=0, pixel=0, dummwy=0, loop=O, mult=0, pixadr=0;ENABLEIMAGEBOARD O;DISABLE_PARITY();LOAD 8BPP(; LOADLUT8(; /* initialize the graphics chip */LOADCR8EKERSS( 20 ); /* load a checker board to verify operation */LOAD DISPLAY( 100 );img.wd[0]=0xc0c0c0c0; img.wd[1]=0xc0c0c0c0; /* load a double word with color */for ( n=0; n<1024; n++ ) dbuf[n] = ( img.dwd ); /* load dbuf with the color */fprintf(stderr, "Starting maxf5l2: %9d frames.\n", (LOOPS*FRAMES) ); fflush(stderr);/* Install the handler, then enable the event */installhandler (EVENTEXTERNAL, vram-write, 0, EVHLOCALEC);for ( loop=1; loop<LOOPS; loop++){maskevent (CSREVENTR, 1<<EVENTEXTERNAL, 1<<EVENTEXTERNAL); /* enable the event */CSRG[0] = 0x02; /* enable event signal */while ( FRAME<FRAMES

fnow = FRAME;if ( now 1= old

{pixel = ( FRAME & 0x0Off );pixel = ( ( pixel<<24 ) I ( pixel<<16 ) I ( pixel<<8 ) pixel );img.wd[0]-=pixel; img.wd(l ]=pixel;for ( j-0; J<128; j++ ) dbuf[j] = img.dwd;old = now;I

pix_adr = ((FRAME+((loop-l)*FRAMES)) & Ox003ffff );

B-16

VRAM(pix-adr] - Oxffffffff;/* draw comet *1

CSAG10 - 0; /, disable the event signal *//* Disable the event before terminating the program or printing out. */mask event(CSR EVENTR, 1<<EVENTEXTERI4AL, 0); /* disable the event process. */fprintf(stderr, "maxf5l2: 16d frames: loop=%6d \n", (loop*FRAME), loop );fflush(stderr);FRAME - 0;

if ( loop%32-0 ) LOADDISPLAY( loop&0x00ff );I /* end of loop */printf("maxf512 is done. Did 46d frames.\n", (loop*FRAME));exit (0);} /* end of main of maxf512 */£

/* EVENTHANDLER: vramwrite - Respond to Graphics controller signal

* This event handler will write pixels to the Image board VRAM as fast as"* possible. The event will be activated with a period depending on the"* pixel depth. When using 8 bits-per-pixel(bpp), the event will be triggered"* every 128 microseconds by the rise of a 2 microsecond wide signal. When"* the 2 microseconds is finished, the graphics controller will be done"* with the VRAM address bus and the iWarp can take control of the VRAM"* for the next 125 microseconds, writing at the maximum 100 nanosecond"* per 64 bit word rate if possible. For 16 bits-per-pixel, signal"* occurs every 64 microseconds.

* This routine will use the page-mode of writing into the VRAM. le.,"* the VRAM RAS signal will go high only once, at which time it latches"* the row address into the VRAM. Then, writes can be performed for"* approximately the next 120 microseconds, in the 8 bpp mode. If the 100"* nanosecond period cannot be achieved, this routine will have to stop"* writing after 120 microseconds and relinquish control to the graphics"* controller so that new image data can be loaded into the VRAM serial"* register. Unless the graphics controller can get control every 128"* microseconds, the display will be noisy and corrupted.

* The pixels can be transfered from an input buffer dbuf, to the VRAM."* The maximum number of writes is 1024 64 bit words. The Image board"* has two banks of VRAM, each having 512 locations per row. Fewer writes"* are acceptable if the number of writes is saved to that the location"* for the next data to be written is available.

*/

void vram write(ev_num, pctnum, dummy, eventr)int ev_num, pctnum, dummy, *eventr;Iunsigned int col=0, start-0, blk=0;vrampage = ( ( PAGE << 11 ) ); /* generate page address ie., VRAM row */

CSRG[vramjpage] 0x01; /* load page into VRAM with RAS - clear the event bit */start - ( LINE * 128 ); /* compute current raster line to load *//*Because of the write cycle length and the available time between G364 SAMT requests,

when doing lKx1K screens, 128 words = 1024 bytes is written in each LINE.A PAGE in the VRAM contains 2x512=1024 double integers - 8096 bytes.So to write a total of 8096 bytes, there were 8 block writes of 128*8=1024 bytes. Butthese block writes could only be done three at a time to fit inside the 120 microsecondsbetween SAMT requests. The code for a 1024x1024 display does a 3 x 128 double word write,another 3 x 128 double word write and then a 2 x 128 double word write. This results in

B-17

about 20 frames aer second for the 1024x1024 8-bit per pixel display.For the 512x512 display, we can fit four 64 double word writes during each page mode write.This results in writing for approximately 78 microseconds out of the 125 microsecondsavailable for a 62% efficiency. This is is about 60 512x512 frames per second.With more assembly code, efficiency could probably be brought up to 90%, or over 100512x512 frames per second.*/for ( blk-0; blk<4; blk++ )

{copy_words(64, &dbufE0], &DPMWR((blk*128) + start + 32 ], sizeof(double), sizeof(double));LINE - LINE + 1;if ( LINE = 8 ) { LINE = 0; PAGE - PAGE + 1; goto DONE; ) /* no 9th LINE */I

DONE:FCSW[O] - 0x02; /* clr PM bit - enable event */if ( PAGE>96 ) { PAGE-32; FRAME++; I /* check for frame done */asmwritecsreg(CSREVENTC, 1<<EVENT EXTERNAL); /* Disable the event */

}/* end of vram write */

B-18

5 - master.c, frame.c, frame.ad, fastio.h - TEST ADAPT USE OF THE DISPLAYMODULE

/* FILE: -symanski/iwarp/documents/report/master.c.add one_bw

Uses stdin0O64 for 512x512 image.

master.c from Jon Webb with additions by Symanski to drive the Sony monitor.

* This program writes frames at about 18 FPS to a 512x512 window centered* in the the lkxlk screen. It uses the ib_receivewords which does a single* word write to FCSW to guarantee an addressing transition. Writes take* about 650 nanoseconds each.

*/:1#include <stdio.h>#include <netcode.h>#define HEIGHT 512#define WIDTH 512#define MAXSIZE 4096#define IMGSIZE 262144#define FRAMES 1000000#define PCSERROR I fprintf(stderr, "PCS Error in file %s line %d\n", _-FILE_, __LINE_);\

pcs_fatal(NULL);main()fint imgid, res_id, frame;char imgqbufr[IMGSIZE];FILE * inputimage;

fprintf(stderr, "master.c.add onebw: \nStarting initialization\n"); fflush(stderr);InitializeAdapt (;fprintf (stderr, "Finished initialization\n"); fflush(stddrr);read input(0, imq_bufr, IMGSIZE );fprintf(stderr, "Read image\n");img id = ad allocateimage(HEIGHT, WIDTH, sizeof (unsigned char));res id = adallocate_image (HEIGHT, WIDTH, sizeof (unsigned char));fprýintf(stderr, "Allocated image\n");ad distribute image( imgbufr, HEIGHT, WIDTH, sizeof(char), res id );for (frame = 0;frame<FRAMES; ++frame)

addclb( resid, 1, res id, HEIGHT, WIDTH );adcollect imageport (outO, res id);I

fprintf(stderr,"master.c.add one bw is done.. .%3d\n", frame); fflush(stderr);TerminateAdapt 0;exit (0);

/* FUNCTION: read input -- Read from stdin to the SIB - cell 64 1read input(fd, buffer, nbytes)

int fd;char *buffer;int nbytes;

int nread;while((nread = read(fd, buffer, nbytes)) < nbytes)if (nread = 0) {

fprintf(stderr, "Premature EOF on read!!\n");return (-1);

B-19

buffer +=nread;nbytes -=nread;

return (0);

/* FUNCTION: write-output -- Write to stdout to the SIB =cell 64 'write-output(fd, buffer, nbytes)

int fd;char *buffer;int nbytes;

while (nbytes>NAXSIZE)

if (write(fd, buffer, MAXSIZE) != MAXSIZE)

fprintf (stderr, "Couldn't complete write! \n");return (-1);

Iif wrtesfd buffIernye); bts

I

fprintf(stderr, "Couldn't complete write!\n");return (-1);I

return (0);

B-20

/ * FILE: -symanski/iwarp/documenta/report/frame. c. addone_bw

* Uses stdin0064 for 512x512 image.

* frame.c from Jon Webb with additions by Symanski to drive the Sony monitor.

* This program writes frames at about 18 FPS to a 512x512 window centered* in the the lkxlk screen. It uses the ib receivewords which does a single* word write to FCSW to guarantee an addressing transition. Writes take* about 650 nanoseconds each.

*/

#include <stdio.h>#include <asm/gen_asm. h>#include <asm/pw_asm.h>#include <pcs/pcs def.h>#include <iwsys/getcfg.h>#include <netcode.h>#include <espl.h>#include <malloc.h>#include <fastio.h>#include <pcs/pcstime.h>#include "ib.h" /* symanski's image board library file */

#define HEIGHT 512#define WIDTH 512#define FRAMES 1000000#define PCS ERROR { fprintf(stderr, "PCS Error in file %s line %d\n", \__FILE _,_ LINE__); pcsfatal (NULL); }main()

int check, line, offset;char *image = (char *) malloc(HEIGHT * WIDTH * sizeof(unsigned char));int inport, frame=0, adr=0;

ENABLEIMAGEBOARD(; /* initialize image board */DISABLEPARITYO; /* load null parity handler */LOADf_8BPP(; /P setup graphics chip - grey LUT 4/COLORDISPLAY8 (200);/*RAMP(); display a ramp pattern 4//PLOAD LUT8); load spectrum LUT 4//*LOADCHECKERS8( 255 ); display a checker pattern 4/offset = (256 * 256) + 63;

pcs_init(ports, NUMPORTS(ports), NULL, 0);bind_systolicgate(ino, GATEO);in_port = esplcbindreceiveport (inO);fprintf(stderr, "frame.c.addone bw: \nStarting frames\n"); fflush(stderr);for (frame=0; frame<FRAMES; frame++)

{if (!receive_openmsg(inO, GATEO)) PCSERROR;for ( line=0; line<512; line++

adr = (line * 256);ibreceivewords( 128, &VRAM[adr + offset ], FCSW ); /4 single write only 4/I

FCSW[0] = OxO8; /P Turn LED on - Used to check hang point */if (!receiveclosemsg(inO, GATEO)) PCSERROR;if ( frame%1000 == 0) fprintf(stderr, "Frame: %6d\n", frame); fflush(stderr);I

fprintf(stderr, "frame.c.add one bw is done... %d\n", frame ); fflush(stderr);exit (0);

B-21

-- FILE: - symanski / iwarp/document s/report/ f tame. ad. addonebw

This file must contain ALL adapt functions used in maater.c

procedure addclb(imagel in image byte,constant : in integer,image2 : out image byte)

isnext begin

image2 :- imagel + constant;end next;end addclb;procedure setvalues( im: out image byte,

val : in integerisnext begin

im :- val;end next;end setvalues;-- add this to test for no frame call

-- add one.ad -- do simple operation on a byte-- image (put this in the addone.ad file)procedure addone (img in : in image byte,

img_out : out image byteIsFIRST BEGIN -- no initialization

END FIRST;NEXT BEGIN -- add one to each pixel

img_out := imgin + 64; -- add 1 to pixelEND NEXT;COMBINE BEGIN -- combine image

img~out := img~out + _mmgout;END COMBINE;END addone;-- scroll function from Jon Webb - 12 Aug 1993

procedure scrollleft(inimg : in image array(-1.. 1,-4..4) of byte border 128,outimg out image byte)

isnext begin

outimg := inimg(O, 4); -- outimg has the pixel from one column to the RIGHTend next; -- so the image moves LEFTend scrollleft;-- scroll_up function from Jon Webb - 12 Aug 1993-- Modified to scroll down by symanski

procedure scrolldown(inimg : in image array(-1..1,-1..1) of byte border 128,outimg: out image byte)

isnext begin

outimg :- inimg(-1,0); -- outimg has the pixel from one row BELOW the inputend next; -- so the image moves downend scroll-down;

-- load image from one buffer to another

procedure loadimg(imag : in image byte,

B-22

constant : in integer,image2 : out image byte)

isnext begin

image2 :- imagel + constant;end next;end loadimg;

B-23

/* FILE: -symanski /iwarp/ documienta/ report/ fast io. h. add-one-by

*various assembly code functions for adapt.

#define BEGINCAf#define ENDCAIP* This works but is a single word write -

Note st.f cnt, (b) line to write to CS req ~asm void ib -receive-worda(n~a,b) {% tmpreq n,a,b,cnt; use gaO; lab less4, again, finish;

clr ontCmp cnt,nbrif ilu. zero, finish. beginloop .LOOP.cOO5 12loop n.c186_-loop_okayst.f cnt,(b)

el st. f qaO, (a, 4) +=* end~loop LOOP

finish:nop

Iasm, void copy_words (n, r, w){It tmpreg n,r,w,cnt; use gaO,lmO~lml,1m2,1m3,1~m4; lab extra~finish;

dlr ontamp cnt, nbrif ilu. zero, finishsub l,nld (r, 4)+=lmwId (r, 4)+=lmrl* beginloop LOOP.C005 16loop n.c186_-loop_okay

el BEGINCA fmova lxnrl, lmw; ld (r, 4) =lmrl; st lmw, (w, 4) += ENDCA.endloop *LOOP18t lmw, (w, 4) +=st lmrl,(w,4)+=

finish:nop

Iasm. void copy-for transpose (m, n, r,incrl, incr2, w, incwl, incw2) f

-t tmpreg m,r,w,da; register n,incrl,incr2,incwl,incw2; use 1mO,lml,1m.2,1m3,1m4; lab loopi,finish;loop1 :

* beginloop LOOPloop n

ld.b (r,incr2)+=,del st.b d,(w,incw2)+=

* endloop LOOPadd incrl,radd incwl,w

flags sub 1,m.brifn ilu. zero, loopl

asm. void copy_:words -for-transpose(m,ri,r, incrl,incr2,w, incwl, inCW2){% tmpreg m,r,w,d; register n,incri,incr2,incw1,incw2; use lmO,Iml,1m2,1m,3,1m4; lab loopi,

B-24

finish;loopi:

.beqinloop .Looploop n

ld (r, incr2) +-, del at d, (w, incw2) +=

.endloop .LOOPadd incrl,radd incwl,w

flags sub l,mbrifn ilu. zero, loopi

asm void pass words (n)It tiupreg n,cflt-; use gao; lab less4, again, finish;

clr ontcmp Cflt,ribrif ilu. zero, finish.beginloop .LOOP.c005 8loop ni.c186_loop_opkay

el movereg gaO,gaO* endloop LOOP

finish:flop

asm void receive words(n,a){% tmpreg n,a,cnt; use gao; lab less4, again, finish;

clr cntcmp cnt,nbrif ilu. zero, finish*beginloop *LOOP.c005 8loop n.c186_-loop_okay

el st.f gaO,(a,4)+=.endloop .LOOP

finish:flop

Iasm void send words (n, a)t tmpreg n,a,cnt; use gaO; lab less4,again, finish;

clr cntcnp cnt,nbrif ilu. zero, finish.beginloop *LOOP*c005 8loop n.c186_Iloop_opkay

el ld.f (a,4)+=,gaO.endloop .Loop

finish:flop

asm void receivey.ass -words(n~a){% tnlpreg n,a,cnt; use gaO; lab finish;

cl: ontcmp cnt,nbrif ilu.zero, finish

B-25

* beginloop LOOP.c005 16loop n.c186_-loop_okay

el BEWflKA fmovni gaO,qgaa; at. f gaO, (a, 4)+ ENDCA* endloop LOOP

finish:flop

asm void receiveJpass2 words (n, a){%S tiupreg ri,a,cnt; use gaO,ga2; lab less4,again, finish;

clr cntCMp cnt,nbrif ilu.zero, finish.beginloop .LOOP.c005 16loop n.c186_loop_okay

el BEG7INCA fmovm qaO,gao; fmova gaO,ga2; st.f gaO, (a,4)+= ENDCA.endloap *LOOP

finish:flop

B-26

I.AECYUEOM L hU .REPORT DOC M NATE O PAG MeOR ft.E AW DTES

December 1993 Final: March 1991-September 19934. TILUE AMe SUB1TITLE 5. ROM4 NjeeMU

IWAJIP DISPLAY MODULE 602234NCS2D

S. ALITHOR(S) RS34J77J. J. Symanaki

7. PERIFORMING ORGANIZAflON NAME(S) AM0 ADORESS(ES &. PERORMING ORANIeZATIONREPORT MJMER

Naval Command, Control and Ocean Surveillance Center (NCCOSC)RDT&E Division TI 2610San Diego, CA 92152-5000

9.- ~.. SPNSIRIaIONTOIN AGENCY NAME(S) AND ADORESS(ES) 10. SPONSORNAINWONITORIINAGENCY REPOIRT NM1IER

Office of Naval Research800 North Quincy St.Arlington, VA 22217-5000

11. SUPPLEMENTARY NOTES

12L. DISTRIU11ON/AVAIL.ABIUITY STATEMENT 12b OLSRILIIO CODE

Approved for public release; distribution is unlimited.

13. ABSTRACT (&bcknea 200 words)

This report describes the design, fabrication, and testing of the iWARP display module. The display module is a customncircuit board designed specifically for the Intel iWarp processor. Software written during this development enables theboard to generate video signals to drive a high-resolution color display, with images processed within the iWarp processorarray.

The module contains 4 megabytes of VRAM which will hold images of user-determined pixel depth and siz. Image dataare converted to analog video signals by the Inmos G364 color video controller chip. Image sizes can range from 1024 by1024 24-bits-per-pixel true-color images to 1-bit-per-pixel monochrome images.

As part of this development, several iWarp programs have been developed to aid in the use of the display To the imageprocessing application developer, data can be displayed with a simple one-line subroutine call.

14. SU5JECTTERMS 15. NJUAER OF RAGES79

high-resolution displaysiWARP 15. PRIC CODE

17. SECURITY CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURITY CLASSIFICATION 20. LIMITATION OF ABSTRACTOF REPORT OF THIS RAGE OF ABSTRACT

UNCLASSIFIED UNCLASSIFIED IUNCLASSIFIED SAME AS REPORT

NSN 754001-280 880 Stondwrd form 20S IFOFT)

UNCLASSUFIE21&. NAME OF WSONMIE PAM0M&W 2).axmb. T.*OM 1avmw Qv= sn.OPIom

J. J. Smik (619) 553-2&3W Code 761

UNCLASSUIIED

INITIAL DISTRIBUTION

Code 0012 Patent Counsel (1)Code 0274B Library (2)Code 0275 Archive/Stock (6)Code 402 R.A. Wasilausky (1)Code70 T.F. Ball (1)Code 76 J.R. Wangler (1)Code7601 K.N. Bromley (1)Code 761 G.W. Byram (1)Code 761 J. J. Symanski (10)

Defense Technical Information CenterAlexandria, VA 22304-6145 (4)

NCCOSC Washington Liaison OfficeWashington, DC 20363-5 100

Center for Naval AnalysesAlexandria, VA 22302-M268

Navy Acquisition, Research and DevelopmentInformation Center (NARDIC)

Arlington, VA 22244-5114

GIDEP Operations CenterCorona, CA 91718-8000

NCCOSC Division DetachmentWarminster, PA 18974-5000

Office of Naval ResearchArlington, VA 22217-5660

Carnegie Mellon UniversityPittsburgh, PA 15213

Approved for public release; distribution is unlimited.