Jan Bogaertsimec 2007 1

Radiometric Performance Enhancement of APS

3rd Microelectronic Presentation Days, Estec, March 7-8, 2007

Jan Bogaertsimec 2007 3

Outline

• Introduction• Backside illuminated APS detector

– Approach

– CMOS APS (readout) design:

• Sensor and pixel architecture• Readout modes

• Technological developments– Thin wafer processing

– Special features on hybrid arrays

– Backside surface treatment

– AR coating

• Conclusions

Jan Bogaertsimec 2007 4

Introduction

• European Space Agency funded project “Hybrid APS” (ITT AO/1-3970/02/NL/EC)Partners:

• FillFactory/Cypress: design• IMEC: technology development • Galileo Avionica: radiometric characterization

• Aim: snapshot shutter CMOS APSdemonstrator for high-end spaceborne imaging

• Hyperspectral imaging2-D sensor with spectrometer slit:

• Spatial information on x-axis• Spectral information on y-axis• Spatial information by scanning

image cube

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Backside illuminated detector: approach

Monolithic approach

backside thinned CMOS readout array mounted on MCM substrate

using Au stud bumps MCM substrate

Hybrid approach

backside thinned diode array flip-chip integrated using In bumps

ROICCMOS readout array

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Backside illuminated detector: CMOS APS design

• synchronous pipelined shutter

• 22.5 µm pixel pitch

• stitched design:– 512 x 512 pixels stitch blocks

– up to 2048 x 2048 pixels

• pseudo-differential output

per 256 columns

• 20 Mpixels/s per output

• SPI interface for upload:addressing, gain & offset, NDR, non-linear

amplifier, etc.

Sensor architecture

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Backside illuminated detector: CMOS APS design

monolithic hybrid

in-pixel storage capacitance (fF) 350 350

full well charge (x 1000 electrons) (FWC) 150 - 200 250 - 1000

read noise (electrons) 15 - 20 25 - 100

dynamic range (FWC/dark noise) (dB) 80 80

maximum SNR 388-447 500 - 1000

C1,2,3 determine read noise and dynamic range

Cph determines charge handling capacity (FWC)and conversion gainon-chip CDS with synchronous pipelined shutter

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Backside illuminated detector: CMOS APS design

single pixel

pad for hybridization

sample capacitors

photodiode

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Backside illuminated detector: normal readout mode

• synchronous shutter:all pixels integrate in parallel

• pipelined:readout while integrate

• correlated double sampling

C1 and C3: reset levelC2: signal level

Tint < Tread

Tint > Tread

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Backside illuminated detector: Optimized readout modes

• Non-destructive readout (NDR)• Line by line variable integration time• Ref.: J. Bogaerts et al.: 2005 IEEE Workshop on CCD and

Advanced Image Sensors, Nagano, Japan, June 2005

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Technology development & challenges

• Realized through stitching stepper lithography5122, 10242 and 20482 pixel arrays

Hybrid diode array: 0.13 µmtechnology @ Imec

Readout: 0.35 µm technology@ commercial foundry

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Technology development & challenges: thin wafer processing

• (post-) processing of thin wafers (35 um)– Backside thinning with excellent thickness (uniformity) control (< 1 um)

– use of temporary carrier for thin wafer handling

– Ref.: K. De Munck et al., IMAPS Device Packaging 2006, IEDM 2006

Device wafer

1st Carrier1st Glue layer

Backside processing

Wafer thinning

Wafer bondingGlue layer deposition

Debonding & frontsideprocessing Wafer bonding

2nd Carrier2nd Glue layer

Device wafer

1st Carrier1st Glue layer

Backside processing

Wafer thinning

Wafer bondingGlue layer deposition

Debonding & frontsideprocessing Wafer bonding

2nd Carrier2nd Glue layer

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Technology development & challenges: special features

backside

frontside

built-in electric field

• Hybrid diode array: special features– Graded epi for built-in

electrical field: enhanced charge collection at low voltage operation

– Doped poly-Si filled trenches for cross-talk reduction

doped poly-Si filled trenches

built-in electric field

22.5 µm

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Technology development & challenges: backside passivation

• Backside surface treatment after thinning– Damage removal by dry/wet etch– Shallow (50nm) backside implantation – Dopant activation by laser annealing

0

10

20

30

40

50

60

70

80

90

100

200 300 400 500 600 700 800 900 1000 1100 1200Wavelength [nm]

Qua

ntum

effi

cien

cy [%

]

implant + anneal: simulated

measured before treatment

implant + anneal: measured

10 nm

20 nm

50 nm

100 nmdoped layer thickness

after treatment10 um thick epi

before treatment25 um thick epi

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Technology development & challenges: AR coating

• Optimized broadband ARC– Reflectivity <3% @ 400 to 850nm

– Spectral response: 60% >80%

1

10

Ref

lect

ivity

(%)

1000800600400Wavelength (nm)

ARC: 50nm ZnS + 100nm MgF2 Measured Simulated

Spectral response spec achieved @ 450-850nm

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Technology development & challenges

• Working detectors realized: COB packageHybrid: both 5122 and 10242 pixelsMonolithic: 10242 pixels

imager

MCM

40 µm

> 99.9 % pixel yield

Readout: 20482 pixels

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Conclusions

• Thinned backside illuminated imagers realized– Hybridized and monolithic

– CMOS APS: synchronous pipelined shutter with true CDS

• New 3D process technology for thin wafer handling and processing– Use of temporary carriers and glues

– 200 mm thin wafer processing on carrier with standard equipment

• Performance enhancing concepts implemented– Graded EPI lower cross-talk and improved QE for same voltage

– Poly-Si filled pixel separating trenches low cross-talk

• Working demonstrators• Detailed characterization is currently ongoing

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