January 2006 1 Verilog Digital System Design Copyright Z. Navabi, 2006 Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Chapter 2 Register Transfer

January 2006 1Verilog Digital System Design Copyright Z. Navabi, 2006

Verilog Digital System Design Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005Z. Navabi, McGraw-Hill, 2005

Chapter 2Chapter 2Register Transfer LevelRegister Transfer Level

Design with VerilogDesign with Verilog

Prepared by:Prepared by:Homa AlemzadehHoma Alemzadeh


Register Transfer Level Register Transfer Level Design Design

with Verilogwith Verilog2.1 RT Level Design2.1 RT Level Design

2.1.1 Control/data partitioning2.1.1 Control/data partitioning2.1.2 Data part 2.1.2 Data part 2.1.3 Control part 2.1.3 Control part

2.2 Elements of Verilog 2.2 Elements of Verilog 2.2.1 Hardware modules 2.2.1 Hardware modules 2.2.2 Primitive instantiations 2.2.2 Primitive instantiations 2.2.3 Assign statements 2.2.3 Assign statements 2.2.4 Condition expression 2.2.4 Condition expression 2.2.5 Procedural blocks2.2.5 Procedural blocks2.2.6 Module instantiations 2.2.6 Module instantiations


Register Transfer Level Register Transfer Level Design Design

with Verilogwith Verilog2.3 Component Description in Verilog 2.3 Component Description in Verilog

2.3.1 Data components 2.3.1 Data components 2.3.2 Controllers2.3.2 Controllers

2.4 Testbenches 2.4 Testbenches 2.4.1 A simple tester 2.4.1 A simple tester 2.4.2 Tasks and functions 2.4.2 Tasks and functions

2.5 Summary2.5 Summary


RT Level DesignRT Level Design RT level design:RT level design:

Taking a high level description of a designTaking a high level description of a design Partitioning Partitioning Coming up with an architectureComing up with an architecture Designing the bussing structureDesigning the bussing structure Describing and implementing various components Describing and implementing various components

of the architectureof the architecture Steps in RT level design:Steps in RT level design:

Control/Data PartitioningControl/Data Partitioning Data Part DesignData Part Design Control Part DesignControl Part Design


RT Level DesignRT Level DesignRT LevelRT Level DesignDesign

Control/data Control/data PartitioningPartitioning

Data PartData Part Control PartControl Part


Control/Data PartitioningControl/Data PartitioningRT LevelRT Level DesignDesign


Data PartData Part Control PartControl Part

Control/data Partitioning


Control/Data PartitioningControl/Data Partitioning

RT Level Design

Flags & status

Opcode

Data flowControl signals

ControlDataPath

Reg

Control

Outputs

Control

Inputs

Data Inputs

Data Outputs


Data PartData PartRT LevelRT Level DesignDesign


Data PartData Part Control PartControl PartData Part


Data PartData Part

Flags & status

Opcode


DataPath

Reg

Data Inputs

Data Outputs


Data PartData Partmodulemodule DataPath DataPath

(DataInput, DataOutput, Flags, Opcodes, (DataInput, DataOutput, Flags, Opcodes, ControlSignals);ControlSignals);

inputinput [15:0] DataInputs; [15:0] DataInputs;output output [15:0] DataOutputs;[15:0] DataOutputs;outputoutput Flags, ...; Flags, ...;outputoutput Opcodes, ...; Opcodes, ...;inputinput ControlSignals, ...; ControlSignals, ...;// instantiation of data components // instantiation of data components // ...// ...// interconnection of data components// interconnection of data components// bussing specification// bussing specification

endmoduleendmodule

DataPath ModuleDataPath Module

Control Control Signals:Signals:

Inputs to data Inputs to data part, sent to part, sent to

the data the data components components and bussesand busses

Output Signals: Output Signals: Going to the Going to the control part, control part, provide flags provide flags and status of and status of

the datathe data

Control Signals for Control Signals for the busses: Select the the busses: Select the sources and routing sources and routing

of data from of data from one data component one data component

to anotherto another


Data PartData Part

modulemodule DataComponent DataComponent (DataIn, DataOut, ControlSignals);(DataIn, DataOut, ControlSignals);

inputinput [7:0] DataIn; [7:0] DataIn;outputoutput [7:0] DataOut; [7:0] DataOut;inputinput ControlSignals; ControlSignals;// Depending on ControlSignals // Depending on ControlSignals // Operate on DataIn and// Operate on DataIn and// Produce DataOut// Produce DataOut

endmoduleendmodule

Partial Verilog Code of a Data ComponentPartial Verilog Code of a Data Component

Data Data ComponentComponent::

Shows how the Shows how the component component

uses its input uses its input control signals control signals

to perform to perform various various

operations on operations on its data inputsits data inputs


Control PartControl PartRT LevelRT Level DesignDesign


Data PartData Part Control PartControl PartControl Part


Control PartControl Part

Flags & status

Opcode


Control

Control

Outputs

Control

Inputs

Consists of one Consists of one or more state or more state

machines machines to keep the to keep the state of the state of the

circuit.circuit.

Makes Makes decisions as to decisions as to when and what when and what control signals control signals

to issue to issue depending on depending on

its state.its state.


Control PartControl Part

modulemodule ControlUnit ControlUnit (Flags, Opcodes, ExternalControls, ControlSignals);(Flags, Opcodes, ExternalControls, ControlSignals);

inputinput Flags, ...; Flags, ...;inputinput Opcodes, ...; Opcodes, ...;inputinput ExternalControls, ...; ExternalControls, ...;outputoutput ControlSignals; ControlSignals;// Based on inputs decide :// Based on inputs decide :// What control signals to issue,// What control signals to issue,// and what next state to take// and what next state to take

endmoduleendmodule

Outline of a ControllerOutline of a Controller

Takes Takes control control

inputs from inputs from thethe

Data PartData Part


Elements of VerilogElements of Verilog

We discuss basic constructs of Verilog language for We discuss basic constructs of Verilog language for describing a hardware module.describing a hardware module.


Elements of VerilogElements of VerilogHardware Hardware Modules Modules

Primitive Primitive InstantiationsInstantiations

Assign Assign Statements Statements

Condition Condition ExpressionExpression

Procedural Procedural BlocksBlocks

Module Module InstantiationsInstantiations


Hardware ModulesHardware ModulesHardware Hardware Modules Modules






Hardware Modules


Hardware ModulesHardware Modules

modulemodule module-name module-name List of ports;List of ports;DeclarationsDeclarations......Functional specification of moduleFunctional specification of module......

endmoduleendmodule

Module SpecificationsModule Specifications

KeyworKeyword d

modulemodule

module :module :The Main The Main ComponeCompone

nt of nt of VerilogVerilog

Keyword Keyword endmodendmod

uleule

Variables, Variables, wires, and wires, and

module module parametersparameters

are declared.are declared.


Hardware ModulesHardware Modules

There is more than one way to describe a Module in Verilog.There is more than one way to describe a Module in Verilog. May correspond to descriptions at various levels of abstraction May correspond to descriptions at various levels of abstraction

or to various levels of detail of the functionality of a module. or to various levels of detail of the functionality of a module. Descriptions of the same module need not behave in exactly Descriptions of the same module need not behave in exactly

the same way nor is it required that all descriptions describe a the same way nor is it required that all descriptions describe a behavior correctly.behavior correctly.

We discuss basic constructs of Verilog language for a hardware We discuss basic constructs of Verilog language for a hardware module description.module description.

We show a small example and several alternative ways to We show a small example and several alternative ways to describe it in Verilog.describe it in Verilog.


Primitive InstantiationsPrimitive InstantiationsHardware Hardware Modules Modules






PrimitiveInstantiations


Primitive InstantiationsPrimitive Instantiations

a

s

b

s_bar

a_sel

b_sel

w

A Multiplexer Using Basic Logic GatesA Multiplexer Using Basic Logic Gates

Logic Logic GatesGatescalledcalled

PrimitivePrimitivess



modulemodule MultiplexerA ( MultiplexerA (inputinput a, b, s, a, b, s, output output w);w);wirewire a_sel, b_sel, s_bar; a_sel, b_sel, s_bar;notnot U1 (s_bar, s); U1 (s_bar, s);andand U2 (a_sel, a, s_bar); U2 (a_sel, a, s_bar);andand U3 (b_sel, b, s); U3 (b_sel, b, s);oror U4 (w, a_sel, b_sel); U4 (w, a_sel, b_sel);

endmoduleendmodule


InstantiatioInstantiationnof of

PrimitivesPrimitives


Assign StatementsAssign StatementsHardware Hardware Modules Modules






AssignStatements


Assign StatementsAssign Statements

modulemodule MultiplexerB ( MultiplexerB (inputinput a, b, s, a, b, s, output output w);w);

assignassign w = (a & ~s) | (b & s); w = (a & ~s) | (b & s);

endmoduleendmodule

Assign Statement and BooleanAssign Statement and Boolean

Continuously Continuously drives drives w w with with

the the right hand right hand

side side expressionexpression

Using Using Boolean Boolean

expressions expressions to describe to describe the logicthe logic


Condition ExpressionCondition ExpressionHardware Hardware Modules Modules






ConditionExpression


Condition ExpressionCondition Expression

modulemodule MultiplexerC ( MultiplexerC (inputinput a, b, s, a, b, s, output output w);w);assignassign w = s ? b : a; w = s ? b : a;

endmoduleendmodule

Assign Statement and Condition OperatorAssign Statement and Condition Operator

Can be used Can be used when the when the

operation of a operation of a unit is too unit is too

complex to be complex to be described by described by

Boolean Boolean expressionsexpressions

Very Effective Very Effective in describing in describing

complex complex functionalities functionalities

Useful in Useful in describing a describing a

behavior in a behavior in a very compact very compact

wayway


Procedural BlocksProcedural BlocksHardware Hardware Modules Modules






ProceduralBlocks


Procedural BlocksProcedural Blocks

modulemodule MultiplexerD ( MultiplexerD (input input a, b, s,a, b, s, output output w); w);regreg w; w;alwaysalways @(a, b, s) @(a, b, s) beginbegin

ifif (s) w = b; (s) w = b;elseelse w = a; w = a;

endendendmoduleendmodule

Procedural StatementProcedural Statement

always always statemestateme

ntnt

if-else if-else statemenstatemen

tt

Can be used when Can be used when the operation of a the operation of a

unit is too unit is too complex to be complex to be described by described by Boolean or Boolean or conditional conditional expressionsexpressions

Sensitivity Sensitivity listlist


Module InstantiationsModule InstantiationsHardware Hardware Modules Modules






ModuleInstantiations


Module InstantiationsModule Instantiations

modulemodule ANDOR ( ANDOR (inputinput i1, i2, i3, i4, i1, i2, i3, i4, outputoutput y); y);assignassign y = (i1 & i2) | (i3 & i4); y = (i1 & i2) | (i3 & i4);

endmoduleendmodule////modulemodule MultiplexerE ( MultiplexerE (inputinput a, b, s, a, b, s, output output w); w);

wirewire s_bar; s_bar;notnot U1 (s_bar, s); U1 (s_bar, s);ANDOR U2 (a, s_bar, s, b, w);ANDOR U2 (a, s_bar, s, b, w);

endmoduleendmodule

Module InstantiationModule Instantiation

ANDOR ANDOR module is module is defineddefined

ANDOR ANDOR module ismodule is

instantiatedinstantiated


Module InstantiationsModule Instantiations

Multiplexer Using ANDORMultiplexer Using ANDOR

i1i2

i3i4

y w

ANDORa

s

b


Component Description Component Description in Verilogin Verilog

ComponentComponentDescriptionDescription

DataDataComponentsComponents ControllersControllers


Data ComponentsData Components


DataDataComponentsComponents ControllersControllers

DataComponents


DataData ComponentsComponents

MultiplexerMultiplexer Flip-FlopFlip-Flop

CounterCounter Full-AdderFull-Adder

Shift-RegisterShift-Register ALUALU

InterconnectionsInterconnections

Data ComponentsData Components







MultiplexerMultiplexer

Multiplexer


MultiplexerMultiplexer

`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule Mux8 ( Mux8 (inputinput sel, sel, inputinput [7:0] data1, data0, [7:0] data1, data0, outputoutput [7:0] bus1); [7:0] bus1);assignassign #6 bus1 = sel ? data1 : data0; #6 bus1 = sel ? data1 : data0;

endmoduleendmodule

Octal 2-to-1 MUXOctal 2-to-1 MUX Selects its 8-bitSelects its 8-bitdata0data0 or or data1data1

input depending input depending on its on its

selsel input. input.

Defines a Time Unit of Defines a Time Unit of 1 ns and Time 1 ns and Time

Precision of 100 ps.Precision of 100 ps.

A 6-ns DelayA 6-ns Delayis specified for is specified for

all values all values assigned to assigned to

bus1bus1







Flip-FlopFlip-Flop

Flip-Flop


Flip-FlopFlip-Flop


modulemodule Flop (reset, din, clk, qout); Flop (reset, din, clk, qout);inputinput reset, din, clk; reset, din, clk;outputoutput qout; qout;regreg qout; qout;alwaysalways @( @(negedgenegedge clk) clk) beginbegin

if if (reset) qout <= #8 1'b0;(reset) qout <= #8 1'b0;elseelse qout <= #8 din; qout <= #8 din;

endendendmoduleendmodule

Flip-Flop DescriptionFlip-Flop Description

SynchronoSynchronous us reset reset

iinputnput

A Signal A Signal declared as a declared as a

reg reg to be to be capable of capable of holding its holding its

values between values between clock edges clock edges

Flip-Flops Flip-Flops are used in are used in

data part for data part for flags and flags and

data storagedata storage

An 8-An 8-ns ns

Delay Delay

A Non-A Non-blocking blocking

AssignmentAssignment

A Software-A Software-Like Like

Procedural Procedural Coding StyleCoding Style

Flip-FlopFlip-Floptriggers on triggers on the falling the falling edge of edge of clkclk

InputInput

The Body of The Body of alwaysalways

statement is statement is executed at executed at the negative the negative

edge of the edge of the clkclk signalsignal







CounterCounter

Counter


CounterCounter

`timescale`timescale 1ns/100ps 1ns/100psmodulemodule Counter4 ( Counter4 (inputinput reset, clk, reset, clk,

outputoutput [3:0] count); [3:0] count);regreg [3:0] count; [3:0] count; alwaysalways @( @(negedgenegedge clk) clk) beginbegin ifif (reset) count <= #3 4'b00_00; (reset) count <= #3 4'b00_00;

elseelse count <= #5 count + 1; count <= #5 count + 1; endend

endmoduleendmodule

Counter Verilog CodeCounter Verilog Code

Counters are used Counters are used in data part for in data part for

registering data, registering data, accessing memory accessing memory

or queues and or queues and register stacksregister stacks

A 4-bit A 4-bit modulo-16 modulo-16

CounterCounter

Constant Constant DefinitionDefinition

4-bit 4-bit RegisterRegister

When When countcount reaches reaches 1111,1111,

the next the next count taken count taken

is 10000is 10000







Full-AdderFull-Adder

Full-Adder


Full-AdderFull-Adder


modulemodule fulladder ( fulladder (inputinput a, b, cin, a, b, cin, outputoutput sum, cout); sum, cout);assignassign #5 sum = a ^ b ^ cin; #5 sum = a ^ b ^ cin;assignassign #3 cout = (a & b)|(a & cin)|(b & cin); #3 cout = (a & b)|(a & cin)|(b & cin);

endmoduleendmodule

Full-Adder Verilog CodeFull-Adder Verilog Code

Full-Adders are Full-Adders are used in data used in data

part for part for building building

Carry-Chain Carry-Chain addersadders

A A combinationcombination

alalcircuitcircuit All Changes All Changes

Occur after Occur after 5 ns5 ns

All Changes All Changes Occur after Occur after

3 ns3 nsOne delay for One delay for every output:every output:

tPLH and tPLH and tPHLtPHL







Shift-RegisterShift-Register

Shift-Register


Shift-RegisterShift-Register`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule ShiftRegister8 ShiftRegister8 ((inputinput sl, sr, clk, sl, sr, clk, inputinput [7:0] ParIn, [7:0] ParIn,

inputinput [1:0] m, [1:0] m, outputoutput regreg [7:0] ParOut); [7:0] ParOut); alwaysalways @( @(negedgenegedge clk) clk) beginbegin

casecase (m) (m) 0: ParOut <= ParOut;0: ParOut <= ParOut; 1: ParOut <= {sl, ParOut [7:1]};1: ParOut <= {sl, ParOut [7:1]}; 2: ParOut <= {ParOut [6:0], sr};2: ParOut <= {ParOut [6:0], sr}; 3: ParOut <= ParIn;3: ParOut <= ParIn; defaultdefault: ParOut <= 8'bX;: ParOut <= 8'bX;

endcaseendcase endend

endmoduleendmodule

An 8-bit An 8-bit Universal Universal

Shift Shift RegisterRegister

2 Mode 2 Mode inputs inputs

m[1:0]m[1:0] form form a a

2-bit 2-bit numbernumber

m=0m=0 : Does : Does NothingNothing

m=3m=3 : Loads its : Loads its Parallel input into Parallel input into

the registerthe register

m=1,2m=1,2: Shifts : Shifts Right and Right and

LeftLeft

Case StatementCase StatementWith 4 case-With 4 case-alternativesalternatives

and default Valueand default Value


Shift-Register Shift-Register (Continued)(Continued)`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule ShiftRegister8 ShiftRegister8 ((inputinput sl, sr, clk, sl, sr, clk, inputinput [7:0] ParIn, [7:0] ParIn,

inputinput [1:0] m, [1:0] m, outputoutput regreg [7:0] ParOut); [7:0] ParOut); alwaysalways @( @(negedgenegedge clk) clk) beginbegin

casecase (m) (m) 0: ParOut <= ParOut;0: ParOut <= ParOut; 1: ParOut <= {sl, ParOut [7:1]};1: ParOut <= {sl, ParOut [7:1]}; 2: ParOut <= {ParOut [6:0], sr};2: ParOut <= {ParOut [6:0], sr}; 3: ParOut <= ParIn;3: ParOut <= ParIn; defaultdefault: ParOut <= 8'bX;: ParOut <= 8'bX;


endmoduleendmodule

Shift Right:Shift Right:The The SLSL input is input is

concatenateconcatenated to the left d to the left of of ParOutParOut

Shifting the Shifting the ParOut ParOut to to the leftthe left







ALUALU

ALU


ALUALU`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule ALU8 ( ALU8 (inputinput [7:0] left, right, [7:0] left, right, inputinput [1:0] mode, [1:0] mode, output regoutput reg [7:0] ALUout); [7:0] ALUout);

alwaysalways @(left, right, mode) @(left, right, mode) begin begin casecase (mode) (mode)

0: ALUout = left + right;0: ALUout = left + right; 1: ALUout = left - right;1: ALUout = left - right; 2: ALUout = left & right;2: ALUout = left & right; 3: ALUout = left | right;3: ALUout = left | right; defaultdefault: ALUout = 8'bX;: ALUout = 8'bX;


endmoduleendmodule

An 8-bit ALUAn 8-bit ALU

2-bit 2-bit modemode Input to Input to

select one of select one of its 4 its 4

functionsfunctions

AddAddSubtracSubtrac

ttANDANDOROR


ALU (Continued)ALU (Continued)`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule ALU8 ( ALU8 (inputinput [7:0] left, right, [7:0] left, right, inputinput [1:0] mode, [1:0] mode, output regoutput reg [7:0] ALUout); [7:0] ALUout);

alwaysalways @(left, right, mode) @(left, right, mode) begin begin casecase (mode) (mode)

0: ALUout = left + right;0: ALUout = left + right; 1: ALUout = left - right;1: ALUout = left - right; 2: ALUout = left & right;2: ALUout = left & right; 3: ALUout = left | right;3: ALUout = left | right; defaultdefault: ALUout = 8'bX;: ALUout = 8'bX;


endmoduleendmodule

An 8-bit ALUAn 8-bit ALU

The The Declaration of Declaration of ALUoutALUout both as both as outputoutput and and reg: reg:

Because of Because of assigning it assigning it

within a within a Procedural Procedural

BlockBlockBlocking Blocking AssignmeAssignme

ntsnts

defaultdefault alternativealternative

puts allputs all X Xss on on ALUOutALUOut

if if mode cmode containsontainsanything but anything but 11s s

andand 0 0ss








Interconnections



Partial Hardware Using Partial Hardware Using MUX8MUX8 and and ALUALU

BsideAsideInbus

select_source

ABinput

Function

Outbus

8 8

8 8

8

Mux8 and Mux8 and ALU examples ALU examples

forming a forming a Partial Partial

HardwareHardware



ALU8 U1 ( .left(Inbus), .right(ABinput), ALU8 U1 ( .left(Inbus), .right(ABinput), .mode(function), .ALUout(Outbus) );.mode(function), .ALUout(Outbus) );Mux8 U2 ( .sel(select_source), .data1(Aside), Mux8 U2 ( .sel(select_source), .data1(Aside),

.data0(Bside), .bus1 (ABinput)); .data0(Bside), .bus1 (ABinput));

Verilog Code of The Partial Hardware ExampleVerilog Code of The Partial Hardware Example

Instantiation Instantiation of of ALU8ALU8 and and

MUX8MUX8

u1u1 and and u2 u2 ::Instance Instance NamesNames

A Set of A Set of parenthesis parenthesis enclose port enclose port

connections to connections to the the

instantiated instantiated modulesmodules



ALU8 U1 ( Inbus, ABinput, function, Outbus );ALU8 U1 ( Inbus, ABinput, function, Outbus );Mux8 U2 ( select_source, Aside, Bside, ABinput );Mux8 U2 ( select_source, Aside, Bside, ABinput );

Ordered Port ConnectionOrdered Port Connection

An Alternative An Alternative format of port format of port

connectionconnection

The actual The actual portsportsof the of the

instantiatedinstantiatedcomponents components are excludedare excluded

The list of local The list of local signals in the signals in the same order as same order as

their connecting their connecting portsports


ControllersControllers


DataDataComponentsComponents ControllersControllersControllers



Controller OutlineController Outline

Decisions Based on : Inputs ,

Outputs , State

Issue Control Signal

Set Next State

Go to Next State



Controller:Controller: Is wired into data part to control its flow of data.Is wired into data part to control its flow of data. The inputs to it controller determine its next states and The inputs to it controller determine its next states and

outputs.outputs. Monitors its inputs and makes decisions as to when and what Monitors its inputs and makes decisions as to when and what

output signals to assert.output signals to assert. Keeps the history of circuit data by switching to appropriate Keeps the history of circuit data by switching to appropriate

states.states. Two examples to illustrate the features of Verilog for describing Two examples to illustrate the features of Verilog for describing

state machines:state machines: SynchronizerSynchronizer Sequence DetectorSequence Detector




SynchronizerSynchronizer SequenceSequenceDetectorDetector


SynchronizerSynchronizer


SynthesizerSynthesizer SequenceSequenceDetectorDetector

Synchronizer



Synchronizing Synchronizing adataadata

Clk

adata

synched




modulemodule Synchronizer ( Synchronizer (inputinput clk, adata, clk, adata, outputoutput reg synched); reg synched);

alwaysalways @( @(posedgeposedge clk) clk) if (adata == 0) synched <= 0; if (adata == 0) synched <= 0; elseelse synched <= 1; synched <= 1;

endmoduleendmodule

A Simple Synchronization CircuitA Simple Synchronization Circuit

If a If a 11 is is Detected on Detected on adataadata on the on the

rising edge of rising edge of clock, clock, synchedsynched becomes becomes 11 and and

remains remains 11 for at least one for at least one

clock period clock period


Sequence DetectorSequence Detector


SynthesizerSynthesizer SequenceSequenceDetectorDetector

SequenceDetector



State Machine DescriptionState Machine Description

Searches Searches onon

it’s it’s aa inputinput

for the for the 110 110

SequenceSequence

When the When the sequence sequence

is detected, the is detected, the w Output w Output

becomes 1 and becomes 1 and stays 1 for a stays 1 for a

complete clock complete clock cyclecycle

If 110 is detected on a, then w gets 1, else w gets 0.

clk

a w



Sequence Detector State MachineSequence Detector State Machine

Initial

State

01

1

1

0

0

1

0reset

S00 0 10

S1 S2 S3

States are States are named:named:

s0s0 , , s1 s1 , , s2s2 , , s3s3

The State in The State in which the 110 which the 110 sequence is sequence is detected.detected.

It Takes at It Takes at least least

3 clock 3 clock periods to get periods to get to the to the s3s3 state state

A Moore A Moore MachineMachineSequence Sequence DetectorDetector


Sequence DetectorSequence Detectormodulemodule Detector110 ( Detector110 (inputinput a, clk, reset, a, clk, reset, outputoutput w); w);

parameterparameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;regreg [1:0] current; [1:0] current;

alwaysalways @( @(posedgeposedge clk) clk) beginbegin

ifif (reset) current = s0; (reset) current = s0; elseelse

casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase

endend

assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;

endmoduleendmodule

Verilog Code for Verilog Code for 110110 Detector Detector



modulemodule Detector110 ( Detector110 (inputinput a, clk, reset, a, clk, reset, outputoutput w); w);

parameterparameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;s3=2'b11;

regreg [1:0] current; [1:0] current;

alwaysalways @( @(posedgeposedge clk) clk) beginbegin ifif (reset) current = s0; (reset) current = s0; elseelse

...................................................... ......................................................


Behavioral Behavioral Description of Description of

the State the State MachineMachine

Parameter Parameter declarationdeclaration

defines constantsdefines constantss0s0, , s1s1, , s2s2, , s3s3

A 2-bit A 2-bit RegisterRegister



......................................................

......................................................alwaysalways @( @(posedgeposedge clk) clk) beginbegin

ifif (reset) current = s0; (reset) current = s0; elseelse

casecase (current) (current) s0: s0: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; s1: s1: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s0; current <= s0; s2: s2: ifif (a) current <= s2; (a) current <= s2; elseelse current <= s3; current <= s3; s3: s3: ifif (a) current <= s1; (a) current <= s1; elseelse current <= s0; current <= s0; endcaseendcase

endend


if-elseif-else statementstatementchecks for checks for

resetresetAt the At the Absence Absence of aof a 1 1 on on

resetreset

The 4 Case-The 4 Case-alternativesalternatives

each correspond each correspond to a state of state to a state of state

machinemachine



State Transitions on Corresponding Verilog CodeState Transitions on Corresponding Verilog Code

s10

s20

s00

a=0

a=1

s1:

if (a)

current <= s2;

else

current <= s0;



endend................................................................................................................assignassign w = (current == s3) ? 1 : 0; w = (current == s3) ? 1 : 0;

endmoduleendmodule


Assigns a Assigns a 11 to to w ow output when utput when

Machine Machine Reaches to Reaches to s3s3

StateState

Outside of Outside of the the alwaysalways

Block:Block:A A

combinationcombinational circuital circuit


TestbenchesTestbenches


A SimpleA SimpleTesterTester

Tasks Tasks And And

FunctionsFunctions


A Simple TesterA Simple Tester



Tasks Tasks And And

FunctionsFunctions

A SimpleTester


A Simple TesterA Simple Tester`timescale`timescale 1ns/100ps 1ns/100ps

modulemodule Detector110Tester; Detector110Tester;regreg aa, clock, rst; aa, clock, rst; wirewire ww; ww;Detector110Detector110 UUT (aa, clock, rst, ww); UUT (aa, clock, rst, ww);

initial begininitial beginaa = 0; clock = 0; rst = 1; aa = 0; clock = 0; rst = 1;

endendinitial repeatinitial repeat (44) #7 clock = ~clock; (44) #7 clock = ~clock;initial repeatinitial repeat (15) #23 aa = ~aa; (15) #23 aa = ~aa;initial begininitial begin

#31 rst = 1;#31 rst = 1;#23 rst = 0;#23 rst = 0;

endendalwaysalways @(ww) @(ww) ifif (ww == 1) (ww == 1)

$display$display ("A 1 was detected on w at time = %t", ("A 1 was detected on w at time = %t", $time$time););endmoduleendmodule

Testbench for Testbench for Detector110Detector110




modulemodule Detector110Tester; Detector110Tester;regreg aa, clock, rst; aa, clock, rst; wirewire ww; ww;Detector110Detector110 UUT (aa, clock, rst, ww); UUT (aa, clock, rst, ww);

........................................................................... .........................


Begins Begins with the with the module module keywordkeyword

Unlike other Unlike other descriptionsdescriptionsdoesn’t have doesn’t have

input or input or output portsoutput ports

Inputs are Declared Inputs are Declared as as regreg

The Instantiation ofThe Instantiation of Detector110 Detector110 ModuleModule

Outputs are Outputs are declared as declared as

wirewire



....................................................

....................................................initial begininitial begin

aa = 0; clock = 0; rst = 1; aa = 0; clock = 0; rst = 1; endendinitial repeatinitial repeat (44) #7 clock = ~clock; (44) #7 clock = ~clock;initial repeatinitial repeat (15) #23 aa = ~aa; (15) #23 aa = ~aa;initial begininitial begin

#31 rst = 1;#31 rst = 1;#23 rst = 0;#23 rst = 0;

endend


initial initial statementstatementdrives test drives test

valuesvaluesinto the into the variablesvariables

connected to connected to thethe

inputs.inputs.

An An initial initial statement: A statement: A sequential sequential

statement that statement that runs once and runs once and stops when it stops when it

reaches its last reaches its last statement statement

All Initial All Initial Blocks Start at Blocks Start at

Time 0 and Time 0 and Run Run

ConcurrentlyConcurrently



....................................................

....................................................initial begininitial begin

aa = 0; clock = 0; rst = 1; aa = 0; clock = 0; rst = 1; endendinitial repeatinitial repeat (44) #7 clock = ~clock; (44) #7 clock = ~clock;initial repeatinitial repeat (15) #23 aa = ~aa; (15) #23 aa = ~aa;initial begininitial begin

#31 rst = 1;#31 rst = 1;#23 rst = 0;#23 rst = 0;

endend


For For Initializing Initializing the Input the Input SignalsSignals

Repeats 44 Repeats 44 times of times of

complementing complementing the the clockclock input input with 7ns delay, with 7ns delay,

generates a generates a periodic signal periodic signal

on on clockclock

Signal Signal aa aa is alsois also assigned a assigned a

periodic signal, periodic signal, with a different with a different

frequencyfrequencyWaits 31 ns Waits 31 ns before before

assigning assigning 11 to to rstrst



....................................................

....................................................alwaysalways @(ww) @(ww) ifif (ww == 1) (ww == 1)

$display$display ("A 1 was detected on w at time = ("A 1 was detected on w at time = %t", %t", $time$time););

endmoduleendmodule


Reports the Reports the Times at Times at

whichwhichthe the wwww

Variable Variable becomes becomes 11

always always Block Block Wakes up Wakes up when when wwww ChangesChanges

This Note Will This Note Will Appear in the Appear in the

Simulation Simulation Environment’s Environment’s

Window: Window: “Console” or “Console” or “Transcript”“Transcript”

A Verilog A Verilog System System TaskTask


Tasks And FunctionsTasks And Functions



Tasks Tasks And And

FunctionsFunctions

Tasks And

Functions


Tasks And FunctionsTasks And Functions Verilog Tasks and Functions:Verilog Tasks and Functions:

System tasks for Input, Output, Display, and Timing System tasks for Input, Output, Display, and Timing ChecksChecks

User defined tasks and functionsUser defined tasks and functions Tasks:Tasks:

Can represent a sub module within a Verilog moduleCan represent a sub module within a Verilog module Begins with a Begins with a task task keywordkeyword Its body can only consist of sequential statements like Its body can only consist of sequential statements like

if-elseif-else and and casecase Functions:Functions:

Can be used for corresponding to hardware entities Can be used for corresponding to hardware entities May be used for writing structured codesMay be used for writing structured codes Applications: Representation of Boolean functions, data Applications: Representation of Boolean functions, data

and code conversion, and input and output formattingand code conversion, and input and output formatting


SummarySummary

This chapter presented:This chapter presented: An overview of Verilog and how this language is An overview of Verilog and how this language is

used for design and test of RT level description used for design and test of RT level description Components of an RT level design Components of an RT level design Small examples to illustrate such components and Small examples to illustrate such components and

at the same time Verilog coding of hardware at the same time Verilog coding of hardware modulesmodules

The descriptions in this part were all synthesizable The descriptions in this part were all synthesizable and had a one-to-one hardware correspondence. and had a one-to-one hardware correspondence.

How testbenches could be developed in Verilog and How testbenches could be developed in Verilog and new constructs of it in this partnew constructs of it in this part

Documents

January 2006 1 Verilog Digital System Design Copyright Z. Navabi, 2006 Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Chapter 2 Register Transfer