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JASMEET KAUR
EDUCATION: University of Southern California, Los Angeles Dec 2016
MASTER’S IN ELECTRICAL ENGINEERING GPA: 3.58/4.0
PEC University of Technology, Chandigarh, India May 2013
BACHELORS IN ELECTRONICS ENGINEERING CGPA: 9.28/10.0
ACADEMIC PROJECTS: Full-custom 5-stage Pipeline Processor (Cadence Virtuoso) Spring 2016
Designed schematic and layout of a 5-stage pipeline optimized for Area,
Power, Delay Product; operating at clock of 3 ns.
1KB SRAM designed for Memory stage, using four banks of 16*16 6-T SRAM.
Domino circuits, Clock and Power gating used for optimization of stages.
Dual-Core Quad-Threaded Processor (Xilinx ISE) Spring 2016
Realized a Network Processor on NetFPGA to prevent Denial of Service attacks with RSA key for secure communication.
Implemented Intrusion Detection System (IDS) to drop ICMP packets from malicious nodes based on IP-address.
Maze Router using Lee’s Algorithm (NCSim) Fall 2016
Executed Maze Router algorithm and corresponding testbench in Verilog for
multi-terminal connection.
7nm FinFET design (HSpice) Spring 2016
Simulated characteristics of FINFETs in SG, IG and LP modes to obtain device
size for balanced rise-fall delays for optimal leakage and switching power.
Phase Locked Loop (Cadence Virtuoso) Fall 2015
Designed schematic and layout of VCO, loop filter, charge pump and PFD of a
PLL operating at 800MHz, using a reference of 100 MHz frequency.
FIFO, LIFO and CAM synthesis (NCSim) Fall 2016
Implemented a two-clock FIFO, LIFO and CAM in Verilog and synthesized
these in Design Compiler (DC).
WORK EXPERIENCE: Intel Corporation, Austin, Texas Summer 2016
Design Automation Intern, Atom CPU
Developed an algorithm to cluster terminals in a floorplan and implemented it in TCL for DA tool.
Integrated the flow for FRAM view generation by enhancing Perl and C-shell scripts for the custom team.
Debugged and optimized TCL scripts for filler cells insertion, shield insertion and routing tool integration.
Texas Instruments India, Bangalore July 2013-July 2015
Design Engineer, Standard Cell Libraries
Structured layout architecture for various standard cell libraries, facilitating
dual-metal routing.
Delivered standard cell layouts, LEF, and placed and routed designs for
the use of Analog Design Teams
Publications: Debugged a silicon issue, resulting in co-authoring a
white paper on ‘Signal Integrity Issues in Silicon Debug using QRC’
presented at CDNLive 2014.
CONTACT: ADDRESS:
1170 W 30th Street,
Los Angeles 90007
PHONE NUMBER:
+1 (213) 326-5332
E-MAIL:
LINKEDIN:
https://www.linkedin.com/in/jasmeet-
kaur-00164536
TOOLS: Cadence Virtuoso (Layout,
Schematic), HSpice, Xilinx ISE, NCSIM,
ModelSim, Cadence Encounter, Design
Compiler, EDI, EPS, MatLab
PROGRAMMING: TCL, Perl, C, SKILL,
Verilog.
COURSE WORK: VLSI System Design-I EE-577a
VLSI System Design-II EE-577b
Network Processors EE-533
Computer Architecture EE-457
MOS VLSI Design EE-477
Diagnosis of Systems EE-658
Solid State Devices EE-504
Probability for Engineers EE-503
ADDITIONAL EXPERIENCE: Texas Instruments India-Intern
Spring 2012
Ported GNSS code’s processor and operating system from ARM7 core and Nucleus RTOS to Cortex M3 and ThreadX RTOS.
OTHER INTERESTS: Hobbies: Badminton, Music.
Volunteered to write thank you cards &
pack gifts for Austin school teachers.
Member of USC Sikh Association.
