1170 W. 30th Street JASMEET KAUR jasmeetk@usc.edu

Los Angeles, CA 90007 https://www.linkedin.com/in/jasmeet-kaur-00164536 +1- (213) 326-5332

EDUCATION Master’s in Electrical Engineering Expected Dec 2016

University of Southern California, LA, CA GPA: 3.58/4.0

Bachelor of Engineering, Electronics and Electrical Communication May 2013

PEC University of Technology, Chandigarh, India GPA: 9.28/10.0

Related Course Work: CMOS VLSI Design (EE-577a), Computer System Organization (EE-457), Network Processor Design

(EE-533), MOS VLSI Design (EE-477), Probability for Electrical Engineers (EE-503)

WORK EXPERIENCE Intel Corporation, Austin, Design Automation Intern - Atom CPU Summer 2016

Merged the flow for FRAM view generation by enhancing the Perl and C-shell scripts for the custom team

Developed algorithm to cluster terminals in a floorplan and implemented it in Tcl for an internal design tool

Debugged and optimized Tcl scripts for filler cells insertion, shield insertion and routing tool integration

Texas Instruments India, Design Engineer, Standard Cells Libraries July ‘13-July ‘15

Delivered standard cell layouts, LEF, routed designs for use of analog design teams

Structured layout architecture for three standard cell libraries, facilitating DLM metal routability

Publications: Debugged a silicon issue, resulting in co-authoring a white paper on ‘Signal Integrity Issues in Silicon

Debug using QRC’ presented at CDNLive 2014

Texas Instruments India, Intern Jan-June 2012

Ported GNSS code base processor and operating system from ARM7 core and Nucleus RTOS to Cortex M3 and

ThreadX RTOS

Indian Institute of Technology (IIT), Bombay, India, Intern Summer 2011

Programmed Phase Locked Loop (PLL) using frequency synthesizer IC TRF3750

TECHNICAL SKILLS Tools: Cadence Virtuoso (Layout, Schematic), HSpice, Xilinx ISE, ModelSim, MatLab, EDI, EPS

Programming: Tcl, Perl, C, SKILL, Verilog

ACADEMIC PROJECTS

5-Stage RISC Pipelined Full-custom Processor (Cadence Virtuoso) Spring 2016

Designed schematic and layout of a 5-stage pipeline optimized for Area, Power, Delay product; for clock of 3ns

1Kb SRAM designed for the memory stage, using four 16*16 blocks of 6T SRAM structure

Domino circuits, Clock gating and Power gating used for optimization of EX-stage circuit

Dual-core quad-threaded Network Pipelined Processor (Xilinx ISE) Spring 2016

Designed a Network Processor to prevent Denial of Service attacks with RSA key for secure communication

Implemented Intrusion Detection System (IDS) to drop ICMP packets from malicious nodes based on IP-address

7nm FinFET design (HSpice) Spring 2016

Implemented FINFETs in SG, IG, LP modes with balanced rise-fall delays and optimal leakage & switching power

Phased Lock Loop (PLL) operating at 800MHz (Cadence Virtuoso) Fall 2015

Designed schematic & layout of PLL consisting of VCO, loop filter, charge pump & PFD; with 100 MHz reference

Synchronous FIFO (Verilog- Modelsim) Fall 2015

Implemented a FIFO in RTL with n-bit Read/Write pointer and n-bit adder to detect full/empty FIFO to produce

ordered array from a random array of numbers