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JAZiO I/O Switching Technology. API. HAL. Topology. Protocol. Link Layer. Logical Spec. Electrical Spec. Transport Spec. Physical Layer. Switching Technology. Why Is Switching Technology Important?. What Makes I/O?. Switching Technology Determines I/O Performance. - PowerPoint PPT Presentation
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JAZiO™ Incorporated1
JAZiO JAZiO I/O Switching I/O Switching TechnologyTechnology
JAZiO™ Incorporated2
What Makes I/O?
API HALTopology Protocol
Link Layer
Physical Layer
Logical
Spec
Transport
SpecElec
trica
l Sp
ec
Switching TechnologySwitching
Technology
SwitchingTechnologyDetermines
I/OPerformance
Why IsSwitching
TechnologyImportant?
I/O performance may determine:Product
Performance
JAZiO™ Incorporated3
Switching Technologies
• Dominant switching technologies today:– Differential – Pseudo-Differential
• JAZiO technology is now available to challenge these current leaders
JAZiO™ Incorporated4
Differential
Fully differential receiver Great for simultaneous switching But two pins per data bit
Data0 Data0-+
DataN DataN-+
CLK -+
Lat
chin
g
Transmitter Receiver
Used in:HyperTransportRapidIOSPI-4 Phase 2LVDSSerial ChannelsEtc.
JAZiO™ Incorporated5
Pseudo-Differential
Constant VREF Less-precise receiver One pin per data bit
CLK -+
Lat
chin
g
Transmitter Receiver
Data0 Data0
DataNDataN
VREF
Used in:GTLPCIAGPSPI-4 Phase 1Rambus RSLDDREtc.
JAZiO™ Incorporated6
JAZiO Technology
Voltage/Timing References Two differential receivers per bit One pin per data bit
Can be used:Anywhere that
Pseudo-DifferentialOr Differential
Are used
VTR VTR-VTR
Transmitter Receiver
Data0
DataN
Data0
DataN
ExceptSerial
Channels
JAZiO™ Incorporated7
Three I/O Switching Technologies
VT
R
R
D0
VT
R-
R
D15
JAZiO
18 Pins
VR
EF
R
D0
R
D15
Pseudo- Differential
19 Pins
CL
K-
CL
K
R
D0-
D0
R
D15
-D
15C
LK
-C
LK
34 Pins
Differential
16 Bits of Each
JAZiO™ Incorporated8
JAZiO Solution
Data is driven coincidentally with these VTRs
DataInput
Like Differential except:VTR stands in for all the complements going in one directionVTR- stands in for all the complements going in the other direction
VTR- Provide alternating Voltage/Timing References switching at the data rate
One Bit Time
Next Bit Time
VTR
Two White Papers atwww.jazio.com
Two Differential Comparators are usedThe Blue Box selects the right comparator
DataOutput
VTR
VTR-
VTR-VTR
A
SL-
XorB
in
in
in
inout
out
Data Input
VTR XorA
B
SL
Steering Logic
Per Bit
Per 4 Bits
JAZiO™ Incorporated9
The receiver cell is: 22um x 55um
(Including routing channels)
A pad cell is:70um x 80um
A JAZiO receiver is 22% of the area of a bonding pad
JAZiO™ Incorporated10
JAZiO vs Differential
• So is JAZiO like Differential except with one pin per data bit?
• No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present
JAZiO™ Incorporated11
Attenuation/ISI
Source Destination
Lone Pulse
Source
DestinationMidpoint
Continuous Pulses
Signal at Destination is Centered Around the Midpoint
JAZiO™ Incorporated12
MIDPOINT
DATA
DATA-
Differential
MIDPOINT
DATA
VTR
JAZiO
VREFPseudo-Differential
DATA
Data Eye with Attenuation/ISIContinuous
PulseEYE
JAZiO Has MUCH LargerWorst-Case Data Eye
~40% Attenuation LonePulseEYE
Sig
nal
s d
rive
n t
he
sam
e fo
r al
l th
ree
tech
nol
ogie
s
JAZiO™ Incorporated13
JAZiO vs Differential
• So is JAZiO like Differential except with one pin per data bit?
• No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present
• A larger data eye can be used to:1. Increase data rate
2. Reduce power
3. Increase robustness
4. Reduce complexity
Or all four!!!
JAZiO™ Incorporated14
Parallel vs Serial Interface• JAZiO is for parallel interfaces• Some claim that high speed interconnect must be
serial due to large bit-to-bit skew• This leads to encoded serial data on a differential
pair and, sometimes, bundles of serial channels• Also leads to complexity, power, and large latency• JAZiO can deal with skew and retain the benefits
of low latency, parallel interface
JAZiO™ Incorporated15
JAZiO Deals with Skew• JAZiO is inherently better able to deal with
skew because data eye opens and closes when data crosses VTR not the midpoint
JAZiO™ Incorporated16
LateData
Midpoint Level
Bit-to-Bit Skew
Signals DrivenIdentically For:JAZiODifferentialPseudo-Diff
CONCLUSION:JAZiO is Inherently
More Immune to Skew
VREF
EyeOpeningVariance
Differential or Pseudo-Diff
VTR
EarlyData
No-SkewData
EyeOpeningVariance
JAZiO
NOTE:Same VariancesAt Trailing Edge
JAZiO™ Incorporated17
JAZiO Deals with Skew• JAZiO is inherently better able to deal with
skew because data eye opens and closes when data crosses VTR not the midpoint
• A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination
JAZiO™ Incorporated18
JAZiO Receiver Monitor
DataOutput
VTR-
A
XorB
in
in
in
inout
out
Data Input
VTR XorA
B Rec
eive
rM
onito
r
XORs ProvideReceiver Monitor
(Feedback to Source)
Can Detect Marginalities In System During Operation Before Failure
See White Papers atwww.jazio.com
JAZiO™ Incorporated19
JAZiO Deals with Skew• JAZiO is inherently better able to deal with skew
because data eye opens and closes when data crosses VTR not the midpoint
• A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination
• JAZiO can use two-VTR pairs offset in time and tuning cycles can be used to select the best pair on each bit
JAZiO™ Incorporated20
Destination Deskew withTwo VTR Pairs
Data
InV
TR
2V
TR
2
R
R
VT
R1
VT
R1
Sel
ect Data
Out
R2
VTR Pairs offset in time selected using receiver monitor
See White Papers atwww.jazio.com
JAZiO™ Incorporated21
Parallel vs Serial• A serial channel at 10 Gbps likely uses a
differential pair and transmits 10 bits for every 8 bits of data (encoding)
• Actual data rate per pin is 4 Gbps with huge die size, latency, and complexity penalties
• JAZiO second generation provides same data rate per pin without die size or latency penalty – and is easily expanded as wide as desired
Conclusion: No need for serial to invade the traditional domain of parallel buses
JAZiO™ Incorporated
What’s Needed for Finished Product?
Pseudo-Diff Technology
Small Eye1 Pin/Bit
DifferentialTechnology
Medium Eye2 Pins/Bit
JAZiOTechnology
Switching Technology
Enhancements Pre-E, Deskew, …
Engineering FinishedProduct
Enhancements Pre-E, Deskew, …
Lots ofEngineering
MediocreProduct
Enhancements Pre-E, Deskew, …
Lots ofEngineering
ExpensiveProduct
Enhancements Pre-E, Deskew, …
LessEngineering
GreatProduct
Large Eye1 Pin/Bit
Data EyePins/Bit
JAZiO™ Incorporated23
First Ever JAZiO Silicon Results
Demo Chip: 0.18u TSMC, Standard ESDEnhancements: No pre-emphasis, encoding, or deskew
Package: 120 Pin TQFP, 5nH Center-8nH Corner, <$1.00PC Board: FR4, No isolation between signals
Previous highest known data rate with these conditions:<400 Megabits/sec/pin
Lowest cost, Highest availability components
PAT GEN
DR
VR
s
RING OSC
M/S MASTER
PAT GEN
RC
VR
s
COMP
M/S SLAVE
DATA (16)
VTR (2)
9”BER
JAZiO™ Incorporated24
Power = 20 mW/bitSkew = 285 pS
Data Rate = 1.5 Gigabits/Sec/Pin
Results
VTR VTR-
JAZiO™ Incorporated25
JAZiO Roadmap
1st GenerationBasic JAZiO0.18u + BGA
2 Gb/sec/pin
2001
3rd GenerationDeskew
Pre-emphasisDual VTR
0.10u + FC BGA
6 Gb/sec/pin
2005
2nd GenerationDeskewSimple
Pre-emphasis0.13u + BGA
4 Gb/sec/pin
2003
Dat
a R
ate
Per
Pin
Time
JAZiO™ Incorporated26
Announcements
• Dolphin Technology (www.dolphin-ic.com)– JAZiO design services partner
– Developing Super PHY with JAZiO technology
• Alliance Semiconductor (www.alsc.com)– 1st JAZiO licensee
– Developing high BW SRAM with JAZiO interface
– Sampling in Q2, 2002
JAZiO™ Incorporated27
Summary• JAZiO is basic I/O technology from which
excellent parallel buses can be built• Using JAZiO, parallel buses can achieve
very high performance – no need to move to serial buses
• JAZiO technology, with large data eye and pin efficiency, is the highest performance and lowest cost technology available