Jitter Fundamentals: Jitter Tolerance Testing with Agilent 81250 ParBERT

Application Note

Introduction

This document allowsdesigners of medium complexdigital chips to gain fast andefficient insight into the operation and performance ofCDR, clock system and jitter tolerance. This type of testingis different to conformancetesting and manufacturing test;this type of testing targets fastand efficient results on GO –NOGO and some qualitativebehavior. Whenever appropriate, this documentgives hints to close the gap forconformance and manufacturing test requirements, especially possibilities to calibrate the proposed test approach.

Figure 1: Agenda & Target

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Jitter Tolerance is:

-Jitter Tolerance – SONET,adapted by nearly all standards

-Sinusoidal Interference,Stressed Eye – 10GbE,optical

-Jitter Amplitude Tolerance(edge displacement!) – XAUI

-Compliance EYE, Common &Differential Mode Noise – PCIExpress

-Jitter Tolerance Mask, JitterMask

All these expressions deal withthe same issue: a receiver of digital data shall tolerate a certain amount of jitter. Theexpression ‘Jitter Tolerance’was originally established bythe SDH/SONET standard; inthe meantime it is adaptedinto most of the modern standards of 10GbE, FibreChannel, PCI Express, etc..Some other expressions haveemerged, fundamentally describing the same thing:Stressed Eye (especially forOptical RX).When dealing with jitter tolerance, we also find the socalled Jitter Tolerance Mask, orsimplified Jitter Mask withinthe documentation.

Jitter Tolerance

Figure 2: Jitter Toleramce Mask

This Jitter Tolerance Mask (seeFigure 2) is taken from the10Gbe standard (802.3ae,XAUI) [2], a similar maskappears for the 10G serialside. This is also similar within other standards, butparameter values may be different.

The intention for such a jittermask is to ensure margin forall types of frequency jitter,wander, noise, crosstalk andother variable system effects.Under these conditions areceive circuitry shall runproperly for a very low BERfigure ( often 10^-12 or lower).

The Jitter Mask defines two different areas:

In-band JitterPhase Lock Loop (PLL)/Cloak-Date-Recovery (CDR) areable to follow, and do notcause eye closure, so this is compensated on the receiverside and does not contributeinto the jitter budget. This isthe case if the PLL/CDR isable to compensate for >1 UI.The jitter mask can define avery high number of UI’s forlow frequencies, this numberdepends on the architecture of

the FIFO buffers. So this is not affected by the physical layer circuit performance; a test for itshould be once conductedwithin conformance testing. Sofor a first Receiver Test it is sufficient to check if thePLL/CDR circuitry works properly.

Outband JitterThese jitter components arebeyond the bandwidth ofPLL/CDR, they cause eye closure and are therefore critical for the BER performance, and so they needspecial care for evaluation.Apart from the sinusoidal part,the total out-band jitter is composed of random and further deterministic content.In the case of XAUI, the deterministic content should beat least .37UI on to of the.1UI sinusoidal. Furthermore,there should be .18UI randomjitter. All together this amountsto .65UI total jitter. So a XAUIreceiver has to work properlywith only 112ps stable datawithin a 320ps data cycle.

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Figure 3: Jitter Tolerance Test Strategy

Outbound jitter causes EyeClosure. As this is most critical, it needs careful characterization and is themost important issue to lookat. Therefore, within the TestStrategy proposed here, it isthe first step to deal with.

Inband Jitter should be tolerated by the DUT. A functional test should answerif the compensation works as expected. If the compensationworks, it is basically a matterof the design, it is able to compensate for a given numberof IUs (depending on the F.FOdepth). So to once verify forIUs is a task for ConformanceTesting.

For manufacturing tests thequestion is if a single device isworking and if it is goodenough. So a functional testwith some low speed clock jitter/wander will answer this.Depending on how much theprocess tolerances affect the outbound jitter tolerance, suchtests are necessary. But it isnot uncommon that chip customers request outboundjitter measurements on a 100%level to avoid surprises.

A (BERT-) pattern generatorstimulates the DUT with a pattern (PRBS, DJ/RJPAT or customer/ application specific)that contains a well defined(norm-conformant or customer/application-specific)amount of jitter possibly of alltypes (RJ, DJ, ISI, PJ, DCD,..)while simultaneously an external BERT-error detectoror a built in patternchecker/error counter checks(quantifies) the DUT’s errorperformance to stay below aspecified limit.

Test Strategy

The tactic to get insight step-by-step is:

Prerequesite: verify the receiver is workingat nominal settings for operation, with no stress.

1st step: - verify immunity to Out-bound Jitter- stress the receiver input byeye closure with different jitter components- inject a modulated eye withall RJ, DJ and PJ componentsup to and beyond the maximum allowed values - check for the BER figure.

2nd step: verify that the CDRis operating. For this testthere are two alternative scenarios possible:a) Use the SpectralDecomposition Tool with whiteNoise Jitter on the PatternGenerator Data; this is possible with any ParBERTanalyzer.

b) Use a modulated clock asext. Clock for PatternGenerator AND Error Detector.For this test it is importantthat the test system errordetector follows the modulation. For a ParBERT

3.3G this test needs to be performed below 10kHz due toembedded PLL restrictions. AParBERT 13G can do that atany modulation frequency.

3rd step: Test for conformance to maximum number of UI’s atlow frequency with help of FMor QM modulated clocksources. Again for a ParBERT3.3 G the restriction of <10KHzapplies.

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The First Step: Outbound Jitter

The first step of the TestStrategy is to verify JitterImmunity/Tolerance toOutbound Jitter:

Jitter injection/eye closureapplies to the Out-band partof the Jitter Mask. Here this ispure edge displacement (without SinusoidalInterference (SI). The edge displacement is basically aPhase Modulation (PM) of theedge. As the Jitter Mask contains the sinusoidal jittercomponent only, the total eyeclosure consists of sinusoidal +deterministic (ISI) + randomjitter.In case of XAUI the total jitterbudget is .65U; this consists of.1 UI sinusoidal + .37 UI deterministic + .18 UI randomjitter.A flexible and accurate combination of jitter components as: X % sinusoidal+ Y % deterministic + Z %random Jitter reduces thehassle of setup.

Figure 4: Eye Closure by edge displacement

Figure 5: Jitter Injection

Figure 5 shows the setup forJitter injection/eye closure byedge displacement (w/o SI): A ParBERT generator (3.3G,E4862B or 13.5G, N4872A) ismodulated via the ‘ControlInput’. We use Noise with 80MHz bandwidth, Sine at20MHz (or variable) andPulse/PRBS at up to 660Mb/s.The signals are put togetherwith help of power dividers11636B. In this case we usepower dividers to back-matchthe signals, and even thiscauses 6dB loss of the amplitude of the modulationsignal sources; the amplitudesprovided are still sufficient.

Using a Pulse/PatternGenerator with PRBS capabilityis a nice approach to emulateISI. With data rate of 660Mb/s,

which is above the bandwidthof the E4862B control Input,some additional ‘data smearing’(randomization) is achieved.Short polynomials like 2^5-1and 2^7-1 are preferred. For abi-modal jitter behaviour, the Generatorcan be used in Pulse mode,this delivers two discretepeaks. The generator outputconnects to the DUT sendingthe data modulated with a mix

of jitter components.

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Calibrating the Jitter Injection

The edge displacement setupcan be calibrated with help ofthe ParBERT Output TimingMeasurement (see Figure 6).This measurement separatesand reports RJ and DJ jittercomponents. In this case theDUT is replaced with a loop-back cable. This makes itpossible to reascertain the eyeopening of the modulated generator output. For close tolerances it is recommendedto check the eye closure foreach modulation content independently.

Figure 6: Calibrate the Jitter Injection

Figure 7: Stressed Eye

Stressed Eye

E/O converter testing in particular requires stressed eyeincluding SinusoidalInterference (SI), as Figure 7demonstrates. This adds a sinusoidal signal to the alreadydiscussed edge displacementfor further horizontal (amplitude wise) eye closure.This is performed with highfrequency (<1GHz typically). Tosimplify the setup, the randompart of the FM componentscan be omitted as the sinu-soidal amplitude is already asynchronous.

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Figure 8 shows the setup forStressed Eye including edge displacement and amplitudenoise (SI).The amplitude noise component is added to thedata output with the help of apower divider.

Figure 8: Stressed Eye Setup

Figure 9: Calibration for Stressed Eye

The calibration of the amplitude modulation can beperformed with the help of theParBERT Output LevelMeasurement (see Figure 9).

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Stressed Eye Signals

Stressed Eye applies to singleended signals driving the optical PHY. A Stressed Eye ismade by a combination ofEdge Displacement (PM) andLevel Modulation (AM). Theedge modulation is a combination of sinusoidal anddeterministic jitter. The ampli-tude/level modulation is sinusoidal.

On a differential signal, theamplitude/level modulation creates either common modenoise, which is harmless as itcancels at the receiver. Or it creates differential noise,which is dangerous, as itreduces the eye opening at thereceiver (see Figure 10).

Figure 10: Stressed Eye Signals & Noise on Differential Signals

The ParBERT 81250 generatorprovides the data on differential lines. To add themodulation signal, there mustbe power dividers added intoboth signal lines. When addingthese power dividers, the electrical length for both datalines between generator outputand DUT RX input must bethe same to keep the signaldifferential.The power dividers are built ofthree resistors to ensure proper termination in eachdirection. Trade-off is amplitude loss of 50 % throughthe divider. So for a specificswing, the data generator mustbe set for double amplitude.For common mode noise it isnecessary to modulate bothdata lines with the same signal. Therefore the noisemodulating from the ArbitraryWaveform Geenrator (AWG)must be split, with the help ofa power divider. This will provide the same amount ofnoise to both data lines with

Figure 11: Common/Differential Mode Noise Setup

clean isolation between dataand complement data line.

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Step 2: Verify PLL/CDR

The 2nd step of the TestStrategy is to verify that theCDR is operating. For this test thereare two alternative scenarios possible:

a) Use the SpectralDecomposition Tool with whiteNoise Jitter on the PatternGenerator Data, this is possible with any ParBERTanalyzer.b) Use a modulated clock asext. Clock for PatternGenerator AND Error Detector.For this test it is importantthat the test system errordetector follows the modulation. For a ParBERT3.3G this test needs to be performed below 10kHz due toembedded PLL restrictions. AParBERt 13G can do that atany modulation frequency. Thisis same setup discussed understep 3.

Figure 12: Verify PLL/CDR

Figure 13: PLL/CDR Verification Setup

This is the setup for CDR/Cut-Off Verification: AParBERT generator (3.3G,E4862B or 13.5G, N4872A) ismodulated via the ‘ControlInput’. We use Noise with 80MHz bandwidth provided fromAgilent 33250A AWG. The generator output connectsto the DUT, sending data withrandom jitter. The amount of jitter modulation should besmall compared to the limit of maximum input tolerance. Apractical value is 5 .. 10% ofUI typically. The DUT will tolerate this amount of jitter.The CDR follows the low frequency content, but filtersthe high frequency content. The ParBERT analyzer therefore will detect the lowfrequency content and reportthis as constant jitter amplitude up to the cut-offfrequency in the JitterDecomposition Tool. From thecut-off the energy decreases.

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Figure 14: Result of PLL/CDR Verification

Result of PLL/CDR Verification

One model of the JitterDecomposition Tool is the charactertization of aCDR/PLL device. This asumesthe device is stimulated with adata signal modulated with jitter of wide band noise(white noise). The CDR willfilter this noise according thebandwidth of it‘s feedback loopdesign. The feedback has acertain bandwith, so there willoccur jitter supression abovethis frequency. Or in otherwords: the device output will follow the low frequency jitterbut suppress the high frequency contents of the jitter.The figure here gives such anexample with cut-off at 1MHz,and there is some peaking atthe roll-off point.

Figure 15: Verify Jitter/Wander of Multiple UI‘s

Step 3The third test step deals withthe capability of compensatingjitter >1Ui up to a maximumnumber of UI’s at low frequen-cy. So this can be jitter orwander.Here we have to take the limi-tations of the ParBERT clock distribution into account, asthere is some bandwidth limitation in the E4808A clockmodule as well as within theE4861B data module. Thisdoes not apply for the E4809Aclock module working togetherwith the N4872A 13.5Gb/s data generators.The jitter modulation is sinusoidal, the modulating frequency should be the lowervalue from:either 10 kHz ( limit byE4808A + E4861B) or mini-mum frequency from jitter mask, inthis case 22.1 kHz In this example the modulating frequency should be chosen for10kHz.

The ParBERT with 13.5G mod-ules does not have such a

multiple UIs can be performedat any frequency.

bandwidth limitation, as thereis a mode with direct clockdistribution. Therefore thiskind of jitter modulation with

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Step 3: Multiple UI Clock Jitterby FM Modulation

To achieve a clock signal modulation with multiple UI‘s,there is the need for a sourcewhich can provide such a modulated clock. There are several possibilities for obtaining such a modulatedclock. This setup heredescribes the use of a signalgenerator with FM modulationcapability. The FM modulationcan be achieved either withinternal or external modulator.In the case of ext. Modulatorthe 33250A AWG can be used.Using ParBERT 3.35G limitsclock modulation to 10kHz. The desired amount ofjitter/wander in terms of UI'scan be achieved by a FM(Frequency Modulation) definedby its deltaF (modulation frequency). The delta F can bederived with help of this for-mula [3]: DeltaF=2π *Jr*Ja, Jr:Jitter Frequency, Ja: JitterAmplitude. With the XAUIexample (needs 8.5 UI's @10kHz ) this results in a deltaF of 534kHz.

So the AWG is set to: Sine,Frequency: 10kHz, Amplitude:534mV. The Modulator withinthe Signal Generator is set toFM with modulation range of1MHz/V

For the analysis we need to consider two scenarios:

1: the DUT output is in phasewith the recovered clock. Inthis case the ParBERT analyzerruns on the same jitteredclock as the generator, a singleclock configuration is sufficient. If the DUT followsproperly, the real-time BERmeasurement can be performed.

2: the DUT has an embedded reference clock. In this casethe DUT includes Fifo’s to

compensate for clock tolerance.So the output data needs tobe sampled based on the reference clock, which needs atwo clock

Figure 16: Multiple UI Clock Jitter by FM Modulation

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Setup 3B: Multiple UI ClockJitter

Another approach to obtainclock modulation is with helpof QM (quadratur modulation)[4]. This is the most flexiblesetup for clock jitter generation, limited only bybandwidth of AWG and carrierfrequency of the modulator.Now the setup here describesthe use of a signal generatorwith IQ modulation capability.The IQ modulation can beachieved either with internalor external wideband AWG.QM enables a large amount ofUI‘s up to high modulationfrequencies, see the comparison of FM and QM modulation below. To make useof the high frequency clockmodulation, the ParBERT13.5G modules with clockbandwidth from DC to maxclock rate are used are usedin this setup.

In case of XAUI (modulationBW 22kHz, 8.5 UI‘s) we setupthe I / Q signal as can beseen in Figure 18.

Table 1 compares the principlelimits of FM vs. QM modulation. QM can providemore UIs at higher modulationrates. The maximum number ofUI that could be generated bythe using the full 1 GHz bandwidth at 10 kHz and 1MHz modulation rates. Usingthe equation:B = 2*(π*UIpp + 1)*fm(Carson's Rule - NOTE: Thisis an approximation.Bandwidth is actually infinite.)where B = bandwidth (1 GHz)and fm = modulation rate (10kHz and 1 MHz) we can solvefor the maximum peak-peakjitter, UIpp.Solving for UIpp and substitut-ing for fm, the results are: fm= 10 kHz ---- Max UIpp =16,000, fm = 1 MHz ----- MaxUIpp = 160 (Approximately)

Figure 17: Multiple UI Clock Jitter by QM Modulation

FFMM

IInnssttrruummeennttsscclloocckk ffrreeqq ((ccaarrrriieerr))mmoodduullaattiioonn ffrreeqquueennccyymmaaxx ## UUIIss (10kHZ / 1Mhz)

E8267C PSG + hbw AWG20GHz1GHz

16000 / 160

QQMMTTaabbllee 11:: CCoommppaarriinngg FFMM aanndd QQMM ffoorr JJiitttteerr GGeenneerraattiioonn

Figure 18: I/Q Signals for XAUI

E4422B + 332504 GHz40MHz

600 / 6

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References

[1]: Agilent 81250 ParBERtJitter Injection and AnalysisCapabilities, Agilent 5988-9756EN

[2]: IEEE 802.3ae, 10GbEStandard

[3]: Understanding Jitter andWander Measurements andStandards, Agilent 5988-6254EN

[4]: Quadrature ModulatedJitter Injection, Timothy J.Peters, Agilent Technologies,Inc, Jul 03

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