J.L. BIARROTTE, S. BOUSSON, C.JOLY, T. JUNQUERA, J. LESREL, L.LUKOVAC

Institut de Physique Nucléaire (CNRS/IN2P3) 91406 Orsay – France

O. LE DORTZ, J-F GENAT, H. LEBBOLO, D. MARTIN

LPNHE PARIS (CNRS/IN2P3) France Abstract: Within the framework of the current European research programs EUROTRANS and EURISOL on High Intensity Proton Accelerators, and particularly on the R&D on superconducting SPOKE cavities, a Low Level Radio Frequency Digital system is developed at IPN Orsay in collaboration with LPNHE Paris, both IN2P3-CNRS laboratories. Due to Lorentz's forces, mechanical vibrations or RF power perturbations, the amplitude and phase of the electromagnetic wave inside the cavities need to be controlled. Other goals are a better reliability, a high level of integration and a fast response time of the feedback control system. Digital techniques should allow to meet all of these goals and provide an improved flexibility compared to analog techniques, with the integration of the main algorithms and functions into an FPGA. The main design options and some preliminary results are presented.

LPNHE PARIS

Stability of the amplitude :0.1% Stability of the phase of the accelerating field : 0.5° Response time : less than 10 µs Reliability close to 100% implying a strong

integration and an efficient monitoring and control software

TECHNICAL TECHNICAL TRENDSTRENDS

Use of standard instrumentation

Hardware structure

Development of Cavity IQ and PID

models

Integration

Use of ADC, DAC,and digital processors

I/Q modulator

AMPLI Down converter system

ADC

IQDemodulation

Control andMonitoring

PID

DAC

I/Q modulator

Communication block

Feed forward

FPGA

Main loop

MATLAB SIMULINK

PXI crate using a PCI bus linkfor the monitoring and control of the FPGA’s algorithmsparameters

ALTERA STRATIXFPGA with internalfast blocks

PXI card

SIMULATIONSSIMULATIONS

14 bits ADC and DACTr ~ 5µs with PI

IQ Demodulation with8 interleaved samples

VHDL simulation of the PXI card

PXI CARDPXI CARD

x 8

Clock 80MHz

multiplierBand pass

filter

IF=10MHz

Ref 352.2MHz

Ref 10MHz

RF generator

Hybridcoupler

90°

Hybridcoupler

90°Combiner

RF1

IF1

RF2

IF2

OL1

OL2

Image reject mixer

G

G G G GAmplification and matching AA

AA A

A

G

342.2MHz

DOWN CONVERTER SYSTEMDOWN CONVERTER SYSTEM

GOALSGOALS

INCI_InTRAN_InREFL_InREFC_In

14 bit ADCAD6645

14 bit ADCAD6645

14 bit ADCAD6645AD

8138

AD8138

cPci Interface Cyclone

EP1C4 BGA324

CompactPCI / PXI

PROMEPCS1

Vregs

3.3 et 5V

-12V

3.3 et 1.5V (FPGA)

+5 et -5V (Analog)

IQ Detection Stratix

EP1S20 BGA484

Active Serial Config

ConfigFPP

JTAGPCK111

Clock driver

80 MHz Clk

14 bit ADCAD6645

14

Add, Dat, R/W

AD8138

AD8138

x4 x4

DACAD9764

DACAD9764

14

14

AD8047

AD8047 256k 18bits 4ns RAMCY7C1327F-133AC

ClocksLVPECL PROM

EPC4

33 MHz Clk

352.2 MHz

RF_Mod

Dig_In4

4Dig_Out

Modul.AD8345

14

AD8047DAC

AD9764

REFC_In INCI_In REFL_In TRAN_In

Pi Pr Pt

SCHEDULESCHEDULE

Tests of the global system with a copper cavityat T°=290K

Development of a second PXI cardfor the research program EUROTRANS :fault-tolerance

Tests of the global system with a SPOKE cavityat T°=4.2K

Digital processing latency: 100ns35 x 9 bit multipliers

SIMULINK modeling of the cavity and feedback loopSimulink simulation results