Jntu Hyd 2 2ece Eca Set 3

S.37Electronic Circuit Analysis (April/May-2012, Set-3) JNTU-Hyderabad

( JNTU-Hyderabad ) B.Tech. II-Year II-Sem.

Code No: R09220402/R09

II B.Tech. II Semester Examinations

April/May - 2012

ELECTRONIC CIRCUIT ANALYSIS (Common to ICE, E.COMP.E, ETM, EIE, ECE)

Time: 3 Hours Max. Marks: 75

Answer any FIVE questions

All questions carry equal marks

- - -1. (a) When n-identical stages of amplifier are cascaded? Derive the expression for lower and upper cutoff frequencies.

(Unit-II, Topic No. 2.1)

(b) Explain the effect of coupling capacitor in a CE amplifier on low frequency response of amplifier. [8+7](Unit-II, Topic No. 2.1)

2. (a) A transistor supplies 0.8 W to a 5 k load. The zero signal DC collector current is 30 mA and the DC collectorcurrent with signal is 36 mA. Determine the percent second-harmonic distortion. (Unit-VII, Topic No. 7.4)

(b) Define conversion efficiency. Determine the maximum value of conversion efficiency for a series-fed class Apower amplifier. [7+8] (Unit-VII, Topic No. 7.2)

3. (a) For the circuit shown in below figure, compute AI, A

V, A

VS, R

i and R'

o. The transistor h-parameters are h

ie = 1.1

k, (hfe = 50, h

re = 2.4 x and h

oe = 25 µA/V). (Unit-II, Topic No. 2.1)

VCC

100 Ω

500 Ω

8 K

100 K

3 K Vo

R′o

−VEE

−

+VS

VCC

100 Ω

500 Ω

8 K

100 K

3 K Vo

R′o

−VEE

−

+VS

Figure

(b) Compare direct coupled amplifiers with RC coupled amplifier. [10+5] (Unit-II, Topic No. 2.4)

4. (a) Obtain CC ‘h’ parameters interms of CE parameters. (Unit-I, Topic No. 1.3)

(b) For a CE amplifier, calculate the voltage gain, input impedance output impedance, current gain. If RL = 10 kΩ,

hie = 1.1 kΩ, h

re = 2.5 × 10–4, h

fe = 50, h

oe = 24 µA/V. [7+8] (Unit-I, Topic No. I.3)

5. (a) Why a FET cannot be explained with h-parameters? (Unit-IV, Topic No. 4.1)

(b) Derive an expression for transconductance using FET model. (Unit-IV, Topic No. 4.1)

(c) Draw and explain the FET high frequency model. [3+6+6] (Unit-IV, Topic No. 4.1)

S e t - 3S o l u t i o n s

S.38 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

B.Tech. II-Year II-Sem. ( JNTU-Hyderabad)

6. (a) Sketch a circuit of a crystal-controlled oscillator and explain its function. (Unit-VI, Topic No. 6.5)

(b) Explain the frequency-stability criterion for a sinusoidal oscillator. [8+7] (Unit-VI, Topic No. 6.6)

7. (a) Compare neutralisation and unilaterlisation methods of tuned amplifiers. (Unit-VIII, Topic No. 8.7)

(b) What are the limitations of stagger tuned amplifiers? (Unit-VIII, Topic No. 8.6)

(c) What happens when number of stages is increased in single tuned cascaded amplifiers? [5+5+5](Unit-VIII, Topic No. 8.4)

8. (a) What is negative feedback? Discuss how it can improve stability in an amplifier. (Unit-V, Topic No. 5.1)

(b) Find Avf, R

if, R

of, for the circuit shown in figure. R

s = 0, h

fe = 50, h

ie = 1100 Ω and h

re and h

oe are negligible. Assume

identical transistors. [5+10] (Unit-V, Topic No. 5.4)

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

Figure



Q1. (a) When n-identical stages of amplifier are cascaded. Derive the expression for lower andupper cutoff frequencies.

Answer : April/May-12, Set-3, Q1(a) M[8]For answer refer Unit-II, Q4, Q5.(b) Explain the effect of coupling capacitor in a CE amplifier on low frequency response of

amplifier.Answer : April/May-12, Set-3, Q1(b) M[7]Effect of Coupling Capacitor ‘C

C’ on Low Frequency Response of CE Amplifier

The low frequency model for CE amplifier with coupling capacitor CC is as shown in figure (i).

~

RS

CC

+

−

VS

−

+

R1||R2 Ri

E

hfe IbRL

CBIb

ViVo

+

–

~

RS

CC

+

−

VS

−

+

R1||R2 Ri

E

hfe IbRL

CBIb

ViVo

+

–

Figure (i): Low Frequency Model for CE Amplifier with Coupling Capacitor

For large values of emitter bypass capacitor (CE), the low frequency gain does not experience any reduction in its

value and the emitter resistance ‘RE’ is effectively bypassed.

The reactance of coupling capacitor (CC) is negligible for mid frequency range.

The lower 3-dB frequency (f1) is given as,

f1= '

1

2 ( )s i CR R Cπ + ... (1)

Where, R'1 = R1 || R2 || Ri

Ri = hie (for ideal CE)and Ri ~ hie + (1 + hfe) RCE (when capacitors series resistance is considered).Therefore, inorder to achieve good low frequency response, the capacitors CC and CE must be maintained large.

Q2. (a) A transistor supplies 0.8 W to a 5 k load. The zero signal DC collector current is 30 mA and theDC collector current with signal is 36 mA. Determine the percent second-harmonic distortion.

Answer : April/May-12, Set-3, Q2(a) M[7]Given that,

For a transistor,AC power supplied (P

A.C) = 0.8 W

Load resistance, RL = 5 kΩ

DC collector current, ICQ

= 30 mACollector current with signal i.e., I

CQ + B

0 = 36 mA ... (1)

Percentage in second-harmonic distortion, D = ?

SOLUTIONS TO APRIL/MAY-2012, SET-3, QP



The expression for percentage of second harmonicdistortion is given as,

% D= 1001

2 ×B

B... (2)

Where, B1 and B2 are constants.

(i) Computation of B2

Since, B2 = B

0... (3)

From equation (1), we have,

B0= 36 – ICQ

= 36 – 30

∴ B0

= 6 mA

⇒ B2

= 6 mA [QFrom equation (3)] ... (4)

(ii) Computation of B1

Since (PA.C

)D

= 0.8 W

We have,

(PA.C)D = LL RBRB 22

21 2

1

2

1+

∴ ][2

1 22

22 BBRL + = 0.8

])106([1052

1 2321

3 −×+×× B = 0.8

⇒ 21B = 3105

6.1

× – (6 × 10–3)2

∴ 21B = (0.32 × 10–3) – (36 × 10–6)

21B = 2.84 × 10–4

∴ B1= 0.016852

∴ B1 = 16.852 mA ... (5)

On substituting equations (4) and (5) in equation(1), we obtain,

% D = 10010852.16

1063

3

××

×−

−

% D= 35.6

%6.35=∴ D

(b) Define conversion efficiency. Determinethe maximum value of conversionefficiency for a series-fed class A poweramplifier.

Answer : April/May-12, Set-3, Q2(b) M[8]For answer refer Unit-VII, Q3, [Note: Exclude, Topic:

Importance of Position of Operation point and CollectorEfficiency].

Q3. (a) For the circuit shown in below figurecompute AI, AV, AVS, Ri and R'o. Thetransistor h-parameters are hie = 1.1 K,hfe = 50, hre = 2.4 × and hoe = 25 µµµµµA/V.

VCC

100 Ω

500 Ω

8 K

100 K

3 K Vo

R′o

−VEE

−

+VS

VCC

100 Ω

500 Ω

8 K

100 K

3 K Vo

R′o

−VEE

−

+VS

FigureAnswer : April/May-12, Set-3, Q3(a) M[10]Note: In the given question value of the hre is incomplete.

Given that,

For a circuit,

hie = 1.1 k

hfe

= 50

hre = 2.4 × 10–4 (Assume)

hoe

= 25 µA/V

AI = ?, A

V = ?, A

VS = ?, R

i = ?, R'

o = ?

VCC

100 Ω

500 Ω

8 k

10 k

3 k Vo

R′o

−VEE

−

+VS

VCC

100 Ω

500 Ω

8 k

10 k

3 k Vo

R′o

−VEE

−

+VS

Figure (1)



Both the stages in figure (1) are in common emitter configuration.

The h-parameter equivalent circuit of two stage amplifier in CE-CE configuration is shown in figure (2),

~

1ci

V2

RS=10 kΩ

−+VS

+

− −

+

V1

8 kΩ

1iR

10R2i

R20R RO

21R =3 kΩ

Vo

2ER=100 Ω

1bI

2bI

2Ic

1ER500 Ω

=~

1ci

V2

RS=10 kΩ

−+VS

+

− −

+

V1

8 kΩ

1iR

10R2i

R20R RO

21R =3 kΩ

21R =3 kΩ

Vo

2ER=100 Ω

1bI

2bI

2Ic

1ER500 Ω

=

Figure (2)

Second Stage Analysis

Here, 2ER = R

L

∴ hoe

RL = (25 × 10–6) × 100

= 0.0025 < 0.1

Since,

hoe

RL < 0.1, approximate analysis method is used.

Current Gain (2iA )

2i

A = – 2

2

b

E

I

I≈ – h

fe

= – 50

502

−=∴ iA

Input Resistance (2iR )

2i

R = hie + (1 + hfe) 2ER

= 1.1 × 103 + (1 + 50)100 = 6.2 × 103

Ω=∴ k2.62i

R

Voltage Gain ( 2VA )

2VA =

o

2

V

V = 2

22

i

Li

R

RA

= 3

3

102.6

)103(50

×××−

= – 24.194

194.242

−=∴ VA



First Stage Analysis

The net load resistance 1LR of this stage is obtained

by,

2iR

1CR

1LR

2iR

1CR

1LR

Figure (3)

1LR =

21|| iC RR

= 21

21

iC

iC

RR

RR

+×

= 33

33

102.6108

102.6108

×+××××

= 3.49 × 103 ≈ 3.5 k

Ω=∴ k5.31LR

Current Gain ( 1iA )

1i

A = 1

1

c

b

I

I

− ≈ – hfe

= – 50

501

−=∴ iA

Input Resistance ( 1iR )

1i

R = hie + (1 + hre) 1ER

= 1.1 × 103 + (1 + 50) 500 = 26.6 × 103

Ω=∴ k6.261i

R


1VA =

1

2

V

V=

1

11

i

Li

R

RA

= 3

3

106.26

105.350

×××−

= – 6.58

58.61

=∴ VA

Output Resistance

Output admittance,

1oy = hoe – Sie

refe

Rh

hh

+

= 25 × 10–6 – 33

4

1010101.1

104.250

×+××× −

= 2.39 × 10–5

1oy = 2.39 × 10–5 A\V

1oR =

1

1

oy = 51039.2

1−×

= 41.8 × 103

141.8koR∴ = Ω

Output impedance of the first stage, considering

1CR ,

'1oR =

1 1||C oR R

= 1 1

1 1

C o

C o

R R

R R

×+

= 33

3

108.41108

108.41108

×+×××× 3

= 6.7 × 103

'1oR = 6.7 kΩ

'1oR is the source resistance for the second stage,

Hence,

2oy = hoe –

1

'

fe re

ie o

h h

h R+

= 25 × 10–6 – 33

4

107.6101.1

104.250

×+××× −

= 2.35 × 10–5

2oy = 2.35 × 10–5

2oR =

2

1

oy = 51035.2

1−×

= 42.6 × 103

2

42.6koR∴ = Ω



2oR is the output impedance of second transistor by

considering 2ER ,

Ro= 2 2

2 2

o E

o E

R R

R R

×+ ( )

2 2| |o ER RQ

= 99.76

99.76oR∴ = Ω

Overall Current Gain (Ai)

Ai=

1

1

2

2 ic

bi A

I

IA

−

2iR

1CR

1cI2bI

C1

2iR

1CR

1cI2bI

C1

Figure 4

⇒ 1

2

c

b

I

I= 1

2 1

C

i C

R

R R

−+

= 33

3

108102.6

108

×+××−

= – 0.563

1

2

c

b

I

I= – 0.563

∴ Ai=

1

1

2

2 ic

bi A

I

IA−

= – (–50) (–0.563) (–50) = 1407.5

5.1407=∴ iA

Overall Voltage Gain (AV

)

AV = 1

oV

V = 2

oV

V = 1

2

V

V

= 12 VV AA

= – 24.194 × (– 6.58) = 159.2

2.159=∴ VA

Overall Voltage Gain ( SVA )

Considering source resistance RS, we get,

SVA =

+ Si

iV RR

RA

1

1

= 159.2 × 33

3

1010106.26

106.26

×+××

= 115.7

7.115=∴SVA

(b) Compare direct coupled amplifiers withRC coupled amplifier.

Answer : April/May-12, Set-3, Q3(b) M[5]

For answer refer Unit-II, Q31, Topics: RC Coupling,Direct Coupling.

Q4. (a) Obtain CC ‘h’ parameters interns of CEparameters.

Answer : April/May-12, Set-3, Q4(a) M[7]

The h-parameter model of CE configuration is shownin figure (1),

HreVce–

hie

+

BIb

Vhe

Ic

Vcehoehfe Ib

HreVce–

hie

+

BIb

Vhe

Ic

Vcehoehfe Ib

Figure (1)

The h-parameter model of CE configuration is redrawnin CC configuration is as shown in figure (2) with Vce = – Vec

hfe Ib hoe

IeIbhieB

Vce

E

+

–

–+hre Vce

C

ebV hfe Ib hoe

IeIbhieB

Vce

E

+

–

–+hre Vce

C

ebV

Figure (2)

Applying KVL at the inner loop, we get,

Vbc

– hie

Ib – h

re V

ce – V

ec= 0

⇒ Vbc

= hie

Ib + h

re V

ce + V

ec

= hie

Ib – h

re V

ec + V

ec(Q V

ec = – V

ce)

⇒ Vbc

= hie

Ib +(1 – h

re)V

ec... (1)



Applying KCL at node E, we get,

Ie

= – Ib – h

feIb + h

oe V

ec

Ie = – (1 + hfe) Ib + hoe Vec ... (2)

For CC configuraton,

Vbc

= hic

Ib + h

rc V

ec... (3)

Ie

= hfc

Ib + h

oc V

ec... (4)

hic in Terms of CE Configuration

From equation (3),

hic = 0=ecVb

bc

I

V

= 0

)1(

=

−+

ecVb

ecrebie

I

VhIh

[ From equation (1)]

= b

bie

I

oIh +

hic = hie

ic ieh h∴ =

hrc

in Terms of CE Configuration

From equation (3)

hrc

= 0b

bc

ec I

V

V =

= 0

)1(

=

−+

bIec

ecrebie

V

VhIh

[Q From equation (1)]

= ec

ecre

V

Vh )1(0 −+

hrc = 1 – hre

Since,

hre

< < 1

hrc

= 1

1rch∴ =

hfc

in Terms of CE ConfigurationFrom equation (4), we get,

hfc = 0=ecVb

e

I

I

= 0

)1(

=

++−

ecVb

ecoebfe

I

VhIh

= b

bfe

I

Ih 0)1( ++−

= – (1 + hfe

)

(1 )fc feh h∴ = − +

hoc is Terms of CE configurationFrom equation (4),

hoc

= 0=bIec

e

V

I

= 0

)1(

=

++−

bIec

ecoebfe

V

VhIh

= ec

ecoe

V

Vh+0

= hoe

oc oeh h∴ =

(b) For CE amplifier, calculate the voltagegain input impedance output impedance,current gain. If RL = 10 ΩΩΩΩΩ, hie = 1.1 kΩΩΩΩΩ,hre = 2.5 × 10–4, hfe = 50, hoe = 24 µµµµµA/V.

Answer : April/May-12, Set-3, Q4(b) M[8]Given that,

For a CE amplifier,

RL = 10 kΩ

hfe

= 50

hoe = 24 µA/V = 24 × 10–6 A/V

hre

= 2.5 × 10–4

hie

= 1.1 kΩ = 1100 ΩCurrent gain (AI) = ?

Input impedance (Zi) = ?

Voltage gain (AV) = ?

Output impedance (Zo) = ?

Assuming RS = 1 kΩ.



The CE hybrid models is as shown in figure (i).

RL VoVb

+

−−+

B C

ICIb

hie

RS

VS

hie.VC hfe.Ib hoe

E −

+

RL VoVb

+

−−+

B C

ICIb

hie

RS

VS

hie.VC hfe.Ib hoe

E −

+

Figure (i): Hybrid Model for CE Amplifier

Current Gain (AI)

The expression for current gain, AI of a single stage CE amplifier is given by,

AI=

Loe

fe

Rh

h

.1+−

= 36 101010241

50

×××+−−

AI= – 40.32

32.40gain,Current −=∴ IA

Input Impedance (Zi)

The expression for input impedance,

Zi of a single stage CE amplifier is given by,

Zi= h

ie + h

re. A

i. R

L

= 1100 + (2.5 × 10–4)(– 40.32)(10 × 103)

= 1100 – 100.8

Zi= 999.2

Input impedance, 0.999kiZ∴ = Ω

Voltage Gain (AV)

The expression for voltage gain, AV of a single stage CE amplifier is given by,

AV

= i

LI

Z

RA .

= 3

3

10999.0

101032.40

×××−

= – 403.6

6.403gain,Voltage −=∴ VA



Output ImpedanceThe expression for output admittance, Y

o of a single stage CE amplifier is given by,

Yo

= hoe

– Sie

refe

Rh

hh

+.

Yo = (24 × 10–6) )101(1100

105.2503

4

×+××−

−

= 24 × 10–6 – 5.952 × 10–6

∴ Yo= 18.048 × 10–6

Output impedance,

Zo

= oY

1

= 610048.18

1−×

Zo

= 55.407 × 103

Output impedance, 55.407koZ∴ = Ω

Q5. (a) Why a FET cannot be explained with h-parameters?Answer : April/May-12, Set-3, Q5(a) M[3]

The h-parameter model of a BJT in CE configuration is shown in figure (1).

+–

BIb hie Ic

C

VC

EE

Vb hreVc hfeIb

oe

1

h+–

BIb hie Ic

C

VC

EE

Vb hreVc hfeIb

oe

1

h

Figure (1)

and the small signal model of FET is CS configuration is shown in figure (2).

IdD

Vds

SS

Vgs

gmVgs

G

rd

IdD

Vds

SS

Vgs

gmVgs

G

rd

Figure (2)



From figure (1) it is clear that the output current generated depends on the input base current. But, FET being avoltage controlled device, the output current generated must depend on the input voltage, which is not possible using h-parameter model.

In addition to the above characteristic, the presence of feedback from output to input through hre

parameter is alsomakes the h-parameter models invalid for FET as shown in figure (1).

Thus, a FET amplifier cannot be analyzed using h-parameter model. However, the FET model shown in figure (2) is alow frequency model and is not valid in the high frequency range.

(b) Derive an expression for transconductance using FET model.


Transconductance ‘gm’ is defined as the ratio of change of current at the output to the change in the input voltage

and given by,

GS

Dm V

Ig

∂∂=

[Q Relating to drain current, ID] ... (1)

Now, consider the relationship between ID and V

GS is non-linear. Therefore, the Schokley’s equation when the terms

are non-linear is given by,

IDS

=

2

1

−

P

GSDSS V

VI ... (2)

Differentiating ‘ID’ with respect to V

GS, then we get,

GS

DS

V

I

∂∂

=

−⋅

−⋅

PP

GSDSS VV

VI

112

GS

DS

V

I

∂∂

=

−

−

P

GS

P

DSS

V

V

V

I1

2... (3)

Now, equating equations (1) and (3), we get,

gm

=

−

−

P

GS

P

DSS

V

V

V

I1

2... (4)

From equations (2) and (4) can be written as,

gm

= DSS

DS

P

DSS

I

I

V

I2− =

P

DSDSS

V

II ⋅−2

= DSDSSP

IIV

⋅−2

2

m DSS DSP

g I IV

∴ = ⋅



Hence proved.

Where,

gm

= Transconductance

IDS

= Saturation drain current

IDSS

= It is the value when the gate is shorted to source i.e., VGS

= 0

VP

= Pinch-off voltage.

(c) Draw and explain the FET high frequency model.

Answer : April/May-12, Set-3, Q5(c) M[6]

The high frequency model of FET is as shown in figure,

GCgd

D

Cds

S

Cgs

S

gmVgs rd

GCgd

D

Cds

S

Cgs

S

gmVgs rd

Figure : High Frequency Model of FET

High frequency model of FET amplifier is obtained by adding capacitance between the nodes of FET low frequencymodel C

gs, C

ds and Cds are the internal capacitances which are responsible for feedback from output to input and decrease

of voltage amplification at higher frequencies.

Where,

Cgs

– Barrier capacitance between gate and source

Cgd

– Barrier capacitance between gate and drain

Cds

– Drain to source capacitance of the channel.

The various parameters of FET with their corresponding magnitudes are as listed in table-1.

Device Parameter gm

rd

Cds

Cgs

,Cgd

rgs

rgd

JFET 0.10-10 mA/VMΩ 0.1-1 pF 0.1.1 pF 1-10 >108 Ω >108 Ω

MOSFET 0.1-20 mA/V 1-50 kΩ 0.1.1 pF 1-10 pF >1010 Ω >1014 Ω

Table 1: Parameter Values of FET (JFET and MOSFET)

Q6. (a) Sketch a circuit of a crystal-controlled oscillator and explain its function.


For answer refer Unit-VI, Q21, Topic: Working of Quartz crystal.



(b) Explain the frequency-stability criterion for a sinusoidal oscillator.


For answer refer Unit-VI, Q23, Q24, Topic: Frequency Stability.

Q7. (a) Compare neutralisation and unilaterlisation methods of tuned amplifiers.


The comparison of between neutralization and unilateralisation are as follows,

Neutralisation Unilateralisation

1. Neutralisation is one of the technique used for 1. Unilateralisation is a special case of neutralisation

reducing the feedback effect provided by inter where-in a bilateral network is converted into a

junction capacitance Cb'C

to obtain better stability. unilateral network.

2. Achieves stability only for a certain band of 2. Achieves stability at almost all frequencies.

frequencies.

3. It removes only reactive feedback. 3. It removes both resistive as well as reactive feedback

effect.

4. It is highly dependent on cancellations. 4. It is less dependent on cancellations.

5. It attempts to eliminate feedback to maximum 5. It performs perfect elimination of undesired feedback.

possible extent.

6. No miller effect is observed. 6. It undergoes miller effect.

(b) What are the limitations of stagger tuned amplifiers?


The following are the limitations of stagger tuned amplifiers,

1. It provides reduced selectivity.

2. The tuning of most tank circuits is critical.

3. It has low input impedance at high frequencies.

4. Needs large number of IF stages.

5. Simultaneous maintenance of broad bandwidth and high gain is required.

(c) What happens when number of stages is increased in single tuned cascaded amplifiers?

Answer : April/May-12, Set-3, Q7(c) M[5]

For answer refer Unit-VIII, Q24.

Q8. (a) What is negative feedback? Discuss how it can improve stability in an amplifier.


Negative Feedback

For answer refer Unit-V, Q1, Topic: Negative Feedback.

Stability

For answer refer Unit-V, Q6, Topic: Gain Stability.



(b) Find Avf, Rif, Rof, for the circuit shown in figure 9. Rs = 0, hfe = 50, hie = 1100 ΩΩΩΩΩ and hre and hoe arenegligible. Assume identical transistors.

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

Figure


Given that,

For a circuit, with two-identical transistors,

RS= 0

hfe

= 50

hio

= 1100 Ω

hre and hoe are negligible (i.e., hre = hoe = 0).

The given circuit is as shown in figure (i).

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

VCC

50 k 10 k 50 k 10 kCb

Cb

Q2

2 k50 k50 k

2 k

100 Ω 4.2 k

Vi

5 µf

Q1

Figure (i)

The input circuit is obtained by making Vo = 0. Hence, the first emitter how consists of a in figure (ii).

The output circuit is obtained by making Ii = 0. This provides a resultant circuit with the series combination of look

and 4.2 k as shown at the output terminals of figure (ii).

vamshee

Highlight



VCC

ViQ1

50 k 10 k 50 k 10 k

V0

100 k

4.2 k

2 k50 k

4.2 k100 k

50 k2 k

VCC

ViQ1

50 k 10 k 50 k 10 k

V0

100 k

4.2 k

2 k50 k

4.2 k100 k

50 k2 k

Figure (ii)

The h-parameter equivalent circuit of above circuit is as shown in figure (iii),

V0

100 k

4.2 k10 khoe

C2

+

−VCCV2

50 k||50 k

10 k

hieC1

Vi

hoe

Ib

Vce

+

−

B1

hie1bI

1cI 2bBI

50 k||50 k

E1 E1 E2

100 k||4.2 kV0

100 k

4.2 k10 khoe

C2

+

−VCCV2

50 k||50 k

10 k

hieC1

Vi

hoe

Ib

Vce

+

−

B1

hie1bI

1cI 2bBI

50 k||50 k

E1 E1 E2

100 k||4.2 k

Figure (iii)

Analysis of Second Stage (CE Amplifier)

As hoe RL = hoe 2CR = 0 < 0.1 (Q hoe is negligible)

Approximate analysis is considered for further calculations.


2i

A = 2

2

b

E

I

I− = '1 Loe

fe

Rfh

h−

≈ – hfe

= – 50

∴ 2i

A = – 50


2i

R = '2 Lireie RAhh +

≈ hie = 1100 Ω

∴ 2i

R = 1100 Ω



Voltage Gain

2VA =

2

oV

V = '

'

2

2

i

Li

R

RA

Where, R'L

= (100 k + 4.2 k) || 10.k

= 104.2 k || 10 k

= 9.12 × 103

⇒ R'L

= 9.12 k Ω

And '2i

R = RB || 2i

R

= (50 k || 50 k) || 1100 = 25 × 103 || 1100

= 1.05 × 103

⇒ '2i

R = 1.05 k Ω

∴ 2VA = '

'

2

2

i

Li

R

RA

= 3

3

1005.1

1012.950

×××−

= – 433.3

∴ 2VA = 433.3

First Stage Analysis CCE Amplifier with Unbypassed RE

The net load resistance 1LR of this stage is obtained by,

1LR = '

21|| iC RR

= 10 k || 1.05 k = 950.23

⇒ 1LR = 950.23 Ω


1i

A = 1

1

b

c

I

I− =

11 Loe

fe

Rh

h

+−

≈ – hfe

= – 50

∴ 1i

A = – 50


1i

R = hie

+ (1 + hfe

) 1ER

= 1100 + (1 + 50) (100 k|| 4.2 k)

= 1.30 × 103

∴ 1i

R = 1.30 kΩ




1VA =

1

2

V

V =

1

11

i

Li

R

RA

1VA = 3101.30

950.213–50

××

= 36.54

∴ 1VA = – 36.54

Overall Output Resistance (Rof)

1oy = h

oe –

sie

refe

Rh

hh

+ (Qhre

and hoe

are negligible and Rs = o)

∴ 1oy = 0

∴ 1oR =

1

1

oy = 0

1 = ∞

Output impedance of the first stage, considering 1cR

1

'oR =

`cR ||1oR = 10 k || ∞ = 10 k

'1oR = 10 kΩ

'1oR is the source resistance for the second stage.

2oy = hoe

1

'

fe re

ie o

h h

h R

−+

= 1

'

fe

ie o

h

h R

−+ ≈ 0

2oy = 0

∴ 2oR =

2

1

oy = 0

1 = ∞

2oR is the output impedance of the transistor, by considering R'L

foR =

20R || '1LR

= ∞ || 9.12 kΩ = 9.12 kΩ

9.12 kfoR∴ = Ω



Overall Input Resistance

fiR = 1i

R || RB

= 1.30 k || (50 k || 50 k)

= 1.30 || 25 k \ 3.47 × 103

Ω=∴ k235.1fiR

Overall Voltage Grain ( fiA )

fVA =

1

oV

V = 0

2 1

oV V

V V×

= 12 VV AA

= – 433.3 × – 36.54 = 15832.7

31083.15 ×=∴

pVA

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