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Looking Ahead to Understand How to Design up to 6.25 Gb/s Interconnects John D’Ambrosia Tyco Electronics

John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

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Page 1: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

Looking Ahead to Understand How to Design up to 6.25 Gb/s InterconnectsJohn D’AmbrosiaTyco Electronics

Page 2: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

2© 2005

Channel Response

Hc(f)

s(t) r(t)Signal

Conditioning

Transmitter

Receive

Equalization

Receiver

The Active Interconnect

Page 3: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

3© 2005

Industry Channel Models

Page 4: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

4© 2005

The Connector / Board Interface

connector pin

layer connection

“TOP” layer connection

“BOTTOM” layer connection

Page 5: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

5© 2005

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

0 1 2 3 4 5 6 7 8 9 10

Frequency (GHz)

Sdd2

1 (d

B)

Sdd21 XAUI 4000-6 Top XAUI 4000-6 Bottom

17" Rogers Backplane Counterbored3" per FR4 Line Card, 12 mil traces on both

16" 4000-6 Backplane Bottom Layer2" per 4000-2 Line Card

16" 4000-6 Backplane Top Layer 2" per 4000-2 Line Card

$$

To improve

$$

Competitive Pressures

Legacy s. Greenfield

Page 6: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

6© 2005

Length Analysis in Backplanes

0 500 1000 1500 2000 2500 3000 3500 4000

Backplane 1

Backplane 2

Backplane 3

Backplane 4

Backplane 5

Backplane 6

Backplane 7

Backplane 8

Backplane 9

Backplane 10

Backplane 11

Diff

eren

t bac

kpla

nes

Number of Differential Pairs

41-47"36-40.99"31-35.99"26-30.99"21-25.99"16-20.99"11-15.99"6-10.99"Under 6"

6" to 10.99"30%

Under 6"45%

11 - 15.99"19%

16 - 20.99"6%

Page 7: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

7© 2005

The Big QuestionHow can the performance of the active interconnect be optimized, while maximizing density / reliability / manufacturability at the lowest cost and lowest power?

The application and its economics dictate the channel!

Page 8: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

8© 2005

Using Pulse Responses

Legacy 6x6 16 OutC0

Note increase in pre-cursor contribution

Note decrease in amplitude and shift in sampling point in relation to peak

Page 9: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

9© 2005

Normalizing a Pulse Response

-20%

0%

20%

40%

60%

80%

100%

120%

-3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 Gb/s3.125 Gb/s6.25 Gb/s10 Gb/s

Legacy 6x6 16 OutC0Note – all cursors normalized to amplitude at t(0). t(0) is chosen as the mid point in time between the 50% edge transitions.

Page 10: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

10© 2005

Standard

4 layers

QuadRoute

2 layers

+72%Med≈ .225”36Std Route Design

-6.6%Low ≈ .125”20Quad Route Design

Option 1 (Nelco N4000-13SI)

+16%Med≈ .225”36Std Route Design

-34%Low ≈ .125”20Quad Route Design

Option 1 (Nelco N4000-13)

BaselineMed≈ .225”36Std Route Design

-Low ≈ .125”20Quad Route Design

* Relative ∆ %

Tech LevelThickness# of

LayersOption 1

(Nelco N4000-6)

+72%Med≈ .225”36Std Route Design

-6.6%Low ≈ .125”20Quad Route Design

Option 1 (Nelco N4000-13SI)

+16%Med≈ .225”36Std Route Design

-34%Low ≈ .125”20Quad Route Design

Option 1 (Nelco N4000-13)

BaselineMed≈ .225”36Std Route Design

-Low ≈ .125”20Quad Route Design

* Relative ∆ %

Tech LevelThickness# of

LayersOption 1

(Nelco N4000-6)

For a full mesh ATCA backplane

Using HM-Zd

Page 11: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

11© 2005

IEEE 802.3ap 10G BackplaneReference Model

Page 12: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

12© 2005

• 10.3125 Gb/s, 28” Topology (6”LC, 16”BP)

• Legacy Backplane

• Decrease in max amplitude

• Increase in pre-cursor

• QuadRoute Backplane

• Max amplitude similar

• Pre-cursor similar

Using Pulse Responses (TP1 – TP4 only)

Page 13: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

13© 2005

Conceptual Observations

SDD21 (dB)

Frequency

Too much loss Signal attenuated increasing impact of noise / reflections

Manageable balance

Potential for increase in xtalk and reflections

Page 14: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

14© 2005

Review of Tyco Channels Provided to IEEE 802.3ap

Length Material Length Material StubChannel ModelTyco - Data to be available within 2 to 3 weeksMargin Test Case

Tyco - Data is available.

Margin Test Case

Tyco - Data is available.

ATCA Full Mesh

Tyco - Data is available.

ATCA Dual Star

Tyco - Data is available.

ATCA Dual Star

Tyco - Data is available.

Adjacent Slot

Tyco - Data is available.

CommentsTotal Length

NOTE: Data for all test cases includes dominant, adjacent NEXT and FEXT aggressors.

13" (330mm)

1" (25mm)

Nelco 4000-13SI

Near Top-Layer (with

stub)

40" (1016mm)

40" (1016mm)

40" (1016mm)

32" (812mm)

22" (558mm)

22" (558mm)

7 6" (152mm)

Nelco 4000-13SI

10" (254mm)

Nelco 4000-13

Bottom (or counter-boring)

6 6" (152mm)

Nelco 4000-13

10" (254mm)

Nelco 4000-13

Top Layer (with stub)

5 6" (152mm)

Nelco 4000-13

20" (508mm)

Nelco 4000-13SI

Bottom (or counter-boring)

4 6" (152mm)

Nelco 4000-13

20" (508mm)

Nelco 4000-13SI

Bottom (or counter-boring)

3 10" (254mm)

Nelco 4000-6

20" (508mm)

Nelco 4000-13SI

Bottom (or counter-boring)

2 10" (254mm)

Nelco 4000-13

20" (508mm)

Nelco 4000-13SI

Bottom (or counter-boring)

1 10" (254mm)

Nelco 4000-13SI

Line Card BackplaneTest Case

Tyco – Data is available.

NOTE – A full mesh ATCA backplane and a dual-star ATCA backplane from independent vendors was used. Neither backplane was optimized for 10 Gb/s operation.

Page 15: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

15© 2005

SDD11 and Impact of Line Card Length (6 and 10 Inches)

LC Bot / BP Bot

Page 16: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

16© 2005

NEXT and Throughput for Different Daughter card Lengths

Page 17: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

17© 2005

FEXT vs. System Length

Note increase in FEXT as channel length decreases

Case 2 – 40”

Case 4 – 32”

Case 7 – 13”

Page 18: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

18© 2005

HM-Zd XAUI Interoperability Platform20 Inch Channel

Data Source – Courtesy of Agere Systems, “The Impact of Environmental Conditions on Channel Performance,” John D’Ambrosia, Greg Sheets, DesignCon 2004.

Page 19: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

19© 2005

Pulse Responses and Environmental Variance

5.15625 Gbits/s

10.3125 Gbits/s

Data Source – Courtesy of Agere Systems, “The Impact of Environmental Conditions on Channel Performance,” John D’Ambrosia, Greg Sheets, DesignCon 2004.

Decrease in t(0) amplitudeIncreases impact of post cursors

Increase in pre-cursor contribution, further complicated by reduction in t(0)

Change in timing

Page 20: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

20© 2005

Return Loss Interacts with Device Terminations

Perfect chip RL

Modeling chip RL as RC to the –8dB spec

Page 21: John D’Ambrosia Tyco Electronicsfpgadownload.intel.com/.../2005_highspeed_tyco.pdf · 3" per FR4 Line Card, 12 mil traces on both 16" 4000-6 Backplane Bottom Layer 2" per 4000-2

21© 2005

ConclusionsTime / Frequency Domain – Use Both!Design for the Backplane not a single case− Different cases have different problems

The application dictates the channelAs you go faster, energy spreads into adjacent bits− Pre-cursor can become more critical

Channel performance is the summation of− Loss− Return loss− NEXT− FEXT

Attenuation is not bad, but it needs managementEnvironmental influenceDevice terminations can cause further problemsConsider the System!