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ECEN 610
Flash ADCs and Comparators
Jose Silva-Martinez
Thanks to Dr. Sebastian Hoyos for providing a large portion of this material
Texas A&M University
Analog and Mixed Signal Group
2
Flash ADC
3
Flash ADC Architecture
• Reference ladder
consists of 2N equal
size resistors
• Input is compared
to 2N-1 reference
voltages.
• Massive parallelism
• Fastest ADC
architecture
• Latency = 1T = 1/fs
• Throughput = fs
• Complexity = 2N
… …
En
co
de
r
VFS Vi
fs
Strobe
Dout
2N-1
comparators
…
Do 0
Vi
Δ
2Δ
5Δ
6Δ
7Δ
VFS
……
0
1
5
6
7
4
1
1
0
1
b2 b1 b0
001
010
110
111
000
ROM encoder
…
… ……
Thermometer Code… …
VFS Vi
fs
Strobe
2N-1
comparators
…
1
1
1
0
Thermometer code
1-of-n code
5
A 10-bit Flash ADC
• VDD = 1.8V
• 10-bit
• VFS = 1V
• DNL < 0.5 LSB
• 0.5mV = 3-5 σ
→ 1023 comparators
→ 1 LSB = 1mV
→ Vos < 0.5 LSB
→ σ = 0.1-0.2mV
• 2N-1 very large comparators
• Large area, large power consumption
• Very sensitive design
• Limited to resolutions of 4-8 bits
1V
1mV
σ
6
Max. Offset vs. Resolution
4 6 8 10
2
8
32
128
N [bits]
Vo
s, m
ax [m
V]
VFS = 1V
VFS = 2V
0.5
• DNL < 0.5 LSB
• Large VFS relaxes
offset tolerance
• Small VFS benefits
conversion speed
(settling, linearity)
7
CMOS Comparators
7
8
Comparator
Transfer characteristic
(ideal)
Circuit symbol
Detects the polarity of the analog input signal and produces a digital
output (1 or 0) correspondingly – zero-crossing detector
Vi
Vo
“1”
“0”
Vth
Φ
ViVo (“Digital”)
Vth
8
9
Design Considerations
• Accuracy (offset, resolution)
• Sensitivity (gain)
• Metastability (gain)
• Settling time (small-signal BW, slew rate)
• Overdrive recovery (memory)
• CMRR
• Power consumption
9
10
Comparator
Amplification Clipping
• Precise gain and linearity are unnecessary → simple, low-gain, open-loop,
wideband amplifiers + latch (positive feedback).
• More gain can be derived by cascading multiple gain stages.
• Built-in sampling function with latched comparators.
Vth
Vi
Vth
Vm
Vth
Vo
10
11
A Typical CMOS Comparator
Vos derives from:
• Preamp diff. pair
mismatch (Vth,W,L)
• PMOS loads and
current mirror
• Latch mismatch
• CI / CF imbalance
of M9
• Clock routing
• Parasitics
M1 M2
Vi
Vos
M3 M4
VDD
M5 M6
M8M7
M9
VSS
Φ
Vo+
Vo-
Preamp Latch
12
Latch Regeneration
Exponential regeneration due to positive feedback of M7 and M8
VDD
VSS
Vo
ΦPA tracking
Latch reseting
Latch
regenrating
Vo+
Vo-
VDD
M5 M6
M8M7
M9
VSS
ΦVo
+Vo
-
CL CL
13
Reg. Speed – Linear Model
./exp00 Lmoo CgttVtV
pole, RHP single ,LmpLm CgssCgs /01/
M8M7
CL CL
Vo+
Vo-
0/1
11
/
o
o
LmLomo
oo
V
V
sCgsCVgV
VV
Vo-
Vo+
CL gmVo-
-1
14
Reg. Speed – Linear Model
0ln
tV
tV
g
Ct
o
o
m
L
M8M7
CL CL
Vo+
Vo-
Vo = 1VVo(t=0)
t
Vo Vo(t=0) t/(CL/gm)
1V 100mV 2.3
1V 10mV 4.6
1V 1mV 6.9
1V 100μV 9.2
15
Reg. Speed – Linear Model
gain. positive for 2
97m
97m
95m2V Rg
Rg2
RgA ,
M5 M6
M8M7
M9
Φ=1Vo
+Vo
-
Vm+
Vm-
M1 M2
Vi
M3 M4
Vm+
Vm-
Vo+
Vo-
R9
2
R9
2
-1
gm7
-1
gm7
gm5Vm+
gm5Vm-
X
3
11
m
mV
g
gA
2V1ViVio AA0VA0V0V
LmVVio CgtAAVtV /exp0 21
x
16
Comparator Metastability
Comparator fails to produce valid logic outputs within T/2 when input falls
into a region that is sufficiently close to the comparator threshold.
LmVVio CgtAAVtV /exp0 21
Curve AV1AV2 Vi(t=0)
10 10mV
10 1mV
10 100μV
10 10μV
Vo+
Φ
Vo-
1 2 3 4
T/2
17
Metastability
• Cascade preamp stages (typical flash comparator has 2-3 PA stages).
• Use pipelined multi-stage latches; PA can be pipelined too.
• Avoid branching off the comparator logic output.
LSB1
ΔBER
LmVVio CgtAAVtV /exp0 21
Vi
DoΔ
j
Vos
j+1
18
Metastability
Vi
1
x
0
0
0
1 1 1
011
100
Logic levels can be regenerated by digital gates.
19
CI and CF in Latches
M5 M6
M8M7
Φ
Vo+
Vo-
CL CLM9
CgdCgs
Vo+
Vo-
Φ
CM
jump
• Charge injection and clock feedthrough introduce CM jump
in Vo+ and Vo
-.
• Dynamic latches are more susceptible to CI and CF errors.
20
Dynamic Offset of Latches
Dynamic offset derives from:
• Imbalanced CI and CF
• Imbalanced load capacitance
• Mismatch b/t M7 and M8
• Mismatch b/t M5 and M6
• Clock routing
Φ
Vo+
Vo-
offset50mV imbalance 10%
jump CM0.5V
Dynamic offset is usually the dominant offset in latches.
21
Typical CMOS Comparator
• Input-referred latch
offset gets divided by
the gain of PA.
• Preamp introduces
its own offset (mostly
static due to Vth, W,
and L mismatches).
• PA also reduces
kickback noise.
M1 M2
Vi
Vos
M3 M4
VDD
M5 M6
M8M7
M9
VSS
Φ
Vo+
Vo-
Preamp Latch
Kickback noise disturbs the reference voltages, must settle before next T.
22
Comparator Offset
M1 M2
Vi
Vos
M3 M4
VDD
M5 M6
M8M7
M9
VSS
Φ
Vo+
Vo-
Preamp Latch
22
222
4
1
L
L
W
WVVV ovthos
97
952
2 Rg
RgA
m
mV
3
11
m
mV
g
gA
2
2
2
1
2
,
2
2
2
1
2
78,
2
1
2
56,
2
34,2
12,
2
VV
dynos
VV
os
V
osos
ososAA
V
AA
V
A
VVVV
Differential pair mismatch:
Total input-referred
comparator offset:
23
Matching Properties
,222
2 DSWL
AP P
P
The variance of parameter ΔP b/t two rectangular devices:
where, W and L are the effective width and length, D is distance.
Ref: M. J. M. Pelgrom, et al., "Matching properties of MOS transistors," IEEE Journal
of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.
.
,
22
2
2
2
22
0
2
00
2
DSWL
A
DSWL
AV VT
VTT
:factor Current
:Threshold
1st term dominates
for small devices.
24
Why Large Devices Match Better?
., 11 RSW
LRR std with
X X X X X X X X…W
L10 identical resistors
R1 R2
.11
10
1
10
10
1
1
1
1
2
2
WLARRRR
RRRR
.1010
,,1010
12
2
1
10
1
22
2
212
RRR
j
RR
RS
j
RW
LRR
std with
“Spatial
averaging”
25
ADC Input Capacitance
2
2
00
2 /10 mfFCWL
AV g
VTT
• N = 6 bits
• VFS = 1V
• σ = LSB/4
• AVT0 = 10mV·μm
→ 63 comparators
→ 1 LSB = 16mV
→ σ = 4mV
→ L = 0.24μm,
W = 26μm
N (bits)# of
comp.Cin (pF)
6 63 3.9
8 255 250
10 1023 ??!
• Small Vos leads to large device sizes, hence large area and power.
• Large comparator leads to large input capacitance, difficult to drive and
difficult to maintain bandwidth.
26
Flash ADC Errors
27
Distributed Parallel Sampling
… …
En
co
de
r
VFS Vi
Dout
2N-1
PA + Latch
…
Do 0
Vi
Δ
2Δ
5Δ
6Δ
7Δ
VFS
……
0
1
5
6
7
…
fs
Strobe
• SHA-less
• Signal and
clock propa-
gation delay
• 2N-1 PA’s plus
latches must
be matched.
• Synchronized
strobe signal
is critical.
Going parallel is fast, but also give rise to inherent problems…
28
Vi
…
VR1
VRj
PA 1
S1
PA j
Sj
PA j+1
… …
……
Preamp Input Common Mode
Input CM difference creates systematic mismatch (offset, gain, Cin,
tracking BW, CMRR) among preamps.
j
R
1
R VV
29
Sampling Aperture Error
• Preamp delay and Vth of sampling switch (M9) are both signal-dependent
→ signal-dependent sampling point (aperture error)
• A major challenge of distributing clock signals across 2N-1 comparators
in flash ADC with minimum clock skew (routing, Vth mismatch of M9)
M1 M2
Vin
M3 M4
Cgs1 Cgs2
CS
VR
RS
M5 M6
M8M7
M9
Φ
Vo+
Vo-
Cgd1 Cgd2Φ Mode
“high” Track
“low” Regen.
30
Nonlinear Input Capacitance
Vin Cin(Vout)
RS
Vout
t
Vin,
Vout
Signal-dependent input bandwidth (1/RSCin) introduces distortion.
31
Input Signal Feedthrough
Feedthrough of Vin to the reference ladder through the serial connection
of Cgs1 and Cgs2 disturbs the reference voltages.
……
Vi
M1 M2
Vin
M3 M4
Cgs1 Cgs2
VRj
RS
32
Fully-Differential Architecture
• VFS doubled
• 3-dB gain in SNR
• Better CMRR
• Noise immunity
• Input feedthrough
cancelled
• Cin nonlinearity
partially removed
• Effect of Vcmi diff.
mitigated
…… … …
En
co
de
r
…
VR+
VR-
Vi+
Vi-
PA Latch
Dout… … …
33
Fully-Differential Comparator
• Double-balanced, fully-differential preamp
• Switches (M7, M8) added to stop input propagation during regeneration
• Active pull-up PMOS added to the latch
M1 M2
Vi+
M5 M6
M9
Φ
Vo+
Vo-
Fully-diff. PA Latch
M3 M4
Vi-
VR+
VR-
M7 M8Φ
34
AC-Coupled Preamp
• PA input node X sees constant bias throughout all preamps.
• Autozeroing eliminates PA offsets (stored in C).
Ref: A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,”
IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979.
PA
Vi
CΦ
Φ
Φ
VR LatchX
35
Vi
0
0
1
……
1
1
0
1 1 0
011
100
0010
Bubbles (Sparkles)
Static and dynamic comparator errors cause bubbles in thermometer code.
36
Bubbles (Sparkles)
j+1
……
Vi
j
0
1
0
1
VRj
VRj+1
t
Vj
Vj+1
VRj
VRj+1
Δt
1 LSB
Comparator offset Timing error
37
Bubble-Tolerant Boundary Detector
Vi
1
0
1
0
1
1
……
1
0
1
1
Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State
Circuits, vol. 14, pp. 932-937, issue 6, 1979.
• 3-input NAND
• Detect “011” instead
of “01” only
• “Single” bubble
correction
• Biased correction
38
Built-In Bias
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
A CB D
1
2
3
Case“011”
Det.
“001”
Det.
A
B Fail
C Fail
D Fail Fail
Inspecting more neighboring comparator outputs improves performance.
39
Majority Voting
Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE
Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
Case“011”
Det.
Majority
voting
A
B Fail
C
D Fail Fail
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
A CB D
1
2
3
1111
*
jjjjjjj CCCCCCC
40
Gray Encoding
43
622
75311
TG
TTG
TTTTG
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Thermometer Gray Binary
G3 G2 G1 B3 B2 B1T1 T2 T3 T4 T5 T6 T7
• One comparator output is ONLY used once → No branching!
• Gray encoding fails benignly in the presence of bubbles.
• Codes are also robust over metastability errors.
Only one transition
b/t adjacent codes
41
Multi-Stage Preamp
A(ω)
Vi
A(ω) A(ω)
… Vo
Vi
CL gmVi CLRL gmVi+1
Vi+1
… …
./
,/1
,/1
000
0
0
0
LLu
LL
CRAA
CR
j
AA
.12,2
,/1/1
1
030
3
2
0
0
0
0
N
dB
N
dBN
NN
N
AA
A
j
AA
N stages:
42
Step Response
tC
gV
CR
tRgV
tfortAV
eAVV
L
min
LL
Lmin
in
t
in
,/
1
0
/
01
.!
1,
,2
11,
1
0
1
2
2
0
12
0
1
in
N
L
m
Nt
Nm
L
NN
in
L
m
t
m
L
in
L
m
t
inm
L
VC
g
N
tdtVg
CVV
tVC
gdtVg
CVtV
C
gdtVg
CV
smal for
Ignore RL in all stages:
Vin gmVin CLRL gmV1
V1
…
V2
43
Optimum N
i
N
L
m
N
o
o
VC
g
N
tV
,V
!
small For
1 2 3 4 5 6 7 8 9 1010
0
101
102
N
t/(C
L/g
m)
Vo/V
i=10
Vo/V
i=100
Vo/V
i=1000
N
i
o
m
L
V
VN
g
Ct
1
!
• Given A0 = Vo/Vi, Nopt can be determined with the above equation.
• For A0 < 100, typical N value ranges between 2 and 4.
44
Comparison
• A higher A0 (= Vo/Vi) requires a larger N.
• In comparison, latches regenerate (PFB) faster than preamp.
i
o
m
L
V
V
g
Ct ln :latch
N
i
o
m
L
V
VN
g
Ct
1
!
100
101
102
103
0
2
4
6
8
10
Vo/V
i
t/(C
L/g
m)
N=1
N=3
N=5
Latch
45
Multi-Stage PA Offset
Total input-referred
Individual stage
A1
Vos1
A2
Vos2
A3
Vos3
A1
Vos
A2 A3
.
,
21
3
1
21
321
AA
V
A
VVV
AAAA
osososos
T
46
Input Offset Cancellation
A
VosΦ1
Φ2
Φ2'
Vi Vo
C
• AC coupling at input with input-referred offset stored in C.
• Two-phase operation, one phase (Φ2) is used to store offset.
47
Offset Storage – Φ2
os
os
oscc
V
VA
A
VVAV
1A
Vos
Φ2
Φ2'
Vo
Vc
Closed-loop stability (amplifier in unity-gain feedback)
Ref: J. L. McCreary and P. R. Gray, "All-MOS charge redistribution analog-to-digital
conversion techniques. I," IEEE Journal of Solid-State Circuits, vol. 10, pp. 371-
379, issue 6, 1975.
48
Amplifying Phase – Φ1
A
VVA
VVVAV
osin
oscino
1
• Offset cancellation is incomplete if A is finite.
• AC coupling at input attenuates signal gain.
A
Vos
1 offset referredInput
A
VosΦ1
Vi Vo
Vc
49
CF and CI of Switches
A
Vos
Φ2
Φ2'
Vo
Vc
• What’s the optimum phase relationship between Φ2 and Φ2'?
• Bottom-plate sampling → Φ2' switches off slightly before Φ2.
Φ2'
Φ1
Φ2
50
Multi-Stage Input Offset
Cancellation
A1
Vos1Φ1
Φ2
Φ3
Vi
C1
A2
Vos2
Φ4
Vo
C2
Φ1
Φ2
Φ3
Φ4
• Multi-stage AC coupling
• Φ3 switches off first
→ ΔV1 on C1 will be
absorbed by C2.
• Φ4 switches off next, Φ2
last.
51
Output Offset Cancellation
• AC coupling at output with offset stored in C.
• A must be small and well controlled (independent of Vo).
• Does not work for high-gain op-amps.
A
VosΦ1
Φ2
Vi Vo
C Φ1
Φ2'
52
Offset Storage – Φ2
ososc AVVAV
• Closed-loop stability is not required.
• CF and CI of Φ2' gets divided by A when referred to input.
Ref: R. Poujois and J. Borel, “A low drift fully integrated MOSFET operational amplifier,”
IEEE Journal of Solid-State Circuits, vol. 13, pp. 499-503, issue 4, 1978.
Vos
Φ2
Vc
Φ2'A
53
Amplifying Phase – Φ1
in
ososio
AV
AVVVAV
• Cancellation is complete if A is constant (independent of Vo).
• AC coupling at output attenuates signal gain.
0 offset referredInput
VosΦ1
Vi Vo
Vc Φ1
A
54
Multi-Stage Output Offset Cancellation
Φ1
Φ2
Φ3
Φ4
• Multi-stage AC coupling
• Φ3 switches off first
→ ΔV1 on C1 will be
absorbed by C2.
• Φ4 switches off next, Φ2
last.
A1
Vos1Φ1
Φ2
Vi
Vo
C1
Φ3 A2
Vos2 C2
Φ4
55
Overdrive Recovery
Fall 2009 S. Hoyos-ELEN-610 56
Overdrive Recovery Test
A small input (±0.5 LSB) is applied to the comparator input in a cycle right
after a FS input (the largest possible input) was applied; the comparator
should be able to resolve to the right output in either case.
Φ
Vo+
Vo-
Vi
Vo
Vi = VFS Vi = -LSB/2
Φ
Vo+
Vo-
Vi
Vo
Vi = VFS Vi = LSB/2
“0” “1”
Case I Case II
57
Passive Clamp
• Limit the output swing
with diode clamps at
output.
• Signal-dependent Ro
• Clamps add parasitics
to the PA output.
M1 M2
M3 M4
Vi+
Vi-
M6
M5Vo+
Vo-
58
Active Reset
• Kill PA gain with a
switch (M5).
• Time-dependent Ro
• M5 adds parasitics to
the PA output.
M1 M2
M3 M4
Vi+
Vi-
M5
Vo+
Vo-
Φ
59
PA Autozeroing
A
VosΦ1
Φ2
Φ2'
Vi Vo
C
• Two-phase operation, Φ2 phase is used for offset storage.
• Autozeroing switch Φ2' also resets and removes the memory of PA.
M1 M2
M3 M4
Vi+
Vi-
M5
Vo+
Vo-
Φ2'
M6
60
CMOS Preamplifier
61
Pull-Up
• NMOS pull-up suffers from body effect, affecting gain setting accuracy.
• PMOS pull-up has no body effect, but is subject to P/N matching.
• Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion,
well, and etc.) don’t track transistors.
M1 M2Vi+
Vi-
Vo+
Vo-
Pull-up
LmL
mV
LW
LW
g
gA 11
:uppull diode NMOS
Lp
n
mL
mV
LW
LW
g
gA 11
:uppull diode PMOS
LmV RgA
1
:uppull Resistor
62
To Obtain More Gain
M1 M2
M3 M4
Vi+
Vi-
Vo+
Vo-
Ip Ip
I
3
1
3
1
2
2
LW
LW
II
I
g
gA
pp
n
m
mV
• Ip diverts current away
from PMOS diodes (M3
& M4), reducing (W/L)3.
• Higher gain, no CMFB
• Needs biasing for Ip
• M3 & M4 may cut off for
large Vin, resulting in
long recovery time.
63
Bult’s Preamp
• NMOS diff. pair loaded
with PMOS diodes and
PFB PMOS pair
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• (W/L)34 > (W/L)56 needs
to be ensured for
stability.
Ref: K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in
1-mm2," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1887-1895, issue 12,
1997.
M1 M2
M7
M3 M4
Vi+
Vi-
Vo+
Vo-
M5 M6
64
Bult’s Preamp (DM)
Vid gm1Vid ro1
1
gm3ro3
-1
gm5ro5
Vod
3//////
1//
1 11531
53
1om
ooo
mm
m
dm
V
rgrrr
gggA
:gain DM
M1 M2
M7
M3 M4
Vi+
Vi-
Vo+
Vo-
M5 M6
65
Bult’s Preamp (CM)
7535371
1
2
11//
1
21 ommmmom
mcm
Vrggggrg
gA
:gain CM
Vic
gm1Vgs1
2ro7
1
gm3
1
gm5
Voc
Vgs1M1 M2
M7
M3 M4
Vi+
Vi-
Vo+
Vo-
M5 M6
66
Song’s Preamp
• NMOS diff. pair loaded
with PMOS diodes and
a pair of resistors
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• Gain depends on precision
of RL
Ref: B.-S. Song et al., "A 1 V 6 b 50 MHz current- interpolating CMOS ADC," in
Symposium on VLSI Circuits Digest of Technical Papers, 1999, pp. 79-80.
M1 M2
M5
M4M3
Vi+
Vi-
Vo+
Vo-
RL RL
X
67
Song’s Preamp (CM)
53
351
1
2
1
1
21
om
mom
mcm
V
rg
grg
gA
Vid gm1Vid ro1
ro3 RL
VodVic
gm1Vgs1
2ro5
1
gm3
Voc
Vgs1
DM CM
Lm
Loom
dm
V
Rg
RrrgA
1
311 ////
68
CMOS Latch
69
Static Latch
• Active pull-up and
pull-down → full CMOS
logic levels
• Very fast!
• Q+ and Q- are not well
defined in reset mode
(Φ = 1).
• Large short-circuit
current in reset mode.
• Zero DC current after
full regeneration
• Very noisy
M6M5
M7
Q+
Q-
Φ
Vi+
Vi-
M1 M2
M3 M4
70
Semi-Dynamic Latch
• Diode divider disabled
in reset mode → less
short-circuit current
• Pull-up not as fast
• Q+ and Q- are still not
well defined in reset
mode (Φ = 1).
• Zero DC current after
full regeneration
• Still very noisy
M6M5
M7
Φ
Φ
M8
Vi+
Vi-
M1 M2
M3 M4
Q+
Q-
71
Current-Steering Latch
• Constant current
→ very quite
• Higher gain in
tracking mode
• Cannot produce
full logic levels
• Fast
• Trip point of the
inverters
M1 M2
M5
Vi+
M6
Vi-
M4M3
M7
Φ
M8
Φ Φ
RL RL
Q+
Q-
72
Dynamic Latch
• Zero DC current in
reset mode
• Q+ and Q- are both
precharged to “0”.
• Full logic level after
regeneration
stability.
• Slow
Ref: A. Yukawa, "A CMOS 8-Bit High-Speed A/D Converter IC," IEEE Journal of Solid-
State Circuits, vol. 20, pp. 775-779, issue 3, 1985.
M4M3
Φ
Vi+
Vi-
M7 M8M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
ΦΦ
Modified Dynamic Latch
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,“
IEEE Journal of Solid-State Circuits, vol. 30, pp. 166-172, issue 3, 1995.
Φ
Vi+
Vi-
M7 M8M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
ΦΦ
M4M3
• Zero DC current in
reset mode
• Q+ and Q- are both
precharged to “0”.
• Full logic level after
regeneration
stability.
• Slow
74
Cho’s Comparator
M1R and M2R added to set the decision threshold
thRR
thii
thRR
thii
VVL
WVV
L
WkG
VVL
WVV
L
WkG
2
1
RR
i
R VVW
WThreshold
M2RM1R
Φ
Vi+
Vi-
M7 M8M5 M6
M1
Q+
Q-
M2
M9 M10 Φ
ΦΦ
M4M3
VR-
VR+
75
Regenerative Sense Amplifier (RSA)
Ref: J.-T. Wu and B. A. Wooley, "A 100-MHz pipelined CMOS comparator," IEEE
Journal of Solid-State Circuits, vol. 23, pp. 1379-1385, issue 6, 1988.
• Offset cancellation
• Fast
• AC coupling reduces
signal gain.
• CM feedback?
Vi+
Vi-
M1 M2
M4 M3
M6M5
Φ Φ
Φ Φ
X Y
Vo+
Vo-
76
DM Equivalent Circuit
M1
M3
M5
X
Vo+
-1
Y
Vi+
M5
X
Vo+
M1
M3
Vo+
-1
Y
Sensing Resetting
DM loopgain in resetting mode is less than 1.
77
CM Equivalent Circuit
Vic
M5
X
M1
M3
Voc • M3 degenerated
• Loopgain < 1 ?
• Needs CMFB
78
RSA Common-Mode Feedback
Vi+
Vi-
M1 M2
M4 M3
M6M5
Φ Φ
Φ Φ
M7
M10M9
Vo+
Vo-
M8
