8/10/2019 Jsaha Resume
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oy eep Sa a 2341 Portland Street, Los Angeles, California,
9000LinkedIn: http://linkd.in/1w5mDmJ Phone: +1 805 900 0714
E-Mail: [email protected]
Objective
Seeking a challenging Entry-level position for Spring 2015
Co-Op/Full Time in ASIC Design/Verification.
Education
University of Southern California, Los Angeles
Graduation Date: May 2015
Master of Science in Electrical Engineering GPA : 3.3/4
Courses: Computer Systems and Organization (EE457), VLSI
ystem Design (EE 577A), Advanced Computer Systems
Architecture(EE 557), Operating Systems (CS 402), VLSI
System
Design and Verification (EE577B)
Institute of Engineering and Management (IEM)
August 2008-Sept 2012
West Bengal University of Technology, India
GPA : 4/4
ww Bachelor of Technology in Electronics and Communication
Engineering
Experience
ASIC and Physical Design / Verification Projects with RTL Coding
and Scripting/(Gluing Languages)Title: 16 bit ALU implementation
and Verification using System C October Given two 16 bit inputs
from the test module via input channels, based on 4bit wide third
input ALU operations were donn alu_calc module to produce 16bit
output. The output was send through the output interface to the
sink module.
Title: TCAM-based Routing Table design for returning destination
network address of any given IP address based on long
prefix match with 32 locations deep Cache Table (Scripting:
Python) October Cache with LRU replacement policy was involved to
store the historical data like network address.
Title: LIFO design with Block of Words, 16 location deep, 8 bit
wide,500Mhz clock(Tool: NCSim HDL: Verilog) October Received words
were in reordered during writing by reversing block of data. Design
was synthesized and ensured time slack
was met. Post Synthesis Verification done.
Title: Design and Verification of FIFO with post synthesis
simulation (Tool: NCSim HDL: Verilog) October
Implementation of synchronous FIFO with Width and Depth
Expansion (clock 500Mhz).
Implementation of 2 clock FIFO. Double synchronization performed
to handle meta-stability issues. Post Synthesis Verificat
was done and ensured it met time slack.
Title: 4-input LRU based fairest arbiter to arbitrate between
multiple requestors. September
ts based on mealy design which takes in four requests who
compete for shared resources but generates one grant. The
prioriti
re updated after the positive edge of the clock and new
priorities are used to process the input requests in the next clock
cycleTitle: Automated Cyclic Redundancy Check Verilog code and Test
Bench Generator (Lang: Python) August With size of data input and
CRC check polynomial as an raw input randomly set by user our
Python scriptauto generates Verilog code for CRC simulation and
synthesis along with relevant testbench.
Title: Design of General Purpose Multiprocessor (Simulator:
Cadence Virtuoso, Scripting Lang: Python) May 2 Designed 64bit CPU,
Area: 500 um x 196 um, Clock Period: 1.5ns, adapted to perform
basic instructions like Add, Div
AND, OR, XOR , Store Word, Load Word Maximum Clock Frequency
3ns. Static Timing Analysis, DRC Check and LVS maRouting
FloorPlanning and Placement, Manual as Automatic Routing.
Title: 1Kb SRAM Design (Simulator: Cadence, Scripting Lang:
Perl) March PERL script for vector file generation and cadence
Simulation of SRAM, Functional Verification Designed the schematic,
S
Timing Analysis, DRC Check and LVS match, Routing Floor Planning
and Placement.
Title: 32 BIT MIPS - 5 stage Pipelined Processor design (Tool :
Modelsim, Lang: Verilog) November 2Implemented the code in RTL and
analysis of the design was performed.
Stall and complete forwarding implemented
Coding Projects (Language: C , Version Control: GitHub,
Debugger: GDB) July . Developed an efficient doubly-linked circular
list library in C which is used in storing and generating bank
transactions for
generating bank statements.. Simulated a traffic shaper who
transmits packets controlled by a token bucket filter using
multi-threading within a single
process, Used Pthread library(POSIX), Implemented signal
handling.. Battle Ship Game, Grade letter publisher and Shopping
Cart Builder implementation using Python[CodeAcademy]
Professional Experience:Cognizant Technology Solutions Private
Limited [Link] December 2012-August
erved as a Programmer Analyst for this Fortune 500 enlisted
software giant. Trained on programming language C.
