KAIST 전산학과 맹 승 렬 [email protected] Memory Management Unit

KAIST 전산학과

맹 승 렬[email protected]

Memory Management UnitMemory Management Unit

2 2004 년 전문대교수연수 ([email protected])2004 CS310 Microprocessors & Lab

The Memory SystemThe Memory System

Embedded systems and applications• The memory system requirements: vary

considerably– Simple blocks– Multiple types of memory– Caches– Write buffers– Virtual memory


Memory management unitsMemory management units

Memory management unit (MMU) translates addresses: Protection checks

CPUmain

memory

memorymanagement

unit

logicaladdress

physicaladdress


Memory management tasksMemory management tasks

Allows programs to move in physical memory during execution

Allows virtual memory:• memory images kept in secondary storage;• images returned to main memory on demand

during execution

Page fault: request for location not resident in memory


Address translationAddress translation

Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses

Two basic schemes:• segmented• paged

Segmentation and paging can be combined (x86)


Segments and pagesSegments and pages

memory

segment 1

segment 2

page 1page 2


Segment address translationSegment address translation

segment base address logical address

rangecheck

physical address

+

rangeerror

segment lower boundsegment upper bound


Page address translationPage address translation

page offset

page offset

page i base

concatenate


Page table organizationsPage table organizations

flat

page descriptor

tree

pagedescriptor


Caching address translationsCaching address translations

Large translation tables require main memory access

TLB: cache for address translation• Typically small

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ARM Memory Management Unit

ARM Memory Management Unit


ARM Memory ManagementARM Memory Management

System control coprocessor(CP15)• Memory• Write Buffers• Caches

Registers• Up to 16 primary registers• Physical registers in CP15 more than 16

Register access instructions• MCR (ARM to CP15)• MRC (CP15 to ARM)


Cached MMU memory systemCached MMU memory system


ARM Memory ManagementARM Memory Management

MMU can be enabled and disabled Memory region types:

• section: 1 Mbytes block• large page: 64 Kbytes• small page: 4 Kbytes• tiny Page: 1 Kbytes

Two-level translation scheme (why?)• First-level table• Second-level table

Page table size for 4-KB pages : 220 X 4 bytes = 4 MB


ARM address translationARM address translation

offset1st index 2nd index

physical address

Translation tablebase register

1st level tabledescriptor

2nd level tabledescriptor

concatenate


First-level descriptorsFirst-level descriptors

AP: access permission C,B: cachability and bufferability


Section descriptor and translating section referencesSection descriptor and translating section references

CP reg 2:

16 KB boundar

y

4K Entries1 MB block (section)

Max: 16KB


Coarse Page table descriptorCoarse Page table descriptor

4 K entries

Max: 16KB

256 entries

Max: 1KB


Fine page table descriptorFine page table descriptor

1 K entries

Max: 4 KB


Second-level descriptorSecond-level descriptor


Translating large page referencesTranslating large page references


Access permissionsAccess permissions

System (S) and ROM (R) in CP15 register 1


TLB functionsTLB functions

Invalidate instruction TLB Invalidate instruction single entry Invalidate entire data TLB Invalidate data single entry

TLB lockdown

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MPC 850 MMUMPC 850 MMU


MPC850 MMUMPC850 MMU

Does not support some PowerPC MMU features

4-, 16-, 512- Kbyte, or 8-Mbyte pages• 1-KB subpages for 4-Kbyte pages

Separate instruction and data MMUs• Can be disabled separately

Supports up to 16 virtual address spaces Supports 16 access protection groups


MPC 850 MMU, cont’dMPC 850 MMU, cont’d

Separate 8-entry, fully-associative data translation lookaside buffer (DTLB) and instruction TLB (ITLB)

High performance and low power consumption

TLB locking, invalidation


Address TranslationAddress Translation

Translation disabled• MSR[DR], MSR[IR]• Effective address = physical address

Translation enabled• TLB

– SW handles the table lookup and TLB reload with little HW assistance in the MPC 850

• MMU supports a multiple virtual address space– Address space ID (ASID)


Address Translation, cont’dAddress Translation, cont’d

Not implemented in the DTLB


TLB operationTLB operation

Current Address ID

Privilege level

8?


Translation Table (4 KB pages)Translation Table (4 KB pages)


Translation Tables (1 KB pages)Translation Tables (1 KB pages)


Level-One descriptorLevel-One descriptor


Level-Two DescriptorLevel-Two Descriptor

1KB protection4KB page HW assist

4KB page 1KB subpage


Page SizePage Size


Programming ModelProgramming Model


Programming Model (cont’d)Programming Model (cont’d)


TLB operationsTLB operations

tlbia: translation lookaside buffer invalidate all

tlbie: translation lookaside buffer invalidate entry

Locking TLB entries


Locking TLB EntriesLocking TLB Entries

IMMU control register(MI_CTR bit 4)

DMMU control register(MD_CTR bit 4)


DTLB reloadDTLB reload

Documents

KAIST 전산학과 맹 승 렬 [email protected] Memory Management Unit