Kande Project 1

7/31/2019 Kande Project 1

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Abstract

The intended objective of this project is to generate manufacturing test patterns for

combinational circuits. The best known algorithms that have been used in manufacturing test

equipment are the D and Podem algorithms. This project demonstrates ATPG test generation by

going through Verilog RTL design synthesis, place and route, logic simulation, fault simulation

and ATPG for manufacturing tests. The synopsys EDA tools such as design compiler, design

vision, VCS (Synopsys Verilog Compiler Simulator), TetraMax, and DVE (Discovery Visual

Environment) have been investigated along with sequential and combinatorial circuit examples

to demonstrate the project objective. The project also gives users an introduction and easy

navigation through the UNIX environment.


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Table of Contents

ABSTRACT ................................................................................................................................................................. I

ACKNOWLEDGMENT ....................................................................................................................................... VIII

PREFACE ................................................................................................................................................................. IX

CONVENTIONS ........................................................................................................................................................ X

I. INTRODUCTION TO DIGITAL DESIGN FLOW ............................................................................................ 1

II.INTRODUCTION TO VERILOG AND VERILOG COMPILED CODE SIMULATOR (VCS) .................. 4

2.1 WHAT IS HDL? ................................................................................................................................................ 4

2.2 VERILOG .......................................................................................................................................................... 4

2.3 STRUCTURE OF VERILOG MODULE ................................................................................................................... 4

2.4 VERILOG PORTS ............................................................................................................................................... 5

2.5 VERILOG OPERATORS ...................................................................................................................................... 5

2.6 LOGICAL OPERATORS ...................................................................................................................................... 6

2.7 VERILOG BOOLEAN LOGICAL OPERATORS........................................................................................................ 6

2.8 VERILOG REDUCTION LOGICAL OPERATORS .................................................................................................... 7

2.9 VERILOG ARITHMETIC OPERATORS ................................................................................................................. 7

2.10 DATA TYPES ..................................................................................................................................................... 8

2.11 VERILOG PROGRAM LEVELS............................................................................................................................. 9

III.OVERVIEW OF DESIGN FLOW ..................................................................................................................... 11

IV.COMPILER .......................................................................................................................................................... 12

V.VERILOG COMPILED CODE SIMULATOR (VCS) .................................................................................... 12

VI.OVERVIEW OF OBERON PROFILE SETUP ................................................................................................ 14

VII. COMPILATION AND SIMULATION OF RAM .......................................................................................... 17

VIII. DVE (DISCOVERY VISUAL ENVIRONMENT) PROCEDURE .............................................................. 18

8.1 SEARCH FOR SIGNALS OR SCOPES ................................................................................................................... 21

8.2 FINDING VALUES ON THE SIGNAL ................................................................................................................... 23

8.3 DEBUGGING STATE MACHINES USING WAVE WINDOW.................................................................................... 25

8.4 SET AN EXPRESSION/CREATE NEW SIGNAL.................................................................................................... 25

8.5 TRACING DRIVERS AND LOADS....................................................................................................................... 28

IX.DESIGN COMPILER.......................................................................................................................................... 30

9.1 INTRODUCTION .............................................................................................................................................. 30

9.2 SPECIFY AND LINK TARGET TECHNOLOGY ..................................................................................................... 30

9.3 ANALYZE AND ELABORATE PHASE ................................................................................................................ 30

9.4 APPLYING CONSTRAINTS................................................................................................................................ 33

9.5 DESCRIBING THE ENVIRONMENT .................................................................................................................... 33

9.6 OPTIMIZING THE DESIGN ................................................................................................................................ 34

9.6.1 Architectural Level ............................................................................................................................... 34

9.6.2 Logic Level Optimizations .................................................................................................................... 34

9.6.3 Gate level Optimizations: ..................................................................................................................... 35

9.7 ANALYSIS OF THE RESULTS ............................................................................................................................ 35

9.7.1 Generating textual reports for design properties ................................................................................. 35


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9.7.2 Visualizing design objects (GUI) .......................................................................................................... 35

9.8 SAVING DESIGN .............................................................................................................................................. 35

X.DESIGN COMPILER TUTORIAL: .................................................................................................................. 36

XI.DESIGN VISION ................................................................................................................................................. 48

11.1 INTRODUCTION .............................................................................................................................................. 4811.2 FEATURES AND BENEFITS ............................................................................................................................... 48

11.3 OVERVIEW OF DESIGN VISION PROCESS......................................................................................................... 48

11.4 STARTING DESIGN VISION ............................................................................................................................. 49

11.4.1 Specifying libraries: ........................................................................................................................... 50

11.4.2 Reading source design ........................................................................................................................ 51

11.4.3 Setting current design ......................................................................................................................... 51

11.4.4 Defining design environment and setting design constraints ............................................................. 51

11.4.5 Check design ...................................................................................................................................... 53

11.4.6 Compiling the design .......................................................................................................................... 53

11.4.7 Analysis of the design ......................................................................................................................... 53

11.4.8 Saving the design database ................................................................................................................ 56

XII. TETRAMAX ...................................................................................................................................................... 57

12.1 INTRODUCTION .............................................................................................................................................. 57

12.2 NECESSITY OF TETRAMAX............................................................................................................................. 57

12.3 INTRODUCING MODERN IC TESTING: ............................................................................................................. 57

12.4 FEATURES AND BENEFITS ............................................................................................................................... 58

12.5 SUPPORTED FAULT MODELS: .......................................................................................................................... 58

12.5.1 Stuck-at fault ...................................................................................................................................... 58

12.5.2 Path delay faults ................................................................................................................................. 59

12.5.3 Transition delay model ....................................................................................................................... 59

12.5.4 IDDQ model ....................................................................................................................................... 59

12.5.5 Bridging model ................................................................................................................................... 60

12.6 OVERVIEW OF TETRAMAX: ............................................................................................................................ 60

12.7 TETRAMAX TUTORIAL WITH AN EXAMPLE: .................................................................................................... 62

12.7.1 Read design and library files .............................................................................................................. 62

12.7.2 Build model ........................................................................................................................................ 63

12.7.3 Design Rule Check (DRC) .................................................................................................................. 64

12.7.4 ATPG patters ...................................................................................................................................... 65

12.7.5RVIEWING RESULTS ................................................................................................................................ 69

12.7.6SAVING PATTERNS.................................................................................................................................. 69

12.8 DEBUGGING USING TETRAMAX: .................................................................................................................... 71

12.8.1 Analyze the module ............................................................................................................................. 71

12.8.2 View complete module ........................................................................................................................ 72

12.8.3 Backward or forward trace ................................................................................................................ 7312.8.4 Applying patterns ............................................................................................................................... 74

XIII. IC COMPILER ................................................................................................................................................ 75

13.1 INTRODUCTION TO MILKYWAY....................................................................................................................... 75

13.2 INTRODUCTION TO IC COMPILER.................................................................................................................... 75

13.3 FLOOR PLANNING .......................................................................................................................................... 77

13.3.1 Aspect ratio ........................................................................................................................................ 78


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13.3.2 Rows of standard cells ........................................................................................................................ 78

13.3.3 Power planning .................................................................................................................................. 78

13.3.4 Pin placement ..................................................................................................................................... 78

13.3.5 Macro placement ................................................................................................................................ 78

13.4 PLACEMENT ................................................................................................................................................... 79

13.4.1 Constructive algorithm ....................................................................................................................... 79

13.4.2 Iterative algorithm .............................................................................................................................. 7913.5 ROUTING........................................................................................................................................................ 79

13.5.1 Global routing .................................................................................................................................... 80

13.5.2 Detailed routing ................................................................................................................................. 80

13.6 END PRODUCTS OF IC COMPILER STAGE ......................................................................................................... 80

XIV. PRIMETIME .................................................................................................................................................... 81

14.1 INTRODUCTION .............................................................................................................................................. 81

14.2 COMPARING PRIMETIME WITH DESIGN COMPILER ......................................................................................... 81

XV. CONCLUSIONS: ............................................................................................................................................... 82

XVI. REFERENCES ................................................................................................................................................. 84XVII. APPENDIX A: VERILOG CODES .............................................................................................................. 85

XVIII. APPENDIX B: ACRONYMS ....................................................................................................................... 96

XIX. APPENDIX C: FILE EXTENSIONS ............................................................................................................. 97

XX. APPENDIX D: TROUBLE SHOOTING......................................................................................................... 99


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List of figures

Figure 1: Stages of ASIC Implementation ..................................................................................................................... 1

Figure 2: Over view of the entire process .................................................................................................................... 11

Figure 3: Compiler....................................................................................................................................................... 12

Figure 4: Process related to VCS ................................................................................................................................. 13

Figure 5: VCS detailed process ................................................................................................................................... 14

Figure 6: Complete scenario of user account ............................................................................................................... 15

Figure 7: DVE and its brief description ....................................................................................................................... 19

Figure 8: Complete GUI view of RAM through DVE............. ........... .......... .......... ........... .......... ........... .......... ........... 20

Figure 9: Showing RAM with waveform view................... .......... ........... .......... ........... .......... ........... .......... .......... ...... 21

Figure 10: Debugging the design by analyzing search options............ ........... .......... ........... .......... .......... ........... ......... 22

Figure 11: Debugging the design by analyzing search options............ ........... .......... ........... .......... .......... ........... ......... 22

Figure 12: Alternate way of searching the signal .......... .......... ........... .......... .......... ........... .......... ........... .......... ........... 23

Figure 13: Figure 9.4: Importance of check box .......... .......... ........... .......... ........... .......... ........... .......... ........... .......... .. 23

Figure 14: Available options in finding values on the signal ........... .......... ........... .......... ........... .......... .......... ........... .. 23

Figure 15: Searching for value on the signal Q [7:0] in a RAM .......... ........... .......... ........... .......... ........... .......... ......... 24

Figure 16: Moving wave window to the top level .......... ........... .......... ........... .......... ........... .......... ........... .......... ......... 24Figure 17: Setting the top level name .......................................................................................................................... 24

Figure 18: Setting name to state machine signal ............ ........... .......... ........... .......... ........... .......... ........... .......... ......... 25

Figure 19: Result of setting state names ...................................................................................................................... 25

Figure 20: Showing wave window with new signal updates .......... ........... .......... .......... ........... .......... .......... ........... .... 25

Figure 21: Setting expression to identify reading phase .............................................................................................. 26

Figure 22: Available options to grid a signal ............................................................................................................... 27

Figure 23: Picture showing grid on rand signal of a module for convenience .......... ........... .......... .......... ........... ......... 27

Figure 24: Grid properties ............ ........... .......... ........... .......... .......... ........... .......... ........... .......... ........... .......... ........... 27

Figure 25: Trace drivers by right click on the signals................ .......... ........... .......... ........... .......... ........... .......... ......... 28

Figure 26: Trace drivers by clicking on tool bar .......... .......... ........... .......... ........... .......... ........... .......... ........... .......... .. 28

Figure 27: DVE showing drivers of rand signal .......... .......... ........... .......... ........... .......... ........... .......... ........... .......... .. 28

Figure 28: Point drivers ofrandin console pane ......................................................................................................... 29

Figure 29: Design compiler process ............................................................................................................................ 31

Figure 30: Design Compiler and its internal process ................................................................................................... 32

Figure 31: Fragment of report showing ports .......... ........... .......... ........... .......... ........... .......... ........... .......... .......... ...... 40

Figure 32: Fragment of compilation phase .................................................................................................................. 42

Figure 33: Qor report showing over all statistics of the design ......... ........... .......... ........... .......... ........... .......... ........... 43

Figure 34: Hierarchical area report .............................................................................................................................. 44

Figure 35: Timing report ............................................................................................................................................. 45

Figure 36: Report showing references to ram module ................................................................................................. 46

Figure 37: Constraints report and their status .............................................................................................................. 47

Figure 38: Design Vision Overview ............................................................................................................................ 49

Figure 39: Design Vision GUI ..................................................................................................................................... 49Figure 40: Library files in design vision ...................................................................................................................... 50

Figure 41: Analyze, elaborate and read options in Design Vision ............................................................................... 51

Figure 42: Design rule constraints ............................................................................................................................... 52

Figure 43: List of all the input/output in the design .......... ........... .......... .......... ........... .......... ........... .......... ........... ....... 53

Figure 44: Settings for timing report ........... ........... .......... ........... .......... ........... .......... .......... ........... .......... ........... ....... 54

Figure 45: Schematic view .......................................................................................................................................... 54

Figure 46: From the tool bar ........................................................................................................................................ 55

Figure 47: Schematic view of ram ............................................................................................................................... 55


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Figure 48: Available timing analysis options .......... ........... .......... ........... .......... ........... .......... ........... .......... .......... ...... 55

Figure 49: Post synthesis results of RAM using dve .......... .......... ........... .......... ........... .......... ........... .......... ........... ..... 56

Figure 50: Modern IC testing ...................................................................................................................................... 58

Figure 51: Circuit to explain stuck-at fault .................................................................................................................. 59

Figure 52: Response of a circuit with a node stuck-at 1 .......... ........... .......... .......... ........... .......... .......... ........... ........... 59

Figure 53: Overview of TetraMax process [15] .......... .......... ........... .......... ........... .......... ........... .......... ........... .......... .. 60

Figure 54: GUI of TetraMax showing various components .................. ........... .......... .......... ........... .......... ........... ....... 61

Figure 55: GSV tool bar .............................................................................................................................................. 62

Figure 56: Check box if the netlist is Library module .......... .......... ........... .......... .......... ........... .......... ........... .......... .... 62

Figure 57: build model of TetraMax............ ........... .......... ........... .......... .......... ........... .......... ........... .......... ........... ....... 63

Figure 58: Build model specifications ......................................................................................................................... 63

Figure 59: ATPG showing initializing of faults ................. .......... ........... .......... ........... .......... ........... .......... .......... ...... 66

Figure 60: Three ATPG engines .................................................................................................................................. 67

Figure 61: Fault classes and their groups .......... ........... .......... ........... .......... ........... .......... ........... .......... .......... ........... .. 69

Figure 62: Saving of patterns in available formats ......... ........... .......... ........... .......... ........... .......... ........... .......... ......... 70

Figure 63: Analyzing stuck-at faults ............................................................................................................................ 71

Figure 64: Showing 100 stuck-at faults from which user can select a port to analyze ............... .......... .......... ........... .. 71

Figure 65: Setup dialog box showing primitive and design .......... ........... .......... ........... .......... ........... .......... .......... ...... 72Figure 66: GSV showing primitive view ..................................................................................................................... 72

Figure 67: Design settings and its view ....................................................................................................................... 72

Figure 68: Forward/backward trace ............................................................................................................................. 73

Figure 69: Select port to be traced ............................................................................................................................... 73

Figure 70: Observe backward trace of primitive 9 ......... ........... .......... ........... .......... ........... .......... ........... .......... ......... 74

Figure 71: Selecting patter to be applied to module ........... .......... ........... .......... ........... .......... ........... .......... ........... ..... 74

Figure 72: Pattern application ...................................................................................................................................... 74

Figure 73: Outline of IC compiler stage ...................................................................................................................... 76

Figure 74: Example of a floor plan .............................................................................................................................. 77

Figure 75: Gcell or routing grid or routing bin .......... ........... .......... .......... ........... .......... ........... .......... ........... .......... .... 79

Figure 76: Interconnection of gcells by global router .......... .......... ........... .......... .......... ........... .......... ........... .......... .... 80


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List of tables

Table 1: Bitwise logical operators ....... ........... .......... ........... .......... ........... .......... .......... ........... .......... .......... ........... ...... 6

Table 2: Boolean logical operators ................................................................................................................................ 6

Table 3: Reduction Logical Operators ........................................................................................................................... 7

Table 4: Verilog Arithmetic Operators .......................................................................................................................... 7

Table 5: Data types of Verilog ......... ........... ........... .......... ........... .......... .......... ........... .......... ........... .......... ........... ......... 8

Table 6: Various Verilog simulators and their manufacturers .......... .......... ........... .......... ........... .......... .......... ........... .. 12

Table 7: Logic level optimization showing structuring .......... ........... .......... .......... ........... .......... .......... ........... ........... 35

Table 8: Synopsys standard library units ..................................................................................................................... 39

Table 9: Highlighting parameters of noramal ATPG and auto ATPG .......... .......... ........... .......... ........... .......... ........... 69

Table 10: End products of IC compiler ................... ........... .......... ........... .......... ........... .......... ........... .......... .......... ...... 80

Table 11: Results of Design Compiler stage (using Single port ram used) ................ .......... ........... .......... ........... ....... 82

Table 12: Conclusions of TetraMax (using addsubtract) ............................................................................................. 82

Table 13: Invoking command for corresponding process ............................................................................................ 83


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Acknowledgment

This project presents a two years effort of pursuing excellence in education and personal goals. It

represents my Masters project and makes me feel happy as this is a part of my interest. During

my research, lot of people extended support technically and morally. It is my real pleasure to

thank those people who made this research possible. I would like to give special thanks to myadvisor, Dr. Reza Raeisi, for his support throughout my research. I am very much thankful to

ECE department staff and faculty for clarifying my queries.

Also, I would like to thank my dear family. This research would have not been accomplished

without their support. I take this opportunity to thank department of Electrical and Computer

Engineering for providing me financial support by giving me Teaching Associate position.

Finally and most important, to everyone who stood by me in all times, supported and gave me

strength to face all the difficulties.


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Preface

I choose this project mainly because of my special interest in VLSI digital testing. I wanted to

get familiar with the design flow process. As a part of my interest I documented the process of

design flow in this research project.

Motivation for this research is the course ECE 242 where testing procedures for digital designs

are introduced.

Audience

This document stands as reference for design engineers and design verification engineers who

want to gain experience in using Synopsys tools for synthesis, analysis, generating test-patterns

(DFT process), and placement and routing of a RTL model designed in Verilog. For better

understanding, familiarity with the below listed process is required

Compilation using VCS

Design compiler and Design visionfor synthesis TetraMaxfor generating test-patterns IC compilerfor placement and routing


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Conventions

The following conventions are used in this documentation.

Convention Description

Courier

Courier italic

Courier bold

[]

|

_

\

/

units

case sensitive

Indicates command syntax.

Indicates a user-defined value in Synopsys

syntax, such as object_name. A user

defined value that is not Synopsys syntax.

Indicates user inputtext you typeverbatimin Synopsys syntax and

examples.

Denotes optional parameters, such aspin1 [pin2 ..pinN]

Indicates a choice among alternatives, such

as low | medium | high

Connects terms that are read as a single term

by the system, such asset_input_delay

Indicates a continuation of a command line

Indicates levels of directory structure

Library units for area- , time - sec

All the commands are case sensitive;

create_clock CLK is different fromcreate_clock Clk.


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I. Introduction to digital design flowIntegrated Circuits (IC) revolutionized modern electronics by serving wider range of

applications, and with their low cost and performance efficiency they replaced huge transistor

circuits. Application Specific IC (ASIC) is a combination of digital and analog circuits packed

into an IC to achieve the desired control/computation function [3]. Advancement of technologyin different areas accordingly led to increase in performance and requirements in that area. This

led to the advent of ASICs to achieve performance in required areas with reasonable cost.

Typical implementation of ICs involves three phases.

Figure 1: Stages of ASIC Implementation

Idea

Requirements

Approach

Design entry

and RTL

Gate level

Netlist

Design

Verification

Physical Design

Implementation

IC Fabricationand Testing

Production and

Monitoring

Synthesis

DVE and TmaxIC compilerPrimetime

Definition and

Exploration phase

Implementation

phase

Manufacturing and

Production phase

GSDII


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Implementation flowchart, figure 1 gives detailed process of real-time ASIC implementation. In

this research project definition and exploration phase and implementation phase are discussed in

detailed. During definition and exploration phase idea to be implemented, specifications like:

speed, power, and functionality, technology constraints like: size and space are considered. After

specifications are decided the idea advances through implementation phase where actual

designing takes place.

Implementation phase is an important phase where most of the specifications are met upon

careful examination. In this phase synopsys tools such as Verilog Compiled code Simulator

(VCS), design compiler, primetime, IC compiler, and Discovery Visual Environment (DVE) are

used to bring shape to the initial idea. Basic implementation of the idea is done in Register

Transfer Level (RTL). RTL is expressed usually in hardware description language (HDL) like

Verilog or VHDL. A Hardware Description Language (HDL) is a language used to describe a

digital system, for example, a network switch, a microprocessor or a memory or a simple flip-

flop. This just means that, by using a HDL one can describe any hardware (digital) at any level.

Functional/Logical verification is performed at this stage to ensure the RTL design matches the

idea [2]. Synopsys VCS is used to simulate and debug the RTL design. Next stage to debug and

simulate is transformation of RTL into gate-level netlist. This process of transforming RTL to

gate-level netlist is called synthesis, and is done using the tools namely Design Compiler

(Synopsys), RTL compiler (Cadence), Blast Create (Magma).

Design compiler is emphasized in this project. Design compiler along with standard 90nm cell

library converts RTL in to gate-level standard cells at the leaves of the design. Next step in

implementation phase is design verification and physical implementation of the design. Tools

like DVE and TetraMax are used to verify the design. DVE takes either RTL or gate-level design

as input and provides excellent amenities to debug and provide good understanding of designs

functionality. TetraMax (Tmax in short) is another exceptional tool provided by Synopsys. Tmax

accepts the synthesized output from design compiler stage along with 90nm standard cell library

as input, and after following few significant steps it generates test patterns. These test patterns

verify complete functioning of the design by assuming the present design as faulty model. Tmax

also provides ways to debug the design using these test patterns. Complete information regarding

these debugging features is discussed later in this project.

Physical design implementation is nothing but geometric representation of gate-level netlist.

Geometric representation is designing layout for the design according to guidelines and

limitations specified in the library files. This process is taken care by IC compiler which is again

a part of Synopsys. Three steps that are followed to complete the physical implementation are

floor planning, placement, and routing. These processes are self-explanatory as per their names.

In floor planning vital features like size of the chip, pin assignment, type of clocks and power

planning is done. Placement first determines how each gate should be placed on the chip.

Routing will then wire these gates together, using heuristic algorithms to group together related

gates and tweak placement in order to minimize routing congestion and wire delay [4]. All these


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details are given to manufacturers in the form of GDSII file as shown in figure 1. Some of the

similar tools are Blast Fusion (Magma), and Encounter (Cadence). Another important process

that is followed in the ASIC implementation is Static Time Analysis (STA) using primetime (PT

synopsys). Prime time checks for violations in the same way that you would do it manually, but

with much greater speed and accuracy. PT breaks the design down into set of timing paths,

calculates signal propagation delay along each path, check violation of timing constraints inside

the design and at the input/output interface.


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II.Introduction to Verilog and Verilog Compiled code Simulator (VCS)2.1 What is HDL?

Hardware Description Language (HDL) is a Computer-Aided Design (CAD) tool for the modern

design and synthesis of digital design. Due to increase in the complexity of digital designs,realization of such circuits with Integrated Circuits (ICs) became impossible. This realization

required sophisticated CAD tools which includes HDL. The designer uses HDL to describe the

system in a computer language, such as C. Debugging a HDL design is stress-free as it includes

packages that implement simulator and test benches [5]. The two streams of HDL that are widely

used are VHDL and Verilog. In this research project I confine my discussion to Verilog.

2.2 VerilogVerilog in non-technical sense is a textual representation of electronic circuits and systems.

Through Verilog electronic design can be analyzed by verifying through simulation, timinganalysis, logic synthesis, and test analysis. The history of Verilog takes back to 1980s when a

company called Gateway Design Automation developed a HDL for its newly introduced logic

simulator, Verilog-XL. Taking over Gateway Design Automation, Cadence brought Verilog

language into public domain in 1990. In December 1995, Verilog HDL became IEEE standard

1364-1995 [5].

2.3 Structure of Verilog moduleVerilog modules structure is similar to other software languages such as C. Source code is

written in high-level language in an editor provided by HDL package, in regards to this researchproject vi editor is used. Verilog module consists of a declaration and a body. The declaration

is part of program where input, output, and inout ports are listed. In the body a meaningful

relation between these declared ports is done.

// D-Flip Flop showing input signal (d), output (q), Clock

//(clk), and reset

`define TICK #2 //Flip-flop delay

module dflipflop (d, clk, reset, q);

inputd, clk, reset;

outputq;regq;

always @ (posedge clk or posedge reset)

begin

if (reset) begin

q


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else begin //perform buffer

q


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2.6 Logical OperatorsVerilog logical operators are internally classified into three groups: bitwise, boolean logical, and

reduction. Table 1.1 shows Verilog Bitwise logical operators

Table 1: Bitwise logical operators [5]

Operators Equivalent Logic Operand Type Result type

& Bit Bit

| Bit Bit

~(&) Bit Bit

~(|) Bit Bit

^ Bit Bit

~^ Bit Bit

~ Bit Bit

Consider the following example of bitwise logical operators; A= 1010, B= 0101, and F = A|B

The name bitwise is self-explanatory, which means the operation is done bit by bit. According to

the values assumed F is a 4 bit signal 1111.

2.7 Verilog Boolean logical operatorsBoolean logical operators respond with 1 (true value) or 0 (false value) for an expression.

Considering an example will make the concepts clear. A= 1000, B= 0111 if F= A||B then F =1.Table 2 shows various Boolean logical operators.

Table 2: Boolean logical operators [5]

Operator Operation Number of operands

&& AND Two

|| OR Two


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2.8 Verilog Reduction logical operatorsThe self-explanatory term reduction operator states some form of reduction to the input bits.

This is explained clearly with the help of an example, statement F=|A, A= 0110 gives an output

of (0 |1|1|0) 1.Various reduction operators and their symbols are given in table 3.

Table 3: Reduction Logical Operators

Operator Operation Number of operands

& Reduction AND One

| Reduction OR One

~& Reduction NAND One

~ | Reduction NOR One

^ Reduction XOR One

~^ Reduction XNOR One

! NEGATION One

2.9 Verilog Arithmetic OperatorsAll the arithmetic operations are performed with the help of arithmetic operators and its syntax is

generally given by F= A (operator) B, this operator can be replaced by any arithmetic operators

from table 4. An example of arithmetic operator is Modulus, F = (A % B) returns the remainder

of (A/B).

Table 4: Verilog Arithmetic Operators [5]

Operator Description A or B type F type

+Addition

A+BA numericB numeric

numeric

-Subtraction

AB

A numeric

B numericnumeric

*Multiplication

A*B

A numeric

B numericnumeric

/Division

A/BA numericB numeric

Numeric

%Modulus

A%B

A numeric, not real

B numeric, not realnumeric, not real

**Exponent

A**B

A numeric

B numericNumeric

{,}Concatenation

{A,B}

A numeric or array

B numeric or arraySame as A


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2.10 Data typesData type refers to data storage format that contains a specific type or range of values. As HDL

is used to describe the digital circuits in the form of text, several formats are required to serve the

purpose. For instance, when a signal is defined we need to specify its type so that we restrict the

signal to admit only few values. Verilog data types are discussed in the following section.

Verilog supports numerous data types namely: nets, integer, registers, parameters, and arrays.

Table 5: Data types of Verilog

Data type Predefine word Syntax Explanation

Nets Wirewire sum;

wire sum= 1b 0

Here in the first case a net

named sum is defined and in

the second case sum is

declared along with a value

assigned to it.

Note: nets do not have any

memory, they are used todrive circuits or as an

interconnection.

Register Reg reg q;

A variable q of register type

is defined.

Note: unlike nets register

data type stores values until

they are updated.

Vector

wire or

reg with

variables

enclosed in []

wire[2:0]x = 3b100;

reg[2:0]y = 3b 101

Here in both the cases

variables x, y are single

variables holding multiple

bits.

Integer Integer Integer k1;Variable k1 is defined as an

integer data type.

Real Real Real average;

Real data type can hold

even floating values along

with integers

Parameter Parameter Parameter M= 2;

Parameter is similar concept

to that of global variables in

C or any other programminglanguage

Array NA

Reg [2:0] x [0:2]

X22 1 0

X12 1 0

X02 1 0

Function of Array is to hold

multiple vectors together.

Here x can hold 3 variables

of 3 bits each.


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These data types are used throughout this research project in various programs. Table 5 shows

different data types and their declaration syntax along with their explanations. And regarding

arrays, Verilog only supports single dimension array.

2.11 Verilog Program levelsVerilog can be used to program the digital designs at various levels namely; behavioral level,

register transfer level, and gate level.

Behavioral Level: When a design is behavioral model, the module will include predefined

words such as always or initial. Describing the design in algorithmic way, the

functionality is defined by which operation must occur, not by how they are implemented in

hardware. Behavioral code is faster to simulate and easy to debug. Behavioral code is not

synthesizable.

module half_adder (X, Y, Sum, Carry);

inputX, Y;

outputsum, carry;regsum, carry;

always @(X, Y)

begin

sum = X^ Y;

carry= X&Y;

end

endmodule

Program 3: Behavioral program for half adder

Register transfer level: RTL design is synthesizable; this is the noticeable feature of RTL. RTL

is description of the function at block level where each block may be synthesizable. The code is

characterized by arithmetic expressions. In RTL design, all the registers are defined and

combination logic is implemented. RTL design is technology and library dependent unlike

behavioral.

module half_adder (X, Y, Sum, Carry);

inputX, Y;

outputsum, carry;

xor x1(sum, X, Y);

and a1(carry, X, Y);

endmodule Program 4: RTL program for half adder

Gate level: The process of synthesized output is the gate-level. In this project we use tools

developed by Synopsys to convert RTL to gate-level.

module full adder ( a, b, c, sum, carry );

input a, b, c;

output sum, carry;


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wire n1;

XOR2X1 U1 ( .IN1(c), .IN2(n1), .Q(sum) );

AO22X1 U2 ( .IN1(a), .IN2(b), .IN3(c), .IN4(n1),

.Q(carry) );

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );

endmoduleProgram 5: Gate level program of fulladder after synthesized

Above three modes of Verilog programming has their own merits and usages but in this project

RTL and gate-level are used. Program 5 is gate-level and plays vital role in the entire process,

acts as inputs to almost all the tools.


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III. Overview of Design flowFigure 2: Over view of the entire process


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Figure 4: Process related to VCS


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Significant processes of this section are:

1. Compilation of Verilog source code2. Simulation of design to review the results3. Debugging graphically with the help of DVE.

Figure 5 shows process in detail and explains how VCS is responsible for viewing and

debugging a design.

Figure 5: VCS detailed process

From figure 5 it is clear that VCS takes RTL code and test bench as input. In the process ofsimulation VCS compiles the code into C source files which are in general referred as object

files. Upon conversion to object files VCS invokes C compiler which generates executable file

(Simv in our case) that is responsible for debugging and graphical representation of design. DVEis responsible for GUI debugging of the design. In order to start the process of simulation one

should go through certain process which is discussed in the following sections.

VI. Overview of Oberon profile setupEntire process of simulation and design flow takes place in working directory of oberon.Working directory internally consists of three folders source, lib, and work. Before the process of

design flow is started, all these folders should be created and complete scenario of this folder

system is given in figure 6.

Verilog

design (RTL)

VCS

Value Change

Dump (VPD)

DVE

Verilog

Testbench

Sim results

using Test

Simv

C source file

(Object file)

Executable File

C compiler RTL Simulation


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Figure 6: Complete scenario of user account

Step 1:

After logging into the Oberon server create a working directory, where entire process is going to

take place. In figure 6 working directory is Verilog. This is just an example you can have your

own names for the working directory.

[mallik@oberon ~]mkdir verilog

Keep in mind that all the operations are to be performed only after you login into the working

directory. After this is accomplished, enter into the directory using the following command;

[mallik@oberon ~]cdverilog[mallik@oberon verilog]cdsource

[mallik@oberon verilog]cdlib

[mallik@oberon verilog]cd ..

[mallik@oberon verilog]source /usr/local/scripts/synopsys

At this point of time as shown in figure 6, user is logged into working directory and has created

three folders with specific names. To view this, use ls at the terminal to have a look at contents

of the directory. Last line in the above set of commands is the most important and should be

given at the terminal every time user logs in.

Step 2:

Once user is in the working directory, he/she can enter into the source sub-directory and start

writing or editing code by opening a text editor. To open a text editor one need to use command

vi file_name. After coding is done press shift+zz without exiting the editor and it saves the workdone taking user back to main screen.

Write the testbench for the following code using the same method discussed above but using a

Verilog

(Working directory)

Source

Work

lib

User enters intooberon server

Library files

Programs

folder

Intermediate files

form Synopsys tool


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different file name or just modifying the file name. For example for the file name.v the testbench

can be name_tb.v so that there is no confusion.

Step 3:

After the program is written, to make sure the program is without any flaws we need to compilethe program along with the testbench. To compile the program, get back to the working

directory and enter the following commands at the terminal.

[mallik@oberon verilog]vcs PP name.v name_testbench.v

Above command compiles the code and the corresponding testbench. In case of any errors while

compilation one needs to check the code and remove errors. After successful compilations of the

code, user advances into the process of simulation. In case user wants to save time in running

these commands, commands can be saved in a text file with an extension of .f in the same

subdirectory where all the main files exists. Once this file is saved, to execute we follow thecommand as shown

[mallik@oberon verilog]vcs PP file.f

Step 4:

Compilation of the file is done, now what? We have to check for the simulation results. To check

the simulation results according to the inputs specified in testbench we use the command ./simv.

./simvat the terminal creates a file in the working directory with an extension .vdp. In most of the

cases the file created is vcdplus.vdp. To view this file in graphical representation use the

command

[mallik@oberon verilog] ./simv

[mallik@oberon verilog]dve vpd vcdplus.vpd

Above command invokes a new interface called DVE (Discovery Visual Environment).

Right click on the name of the module in the box and select add to waveform which shows

the simulation results in the form of a waveform. DVE will be discussed in depth later in the

document.

Note: To get vcdplus.vpd file in the current working directory, user should include $vcdpluson();

in testbench inside the initial block.

Entire process of simulation and all the above four steps will be discussed in detail with an

example in the form of a tutorial. VCS takes a set of Verilog files as input and produces an

executable simulator as an output. VCS is capable of compiling both behavioral Verilog models

and RTL Verilog models. Behavioral models are often not synthesizable, so any hardware we

intend to synthesize will need to be written at the register transfer level.


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VII. Compilation and simulation of a digital design1. Once user enters into the oberon server and then into the working directory (verilog),

compilation and simulation can be done in the following way.

[mallik@oberon ~] cd verilog

[mallik@oberon verilog] vcsPP ram_iitk.v ram_iitk_tb.v

Parsing design file 'ram_iitk.v'Parsing design file 'ram_iitk_tb.v'Top Level Modules:testTimeScale is 1 ns / 100 psStarting vcs inline pass...1 module and 0 UDP read.

However, due to incremental compilation, no re-compilation isnecessary.ld -r -m elf_i386 -o pre_vcsobj_1_1.o --whole-archive pre_vcsobj_1_1.a --no-whole-archiveif [ -x ../simv ]; then chmod -x ../simv; fi

g++ -o ../simv -melf_i386 -m32 SIM_l.o 5NrI_d.o 5NrIB_d.opre_vcsobj_1_1.o rmapats_mop.ormapats.o/usr/local/synopsys/linux/lib/libvirsim.so/usr/local/synopsys/linux/lib/librterrorinf.so/usr/local/synopsys/linux/lib/libsnpsmalloc.so/usr/local/synopsys/linux/lib/libvcsnew.so/usr/local/synopsys/linux/lib/vcs_save_restore_new.o/usr/local/synopsys/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl../simv up to dateCPU time: .048 seconds to compile + .024 seconds to elab + .180 seconds tolink

After compilation is done an executable file simv is generated by VCS as shown in figure 5. And

accessing this simv will give simulation results.VCS compiles the code based on any change inthe module or in the inputs. If there is no change in the design from the time of previous

compilation VCS gives a message as shown below;

The design hasn't changed and need not be recompiled.If you really want to, delete the file simv.daidir/.vcs.timestamp and run VCSagain.

If there is change in only few modules, only those modules will be recompiled as shown below;

TimeScale is 1 ns / 100 psStarting vcs inline pass...

1 module and 0 UDP read.recompiling module test because:This module or some inlined child module(s) has/have been modified.

if [ -x ../simv ]; then chmod -x ../simv; fig++ -o ../simv -melf_i386 -m32 _vcsobj_1_1.o 5NrI_d.o 5NrIB_d.oSIM_l.ormapats_mop.ormapats.o/usr/local/synopsys/linux/lib/libvirsim.so/usr/local/synopsys/linux/lib/librterrorinf.so/usr/local/synopsys/linux/lib/libsnpsmalloc.so/usr/local/synopsys/linux/lib/libvcsnew.so


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/usr/local/synopsys/linux/lib/vcs_save_restore_new.o/usr/local/synopsys/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl../simv up to dateCPU time: .092 seconds to compile + .020 seconds to elab + .180 seconds tolink

2. Once the compilation phase is completed, to view simulation results we need to access simvfolder at terminal so that it gives all the simulation results according to the time specified in

testbench.[mallik@oberon verilog] ./simv

Beginning Simulation...Pattern# 0 time 1950: WE=0; Address=0; Data=00; Expected Q=xx; Actual Q=xxPattern# 1 time 2950: WE=1; Address=0; Data=01; Expected Q=01; Actual Q=01Pattern# 2 time 3950: WE=1; Address=1; Data=02; Expected Q=02; Actual Q=02Pattern# 3 time 4950: WE=1; Address=2; Data=04; Expected Q=04; Actual Q=04Pattern# 4 time 5950: WE=1; Address=3; Data=08; Expected Q=08; Actual Q=08Pattern# 5 time 6950: WE=1; Address=4; Data=10; Expected Q=10; Actual Q=10Pattern# 6 time 7950: WE=1; Address=5; Data=20; Expected Q=20; Actual Q=20Pattern# 7 time 8950: WE=1; Address=6; Data=40; Expected Q=40; Actual Q=40Pattern# 8 time 9950: WE=1; Address=7; Data=80; Expected Q=80; Actual Q=80

Pattern# 9 time 10950: WE=0; Address=0; Data=07; Expected Q=01; Actual Q=01Pattern# 10 time 11950: WE=0; Address=1; Data=08; Expected Q=02; Actual Q=02Pattern# 11 time 12950: WE=0; Address=2; Data=09; Expected Q=04; Actual Q=04Pattern# 12 time 13950: WE=0; Address=3; Data=10; Expected Q=08; Actual Q=08Pattern# 13 time 14950: WE=0; Address=4; Data=11; Expected Q=10; Actual Q=10Pattern# 14 time 15950: WE=0; Address=5; Data=12; Expected Q=20; Actual Q=20Pattern# 15 time 16950: WE=0; Address=6; Data=13; Expected Q=40; Actual Q=40Pattern# 16 time 17950: WE=0; Address=7; Data=14; Expected Q=80; Actual Q=80Pattern# 17 time 18950: WE=1; Address=0; Data=aa; Expected Q=aa; Actual Q=aaPattern# 18 time 19950: WE=0; Address=0; Data=55; Expected Q=aa; Actual Q=aaPattern# 19 time 20950: WE=1; Address=0; Data=55; Expected Q=55; Actual Q=55Pattern# 20 time 21950: WE=0; Address=0; Data=aa; Expected Q=55; Actual Q=55

Good! End of Good Simulation.$finish called from file "ram_iitk_tb.v", line 94.$finish at simulation time 229500

V C S S i m u l a t i o n R e p o r t

Time: 22950000 psCPU Time: 0.480 seconds; Data structure size: 0.0MbWed Feb 29 09:44:39 2012

As mentioned earlier simulation results are according to testbench. Programs for ram ram_iitk.vand its testbench ram_iitk_tb.vare given later in the document (Appendix A).

VIII. DVE (Discovery Visual Environment) procedureNext step in this process is to debug the simulated design graphically. To fulfill this purposeDVE (Discovery Visual Environment) is used. DVE is a Graphical User Interface (GUI) for

debugging Verilog, VHDL, SystemVerilog, and System C digital designs. DVE is invoked from

VCS. A dump file vcdplus.vpd is given as input to DVE; this dump file has information

regarding simulation. Dump file is created upon introducing $vcspluson(); in the testbench of thedesign after declaration of initial block. This dump file is given as input to dve in the following

way.

[mallik@oberon verilog] dve vpd vcdplus.vpd


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Figure 7 gives an outline of DVE and gives information regarding all the possible views. Once

DVE is invoked, it displays current program and its test bench in the hierarchy panel and one cancontinue debugging by following steps mentioned in the coming sections.

Figure 7: DVE and its brief description

1. Hierarchy pane: List of all the designs modules and its testbench.2. Variable/data pane: List of all the variables that can be viewed in GUI is listed.3. Console pane: When user double clicks on a module in hierarchy pane, the code

associated with that model is displayed for debugging.

4. Tool bar: Tool bar consists of various tools that will be highlighted according to the panein which user is operating.

5. This portion of the DVE can be used for graphing signals or for viewing drivers of targetsignal. The wave view can be found in later figures regarding DVE.

6. History/Log pane: User can find list of previously used commands and can save session ifrequired.

DVE can be invoked in two different modes, post-processing mode and interactive mode. This

project deals with post-processing mode. As mentioned earlier in this post processing mode a

dump file is created from simulation and this dump file (vcdplus.vpd) is given as input to DVE.

1 2

3

4

56


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A view can have multiple instances per TopLevel window. Examples of views are Source,

Wave, List, Memory, and Schematic. Panes can be docked on any side to a Top Level window orleft floating in the area of a frame not occupied by docked panes(called the workspace) [2].

To invoke dve in post-processing mode one should give the following command at unix prompt

after simulation phase.

[mallik@oberon verilog] dve vpd vcdplus.vpd

-vpdin the above command specifies the file format that is being fed to dve. An example to theabove process regarding ram is shown in figure 8.

Figure 8: Complete GUI view of RAM through DVE


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To view wave form, right click on the name of the module and select add to waveforms new

waveform. This invokes a wave view to existing DVE as shown in figure 9.

Figure 9: Showing RAM with waveform viewOnce we have this view, all the possible ways to debug the design are discussed in the followingssections of document.

8.1 Search for signals or scopes: Noteworthy process in debugging is to find the signal andits occurrence in the design. Selecting edit > search for signals/instances pops up awindow as shown in figure 10. User can search for signals/variables, scopes, and modules

accessing figure 10. For instance, here a signal named clockis searched in the design, sosignals/variables is selected. Observe figure 11 where name of the scope is given and soscope is selected. Upon clicking search all the occurrences of the target signal are

displayed.


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Figure 10: Debugging the design by analyzing search options

Figure 11: Debugging the design by analyzing search options

Apart from this way, we can drag and drop the signal from the console pane to search

shown in figure 12.


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Figure 12: Alternate way of searching the signal

Searching signal using figure 12 takes it to the first occurrence of that signal in thesource code. Another handy feature is to check/uncheck the box at right corner of

console. This will enable or disable to open in new views. If the box is checked, there

wont be multiple views on the screen, new view is just updated on the current screenand vice versa. Refer to figure 13 for details.

Figure 13: Figure 9.4: Importance of check box

8.2 Finding values on the signal: This feature of DVE is useful in locating values on thesignal or occurrence of values on the signal. User has various options to do this step; all

the options are shown in figure 14.

Figure 14: Available options in finding values on the signal

From above figure if any edge, rising, and falling is selected, in the wave windowoccurrence of correspond edges is displayed and one can navigate among the occurrencesusing the circled option in the figure 14. If a particular value is to be searched then we

have to select value from the drop down menu and enter the target value. Figure 15

shows the scenario when it detects the target, it is represented with a vertical line across

the signal.


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Figure 15: searching for value on the signal Q [7:0] in a RAM

This particular function is to ease users debugging. It includes moving wave window to

top level or to bottom level, setting name to GUI. Refer to figures 16 and 17 for details.

When user is working with several DVE windows it is difficult to decide the desiredwindow, so giving name to each window will reduce the efforts of user. Window>moveto> new toplevel. To select a new title for the window;Window>set top level title.

Figure 16: Moving wave window to the top level

Figure 17: Setting the top level name


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8.3 Debugging state machines using wave window: While dealing with state machines, itmight become difficult to deal with number. There is a powerful and important toolprovided by DVE, to set names of states and signal shows exact name of the state as in

figure 18. Right click on the target signal and select set radix > state name to set name tothe state as defined in testbench.

Figure 18: Setting name to state machine signal

Figure 19: Result of setting state names

8.4 Set an expression / create new signal: This feature of DVE allows user to debug bysetting a new expression in the design with actually making any changes to source code.

This is an innovative feature and solves numerous glitches at its root level. Figure 20 give

complete details of how to set an expression.Right click on the signal > set expression.In figure 21 user wants to create a signal which goes to 1 (high)when signal is read but

not right in equation terms; reading phase = !WE&RE; and the wave view isupdated with a new signal as shown in fig 20. As highlighted with a dotted rectangle in

figure 21, user has various logical and combinational logic operators to set an expression.

Figure 20: Showing wave window with new signal updates


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Figure 21: setting expression to identify reading phase

Grid: Signal grid is another problem solver. User can grid signals and enable the grid count to

debug the design. This process is illustrated in figure 22. In order to enable grid on a signal,select a signal, click on grid and a new grid window opens up as shown in figure 22. Next

immediate step in starting the grid process is to clickget selected signal(s) as highlighted in thefigure. Next check the boxes enable grid count ,and show grid. User has an option to select therange (from time A to time B) of signal to be grid. Refer to figure 23 to see the grid properties.

Figure 22 and 23 shows different signals just for convenience. Viewers are not to be confused by

the signals used in both the figures. The Grid Properties window lets you have even more controlover the grid. For example you can set its cycle time to a custom value. This could be very

useful if you want to be able to visually inspect drifting clocks or duty-cycle issues, etc [7] refer

to figure 24.


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Figure 22: Available options to grid a signal

Figure 23: picture showing grid on rand signal of a module for convenience

Figure 24: Grid properties [7]


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8.5 Tracing drivers and loads: Tracing drivers plays vital role in debugging and is a veryimportant feature presented by DVE. Tracing option enables user to view drivers/loadsthat contribute to change in the value of a signal. When a driver is traced, a new Driver

pane will be created if none exists in the current top level frame. If a driver pane exists,

the driver information will be added to the top of the list. Furthermore DVE highlights

the occurrence of first driver/load in the console pane. To do this we can follow 4different ways which are listed in the document.

a. Right click on the signal and select trace loads/driversb. Directly double clicking the signalc. Using options from tool bar as showing in figure 26d. Trace >drivers/loads

Figure 255: trace drivers by right click on the

signals

Figure 266: Trace drivers by clicking on tool bar

Figure 27 shows tracing of drivers for signal randin the design. The drivers pane on theright shows the occurrence of the drivers, and it reads V1:mainpr. This mean the signalrand is found in the main program of source code (not the rest bench) and is highlighted

in the hierarchy pane.

Figure 27: DVE showing drivers of rand signal

Figure 27 shows all the possible mentions of rand signal occurrences except for theoccurrence in the console pane. Occurrence of rand signal in console pane is shown infigure 28.


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Figure 28: Point drivers ofrandin console pane

DVE when ran in interactive mode, many other debugging features come into practice.

a. Execute UCLI/Tcl commandsb. Set line, time, or event break pointsc. Line steppingd. Using interactive rewind feature (extremely useful)e. View annotations reflecting the actual value (powerful debug tool)

Verilog code for RAM design: ram_iitk.v. Refer to appendix AVerilog testbench for RAM: ram_iitk_tb.v Refer to appendix A

Next stage to compilation, simulation, and debugging is synthesis. At this stage, design compiler

(dc_shell in short) accepts totally simulated and verified design along with standard cell library

as input and initiates the process of synthesis.


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IX. Design Compiler9.1 Introduction

Design compiler is a logic synthesis tool provided by Synopsys. The process of translating RTL

design into a gate-level design is called synthesis.RTL synthesis is an automated design task in

which high-level design descriptions written in Hardware Description Languages (such as

VHDL, Verilog, or SystemVerilog) are transformed into gate-level netlist that is technology

dependent. Gate-level netlist is fundamentally an implementation of the current design using

library modules (pre-defined gates in the standard cell (technology) library) and their

interconnections. Complete picture of design compiler is shown in figure 29. The synthesis tool

(dc compiler) follows several steps in achieving the end product (gate-level netlist) which are

outlined in figure 30. Each of these steps will be discussed in detail in the following sections.

9.2 Specify and link Target technology: At this stage user specifies various technology libraryfiles and their locations. To synthesize a design, user needs technology library that will

contain description of the cells from the manufacturer, and their timing. This is usually a .dbfile found in library installation directory [8]. To synthesize a design we need to follow the

process as given below

i. Specify search path to acquire .db file by search_pathii. Specify technology library that user wants his/her design to be mapped to.

settarget_libraryiii. Specify link libraries, this is an optional .db files which are pre synthesized and

ready to be read in.setlink_library

iv. Specify symbol library: Symbol libraries contain definitions of the graphicsymbols that represent library cells in the design schematics. Semiconductor

vendors maintain and distribute the symbol libraries. Design Compiler usessymbol libraries to generate the design schematic [9].Set symbol_library

The entire process is done in our case by setup file .synopsys_dc.setup which isusually found in either synopsys root directory or in users home directory. Fragment of

setup file is displayed below.

# Search Pathsetsearch_path "$search_path ./libs ./source ./db ./"

# Setup libraries

setlink_library "* core_typ.db"settarget_library "core_typ.db"setsymbol_library "core.sdb"

9.3 Analyze and Elaborate phase: Synthesis is a complex task consisting of many phases andrequires various inputs in order to produce a functionally correct netlist [8]. At this step the

HDL design is read into design compiler for synthesis.


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Overview of Design compiler

Figure 29: Design compiler process


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Figure 30: Design Compiler and its internal process

This is done in two steps analyze and elaborate. In analyze phase, the source design is

read and checked for any syntax errors, if found should be rectified before proceeding to

elaborate phase. Creates HDL library objects in an HDL-independent intermediate

Verilog

design (RTL)

Library Files

Design

Compiler

Analyze and

Elaborate

Phase

Apply

Constraints

Specify and link

Target technology

Uniquify

Mapping and

Optimization

Compile

Gate-levelNetlist

StandardDelay Format

DesignConstraints file


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format and saves these intermediate files in a specified location

home/verilog/work

Once an analysis is completed we proceed to elaborate phase. During elaborate phase:i. Design Compiler translates the design into a technology-independent design

(GTECH) from the intermediate files produced during analysis

ii. Replaces the HDL arithmetic operators in code with technology librarycomponentsiii. Links the design automatically to all the essential referencesiv. Allows changing of parameter values (generics) defined in the source codemoduleRamChip (Address, Data, CS, WE, OE);parameterAddressSize = 1;parameterWordSize = 1;input [AddressSize-1:0] Address;inout [WordSize-1:0] Data;input CS, WE, OE;

reg [WordSize-1:0] Mem [0:1


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technology library. The cell and wire delays are scaled according to these

conditions.ii. Modeling wire loads: Wire load models are used to estimate the effect of

interconnect nets on capacitance, resistance, and area before real data is obtained

from the actual layout. These models are statistical models and they estimate the

wire length as a function of net's fanout [10].9.6 Optimizing the design: At this particular point of time, Design Compiler maps the HDLsource code with cells available in the technology library. After the mapping is completed

it translates the HDL into gate-level netlist. Optimization is done in several phases.According to the constraints specified during synthesis, different optimization procedures

are applied. Optimization is done on three different levels.

9.6.1 Architectural Level: High-level optimization on HDL design modules correspondsto architectural level. Some of the tasks included in architectural level are:

a.Arithmetic Optimization: Design Compiler rearranges the operations inarithmetic expressions according to constraints applied, to minimize

timing or the area of gate-level design. These rearrangements are

performed to improve implementation of the design and are based on rulesof algebra.

b.Resource Sharing: Resource Sharing is done for better area constraint(minimum area). Resource sharing refers to sharing of single hardware

resource with multiple hardware operators in GTECH (generic

technology-independent netlist). Nonexistence of resource sharing resultsin repeated hardware of similar functionality and also in the increase of

area.

c. Selecting DesignWare Implementation: Selecting a DesignWareimplementation means that the implementation selection of a particularresource is left to the Design Compiler. For example, the Basic IP Library

contains two implementations (ripple and carry-lookahead) for the +

operator (the DesignWare Foundation Library provides more

implementations for the '+' and other operators). When selectingDesignWare implementation, Design Compiler considers all available

implementations and makes it selection according to your constraints [10].

9.6.2 Logic Level Optimizations: In the synthesis process HDL design is now a GTECHnetlist. As a part of Logic level optimizations on the design, structuring andflattening of the design is implemented.

a. Structuring: Structuring evaluates the design equations represented by theGTECH netlist and tries by using Boolean algebra to factor out common

sub-expressions in these equations. The sub-expressions that have been

identified and factored out can then be shared between the equations [10].

Structuring can be set for timing(default) or Boolean optimization. Thelater helps in reducing area, but has a greater impact on timing. Thus

circuits that are timing sensitive should not be structured for Boolean

optimization.


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Table 7: Logic level optimization showing structuring [2]

Before structuring After structuring

P = ax + ay + cQ = x + y + z

I = x + y

P = aI + cQ = I + z

b.Flattening: Conversion of logic into two level sum-of-products form iscalled Flattening. Flattening produces fast logic (by minimizing the levels

of logic between the inputs and outputs) at the expense of the area increase

[10]. In general one should compile the design using default settings(flatten and structure are set as false). If timing objectives are not met

flattening and structuring should be employed. Flattening of a design is

recommended if and only if the design contains unstructured or random

logic.9.6.3 Gate level Optimizations: Conversion of technology-independent netlist into

technology-dependent netlist is known as Gate level optimizations. This

conversion is done by mapping cells in technology-independent netlist to standard

library cells. Several gate-level optimizations in the synthesis process are listedbelow:

a.Mapping: The term Mapping is self-explanatory. The above discussedmapping which aids in conversion is done at this particular stage.

b.Delay Optimization: After mapping to cells in standard technology librarythere is a possibility of timing violations. This timing violations is fixed by

delay optimization.c.Design rule fixing: Design Compiler inserts buffers or resizes existing

cells in order to fix design rule violations. In this process of fixing design

rules timing constraints can be violated (as discussed in stage 3).

d.Area Optimization: Area optimization is the last step that Design Compilerperforms on the design. During this phase, only those optimizations thatdon't break design rules or timing constraints are allowed [10].

All the optimizations performed depend on constraints specified by user. As a

matter of this reason, setting realistic constraints is mandatory in the process of

synthesis.

9.7 Analysis of the results: Analyzing the results is as important as all the above steps insynthesis process. User can choose to use Design Vision (GUI of Design compiler) toanalyze the results. Design analysis can be done using two methods:

9.7.1 Generating textual reports for design properties: This step includes invokingseveral commands at terminal to generate reports for vital design objects namely

timing and area, cells, clocks, ports, buses, pins, nets, hierarchy, resources,

constraints in the design.9.7.2 Visualizing design objects (GUI): Viewing schematic, symbol view, hierarchy

view, and viewing other graphical properties can be performed at this stage.Analysis is done to examine and confirm that the user specified constraints is met during

the synthesis process and if needed re-synthesis is done.

9.8 Saving design: Saving design in several useful formats should be done to convey thespecified constraints during the synthesis process, to successive stages of ASIC

implementation flow (figure 1).


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X.Design Compiler tutorial:First and foremost process is to invoke design compiler. In order to do this, user has to be in

working directory (verilog, in this case, refer to figure 6).

[mallik@oberon verilog] dc_shell

10.1 After invoking the Design Compiler (will be referred as dc_shell ), linking the targetlibrary and source library is done. and the process of analyze and elaborate is to beperformed. Refer to previous section for more details on analyze and elaborate:

dc_shell> set link_librarysaed90nm_max.dbsaed90nm_max.dbdc_shell> set target_librarysaed90nm_max.dbsaednm90nm_max.db

10.2 The next stage is to read the design. This can be done in two ways. If the design is in.ddc format we can directly perform analyze and elaborate in a single step with the

help ofread_ddc. For designs in verilog the process ofanalyze and elaborate is to beperformed. Refer to previous section for more details on analyze and elaborateFormat for both analyze and elaborate:

dc_shell>analyze -format -lib \

dc_shell>elaborate -arch -lib param

Correspondingly commands applied on ram_iitk.v whose module name is reg_sram isgiven below:

dc_shell> analyze -format verilog -lib work ram_iitk.vRunning PRESTO HDLCSearching for ./ram_iitk.vSearching for /usr/local/synopsys/libraries/syn/ram_iitk.vSearching for /usr/local/synopsys/dw/syn_ver/ram_iitk.vSearching for /usr/local/synopsys/dw/sim_ver/ram_iitk.vSearching for ./libs/ram_iitk.vSearching for ./source/ram_iitk.vCompiling source file ./source/ram_iitk.vWarning: ./source/ram_iitk.v:24: Intraassignment delays for blockingassignments are ignored. (VER-129)Warning: ./source/ram_iitk.v:32: Intraassignment delays for blockingassignments are ignored. (VER-129)Presto compilation completed successfully.

Loading db file '/home/mallik/verilog/libs/saed90nm_max.db'1

Success message is indicated by binary notation, 1 for success and 0 for failure.

In the elaborate command, name of the module is reg_sram and format of thearchitecture is verilog:


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dc_shell> elaborate -arch verilog -lib work reg_sramRunning PRESTO HDLC

Inferred memory devices in processin routine reg_sram line 17 in file'./source/ram_iitk.v'.===============================================================================

| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |===============================================================================| mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N || mem_data_reg | Flip-flop | 8 | Y | N | N | N | N | N | N |===============================================================================Statistics for MUX_OPs===========================================================| block name/line | Inputs | Outputs | # sel inputs | MB |===========================================================

| reg_sram/20 | 8 | 8 | 3 | N |===========================================================Presto compilation completed successfully.Elaborated 1 design.Current design is now 'reg_sram'.1

This information tells you the Design Compiler decided to infer memory type (flip-flop

or latch) as flip-flop, the number of bits (8), whether it uses an asynchronous set/reset

(AS, AR) or synchronous set/reset (SS, SR) and some other information. Verifying theseresults would give user accuracy.

10.3 To ensure that we are optimizing top_level design, we use current_design. At this stageuser sets module of interest as current module:

dc_shell>current_designCurrent design is 'reg_sram'.{reg_sram}

10.4 At this stage user verifies that the design compiler is able to read all modules regardingsource design (link). Command uniquify instantiates all defined modules as aseparate modules. If a module is instantiated more than one time, this command will

make separate modules for each instance. This allows each to be optimized independentlyfor their particular usage [11]:

dc_shell> linkLinking design 'reg_sram'

Using the following designs and libraries:-------------------------------------------------------------saed90nm_max (library) /home/mallik/verilog/libs/saed90nm_max.db

1dc_shell>uniquify // check the design for errors such as

//missing module definitions1


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10.5 Following above process design is read into the Design Compilers memory. The designis analyzed for the syntactical errors and non-synthesizable structures and prepared forsynthesis by analyze and elaborate commands. Designs consistency never came as a point

of interest but at this stage user needs to check the design consistency and internal

representation of the design so ru

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