Kcr VerilogHDL Summer Course 08 (1)

8/7/2019 Kcr VerilogHDL Summer Course 08 (1)

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Digital Designusing

VerilogHDL

Presented by

Kailash Chandra [email protected] VLSI Design Laboratory

Indian Institute Of Technology, Kharagpur


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VLSI DESIGN FLOW :Front End Design

Logic design

Logic Net list

specification

Architectural Design

Design verification

Logic verification

Behavioral

representation

Gate levelrepresentation

Algorithmic analysis

SYNTHESIS


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CONTROLLERLOGIC

REG1 REG2

REG3

LogicMainLogicUnit

DATA PATH CONTROL

An Example: Typical Architecture of IC

Logic


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A Laboratory Flow for ASIC Design (Cell Based)

Verilog-XL (Cadence)

SimVision (Cadence)

Design Compiler (Synopsys)

Silicon Ensemble (Cadence)

Hercules (Avant)

HDL

Logic Simulation

Synthesis

Physical Design

Physical

Verification


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Hardware Description Language

HDL

VHDL VerilogHDL


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VerilogHDL: History

Gateway Design Automation Cadence purchased Gateway in 1989. Verilog was placed in the public domain. Open Verilog International (OVI) was created

to develop the Verilog Language as IEEEstandard.


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Identifiers & Logic Values in Verilog

Identifiers

Any Sequence of letter, digits,dollar sign, underscore.

First character must be aletter or underscore.

It cannot be a dollar sign.

Cannot use characters such ashyphen, brackets, or # inverilog names

Logic Values

Predefined logic value systemor value set:0, 1 ,x and z;

x means uninitialized orunknown logic value

z means high impedancevalue .


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Verilog Data Types

Integer

Nets: Key Word is WIRE

Registers : Key Word is REG

Temporary storage of variables similar to high level languages.

Wires: Key Word is WIRE

Analogous to a wire in an ASIC. Cannot store or hold a value.


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Hierarchical Design using modular concept

top_module

module1 module2 Module-n


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Black Box Design for VLSI Architecture of aCHIP

BLACK BOX(Module)I/P PORTS

Module Definition

O/P PORTS

I/O PORTS


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module module_name (port_names );-----------port_types-----------wire declarationreg declaration

-----------

endmodule

Modular Design using Verilog HDL

Black Box

description

input [port_size ] input_port_names ; output [port_size ] output_port_names ;wire [wire_size ] wire_names ;

reg [reg_size ] reg_names ;


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Module Instatiation

Module top_module_name(Port_names);input [port_size] input_port_names;

output [port_size] output_port_names;wire [wire_size] wire_names;------------module_name1 instatiation_name1( port_conections );module_name2 instatiation_name2( port_conections );-----------endmodule

By Position/Ordering By Names


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PORT CONNECTIONS: An Example

moda

modb

modc

in0

in1

in3

w1

w2

top_mod

out

a1

a2

a3

b1

b2 b3

c1

c2

c3


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Port Connections in Verilog HDL(By Position/Ordering)

module moda (a1,a2,a3);input a1,a2;output a3;

-----endmodule

module modb (b1,b2,b3)input b1,b2;output b3-----Endmodule

module modc (c1,c2,c3)input c1,c2;output c3-----endmodule

moda

modb

modc

in0

in1

in3

w1

w2

top_mod

out

a1

a2a3

b1b2 b3

c1

c2c3

module top_mod(in0,in1,in2,out);input in0,in1,in2;output out;

wire w1,w2; moda mi0(in0,in1,w1); modb mi1(in1,in2,w2); modc mi2(w1,w2,out);endmodule


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Port Connections in Verilog HDL (By Name)

module moda (a1,a2,a3);input a1,a2;output a3;

-----endmodule

module modb (b1,b2,b3)input b1,b2;output b3-----endmodule

module modc (c1,c2,c3)input b1,b2;output c3-----endmodule

moda

modb

modc

in0

in1

in3

w1

w2

top_mod

out

a1

a2a3

b1b2 b3

c1

c2c3

module top_mod(in0,in1,in2,out);input in0,in1,in2;output out;wire w1,w2;

moda mi0(. a1 (in0), . a2 (in1), . a3 (w1)); modb mi1(. b1 (in1), . b2 (in2), . b3 (w2)); modc mi2(. c1(w1), . c2(w2), . c3(out));

endmodule


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Modular Design using Verilog HDL

module module_name (port_names);-----------

port_types-----------wire declarationreg declaration

endmodule

Black Boxdescription

Switch level description

Gate level description

Data Flow description

Behavioral description


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Switch Level Design

nmospmos

MOS Transistors as Switch

S D

G

DS

G


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Switch Level Design (cont..)

CMOS Inverter design : As an Example

in out

vdd

gnd

nmos

pmos

module cmos_inv (vdd, gnd, in, out);input vdd, gnd;input in;output out;

pmos p0 (vdd, out, in);nmos n0 (out, gnd, in);

endmodule


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Switch Level Design (cont..)

Design and Model following components usingVerilog HDL

Design NAND,NOR gates using CMOS logic

Integrate for AND,OR,XOR gates

Design Transmission gates using pass transistors

Design Macro modules like multiplexers,demultiplexers, Flipflops, Adder, Subtractor and etc.


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Gate Level/Structural Design

Multiplexer using primitives module mux (f, a, b, sel );output f ;

input a, b, sel ;wire nsel, f1, f2 ;

and g1( f1, a, nsel ),and g2( f2, b, sel );or g3( f, f1, f2 );

not g4( nsel, sel );

endmodule

a

b

sel

fnsel f1

f2

g1

g2

g3g4


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An Example: 4-bit Adder design

4-bit adder

FA FA FA

sum carry sum carry sum

FA

sumcarry carry


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Structural representation example

//4-bit addermodule add4bit (s, c4, ci, a, b);input [3:0] a, b;input ci;output [3:0] s;output c4;

wire [2:0] co;FA a0 (co[0], s[0], a[0], b[0], ci);FA a1 (co[1], s[1], a[1], b[1], co[0]);

FA a2 (co[2], s[2], a[2], b[2], co[1]);FA a3 (c4, s[3], a[3], b[3], co[2]);endmodule

module FA (co, s, a, b, c);input a, b, c;

output s, co;sum s1 (s, a, b, c);carry c1 (co, a, b, c);endmodule

module carry (co, a, b, c);input a, b, c;

output co;wire x, y, z;and g1 (x, a, b);and g2 (y, a, c);and g3 (z, b, c);

or g4 (co, x, y, z);endmodulemodule sum ( s, a, b, c);input a, b, c;

output s;xor x1(s,a,b,c)endmodule


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Dataflow Design

RHS assigned by LHS

Conditional statementsOrLogic Expressions


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Dataflow Design (cont..)

RHS assigned by LHS Usingconditional statements

module mux (f, a, b, sel);output f;input a, b, sel;

assign f


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Behavioral Design

Some of Behavioral Key words are

Conditional Statements : If, ifelse, case;

Loop Statements : for, while, forever;

Behavioral Blocks: always, initial


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module module_name (port_names );

endmodule

module mux (f, a, b, sel );

input [ 3:0 ]a, b ;input sel ;output [ 3:0 ] f ;reg [ 3:0 ] f ;

always @( a or b or sel )

if (sel)

f = b ;else

f = a ;

endmodule

Behavioral Verilog HDL codes

always @(sensitivity list).behavioral statements

.

input [port_size ] input_port_names ;

output [port_size ] output_port_names ;wire [wire_size ] wire_names ; reg [reg_size ] reg_names ;

Multiplexer: As an Example


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Flipflop Design: An Example

module DFF ( d, q, qbar, clk, reset );input d,clk,reset ;output q,qbar ;reg q,qbar ;

always @( posedge clk or posedge reset )beginif ( sel )

beginq = 1b0 ;qbar = 1b1 ;end

elsebeginq = d;qbar = ~d ;end

endendmodule


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Behavioral Statements

Continuous assignment Statementsusing assign

Procedural assignment statements:

Blocking assignment ( using = )

Non blocking assignment ( using


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Blocks Statements

Sequential Block statements: Sequential block is a group of statements between a

begin and an end . A sequential block, in an always statement executes

repeatedly.

Inside an initial statement, it operates only once .Parallel Block statements :Statements are enclosed within

fork ....

join


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Block statements: Examples

always @(a or b or c);begin

#5 d = a+b;#10 e = a-c;#15 f = b+c;

end

always @(a or b or c);fork

#5 d = a+b;#10 e = a-c;#15 f = b+c;

join

initialbegin#5 d = a+b;#10 e = a-c;#15 f = b+c;

end

E l


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Examples

Blocking:always @(A1 or B1 or C1 or M1)begin

M1=#3(A1 & B1);Y1= #1(M1|C1);end

Non-blocking:always @(A2 or B2 or C2 or M2)begin

M2


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Example: Physical Implementation

Blocking Assignmentmodule BA (clk, a, b, c )input clk, a, b;output c;reg b, c;always @(posedge clk)

beginb =a;c =b;

endendmodule

Non Blocking Assignmentmodule NBA (clk, a, b, c )input clk, a, b;output c;reg b, c;always @(posedge clk)

beginb


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Example: Physical Implementation

DFF

DFF

DFF DFF

a b

c

a

b c

blocking Non-blocking


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Design using Functions & Tasks

Functionmodule m_name (port_declaration)Beginret_val = func_name (arguments );end

function func_name ;// declarationinput declarationvariable_declarationbegin

endendfunction

endmodule

Taskmodule m_name (port_declaration)Begintask_name (arguments );end

task task_name ;// declarationinput declarationoutput declarationvariable_declaration

begin end

endtask

endmodule


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FSM Design using VerilogHDL

module parity (clk, reset, i, o);input clk, reset, i;output o;reg st, next_st, o;

parameter st_even = 0, st_odd = 1;

always @(posedge clk or posedge reset) begin

if (reset == 1)st


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State Transitions & Output computations

//State Transitionsalways @(i or st)begin

if (i == 1) beginif (st == st_even)

next_st = st_odd;else

next_st = st_even;endelse

next_st = st;

end

//Output Computationalways @(st)begin

if (st == st_even)o = 0;else

o = 1;end

Even/0

Odd/1

Reset

i=1 i=1

l h


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Test VectorGenerator

Simulation using Test Bench

Testbench generates stimulus and checks response Coupled to model of the system Pair is run simultaneously

Testbench

(tb.v)

System Model

(top.v )

Stimulus

ResponseResult

checker

An Example: multiplexer


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An Example: multiplexer

//mux21.v module mux21 (in0, in1, sel, out);input in0,in1,sel;output out;assign out = (~sel & in0)| (sel & in1);

endmodule

//tb_mux21.v module tb_mux21 (in0, in1, sel, out);

reg IN0,IN1,SEL;wire OUT;

mux21 muxtop(IN0, IN1, SEL, OUT);initial //Test Vector Generator

begin

IN0=1b1; IN1=1b0;SEL=1b1;#2 IN0=1b1; #3 IN1=1b0; #5 SEL=1b1;endinitial //Check Response$display(%b,%b,%b,%b, IN0, IN1,SEL,OUT);

endmodule

T t B h ith Hi h l l L


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Test Bench with High level Language

PLI

Test VectorGenerator

Testbench (tb.c/c++)

System Model(top.v )

Result

checker

C l i


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Conclusion

Write RTL codes i.e. Synthesizable codes fordesign

Avoid Non Synthesizable codesi.e. initial, #, while

Write Mixed codes in Test BenchWrite codes which can be translated into hardware

Write structural codes for design on your effort

Finally, remember that you are a better designer than the tool!

Reference


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Reference

1. Introduction to Verilog HDL

By Sameer Panitkar


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Thank You

Documents

Kcr VerilogHDL Summer Course 08 (1)