Electronic-Photonic IntegrationGrand Challenges and Key Needs for 2019

Datacom – RF – SensingCost – Energy Density - Bandwidth Density

Lionel C. KimerlingMIT

AIM Photonics Institute

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Challenges and Needs for 2019

§ Critical Themes (2019)r ASIC co-packaging – Optical Connectors – High Density

§ Technologyr TxRx (DC) - RF Signal Processing (5G) – Sensing (chem)

§ Economicsr Time-to-$ - Supply Chain Coordination

§ Success in 2019 r Continuity: electronic-photonic integration

Outline: Economics, Technology, Manufacturing

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“More Moore”§ scaling clock frequency, transistor count and

dimensions§ scaling chips/package or packages/board count?“More-than-Moore”§ everything is an option for continued scaling§ new technology (nano, quantum, photons?)Integrated Photonics§ communication-centric architectures§ system level design

Define the Scaling Vector3

Integrated Photonic Manufacturing Ramp§ Commercial ramp is strong, as expected.

r Luxtera and Kotura first to marketr Intel® Silicon Photonics 100G PSM4 QSFP28 Optical Transceiver

§ hyperscale data centers: Amazon, Google, Microsoft, Baidu, Tencent, LinkedIn, Alibaba, and Facebook

r System vendors: Juniper, Dell, NTT, HPE, CISCO, CIENA, IBM, HUAWEI, TEr Chip manufacturers and supply chain: Broadcom, STMicro, Seagate, MACOM r Global Foundries, ST Micro, TSMC, TowerJazz run product.r AIM, CEA-LETI, imec, VTT, IHP, TUE, NRC, IME,… run R&D with PDKs.

§ Design infrastructure has been truly disruptive to chip fab§ Cpk and Test are the critical path to on-time product IPSR-I 2018

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Charter: Determine the evolution of the chip-package-system level interconnection hierarchy for electronic-photonic systems.The introduction of distance independent photonic interconnection will likely be disruptive to the standard 7-level interconnection hierarchy. Specification and scaling paths for the following metrics will be delivered.§ cost, density, bandwidth, latency, power dissipation, materials integration

system requirements for data centers§ mesh architectures, global network reconfiguration§ optical and electrical power delivery, I/O ports§ supply chain nodes§ interfaces, connectors, circuit stacking, form factors at all levels§ test, yield and reliability

Grand Challenge: Electronic-Photonic Interconnection 2035

MIT Microphotonics Center

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Miniaturization – Disaggregation – System-in-Package – System-on-Chip

Si Photonic SiP Si Photonic SoCOn-Board Optics

Conventional Server Motherboard

Facebook-Designed Motherboards Disaggregation

• Optics-on-Board (2016)• DC switch: 51.2 Tbps (2023)

• Optics-in-Package (2020)• TxRx “Chiplet”

• Optics-on-Chip (2025)• Optical Signal Processor (5G)

Where is the laserduring these transitions?

Embedded MonolithicChiplet-in-Package

Pluggable

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from TxRx to Package Integration

compliments of Robert Blum, Intel

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E-P Interconnection 2018§ Cu Technologies: Well Advanced with no Supply or Technical Issues

r Cu on chip R&D vs. Al incumbent solutions: CMP, low k dielectric, diffusion barriers

§ Optics on Board Needs Solutionsr Planar SM waveguide technology; TxRx surface mount technology (board,package)

§ Conventional motherboard packaging reduced as Modules increase§ Business Trends: value point migration is changing business models

r end users (e.g., data center) designing their own chips

§ Silicon Photonics is critically dependent on the evolving supply chainr Materials, processes, architectures and designsr Chip functionality developments and a Roadmap to E-P circuitry

John MacWilliams, E-P 2035 study

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Moving Photonics from the I/O ports into the System9

Photonic Interconnection: Board

Board – Package - Chip

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On-Board Optical Interconnection Before the benefits of silicon photonics can be realized, new high performance and cost effective solutions to optical packaging and connectorization must be developed.§ Optimum performance and functionality from silicon photonic devices and

circuits require single mode (SM).§ SM requires precision alignment inside the package and in optical connectors.

r expanded-beam (10um expanded to 80um) optical connectors relieve alignment and dust limitations

r early entry for MM at short reach?

Technology: TxRx

Optical interfaces degrade performance and increase cost.OBOI AIG: Terry Smith, 3M; Tom Marrapode, Molex

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AIG for On-Board Optical Interconnection

Charter: assess technology benefits and issues§ SM expanded-beam

connector interfaces in board-level optical interconnection

by building and testing systems.Phase 1§ Surface mount > pluggable§ SM e-b connector loss

r 0.3dB best channelr 0.6dB average all channels

Phase 2§ Package-level connector

Line Card

SubstrateSiPh

Back

plan

e

Laser

Chip-to-FiberAttachment Element

Module-MountedReceptacle Body

Expanded-BeamFerrules

Module ConnectorBody

Backplane AdaptorBody

BackplaneConnector

Body Expanded-BeamFerrules

SM FiberCables

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iNEMI-IPSR-AIM-MIT Microphotonics Center Consortium Connector Technology Working Group

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Expanded-Beam Connector ImplementationConcerns• Typically higher loss.

• Anti-reflection coatings may be required.

• Tighter angular alignment• Typically easier to obtain than lateral

alignment.• Tight tolerances for fiber-connector

• Molded optics and fiber holder

Advantages• Relaxed alignment precision

• Beam size ~ 80µ instead of 9µ• Greater tolerance to debris• Lower mating force

• No need for “physical contact” of optical cores.

• Potential for lower-cost systems• Lower precision in manufacturing• Lower maintenance

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AIGs: Application Interest Groups

§ Phase 1: define system requirements§ Phase 2: define technology gaps and options§ Phase 3: prototype and test solutions

r Datacom: A Scalable Transceiver for On-Board Datacom r LIDAR: A Higher Definition AR Camera System r Analog RF: A Compact Base Station for 5Gbit/s Wireless r Sensing: An Integrated Photonic CH4 Sensor for Pipelines

currently active: INEMI administrative support for “On-Board”

Marrapode, Smith, Agarwal, Glick, Saini, Wada

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Photonic Interconnection: Package

Board – Package - Chip

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Laser IntegrationIPSR Spring 2016, Ishii

Dist

ance

from

Chi

p

IntelNTT

Ghent

Luxtera

AIST

Package Architecture

IPSR Fall 2018

AIMAIO CoreMACOM

chip

interposer

board

rack

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IPSR International: Evaluation of Laser Integration Options

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Techniquesà Hybrid (flip-chip) Integration Heterogeneous integration by adhesive/direct bonding Direct Growth of InP on Siliconun-patterned III-V epitaxy

(die-to-wafer bonding /transfer printing)

(semi-)processed lasers by transfer printing

Specification 2018 2020 2025 2035 2018 2020 2025 2035 2018 2020 2025 2035 2018 2020 2025 2035

Integration process

complexity

Heat Sinking

Integration density

III-V material usage efficiency

Wafer scale integration

Laser integration process

throughputLaser test before

integration

Option Maturity (TRL)

Abdul Rahim, U Ghent

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Electronic-Photonic Integration

§ Hybrid always precedes monolithicr E and P technology nodes advancing at different ratesr Chip-package co-design necessary for performance scalingr Assembly yield penalty limits cost scaling

§ Monolithic is the ultimate solutionr Benefits: cost, design, performancer Challenges: density, interconnection, packaging

Near term compromise proposal: integrate node-insensitive e-p functionse.g., stability control circuitry for a universal WDM interface

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Photonic Interconnection: Chip

Board – Package - Chip

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Monolithic Integrated Isolator: 40dB isolation, 3dB loss

Resonant isolator• Small footprint• Resonant λ

depends on propagation direction

C A Ross and J J Hu, MIT

TE and TM mode optical isolatorsDemonstrated ring resonator and Mach-Zehnder interferometer devices• TM Ring resonator: 40 dB isolation, 3 dB loss• TE Ring resonator: 20 dB isolation, 11.5 dB loss• TM MZI: 30 dB isolation, 20 dB over 2 nm bandwidth, 6 dB loss.• TE MZI: 30 dB isolation, 10 dB over 2 nm bandwidth, 9 dB loss.

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World best performance integrated isolator:A monolithic magneto-optical isolator with 3 dB insertion loss and 40 dB isolation ratio

• CeYIG is under the waveguide• Grey scale lithography

ACS Photonics (21 Nov 2018)

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Integrated Photonics Applications

Sensing – RF/5G/Lidar – Videoproduction – transport – process – display

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Telepresence

§ Simulation and 3D visualization wil transmit nuance of “presence.”§ Benefit metrics for telepresence: FoM = function/joule

r decreased carbon footprint of optional transportationr lesser exposure to global pathogensr Efficiency and security of temporal “presence”r savings in space, weight and energy

§ What is a reasonable telepresence scaling target?r 7680 x 4320 pixels, RGB, 12bit, 240 fps, 2 views = 600 Gbpsr scale to 600 fps x 256 views = 180 Tbps per participant

video: production – transport – process – display2

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2020 Olympics: Consider a stadium being covered by eight 8K UHD cameras. How would these be sighted around the action?§ Uncompressed data from cameras would be 7680 x 4320 pixels, 3 x 12bit

per pixel at 120 fps = 143.33Gb/s multiplied by the number of cameras in this example = 1147Gb/s. (higher frame rates are likely in future)

§ To extract live multi-platform “scene” streams from this pool of datar cameras must be synchronized and their positions closely referencedr optical connections would be required between cameras and “scene processing”

How much processing power will reside in the Data Center?How much ‘reality’ will survive “live VR” compression by simulation.

NHK’s Super High Vision: Video

Chris Chambers, BBC, retired

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NHK’s Super High Vision: Audio§ The cost of the audio bandwidth is small compared to the cost of the

codex, latency and potential quality issuesr linear stereo stream at 48Khz 24 bits will fit within 3Mhz

§ Super High Vision's 22.2 sound format: 24 channels in layersr a large set of microphones to produce audio perspectiver 22.2 format in linear format stream is 55 Mbits which extremely small compared

to the 8k videor the challenge is how an end consumer gets a sensible balance in 7.1, 5.1, stereo

or even mono if the source is 22.2.Telepresence is much more than high data rate hardware.

Capturing, transmitting and reproducing audio perception is an unsolved problem.Chris Chambers, BBC, retired

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Integrated Photonics Applications

Sensing – RF/5G/Lidar - Video

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5G Service Provider Goals

Dennis Prather, U Delaware

Conventional Free Space Communication

• reduced interference by "imaging" RF signals on to a detector plane

• passive optical processing of "up-converted” RF signals from multiple sources

• reduced SWaP-C by integration of the major components of the system

RF-Photonic Communication

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Dennis Prather, U Delaware

5G is more than BW: Beam-Space Processing

Beam-Space Processing• Optical phased arrays• Electrical phased arrays• Optical matrix address• Efficient point-to-point• Spatially resolved sources

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Integrated Photonics Applications

Sensing – RF/5G/Lidar - Video

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IoT and Sensor Networks30

Basic sensor component: photon source, filter, detector, ASIC§ Free space apps should not be neglected.

Generic IoT: 3D-SiP package architecture§ heterogeneous integration of sensors, RF, memory, photonics§ general purpose SiP-IoT hub environments (uncontrolled)§ both tethered and energy scavenged power§ redundancy to ensure long term, service free reliability

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Quantitative analysis of multi-component mixtures

Dual-mode Detectionrefractometry and absorption spectroscopy

Chen et al., ACS Nano 8, 6955 (2014).

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Photonic Microfluidic Integration

Optofluidic integration• Minimal sample amount requirement: < 0.1 µL

• Multiple functionalities on a single chip• analyte sampling, separation, purification

PDMS: POLY-DI-METHYL-SILOXANE

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Digital Fourier Transform (dFT) Spectrometer

input detection

dL

-2 dL

22 dL

-23 dL -25 dL

24 dL

DOWN

UP

DOWN DOWN

UP UPDOWN

UP

21

gn dLllD = ×

2 j

N = 2 j

J J Hu, MIT

Device fabricated using R&D silicon photonics foundry

service

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Economically-Aware Photonics

Understanding Cost Barriers to Widescale Adoption

Randy Kirchain, MIT

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Disaggregation is Modular DesignThe traditional data center design has been hitting several challenges:The various server elements follow different trends of cost and performance. § Upgrading of the CPU or memory in the traditional design requires an entirely new server with

new motherboard design at considerable expense and economic waste.

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Cost of lead time and uncertainty for datacenters

§ Interconnects represent a significant cost for datacenters

§ For all hardware, data centers incur an inventory holding cost

§ Because bandwidth demand is growing and capital comes in “chunks”, a data center is often capacitized to meet the demands at the end of the hardware life cycle

§ This extra capacity costs to purchase and maintain, but sits as idle inventory

Datacenter“inventory” cost

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The Data Center Upgrade Decision

W. Yu and R. Kirchain, MIT

§ Total cost =

+ (Purchase + Operating) cost

+ Inventory cost

+ Shortage cost (Revenue loss from not

having enough capacity)

§ Longer or uncertain lead time can

lead to equal total cost even when (Purchase + Operating) cost is 25%

lower.

§ Creates a strong incentive to stick

with an existing technology

r has lower conventional life-cycle cost

(i.e., lower purchase+ operating cost)(Purchase + Operating) Cost ($/unit)

Lead

tim

e (m

onth

s)

Iso-Total-Cost Curve

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Supply Chain Coordination

Outline: Economics, Technology, Manufacturing

• Extend this table to 3D waveguide (industry expects this to happen by 2020)• Extend this table to independently routable optical layers (vertically integrated

WG)• Integration level complexity to be added• Study cost scaling at system level

Ajey Jacob, Global Foundriesco-chair, Monolithic Integration TWG

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Fabless Business Model

§ Design into Foundry PDK (Process Design Kit)r Design manualr Process flow (layer thickness, doping levels)r Device library with compact models

§ Design for Manufacturingr Optimization of nominal design is rarely successfulr Source and statistics of variation are critical design inputsr Design centering compensates for process deficiencies

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The AIM Virtual Design Lab: Overview

Phase 1 – Simulation Library (2018-2019)

Phase 2 – Blended Learning (2019-2020)

InstructionEPDA Software

AIM Academy Virtual Lab

Workforce Training

Dr. Erik Verlage – everlage@mit.eduDr. Sajan Saini– sajan@mit.edu

interactive modules for the manufacturing workforce• PIC engineers• Fab and Test technician certification

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Demo – Directional Coupler

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Fall 2018 Technical Meeting: Technology§ Data Center global footprint: 20M sqft and increasing 2x/2yrs (new Moore’s Law?)§ Intra Data Center short reach tradeoff: MM bandwidth limits vs. connector loss§ Fiber Connect: surface mount TxRx with pluggable fiber connector§ Chip-Package co-design: TxRx-ASIC integration§ System-in-Package: edge fiber connect with 128 fibers/chip edge§ Interposers: active/passive; digital/RF; PIC/laser/fiber connect; PIC evaluation§ Lasers: etched facet, wafer-level passivation and packaging, reliability 95C/1000hr§ DfM: statistical compact models; nominal design optimization vs. design centering§ AIM PDK 2.5: process flow, compact models; device library (high performance)§ Quantum Entanglement Repeaters: for long distance connection§ Roadmap Scaling Metric: Density; Tbps/cm3; Joules/function

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Fall 2018 Technical Meeting: Applications§ Markets: increasing world age and education is creating a technology pull

r DC and Sensors lead; mobile, automotive, wearables, security

r penetration rate into $350B semiconductor market critical with good enough performance

§ DataCom: board - surface mount and connector; package – TxRx chipletsr Expanded beam connector: WDM for BW density; low mating force; low cost

§ RF for 5G: wireless to PIC TxRxr low index interposer; multiple beams-frequencies-targets

r 100G modulation; SFDR amps; efficient power amps

§ Sensor Systems:r ”If you build it they will come”: ADI Sensors (the next MEMS?): LED/PD/filter/ASIC

§ 3D ToF: facial recognition; sensors; roughness measurement

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Thank Youand Happy Holidays

Acknowledgements

• AIM Photonics Institute members• IPSR International TWG contributors• MIT Microphotonics Center members• iNEMI members• OSA/OIDA members• IEEE Photonics Society members• SPIE Photonics West participants• Photon Delta and the World Technology Mapping Forum TWGs

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