Konstantin Stefanov, Rutherford Appleton Laboratory p. 1

1 mm

Level 1 metal

Polyimide

Φ2

Φ2

Φ1

Φ1 To wire bonds

To wire bonds

Baseline Design

Single level metal ≈ 1 μm thick Al;

Busline width ≈ 1 mm;

For slow (1 MHz) column parallel readout;

Contact holes to polySi gates Channel stops

20 μm

20 μm

Konstantin Stefanov, Rutherford Appleton Laboratory p. 2

Φ1 Φ2

Φ1 Φ2

Level 1 metal

Polyimide

Level 2 metal

Φ2 Φ1

Φ2 Φ1

To microstrip connector

To microstrip connector

1 mm

Busline-free Design

Same underlying Si/polySi structure as in the Baseline Design;

Area for external connections ≈ 1 mm;

Two-level metal ≈ 1 μm thick Al;

Notes:

1. Contact holes in the area for external connections can be placed provided that there is no shorting between P1 and P2 by the first level metal.

2. To maximize conductor area and facilitate manufacture the contact holes along horizontal direction need not be every 2nd pixel – every 4th may be fine.

3. The same applies to the holes along the vertical direction as long as every gate is connected to the metal.

Apertures for resistance matching

Konstantin Stefanov, Rutherford Appleton Laboratory p. 3

Busline-free Design Optimization I

Konstantin Stefanov, Rutherford Appleton Laboratory p. 4

Busline-free Design Optimization II

Konstantin Stefanov, Rutherford Appleton Laboratory p. 5

RF Power Amplifier

1-50 MHz (100 W)

50 12.5

450 coax cables

2:1

200 Vpp

On CPC-2 MBExternal

Clock Delivery I

1

Termination and equalization

1

3.5:1

To CPC-2 clock pads

Via multiple wire bonds12.5

Following discussions with Colin Perry

Konstantin Stefanov, Rutherford Appleton Laboratory p. 6

RF Power Amplifier

1-50 MHz (100 W)

50

50 coax cable

200 Vpp25

25

On CPC-2 MBExternal

Clock Delivery II

1

Termination and equalization

1

5:1

To CPC-2 clock pads

Via multiple wire bonds

Following discussions with Colin Perry