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K thut s
Chng 7_2: M VHDL lung d liu
Bin son: Tng Vn On B mn: K thut in t Khoa: in & in t Trng: i hc Bch khoa TP H Ch Minh
Nm hc 2011 - 2012
(Ti liu gc: Introduction to VHDL, Department of Electrical and Computer Engineering, George Mason University, Fall 2007).
2
Phc tho
VHDL lung d liu (dataflow VHDL) (cho mch
logic t hp). S hc s dng std_logic_arith.
M t mch logic t hp s dng
VHDL lung d liu
4
Mch logic t hp
Mch logic t hp
Cc thanh ghi, flipflop.
Vn ca bi hc ny
M t thit k mc truyn thanh ghi (RTL)
5
Cc kiu thit k ca VHDL (architecture)
STRUCTURAL
(cu trc) Cc component v lin kt ni
Cc kiu thit k ca VHDL
DATAFLOW
(lung d liu) Cc pht biu ng thi My trng thi.
Thanh ghi. Mch logic t hp phc tp.
Cc pht biu tun t
NON- SYNTHESIZABLE
SYTHESIZABLE
(kh tng hp)
BEHAVIORAL (hnh vi)
Test Bench. M hnh IP. Cc cng.
Mch logic t hp n gin.
6
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else) php gn tn hiu ng thi la chn (with-select-when) to s cho cc phng trnh (for-generate)
Cc lnh chnh
Cc pht biu ng thi
VHDL lung d liu
7
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else) php gn tn hiu ng thi la chn (with-select-when) to s cho cc phng trnh (for-generate)
Cc lnh chnh
Cc pht biu ng thi
VHDL lung d liu
8
VHDL lung d liu: mch cng y
0 0 0 1 0 1 1 1
c i 1 +
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
c i x i y i
00 01 11 100
1
x i y i c i
1
1
1
1
s i x i y i c i =
00 01 11 100
1
x i y i c i
1
1 1 1
c i 1 + x i y i x i c i y i c i + + =
c i
x i y i s i
c i 1 +
(a) Truth table
(b) Karnaugh maps
(c) Circuit
0 1 1 0 1 0 0 1
s i
9
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN
s
10
Ton t logic
Ton t logic
Th t u tin ca ton t logic and or nand nor xor not xnor
not and or nand nor xor xnor
Cao nht
Thp nht
ch c trong VHDL-93 v tip theo.
11
Ta mun: y = ab + cd Khng ng y
12
Ni
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e, f: STD_LOGIC_VECTOR(7 DOWNTO 0); a
13
a(3) a(2) a(1) a(0)
a(2) a(1) a(0) a(3)
a_rotL
14
Dch trong VHDL (chn zero)
a(3) a(2) a(1) a(0)
a(2) a(1) a(0) a(3)
a_shiftL
15
Dch trong VHDL (s dng cc th vin)
S dng gi std_logic_arith: function SHL(ARG: UNSIGNED; COUNT: UNSIGNED)
return UNSIGNED; function SHL(ARG: SIGNED; COUNT: UNSIGNED)
return SIGNED; function SHR(ARG: UNSIGNED; COUNT: UNSIGNED)
return UNSIGNED; function SHR(ARG: SIGNED; COUNT: UNSIGNED)
return SIGNED; m bo rng c php ca ta l ng.
16
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else) php gn tn hiu ng thi la chn (with-select-when) to s cho cc phng trnh (for-generate)
Cc lnh chnh
Cc pht biu ng thi
VHDL lung d liu
17
target_signal
18
Ton t quan h
Th t u tin ca ton t quan h v logic = /= < >=
not = /= < >= and or nand nor xor xnor
Cao nht
Thp nht
Cc ton t
19
so snh a = bc Khng ng when a = b and c else tng ng vi when (a = b) and c else ng when a = (b and c) else
Mc u tin ca ton t logic v quan h
20
Mch m 3-trng thi th d
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 downto 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END tri_state; ARCHITECTURE tri_state_dataflow OF tri_state IS BEGIN output Z); END tri_state_dataflow;
input output ena
OTHERS ngha l mi bit khng c ch ra trc tip, trong trng hp ny tt c bit.
21
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else) php gn tn hiu ng thi la chn (with-select-when) to s cho cc phng trnh (for-generate)
Cc lnh chnh
Cc pht biu ng thi
VHDL lung d liu
22
with choice_expression select target_signal
23
Cc dng c php ca choices_k
WHEN value WHEN value_1 to value_2 WHEN value_1 | value_2 | .... | value N
C ngha l or boolean
24
Cc dng c php ca choices_k th d
WITH sel SELECT y
25
Th d MLU
26
MLU: S khi
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3 OUTPUT
SEL1
SEL0
MUX_4_1
L0L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1MUX_2
MUX_3
27
MLU: Khai bo entity
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC );
END mlu;
28
MLU: phn khai bo architecture
ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);
29
MLU Thn architecture BEGIN A1
30
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else) php gn tn hiu ng thi la chn (with-select-when) to s cho cc phng trnh (for-generate)
Cc lnh chnh
Cc pht biu ng thi
VHDL lung d liu
31
Pht biu for generate
For - Generate
label: FOR identifier IN range GENERATE BEGIN
{Concurrent Statements} END GENERATE [label];
32
Th d PARITY
33
PARITY: S khi
34
PARITY: Khai bo entity
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
parity_out : OUT STD_LOGIC ); END parity;
35
PARITY: s khi
xor_out(1) xor_out(2)
xor_out(3) xor_out(4) xor_out(5) xor_out(6)
36
PARITY: Architecture
ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: std_logic_vector (6 downto 1); BEGIN
xor_out(1)
37
PARITY: s khi (2)
xor_out(1) xor_out(2)
xor_out(3) xor_out(4) xor_out(5) xor_out(6)
xor_out(7)
xor_out(0)
38
PARITY: Architecture
ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0); BEGIN
xor_out(0)
39
PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0)
Tng hp mch logic t hp cho
ngi bt u
41
Vi mch logic t hp, ch s dng cc pht biu ng thi:
Cc qui lut n gin
php gn tn hiu ng thi () php gn tn hiu ng thi c iu kin (when-else)
php gn tn hiu ng thi la chn (with-select-when)
to s cho cc phng trnh (for-generate)
42
Cc qui lut n gin
Vi cc mch bao gm: cc php ton logic n gin (cng logic). cc php ton s hc n gin(cng, tr, nhn). dch/quay vi hng s.
S dng php gn tn hiu ng thi ()
43
Cc qui lut n gin
Vi cc mch bao gm: mch ghp knh. mch m ha, gii m. mch m 3-trng thi.
S dng: php gn tn hiu ng thi c iu kin (when-else ) php gn tn hiu ng thi la chn (with-select-when)
44
S hc c du v khng du
46
Cc php ton s hc
Cc php ton s hc tng hp c: Cng: + Tr: - So snh: >, >=,
47
Cc php ton s hc
Kt qu tng hp ca php ton s hc l: - mch t hp. - khng to ng ng. architecture bn trong chnh xc c s dng (v do vy tr hon v din tch ca mch) c th ph thuc vo cc rng buc nh thi c ch ra trong thi gian tng hp (e.g., tn s clock cc i c
yu cu).
48
Cc gi IEEE cho s hc
std_logic_1164 Chun IEEE chnh thc. nh ngha std_logic v std_logic_vector
Th d: std_logic_vector(7 downto 0) Ch dnh cho cc php ton logic (AND, OR), khng
dnh cho php ton s hc (+, *). std_logic_arith
Khng l chun IEEE chnh thc (Synopsys to ra). nh ngha cc kiu d liu unsigned v signed, th
d: unsigned(7 downto 0) Ch dnh cho s hc (+,*), khng dnh cho logic (AND,
OR).
49
Cc gi IEEE cho s hc
std_logic_unsigned Khng l chun IEEE chnh thc (Synopsys to ra). Vic bao gm th vin ny bo trnh dch x l kiu
std_logic_vector ging unsigned trong mt s trng hp. Th d, c th thc hin php cng trn std_logic_vector.
c s dng lm cng c h tr trnh cc hm bin i tng minh.
std_logic_signed Khng l chun IEEE chnh thc (Synopsys to ra). Cng chc nng nh std_logic_unsigned, bo trnh dch x l
kiu std_logic_vector ging signed trong mt s trng hp. Khng s dng c hai std_logic_unsigned v
std_logic_signed cng thi im! Nu cn thc hin c s hc c du ln khng du trong cng mt
entity, khng s dng cc gi std_logic_unsigned hoc std_logic_signed thc hin mi bin i mt cch r rng.
50
Bao gm th vin
Khi x l s hc khng du s dng: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ! needed for using unsigned data type USE ieee.std_logic_unsigned.all;
Khi x l s hc c du s dng: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; need for using signed data type USE ieee.std_logic_signed.all;
Khi x l s hc khng du ln c du s dng: LIBRARY IEEE;
USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
k n thc hin mi bin i kiu mt cch r rng
51
std_logic_arith so vi numeric_std
Lch s Gi std_logic_arith c to ra bi Synopsys. Sau cng, IEEE to ra phin bn std_logic_arith chnh
thc gi l numeric_std. numeric_std
Chun IEEE chnh thc. nh ngha unsigned v signed. Dnh cho s hc (+,*), khng dnh cho logic (AND, OR).
Th d: unsigned(7 downto 0) S dng hoc numeric_std hoc std_logic_arith, khng
phi c hai!
52
std_logic_arith so vi numeric_std
Khi x l cc kiu khng du v/hoc c du s dng numeric_std, hy dng:
LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;
Do cc nh cung cp CAD khc nhau c th thc hin std_logic_arith khc nhau, ta c th s dng numeric_std cho an ton. Tuy nhin nhiu cng ty v thit k k tha s dng
std_logic_arith cng vi std_logic_unsigned hoc std_logic_signed.
Cc th d ca ta s s dng std_logic_arith cng vi std_logic_unsigned/signed, khng s dng numeric_std.
Nu ta s dng numeric_std, cn m bo khai bo r rng.
53
Th d: std_logic_arith v numeric_std
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c
54
Cc hm bin i
From: http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html
55
c thm thng tin?
S dng: http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html
Np xung std_logic_arith.vhd std_logic_unsigned.vhd std_logic_signed.vhd numeric_std v so snh chng.
56
S khng du v c du
S khng du N-bit: unsigned(N-1 downto 0) C tm thp phn t 0 n 2N-1
Th d: unsigned(7 downto 0) c tm thp phn t 0 n 255. S c du N-bit (b-2): signed(N-1 downto 0)
C tm thp phn t -2N-1 n 2N-1-1 Tm khng i xng do biu din khng d tha s 0. Th d: signed(7 downto 0) c tm thp phn t -128 n 127.
57
S khng du v c du (tip theo)
S c du N-bit (b-2): signed(N-1 downto 0) (tip theo) MSB ch ra du
0 MSB c ngha l khng m (0 hoc dng). 1 MSB c ngha l m.
ly b s b-2: o logic mi bit, cng 1 vo LSB 010 = 2 c -2, o logic ri cng 1: 101 +1 = 110
M rng du khng nh hng n gi tr. Th d: 010 v 00010 u biu din thp phn 2. Th d: 110 v 11110 u biu din thp phn -2.
58
Khng du so vi c du
Binary Unsigned value (decimal) Signed value (decimal)
0000 0 (zero) 0 (zero)
0001 1 1
0010 2 2
0011 3 3
0100 4 4
0101 5 5
0110 6 6
0111 7 7 (largest positive value)
1000 8 -8 (largest negative value)
1001 9 -7
1010 10 -6
1011 11 -5
1100 12 -4
1101 13 -3
1110 14 -2
1111 15 (largest positive value) -1 (smallest negative value)
59
Cng s khng du A (2 bits) B (2 bits) SUM = A + B
DECIMAL SUM BINARY
SUM and CARRYOUT BINARY
00 00 0 + 0 = 0 00 000
01 00 1 + 0 = 1 01 001
10 00 2 + 0 = 2 10 010
11 00 3 + 0 = 3 11 011
00 01 0 + 1 = 1 01 001
01 01 1 + 1 = 2 10 010
10 01 2 + 1 = 3 11 011
11 01 3 + 1 = 4 00 100
00 10 0 + 2 = 2 10 010
01 10 1 + 2 = 3 11 011
10 10 2 + 2 = 4 00 100
11 10 3 + 2 = 5 01 101
00 11 0 + 3 = 3 11 011
01 11 1 + 3 = 4 00 100
10 11 2 + 3 = 5 01 101
11 11 3 + 3 = 6 10 110
ch ra mt thng tin (i.e. p s sai) nu s nh ng ra khng c gi v ch th i vi SUM m zero.
60
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0)); end adder_unsigned; architecture arch of adder_unsigned is begin sum
61
Cng khng du: c s nh ng ra library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned_carryout is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0); cout : out STD_LOGIC ); end adder_unsigned_carryout; architecture arch of adder_unsigned_carryout is signal tempsum : std_logic_vector(2 downto 0); begin tempsum
62
Cng s c du A (2 bits) B (2 bits) SUM = A + B
DECIMAL SUM BINARY
SUM and CARRYOUT BINARY
00 00 0 + 0 = 0 00 000
01 00 1 + 0 = 1 01 001
10 00 -2 + 0 = -2 10 110
11 00 -1 + 0 = -1 11 111
00 01 0 + 1 = 1 01 001
01 01 1 + 1 = 2 10 010
10 01 -2 + 1 = -1 11 111
11 01 -1 + 1 = 0 00 000
00 10 0 + -2 = -2 10 110
01 10 1 + -2 = -1 11 111
10 10 -2 + -2 = -4 00 100
11 10 -1 + -2 = -3 01 101
00 11 0 + -1 = -1 11 111
01 11 1 + -1 = 0 00 000
10 11 -2 + -1 = -3 01 101
11 11 -1 + -1 = -2 10 110
ch ra mt thng tin (i.e. p s sai) nu s nh ng ra khng c gi v ch th i vi SUM m rng du.
63
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0)); end adder_signed; architecture arch of adder_signed is begin sum
64
Cng c du: c s nh ng ra library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed_carryout is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0); cout : out STD_LOGIC ); end adder_signed_carryout; architecture arch of adder_signed_carryout is signal tempsum : std_logic_vector(2 downto 0); begin tempsum
65
Testbench: cng c du c s nh ng ra library ieee; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; entity adder_signed_carryout_tb is end adder_signed_carryout_tb; architecture TB_ARCHITECTURE of adder_signed_carryout_tb is
component adder_signed_carryout port( a : in std_logic_vector(1 downto 0); b : in std_logic_vector(1 downto 0); sum : out std_logic_vector(1 downto 0); cout : out std_logic ); end component; signal a : std_logic_vector(1 downto 0) := "00"; signal b : std_logic_vector(1 downto 0) := "00"; signal sum : std_logic_vector(1 downto 0); signal cout : std_logic;
66
Tesbench (tip) begin
UUT : adder_signed_carryout port map ( a => a, b => b, sum => sum, cout => cout ); process begin for i in 0 to 3 loop for j in 0 to 3 loop wait for 10 ns; b
67
Dng sng
68
Nhn
S khng du N-bit x s khng du M-bit cho kt qu s khng du N+M bit. Th d: 3 bit x 4 bit = 7 bit 111 (7) x 1111 (15) = 1101001 (105) dng ln nht x dng ln
nht cn 7 bit S c du N-bit x s c du M-bit dn n s khng du N+M bit
Th d: 3 bit x 4 bit 100 (-4) x 1000 (-8) = 0100000 (+32) m ln nht x m ln nht cn
7 bit (y ch l kch bn yu cu tm u ra y ). 100 (-4) x 0111 (7) = [1]100100 (-28) m ln nht x dng ln nht
cn 6 bit, [ ] ch ra khng cn thit. 011 (3) x 0111 (7) = [0]010101 (21) dng ln nht x dng ln
nht cn 6 bit. 011 (3) x 1000 (-8) = [1]101000 (-24) dng ln nht x m ln nht
cn 6 bit.
69
Nhn cc s c du v khng du (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity multiply is port( a : in STD_LOGIC_VECTOR(15 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(23 downto 0); cs : out STD_LOGIC_VECTOR(23 downto 0) );
end multiply; architecture dataflow of multiply is SIGNAL sa: SIGNED(15 downto 0); SIGNAL sb: SIGNED(7 downto 0); SIGNAL sres: SIGNED(23 downto 0); SIGNAL ua: UNSIGNED(15 downto 0); SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL ures: UNSIGNED(23 downto 0);
Do s dng c hai kiu d liu signed v unsigned, khng s dng std_logic_unsigned/signed. Thc hin mi php bin i bng tay.
70
Nhn cc s c du v khng du (2)
begin
-- signed multiplication sa
71
Kiu nguyn (integer)
Cc php ton trn nhng tn hiu (bin) c cc kiu (type) nguyn:
INTEGER, NATURAL, v cc kiu con ca chng, nh l TYPE day_of_month IS RANGE 0 TO 31; l kh tng hp trong tm (range)
-(231-1) .. 231 -1 i vi INTEGER v cc kiu con. 0 .. 231 -1 for NATURAL v cc kiu con.
72
Kiu nguyn (integer)
Cc php ton trn nhng tn hiu (bin) c cc kiu (type) nguyn:
INTEGER, NATURAL, s km linh hot v kh iu khin hn so vi cc php ton
trn nhng tn hiu (bin) c kiu: STD_LOGIC_VECTOR UNSIGNED SIGNED v do vy
c khuyn co nhng ngi mi bt u trnh, tr khi cn thit.