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7/29/2019 Lab 8_Current Mirror
1/18
Analog Integrated Circuits
Laboratory
Analog ICs;Hong-Yi Huang2-1Current Source
Hong-Yi Huang
Nano Integrated Circuits and Systems Lab.
Graduate Inst itute of Electrical Engineering
7/29/2019 Lab 8_Current Mirror
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Outline
NMOS Current Source
Basic NMOS Current Mirror
Cascode Current Mirrors
Improve Current Mirror
High-Swing Cascode Current Mirror
Analog ICs;Hong-Yi Huang2-2Current Source
Wilson Current Mirror
Low-Voltage Current Mirror
Experiment Steps
Questions
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NMOS Current Source
Analog ICs;Hong-Yi Huang2-3Current Source
For NMOS get into saturation region
VGS Vt, VGD Vt
VGD = VBIAS VDS Vt , we get VDS VBIAS-Vt
Define VBIAS-Vt is VMIN
So VDS VMIN is a Current Source
NL
KWhere
I
1
I
V1r
CHDD
DSds
K=dimensional factor
NCH=doping concentration
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NMOS Current Source
Analog ICs;Hong-Yi Huang2-4Current Source
Let VBIAS = 0.8V
VMIN=VBIAS Vt 0.4V
7/29/2019 Lab 8_Current Mirror
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Basic NMOS Current Mirror
Analog ICs;Hong-Yi Huang2-5Current Source
In fact, in analog IC design, using Current Mirror (as seen in the figure above) to get
current source from a current reference is a typical method.
2
tGS1o )VV(L
WCu
2
1I
1
oxn -
2tGS2REF )VV(
L
WCu
2
1I
2
oxn -
REF
2
1o I
L/W
L/WI
7/29/2019 Lab 8_Current Mirror
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If we take Short Channel Effect into analysis
Basic NMOS Current Mirror _ Second Order Effect
)V1()VV(L
WCu
2
1I
1
oxn DS12
tGS1o -
)V1()VV(L
WCu
2
1I
2
oxnREF DS22
tGS2 -
Analog ICs;Hong-Yi Huang2-6Current Source
REF
2
1 I)V1(L/W
)V1(L/WI
DS2
DS1o
From the formula, if we want to reduce the Short Channel Effect, increase the
channel length will increase rO, so that the current source become more ideal.
7/29/2019 Lab 8_Current Mirror
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Basic NMOS Current Mirror _ Second Order Effect
Analog ICs;Hong-Yi Huang2-7Current Source
If we increase the channel length then we get a more constant current source.
7/29/2019 Lab 8_Current Mirror
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Cascode Current Mirror
MN1MN2
MN3MN4
IOIREF
rO
+
+
+
+
+
+
-
-VR
Vd
Vb
Vc
Va
Vo
rO3
rO1
gm3va
gmb3va
io
Vo
+
-
+
-Va
+
-
Vc
Analog ICs;Hong-Yi Huang2-8Current Source
Use cascode structure to enhance ro.
Vo = Va + Vc = Va + ro3[ Io + gmb3Va +gm3Va ] and Va = Io ro1
Vo = Io[ ro1 + ro3 + gmb3 ro1 ro3+ gm3 ro1 ro3 ]
We get ro = Vo / Io =ro1 + ro3 + gm3 ro1 ro3 (1+3)
Where 3 = gmb3 / gm3
- - - -
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Now we analyze the VMIN of Cascode
Current Mirror
VDS(sat) = VGS Vt
VGS = VDS(sat) + Vt
= =
Cascode Current Mirror
Analog ICs;Hong-Yi Huang2-9Current Source
sa
Vo = VR - Vt
We get Vo =2VDS(sat) + Vt = VMIN
In this case, VMIN 2 0.15 + 0.4 = 0.7V
7/29/2019 Lab 8_Current Mirror
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High-Swing Cascode Current Mirror
MN3Wn/Ln=4/1
IO
rO
+
Vo
+
-
+
VGS4
IREF
MN4Wn/Ln=4/4
MN1Wn/Ln
MN3Wn/Ln
4 1
Analog ICs;Hong-Yi Huang2-10Current Source
In order to reduce VMINadjust the Channel Length of MN4 as four times to the
other NMOSaccording to the current formula in saturation
(VGS4 Vt) = 2(VGS2 Vt) = 2VDS(sat)so VGS4 = 2VDS(sat) + Vt
we getVo = VGS4 Vt
Vo = (2VDS(sat) + Vt ) Vt =2VDS(sat) = VMIN
--
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High-Swing Cascode Current Mirror
Analog ICs;Hong-Yi Huang2-11Current Source
From the simulation, we can see that the VMIN of High-Swing Cascode Current
Mirror is smaller than Cascode Current Mirror.
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Wilson Current Mirror
Analog ICs;Hong-Yi Huang2-12Current Source
From the small signal analysis we get the output resistance to be
ro
= = Vo
/ Io
= ro3
+ ro2
+[ ]
if we increase the ro3 means we can increase output resistance obviously.
2o2m
3o1om3m13o3m3
rg1
1rrggr)1(g
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Wilson Current Mirror
Analog ICs;Hong-Yi Huang2-13Current Source
We increase the width of MN3 in order to increase the output resistance, from the
simulation, the larger width produce smaller slope current curve, means we
increase the output resistance.
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Low-Voltage Current Mirror
Now, we introduce a Low-Voltage Current Mirror.
M4
Vb
VDD
X
A
IREF
M3
M1
Iout
B
VOUT V2V
VV2VVVVVVV
minOUT
tminb
4t2GSb2t2GS4GS
1DS3GS2DS4GSb VVVVV
3GS4GS VVIf
Analog ICs;Hong-Yi Huang2-14Current Source
M2 REFOUT2GS1GS IIVVAnd
From the small signal, the output resistance
ro = Vo / Io = 1 + ro1(1 + gm3ro3 + gmb3ro3) .
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Low-Voltage Current Mirror
From above-mentioned, we can increase the output resistance ro by increasing the
width of MN3MN4.
Analog ICs;Hong-Yi Huang2-15Current Source
m=1m=2m=10
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Experiment Steps
Use a single MOS as a current source as page 3, simulate output current ID. Try to
increase the channel length to see what change in ID.
Use a simple type current mirror as page 5, get the output current Io from the
reference current IREF. Try to increase the channel length to see what change in ID.
Use a cascode current mirror as page 8, get the output current Io from the reference
current IREF. Try to increase the channel length to see what change in ID.
Analog ICs;Hong-Yi Huang2-16Current Source
Use high swing cascode current mirror as page 10, get the output current Io from
the reference current IREF. Try to increase the channel length to see what change in
ID.
Use wilson current mirror as page 12, get the output current Io from the reference
current IREF. Try to increase the channel width of MN3 to vary gm3 and to see what
change in ro.
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Steps
Use low voltage current mirror as page 14, get the output current Io from the
reference current IREF
. Try to increase the channel width of MN3 to vary gm3
and to
see what change in ro.
Analog ICs;Hong-Yi Huang2-17Current Source
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Questions
Assuming IREF=100uA, how can we use IREF to generate 500uA300uA current
source (sink) respectively ?
An advantage of the High-Swing Cascode Current Mirror is that its VMIN is 2VDS(sat),
but what is the drawback for this structure?
Can you describe the voltage operation range of a Low-Voltage Current Mirror?
Analog ICs;Hong-Yi Huang2-18Current Source